340 lines
12 KiB
C
340 lines
12 KiB
C
/*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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*/
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/************************************************************************
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*
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* anomaly_macros_rtl.h : $Revision$
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*
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* (c) Copyright 2005-2011 Analog Devices, Inc. All rights reserved.
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*
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* This file defines macros used within the run-time libraries to enable
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* certain anomaly workarounds for the appropriate chips and silicon
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* revisions. Certain macros are defined for silicon-revision none - this
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* is to ensure behaviour is unchanged from libraries supplied with
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* earlier tools versions, where a small number of anomaly workarounds
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* were applied in all library flavours. __FORCE_LEGACY_WORKAROUNDS__
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* is defined in this case.
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*
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* This file defines macros for a subset of all anomalies that may impact
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* the run-time libraries.
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*
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************************************************************************/
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#ifdef _MISRA_RULES
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#pragma diag(push)
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#pragma diag(suppress:misra_rule_2_4:"Assembly code in comment used to illustrate anomalous behaviour")
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#endif /* _MISRA_RULES */
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#if !defined(__SILICON_REVISION__)
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#define __FORCE_LEGACY_WORKAROUNDS__
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#endif
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/* 050000245 - "False Hardware Error from an Access in the Shadow of a
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** Conditional Branch"
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**
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** If a load accesses reserved or illegal memory on the opposite control
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** flow of a conditional jump to the taken path, a false hardware error
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** will occur.
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**
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** This macro is used by System Services/Device Drivers.
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**
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** This is for all Blackfin LP parts.
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*/
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#define WA_05000245 \
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(defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__))
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/* 05-00-0229 - "SPI Slave Boot Mode Modifies Registers".
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* When the SPI slave boot completes, the final DMA IRQ is cleared
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* but the DMA5_CONFIG and SPI_CTL registers are not reset to their
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* default states.
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*
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* We work around this by resetting the registers to their default
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* values at the beginning of the CRT. The only issue would be when
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* users boot from flash and make use of the DMA or serial port.
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* In this case, users would need to modify the CRT.
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*
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* This problem impacts all revisions of ADSP-BF531/2/3/8/9
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*/
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#define WA_05000229 \
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(defined(__ADSPBLACKFIN__) && defined (__SILICON_REVISION__) && \
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(defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
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defined(__ADSPBF533__) || defined(__ADSPBF538__) || \
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defined(__ADSPBF539__)))
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/* 05-00-0283 - "A system MMR write is stalled indefinitely when killed in a
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* particular stage".
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*
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* Where an interrupt occurs killing a stalled system MMR write, and the ISR
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* executes an SSYNC, execution execution may stall indefinitely".
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*
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* The workaround is to execute a mispredicted jump over a dummy MMR read,
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* thus killing the read. Also to avoid a system MMR write in two slots
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* after a not predicted conditional jump.
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*
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* This problem impacts:
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* BF531/2/3 - < 0.6
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* BF534/6/7 - < 0.3
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* BF538/9 - < 0.4
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* BF561/6 - < 0.5
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*
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* Since this impacts 538/9 0.3 but not 534 0.3 (the libraries that they use)
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* we have to enable this workaround for the 534 0.3 libraries (see bottom
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* two lines).
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*/
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#define WA_05000283 \
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(defined (__SILICON_REVISION__) && \
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(((defined(__ADSPBF531__) || \
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defined(__ADSPBF532__) || \
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defined(__ADSPBF533__)) && \
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(__SILICON_REVISION__ == 0xffff || \
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__SILICON_REVISION__ < 0x6)) || \
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((defined(__ADSPBF534__) || \
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defined(__ADSPBF536__) || \
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defined(__ADSPBF537__)) && \
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(__SILICON_REVISION__ == 0xffff || \
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__SILICON_REVISION__ < 0x3)) || \
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((defined(__ADSPBF538__) || \
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defined(__ADSPBF539__)) && \
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(__SILICON_REVISION__ == 0xffff || \
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__SILICON_REVISION__ < 0x4)) || \
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(defined(__ADSPBF561__)) || \
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(defined(__ADSPBF534__) && __SILICON_REVISION__ == 0x3 && \
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defined(__ADI_LIB_BUILD__))))
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/* 05-00-0311 - Erroneous Flag (GPIO) Pin Operations under Specific Sequences
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**
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** Impacted:
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** ADSP-BF53[123] - 0.0-0.5 (fixed in 0.6)
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**
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** Use by System Services/Device Drivers.
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*/
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#define WA_05000311 \
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(defined(__ADSPBF533_FAMILY__) && \
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(defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ <= 0x5 || __SILICON_REVISION__ == 0xffff)))
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/* 05-00-0312 - Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers
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** Are Interrupted
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**
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** Impacted:
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** ADSP-BF53[123] - 0.0-0.5 (fixed in 0.6)
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** ADSP-BF53[467] - all supported revisions
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** ADSP-BF53[89] - 0.0-0.4 (fixed in 0.5)
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** ADSP-BF561 - all supported revisions
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** ADSP-BF54[24789] - 0.0 (fixed in 0.1)
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**
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** Used by VDK
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*/
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#define WA_05000312 \
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(defined(__SILICON_REVISION__) && \
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((defined(__ADSPBF533_FAMILY__) && \
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(__SILICON_REVISION__ <= 0x5 || __SILICON_REVISION__ == 0xffff)) || \
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(defined(__ADSPBF537_FAMILY__)) || \
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(defined(__ADSPBF538_FAMILY__) && \
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(__SILICON_REVISION__ <= 0x4 || __SILICON_REVISION__ == 0xffff)) || \
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(defined(__ADSPBF548_FAMILY__) && \
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(__SILICON_REVISION__ == 0x0 || __SILICON_REVISION__ == 0xffff)) || \
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(defined(__ADSPBF561_FAMILY__))))
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/* 05-00-0323 - Erroneous Flag (GPIO) Pin Operations under Specific Sequences
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**
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** Impacted:
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** ADSP-BF561 - all supported revisions
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**
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** Use by System Services/Device Drivers.
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*/
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#define WA_05000323 \
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(defined(__ADSPBF561__) && defined(__SILICON_REVISION__))
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/* 05-00-0365 - DMAs that Go Urgent during Tight Core Writes to External
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** Memory Are Blocked
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**
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** Impacted:
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** ADSP-BF54[24789] - all supported revisions
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** ADSP-BF54[24789]M - all supported revisions
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**
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** Use by System Services/Device Drivers.
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*/
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#define WA_05000365 \
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((defined(__ADSPBF548_FAMILY__) || defined(__ADSPBF548M_FAMILY__)) && \
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defined(__SILICON_REVISION__))
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/* 05-00-0371 - Possible RETS Register Corruption when Subroutine Is under
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** 5 Cycles in Duration
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**
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** This problem impacts:
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** BF531/2/3 - 0.0-0.5 (fixed in 0.6)
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** BF534/6/7 - 0.0-0.3
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** BF538/9 - 0.0-0.4 (fixed in 0.5)
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** BF561 - 0.0-0.5
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** BF542/4/7/8/9 - 0.0-0.1 (fixed in 0.2)
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** BF523/5/7 - 0.0-0.1 (fixed in 0.2)
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**
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*/
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#define WA_05000371 \
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(defined(__SILICON_REVISION__) && \
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((defined(__ADSPBF533_FAMILY__) && \
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(__SILICON_REVISION__ <= 0x5 || __SILICON_REVISION__ == 0xffff)) || \
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(defined(__ADSPBF537_FAMILY__) && \
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(__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff)) || \
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(defined(__ADSPBF538_FAMILY__) && \
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(__SILICON_REVISION__ <= 0x4 || __SILICON_REVISION__ == 0xffff)) || \
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(defined(__ADSPBF548_FAMILY__) && \
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(__SILICON_REVISION__ <= 0x1 || __SILICON_REVISION__ == 0xffff)) || \
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(defined(__ADSPBF527_FAMILY__) && \
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(__SILICON_REVISION__ <= 0x1 || __SILICON_REVISION__ == 0xffff)) || \
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(defined(__ADSPBF561__) || defined(__ADSPBF566__))))
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/* 05-00-0412 - "TESTSET Instruction Causes Data Corruption with Writeback Data
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* Cache Enabled"
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*
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* If you use the testset instruction to operate on L2 memory and you have data
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* in external memory that is cached using WB mode, data in external memory
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* and/or L2 memory can be corrupted.
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*
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* Workaround: Either do not use writeback cache or precede the TESTSET
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* instruction with an SSYNC instruction. If preceding the TESTSET instruction
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* by an SSYNC instruction, do the following:
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*
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* CLI R0
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* R1 = [P0] // perform a dummy read to make sure CPLB is installed
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* NOP
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* NOP
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* SSYNC
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* TESTSET (P0)
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* STI R0
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*
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* This problem impacts:
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* BF561/6 - rev 0.0-0.5
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*
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*/
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#define WA_05000412 \
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(defined (__SILICON_REVISION__) && defined(__ADSPBF561__))
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/* 05-00-0426 - Speculative Fetches of Indirect-Pointer Instructions Can
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** Cause False Hardware Errors
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**
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**
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** A false hardware error is generated if there is an indirect jump or
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** call through a pointer which may point to reserved or illegal memory
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** on the opposite control flow of a conditional jump to the taken path.
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** This commonly occurs when using function pointers, which can be
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** invalid (e.g., set to -1).
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**
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** Workaround: If instruction cache is on or the ICPLBs are enabled,
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** this anomaly does not apply. If instruction cache is off and ICPLBs
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** are disabled, the indirect pointer instructions must be 2 instructions
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** away from the branch instruction, which can be implemented using NOPs:
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**
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**
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** Impacted:
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** All parts and revisions other than BF535 based parts.
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**
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** Used by System Services/Device Drivers.
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*/
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#define WA_05000426 \
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(defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__))
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/* 05-00-0428 - "Lost/Corrupted Write to L2 Memory Following Speculative Read
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* by Core B from L2 Memory"
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*
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* This issue occurs only when the accesses are performed by core B of a BF561.
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*
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* When a write to internal L2 memory follows a speculative read from internal
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* L2 memory, the L2 write may be lost or corrupted. For this anomaly to occur,
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* the speculative read must be caused by a read in the shadow of a branch. The
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* accesses do not have to be consecutive accesses. In other words, the problem
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* can occur even if there are multiple instructions between the speculative
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* read and the write, as shown in the following example:
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*
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* R1 = 1; R2 = 1;
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* CC = R1 == R2;
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* IF CC JUMP X; // Always true...
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* R0 = [P0]; // If any of these three loads accesses L2 memory from Core
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* R1 = [P1]; // B, speculative execution in the pipeline causes the
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* R2 = [P2]; // anomaly trigger condition.
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* X:
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* ... // Any number of instructions...
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* [P0] = R0; // This write can be corrupted or lost.
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*
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* The issue does not occur if the speculative read access is caused by an
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* interrupt or exception.
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*
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* The workaround required depends upon the conditional branch instruction.
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* If the evaluated condition is true and the branch is predicted, then the
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* workaround is to ensure that the target instruction is not be a load
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* instruction, for example:
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*
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* IF CC JUMP X (BP);
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* ...
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* X: <load that might be from L2 memory>
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*
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* If the evaluated condition is false and the branch is not predicted, then
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* the workaround is to make sure that none of the three instructions that
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* are executed after the conditional JUMP are load instructions, for example:
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*
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* IF CC JUMP ...;
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* <load that might be from L2 memory>
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* <load that might be from L2 memory>
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* <load that might be from L2 memory>
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*
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* This problem impacts:
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* BF561 - rev 0.4,0.5
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*
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*/
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#define WA_05000428 \
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(defined(__SILICON_REVISION__) && \
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defined(__ADSPBF561__) && \
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((__SILICON_REVISION__ == 0xffff) || \
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(__SILICON_REVISION__ == 0x4) || \
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(__SILICON_REVISION__ == 0x5)))
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/* 05-00-0443 - IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall
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**
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** Impacted:
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** All parts and revisions other than BF535 based parts.
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**
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** Used by System Services/Device Drivers.
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*/
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#define WA_05000443 \
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(defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__))
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/* 16-00-0005 - "Using L1 Instruction Cache with Parity Enabled is Unreliable."
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**
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** Using L1 instruction cache with parity enabled is unreliable and may cause
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** unpredictable results.
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**
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** Impacted:
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** BF6xx.
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*/
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#define WA_16000005 \
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(defined(__ADSPBF60x__) && defined(__SILICON_REVISION__))
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#ifdef _MISRA_RULES
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#pragma diag(pop)
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#endif /* _MISRA_RULES */
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