4e952f53dc
* mep.h (EF_MEP_CPU_C5): New. [bfd] * archures.c: Add bfd_mach_mep_c5. * bfd-in2.h: Likewise. * cpu-mep.c: Add bfd_c5_arch. * elf32-mep.c: Support it. [gas] * config/tc-mep.c: Add UCI/DSP instruction support. Add C5 support. (md_show_usage): Change default endian to little. * config/tc-mep.h (TARGET_BYTES_BIG_ENDIAN): Change default to little. [ld] * emulparams/elf32mep.sh: Change default endian to little.
87 lines
3.9 KiB
C
87 lines
3.9 KiB
C
/* Toshiba MeP ELF support for BFD.
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Copyright (C) 2001, 2004, 2005 Free Software Foundation, Inc.
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This file is part of BFD, the Binary File Descriptor library.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#ifndef _ELF_MEP_H
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#define _ELF_MEP_H
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/* Bits in the sh_flags field of Elf32_Shdr: */
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#define SHF_MEP_VLIW 0x10000000 /* contains vliw code */
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/* This bit is reserved by BFD for processor specific stuff. Name
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it properly so that we can easily stay consistent elsewhere. */
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#define SEC_MEP_VLIW SEC_TIC54X_BLOCK
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#include "elf/reloc-macros.h"
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/* Note: The comments in this file are used by bfd/mep-relocs.pl to
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build parts of bfd/elf32-mep.c. */
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/* Relocations. */
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START_RELOC_NUMBERS (elf_mep_reloc_type)
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/* These two must appear first so that they are not processed by bfd/mep-relocs.pl. */
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RELOC_NUMBER (R_MEP_NONE, 0)
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RELOC_NUMBER (R_RELC, 1)
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RELOC_NUMBER (R_MEP_8, 2) /* 7654 3210 U */
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RELOC_NUMBER (R_MEP_16, 3) /* fedc ba98 7654 3210 U */
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RELOC_NUMBER (R_MEP_32, 4) /* vuts rqpo nmlk jihg fedc ba98 7654 3210 U */
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RELOC_NUMBER (R_MEP_PCREL8A2, 5) /* ---- ---- 7654 321- S PC-REL */
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RELOC_NUMBER (R_MEP_PCREL12A2, 6) /* ---- ba98 7654 321- S PC-REL */
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RELOC_NUMBER (R_MEP_PCREL17A2, 7) /* ---- ---- ---- ---- gfed cba9 8765 4321 S PC-REL */
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RELOC_NUMBER (R_MEP_PCREL24A2, 8) /* ---- -765 4321 ---- nmlk jihg fedc ba98 S PC-REL */
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RELOC_NUMBER (R_MEP_PCABS24A2, 9) /* ---- -765 4321 ---- nmlk jihg fedc ba98 U */
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RELOC_NUMBER (R_MEP_LOW16, 10) /* ---- ---- ---- ---- fedc ba98 7654 3210 U no-overflow */
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RELOC_NUMBER (R_MEP_HI16U, 11) /* ---- ---- ---- ---- vuts rqpo nmlk jihg U no-overflow */
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RELOC_NUMBER (R_MEP_HI16S, 12) /* ---- ---- ---- ---- vuts rqpo nmlk jihg S no-overflow */
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RELOC_NUMBER (R_MEP_GPREL, 13) /* ---- ---- ---- ---- fedc ba98 7654 3210 S GP-REL*/
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RELOC_NUMBER (R_MEP_TPREL, 14) /* ---- ---- ---- ---- fedc ba98 7654 3210 S TP-REL*/
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RELOC_NUMBER (R_MEP_TPREL7, 15) /* ---- ---- -654 3210 U TP-REL */
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RELOC_NUMBER (R_MEP_TPREL7A2, 16) /* ---- ---- -654 321- U TP-REL */
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RELOC_NUMBER (R_MEP_TPREL7A4, 17) /* ---- ---- -654 32-- U TP-REL */
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RELOC_NUMBER (R_MEP_UIMM24, 18) /* ---- ---- 7654 3210 nmlk jihg fedc ba98 U */
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RELOC_NUMBER (R_MEP_ADDR24A4, 19) /* ---- ---- 7654 32-- nmlk jihg fedc ba98 U */
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RELOC_NUMBER (R_MEP_GNU_VTINHERIT, 20) /* ---- ---- ---- ---- U no-overflow */
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RELOC_NUMBER (R_MEP_GNU_VTENTRY, 21) /* ---- ---- ---- ---- U no-overflow */
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END_RELOC_NUMBERS(R_MEP_max)
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#define EF_MEP_CPU_MASK 0xff000000 /* specific cpu bits */
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#define EF_MEP_CPU_MEP 0x00000000 /* generic MEP */
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#define EF_MEP_CPU_C2 0x01000000 /* MEP c2 */
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#define EF_MEP_CPU_C3 0x02000000 /* MEP c3 */
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#define EF_MEP_CPU_C4 0x04000000 /* MEP c4 */
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/* 5..7 are reseved */
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#define EF_MEP_CPU_C5 0x08000000 /* MEP c5 */
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#define EF_MEP_CPU_H1 0x10000000 /* MEP h1 */
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#define EF_MEP_LIBRARY 0x00000100 /* Built as a library */
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#define EF_MEP_INDEX_MASK 0x000000ff /* Configuration index */
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#define EF_MEP_ALL_FLAGS 0xff0001ff
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#endif /* _ELF_MEP_H */
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