3f4df6211e
* configure: Regenerate. * ms1/16-002.ld: New. * ms1/16-003.ld: New. * ms1/64-001.ld: New. * ms1/access.c: New. * ms1/chmod.c: New. * ms1/close.c: New. * ms1/configure: New. * ms1/configure.in: New. * ms1/crt0-16-002.S: New. * ms1/crt0-16-003.S: New. * ms1/crt0-64-001.S: New. * ms1/crt0.S: New. * ms1/exit-16-002.c: New. * ms1/exit-16-003.c: New. * ms1/exit-64-001.c: New. * ms1/exit.c: New. * ms1/fstat.c: New. * ms1/getpid.c: New. * ms1/gettime.c: New. * ms1/isatty.c: New. * ms1/kill.c: New. * ms1/lseek.c: New. * ms1/Makefile.in: New. * ms1/open.c: New. * ms1/read.c: New. * ms1/sbrk.c: New. * ms1/startup-16-002.S: New. * ms1/startup-16-003.S: New. * ms1/startup-64-001.S: New. * ms1/stat.c: New. * ms1/time.c: New. * ms1/times.c: New. * ms1/trap.h: New. * ms1/trap.S: New. * ms1/unlink.c: New. * ms1/utime.c: New. * ms1/write.c: New.
379 lines
8.8 KiB
ArmAsm
379 lines
8.8 KiB
ArmAsm
/*
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* $Header$
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*
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* interrupt_vectors.s -- the interrupt handler jump table.
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*
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*
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* There are a total of 32 interrupt vector possible, however, only
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* 11 of those are currently used (the others are reserved). The
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* order of vectors is as follows:
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*
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* 1. Boot Vector. Vector for power-on/reset.
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* 2. Software Vector. Vector for handling the SI instruction (an
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* explicit interrupt caused by software).
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* 3. Break Vector. Vector for handling the Break instruction.
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* 4. Device 0 Vector. Service vector for device zero.
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* 5. Device 1 Vector. Service vector for device one.
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* 6. Device 2 Vector. Service vector for device two.
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* 7. Device 3 Vector. Service vector for device three.
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* 8. Device 4 Vector. Service vector for device four.
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* 9. Device 5 Vector. Service vector for device five.
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* 10. Device 6 Vector. Service vector for device six.
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* 11. Device 7 Vector. Service vector for device seven.
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*
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* The rest of the interrupt vectors are reserved for future use.
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*
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*
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* Each jump table entry consists of the following two instructions:
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*
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* jmp Label ; Label as appropriate
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* nop ; implemented as or r0,r0,r0
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*
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* The following labels are reserved for the vectors named above,
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* respectively:
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*
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* _BOOTIVEC, _SOFTIVEC, _BRKIVEC, _DEV0IVEC, _DEV1IVEC, _DEV2IVEC,
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* _DEV3IVEC, _DEV4IVEC, _DEV5IVEC, _DEV6IVEC, _DEV7IVEC
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*
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*
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* 26Sep01 (DJK) The memory map is changed and the device interrupts are
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* now memory-mapped.
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*
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* 10Oct01 (DJK) The memory map is finalized and the first 4K of address
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* space is now reserved for memory-mapped I/O devices.
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* (There is over 2K unused, reserved space in this area.)
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*
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* 27Jul02 (DJK) Fixed the address for the interrupt mask register. Old
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* documentation stated the port address as 0x140, but
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* the implementation uses 0x13c.
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*
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* 30Jul02 (DJK) Added support for printf. This only supports output to
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* stderr and stdout. Using the message box interface,
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* a (newly defined) message or series of messages is
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* passed to the controller to output bytes as text to
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* the debug console. These messages are constructed in
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* the interrupt handler for the SI instruction.
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* With this implementation, the user is unable to
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* utilize the message box interface in applications as
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* specialized interrupt handlers for the external
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* interrupts are necessary.
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*
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*
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*
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* Copyright (c) 2001, 2002, 2003, 2004 Morpho Technologies, Inc.
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*
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*/
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.section .startup, "a", @progbits
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.global __boot_start
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_INTERRUPT_VECTOR_TABLE:
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__boot_start:
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jmp _BOOTIVEC ; Boot vector
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or r0, r0, r0
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jmp _SOFTIVEC ; Vector for SI instruction
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or r0,r0,r0
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jmp _BRKIVEC ; Vector for Break instruction
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or r0,r0,r0
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; This is the memory-mapped I/O region.
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; Hardware Interrupt Registers
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.org 0x100
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.global _DEV0_INTERRUPT_REG
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_DEV0_INTERRUPT_REG:
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.word 0x00000000
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.global _DEV1_INTERRUPT_REG
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_DEV1_INTERRUPT_REG:
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.word 0x00000000
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.global _DEV2_INTERRUPT_REG
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_DEV2_INTERRUPT_REG:
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.word 0x00000000
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.global _DEV3_INTERRUPT_REG
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_DEV3_INTERRUPT_REG:
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.word 0x00000000
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.global _DEV4_INTERRUPT_REG
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_DEV4_INTERRUPT_REG:
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.word 0x00000000
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.global _DEV5_INTERRUPT_REG
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_DEV5_INTERRUPT_REG:
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.word 0x00000000
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.global _DEV6_INTERRUPT_REG
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_DEV6_INTERRUPT_REG:
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.word 0x00000000
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.global _DEV7_INTERRUPT_REG
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_DEV7_INTERRUPT_REG:
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.word 0x00000000
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; 60 bytes minus eight registers (four bytes per register)
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.fill (60 - 8 * 4)
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.global _INTERRUPT_MASK_REG
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_INTERRUPT_MASK_REG:
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.word 0x00000000
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; 256 bytes minus sixteen registers (four bytes per register)
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.fill (256 - 16 * 4)
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.org 0x200
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; MorphoSys Decoder Registers
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.global _MS_DEC_AUTO_INCREMENT_REG
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_MS_DEC_AUTO_INCREMENT_REG:
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.word 0x00000000
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.global _MS_DEC_SKIP_FACTOR_REG
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_MS_DEC_SKIP_FACTOR_REG:
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.word 0x00000000
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.global _MS_DEC_CUSTOM_PERMUTATION_REG
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_MS_DEC_CUSTOM_PERMUTATION_REG:
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.word 0x00000000
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.global _MS_DEC_CONTEXT_BASE_REG
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_MS_DEC_CONTEXT_BASE_REG:
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.word 0x00000000
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.global _MS_DEC_LOOKUP_TABLE_BASE_REG
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_MS_DEC_LOOKUP_TABLE_BASE_REG:
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.word 0x00000000
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.global _MS_CIRCULAR_BUFFER_END_REG
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_MS_CIRCULAR_BUFFER_END_REG:
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.word (__FRAME_BUFFER_END)
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.global _MS_CIRCULAR_BUFFER_SIZE_REG
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_MS_CIRCULAR_BUFFER_SIZE_REG:
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.word __FRAME_BUFFER_SIZE
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.global _MS_DATA_BLOCK_END_REG
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_MS_DATA_BLOCK_END_REG:
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.word 0x00000000
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.global _MS_DATA_BLOCK_SIZE_REG
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_MS_DATA_BLOCK_SIZE_REG:
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.word 0x00000000
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; 256 bytes minus nine registers (four bytes per register)
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.fill (256 - 9 * 4)
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.org 0x300
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; Debug Registers
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.global _DEBUG_HALT_REG
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_DEBUG_HALT_REG:
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.word 0x00000000
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.global _DEBUG_BREAK_REG
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_DEBUG_BREAK_REG:
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.word 0x00000000
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.global _DEBUG_HW_RESERVED0_REG
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_DEBUG_HW_RESERVED0_REG:
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.word 0x00000000
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.global _DEBUG_HW_RESERVED1_REG
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_DEBUG_HW_RESERVED1_REG:
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.word 0x00000000
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.global _DEBUG_HW_RESERVED2_REG
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_DEBUG_HW_RESERVED2_REG:
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.word 0x00000000
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.global _DEBUG_HW_RESERVED3_REG
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_DEBUG_HW_RESERVED3_REG:
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.word 0x00000000
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.global _DEBUG_HW_RESERVED4_REG
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_DEBUG_HW_RESERVED4_REG:
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.word 0x00000000
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.global _DEBUG_SW_SYSREQ_REG
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_DEBUG_SW_SYSREQ_REG:
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.word 0x00000000
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; 256 bytes minus eight registers (four bytes per register)
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.fill (256 - 8 * 4)
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.org 0x400
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; Sequence Generator Registers
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_SEQ_GEN_REGS:
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.fill 256
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.org 0x500
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_RESERVED_SEQ_GEN_REGS:
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.fill 256
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.org 0x600
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.global _TIMER0_VAL_REG
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_TIMER0_VAL_REG:
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.word 0x00000000
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.global _TIMER0_CTRL_REG
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_TIMER0_CTRL_REG:
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.word 0x00000000
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.global _TIMER1_VAL_REG
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_TIMER1_VAL_REG:
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.word 0x00000000
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.global _TIMER1_CTRL_REG
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_TIMER1_CTRL_REG:
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.word 0x00000000
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.global _TIMER2_VAL_REG
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_TIMER2_VAL_REG:
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.word 0x00000000
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.global _TIMER2_CTRL_REG
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_TIMER2_CTRL_REG:
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.word 0x00000000
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; 256 bytes minus six registers (four bytes per register)
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.fill (256 - 6 * 4)
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.org 0x700
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.global _OUTPUT0_CONTROL
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_OUTPUT0_CONTROL:
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.word 0x00000000
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.global _OUTPUT1_CONTROL
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_OUTPUT1_CONTROL:
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.word 0x00000000
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.global _OUTPUT2_CONTROL
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_OUTPUT2_CONTROL:
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.word 0x00000000
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.global _OUTPUT3_CONTROL
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_OUTPUT3_CONTROL:
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.word 0x00000000
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.global _OUTPUT4_CONTROL
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_OUTPUT4_CONTROL:
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.word 0x00000000
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.global _OUTPUT5_CONTROL
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_OUTPUT5_CONTROL:
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.word 0x00000000
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.global _OUTPUT6_CONTROL
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_OUTPUT6_CONTROL:
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.word 0x00000000
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.global _OUTPUT7_CONTROL
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_OUTPUT7_CONTROL:
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.word 0x00000000
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; 256 bytes minus eight registers (four bytes per register)
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.fill (256 - 8 * 4)
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.org 0x800
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; Reserved memory-mapped space.
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.fill (0x1000 - 0x800)
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.text
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.equ SI_IOPORT_ADR, _DEBUG_SW_SYSREQ_REG
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.equ SI_IOPORT_BIT, 0x1
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.equ BRK_IOPORT_ADR, _DEBUG_BREAK_REG
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.equ BRK_IOPORT_BIT, 0x1
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.global _BOOTIVEC
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_BOOTIVEC:
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; Initialize the interrupt controller's interrupt vector registers
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; for devices zero through seven.
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ldui r1, #%hi16(_IVEC_DEFAULT)
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ori r1, r1, #%lo16(_IVEC_DEFAULT)
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stw r1, r0, #%lo16(_DEV0_INTERRUPT_REG)
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stw r1, r0, #%lo16(_DEV1_INTERRUPT_REG)
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stw r1, r0, #%lo16(_DEV2_INTERRUPT_REG)
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stw r1, r0, #%lo16(_DEV3_INTERRUPT_REG)
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stw r1, r0, #%lo16(_DEV4_INTERRUPT_REG)
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stw r1, r0, #%lo16(_DEV5_INTERRUPT_REG)
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stw r1, r0, #%lo16(_DEV6_INTERRUPT_REG)
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stw r1, r0, #%lo16(_DEV7_INTERRUPT_REG)
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; Jump to the beginning of the application and enable interrupts.
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jmp _start
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ei
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; Handler for the SI instruction. To perform a system call, the
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; C model uses a trapping mechanism which executes an SI instruction.
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; The Morpho Technologies simulator simply performs a branch to
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; this vector to simulate the SI instruction (this is as the hardware
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; behaves). In order to trigger the simulator that a system call
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; is needed, a write into the I/O register at address $40005 to
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; set bit #2 (0x4) is necessary.
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;
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; The above address has been changed to 0x31C and the bit number
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; is zero. (The manifest constants have been changed to reflect this.)
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;
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.global _SOFTIVEC
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_SOFTIVEC:
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; Build a frame to save registers.
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subi sp, sp, #$8
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stw r9, sp, #$4
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ldui r9, #%hi16(SI_IOPORT_ADR)
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stw r10, sp, #$0
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ori r9, r9, #%lo16(SI_IOPORT_ADR)
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ori r10, r0, #SI_IOPORT_BIT
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stw r10, r9, #$0
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; SYS_call is handled by simulator here...
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or r0, r0, r0
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ldw r10, sp, #$0
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or r0, r0, r0
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ldw r9, sp, #$4
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reti r14
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addi sp, sp, #$8
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.global _BRKIVEC
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_BRKIVEC:
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; Build a frame to save registers.
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subi sp, sp, #$8
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stw r9, sp, #$4
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ldui r9, #%hi16(BRK_IOPORT_ADR)
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stw r10, sp, #$0
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ori r9, r9, #%lo16(BRK_IOPORT_ADR)
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ori r10, r0, #BRK_IOPORT_BIT
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stw r10, r9, #$0
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or r0, r0, r0
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ldw r10, sp, #$0
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subi r15, r15, #$4 ; Backup to address of break
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ldw r9, sp, #$4
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reti r15
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addi sp, sp, #$8
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.global _IVEC_DEFAULT
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_IVEC_DEFAULT:
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reti r15
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or r0, r0, r0
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