91 lines
3.6 KiB
C
91 lines
3.6 KiB
C
/*
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* Copyright (c) 2011 ARM Ltd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _LIBGLOSS_ARM_H
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#define _LIBGLOSS_ARM_H
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#include "acle-compat.h"
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/* Checking for targets supporting only Thumb instructions (eg. ARMv6-M) or
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supporting Thumb-2 instructions, whether ARM instructions are available or
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not, is done many times in libgloss/arm. So factor it out and use
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PREFER_THUMB instead. */
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#if __thumb2__ || (__thumb__ && !__ARM_ARCH_ISA_ARM)
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# define PREFER_THUMB
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#endif
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/* Processor only capable of executing Thumb-1 instructions. */
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#if __ARM_ARCH_ISA_THUMB == 1 && !__ARM_ARCH_ISA_ARM
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# define THUMB1_ONLY
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#endif
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/* M profile architectures. This is a different set of architectures than
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those not having ARM ISA because it does not contain ARMv7. This macro is
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necessary to test which architectures use bkpt as semihosting interface from
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architectures using svc. */
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#if !__ARM_ARCH_ISA_ARM && !__ARM_ARCH_7__
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# define THUMB_VXM
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#endif
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/* Defined if this target supports the BLX Rm instruction. */
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#if !defined(__ARM_ARCH_2__) \
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&& !defined(__ARM_ARCH_3__) \
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&& !defined(__ARM_ARCH_3M__) \
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&& !defined(__ARM_ARCH_4__) \
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&& !defined(__ARM_ARCH_4T__)
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# define HAVE_CALL_INDIRECT
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#endif
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/* A and R profiles (and legacy Arm).
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Current Program Status Register (CPSR)
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M[4:0] Mode bits. M[4] is always 1 for 32-bit modes.
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T[5] 1: Thumb, 0: ARM instruction set
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F[6] 1: disables FIQ
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I[7] 1: disables IRQ
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A[8] 1: disables imprecise aborts
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E[9] 0: Little-endian, 1: Big-endian
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J[24] 1: Jazelle instruction set
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*/
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#define CPSR_M_USR 0x00 /* User mode. */
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#define CPSR_M_FIQ 0x01 /* Fast Interrupt mode. */
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#define CPSR_M_IRQ 0x02 /* Interrupt mode. */
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#define CPSR_M_SVR 0x03 /* Supervisor mode. */
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#define CPSR_M_MON 0x06 /* Monitor mode. */
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#define CPSR_M_ABT 0x07 /* Abort mode. */
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#define CPSR_M_HYP 0x0A /* Hypervisor mode. */
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#define CPSR_M_UND 0x0B /* Undefined mode. */
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#define CPSR_M_SYS 0x0F /* System mode. */
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#define CPSR_M_32BIT 0x10 /* 32-bit mode. */
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#define CPSR_T_BIT 0x20 /* Thumb bit. */
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#define CPSR_F_MASK 0x40 /* FIQ bit. */
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#define CPSR_I_MASK 0x80 /* IRQ bit. */
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#define CPSR_M_MASK 0x0F /* Mode mask except M[4]. */
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#endif /* _LIBGLOSS_ARM_H */
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