193 lines
3.9 KiB
C
193 lines
3.9 KiB
C
/*
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* bdm-isv.c --
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*
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* Copyright (c) 2006 CodeSourcery Inc
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*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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*/
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/* This file contains default interrupt handlers code for the
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interrupt vector. All but one of the interrupts are user
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replaceable.
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These interrupt handlers are entered whenever the associated
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interrupt occurs. All they do is stop the debugger to give the user
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the opportunity to determine where the problem was.
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User trap BDM_TRAPNUM (15) is used for semi hosting support.
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If you replace this one, semihosting will cease to function. */
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/* Each ISR is a loop containing a halt instruction */
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#define ISR_DEFINE(NAME) \
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void __attribute__((interrupt_handler)) NAME (void) \
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{ \
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while (1) \
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__asm__ __volatile__ ("halt" ::: "memory"); \
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} \
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struct eat_trailing_semicolon
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#if defined (L_other_interrupt)
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ISR_DEFINE (__other_interrupt);
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#endif
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#if defined (L_reset)
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ISR_DEFINE (__reset);
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#endif
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#if defined (L_access_error)
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ISR_DEFINE (__access_error);
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#endif
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#if defined (L_address_error)
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ISR_DEFINE (__address_error);
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#endif
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#if defined (L_illegal_instruction)
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ISR_DEFINE (__illegal_instruction);
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#endif
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#if defined (L_divide_by_zero)
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ISR_DEFINE (__divide_by_zero);
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#endif
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#if defined (L_privilege_violation)
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ISR_DEFINE (__privilege_violation);
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#endif
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#if defined (L_trace)
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ISR_DEFINE (__trace);
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#endif
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#if defined (L_unimplemented_line_a_opcode)
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ISR_DEFINE (__unimplemented_line_a_opcode);
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#endif
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#if defined (L_unimplemented_line_f_opcode)
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ISR_DEFINE (__unimplemented_line_f_opcode);
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#endif
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#if defined (L_non_pc_breakpoint_debug_interrupt)
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ISR_DEFINE (__non_pc_breakpoint_debug_interrupt);
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#endif
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#if defined (L_pc_breakpoint_debug_interrupt)
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ISR_DEFINE (__pc_breakpoint_debug_interrupt);
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#endif
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#if defined (L_format_error)
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ISR_DEFINE (__format_error);
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#endif
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#if defined (L_spurious_interrupt)
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ISR_DEFINE (__spurious_interrupt);
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#endif
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#if defined (L_trap0)
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ISR_DEFINE (__trap0);
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#endif
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#if defined (L_trap1)
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ISR_DEFINE (__trap1);
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#endif
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#if defined (L_trap2)
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ISR_DEFINE (__trap2);
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#endif
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#if defined (L_trap3)
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ISR_DEFINE (__trap3);
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#endif
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#if defined (L_trap4)
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ISR_DEFINE (__trap4);
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#endif
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#if defined (L_trap5)
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ISR_DEFINE (__trap5);
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#endif
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#if defined (L_trap6)
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ISR_DEFINE (__trap6);
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#endif
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#if defined (L_trap7)
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ISR_DEFINE (__trap7);
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#endif
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#if defined (L_trap8)
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ISR_DEFINE (__trap8);
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#endif
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#if defined (L_trap9)
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ISR_DEFINE (__trap9);
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#endif
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#if defined (L_trap10)
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ISR_DEFINE (__trap10);
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#endif
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#if defined (L_trap11)
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ISR_DEFINE (__trap11);
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#endif
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#if defined (L_trap12)
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ISR_DEFINE (__trap12);
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#endif
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#if defined (L_trap13)
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ISR_DEFINE (__trap13);
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#endif
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#if defined (L_trap14)
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ISR_DEFINE (__trap14);
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#endif
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#if defined (L_trap15)
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ISR_DEFINE (__trap15);
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#endif
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#if defined (L_fp_branch_unordered)
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ISR_DEFINE (__fp_branch_unordered);
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#endif
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#if defined (L_fp_inexact_result)
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ISR_DEFINE (__fp_inexact_result);
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#endif
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#if defined (L_fp_divide_by_zero)
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ISR_DEFINE (__fp_divide_by_zero);
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#endif
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#if defined (L_fp_underflow)
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ISR_DEFINE (__fp_underflow);
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#endif
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#if defined (L_fp_operand_error)
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ISR_DEFINE (__fp_operand_error);
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#endif
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#if defined (L_fp_overflow)
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ISR_DEFINE (__fp_overflow);
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#endif
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#if defined (L_fp_input_not_a_number)
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ISR_DEFINE (__fp_input_not_a_number);
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#endif
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#if defined (L_fp_input_denormalized_number)
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ISR_DEFINE (__fp_input_denormalized_number);
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#endif
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#if defined (L_unsupported_instruction)
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ISR_DEFINE (__unsupported_instruction);
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#endif
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