18b47e05d3
While running tests on internal systems, we identified an issue in the startup code for newlib on AArch32 systems with Multiprocessor Extensions to the architecture. The issue is we were configuring page table flags to be Inner cacheable/Outer non-cacheable, while for at least architectures with Multiprocessor Extension, we'd configure it to Inner/Outer write-back, no write-allocate, and cacheable. The attached patch fixes this, and no regression on arm-none-eabi bare-metal tests. Adopted suggestion given by Richard offline to avoid using jump. libgloss/ * arm/cpu-init/rdimon-aem.S: Set TTBR0 to inner/outer cacheable WB, and no allocate on WB for arch with multiprocessor extension. |
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.. | ||
aarch64 | ||
arc | ||
arm | ||
bfin | ||
config | ||
cr16 | ||
cris | ||
crx | ||
d30v | ||
doc | ||
epiphany | ||
fr30 | ||
frv | ||
ft32 | ||
hp74x | ||
i386 | ||
i960 | ||
iq2000 | ||
libnosys | ||
lm32 | ||
m32c | ||
m32r | ||
m68hc11 | ||
m68k | ||
mcore | ||
mep | ||
microblaze | ||
mips | ||
mn10200 | ||
mn10300 | ||
moxie | ||
msp430 | ||
mt | ||
nds32 | ||
or1k | ||
pa | ||
rl78 | ||
rs6000 | ||
rx | ||
sh | ||
sparc | ||
sparc_leon | ||
spu | ||
testsuite | ||
tic6x | ||
v850 | ||
visium | ||
wince | ||
xc16x | ||
xstormy16 | ||
acinclude.m4 | ||
aclocal.m4 | ||
ChangeLog | ||
ChangeLog-2015 | ||
close.c | ||
configure | ||
configure.in | ||
debug.c | ||
debug.h | ||
fstat.c | ||
getpid.c | ||
glue.h | ||
isatty.c | ||
kill.c | ||
lseek.c | ||
Makefile.in | ||
open.c | ||
print.c | ||
putnum.c | ||
read.c | ||
README | ||
sbrk.c | ||
stat.c | ||
syscall.h | ||
unlink.c | ||
write.c |
bfin - Analog Devices Blackfin processor. sparc - Fujitsu Sparclite board. Works on the ex930, ex931, ex933 hp74x - Hewlett Packard HP742 board. Also some support for the hp743. m68hc11 - Motorola 68HC11 or 68HC12 support. m68k - Motorola MVME135 and IDP board. For CPU32 systems. mep - Toshiba Media Processor. pa - WinBond and Oki boards with a PA. mips - R3000 support. Array Tech LSI33k based RAID disk controller. lm32 - Lattice Mico32 simulator. epiphany - Adapteva Epiphany multicore processor. or1k - OpenRISC 1000 processor.