17725 lines
1.5 MiB
17725 lines
1.5 MiB
/*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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*/
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/* ================================================================================
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Project : ADSP-BF606
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File : defBF606.h
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Description : Register Definitions
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Date : 06-07-2012
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Tag : BF60X_TOOLS_CCES_1_0_1
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Copyright (c) 2011-2012 Analog Devices, Inc. All Rights Reserved.
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This software is proprietary and confidential to Analog Devices, Inc. and
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its licensors.
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This file was auto-generated. Do not make local changes to this file.
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================================================================================ */
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#ifndef _DEF_BF606_H
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#define _DEF_BF606_H
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#if defined (_MISRA_RULES)
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#pragma diag(push)
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#pragma diag(suppress:misra_rule_19_7:"ADI header allows function-like macros")
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#pragma diag(suppress:misra_rule_19_13:"ADI headers can use the # and ## preprocessor operators")
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#endif /* _MISRA_RULES */
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/* do not add casts to literal constants in assembly code */
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#if defined(_LANGUAGE_ASM) || defined(__ASSEMBLER__)
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#define _ADI_MSK( mask, type ) (mask) /* Make a bitmask */
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#else
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#define _ADI_MSK( mask, type ) ((type)(mask)) /* Make a bitmask */
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#endif
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#ifdef _MISRA_RULES
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#pragma diag(pop)
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#endif /* _MISRA_RULES */
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#ifndef __ADI_GENERATED_DEF_HEADERS__
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#define __ADI_GENERATED_DEF_HEADERS__ 1
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#endif
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/* MMR modules defined for the ADSP-BF606 */
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#define __ADI_HAS_SYS__ 1
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#define __ADI_HAS_SIMENV__ 1
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#define __ADI_HAS_CNT__ 1
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#define __ADI_HAS_RSI__ 1
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#define __ADI_HAS_CAN__ 1
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#define __ADI_HAS_LP__ 1
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#define __ADI_HAS_TIMER__ 1
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#define __ADI_HAS_CRC__ 1
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#define __ADI_HAS_TWI__ 1
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#define __ADI_HAS_UART__ 1
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#define __ADI_HAS_PORT__ 1
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#define __ADI_HAS_PADS__ 1
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#define __ADI_HAS_PINT__ 1
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#define __ADI_HAS_SMC__ 1
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#define __ADI_HAS_WDOG__ 1
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#define __ADI_HAS_EPPI__ 1
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#define __ADI_HAS_PWM__ 1
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#define __ADI_HAS_VID__ 1
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#define __ADI_HAS_SWU__ 1
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#define __ADI_HAS_SDU__ 1
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#define __ADI_HAS_EMAC__ 1
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#define __ADI_HAS_SPORT__ 1
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#define __ADI_HAS_SPI__ 1
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#define __ADI_HAS_DMA__ 1
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#define __ADI_HAS_ACM__ 1
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#define __ADI_HAS_DMC__ 1
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#define __ADI_HAS_SCB__ 1
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#define __ADI_HAS_L2CTL__ 1
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#define __ADI_HAS_SEC__ 1
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#define __ADI_HAS_TRU__ 1
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#define __ADI_HAS_RCU__ 1
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#define __ADI_HAS_SPU__ 1
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#define __ADI_HAS_CGU__ 1
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#define __ADI_HAS_DPM__ 1
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#define __ADI_HAS_EFS__ 1
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#define __ADI_HAS_USB__ 1
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#define __ADI_HAS_L1DM__ 1
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#define __ADI_HAS_L1IM__ 1
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#define __ADI_HAS_ICU__ 1
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#define __ADI_HAS_TMR__ 1
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#define __ADI_HAS_DBG__ 1
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#define __ADI_HAS_TB__ 1
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#define __ADI_HAS_WP__ 1
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#define __ADI_HAS_PF__ 1
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/* =========================
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REGFILE
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========================= */
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/* ------------------------------------------------------------------------------------------------------------------------
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ASTAT Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_ASTAT_VS 25 /* Sticky version of ASTAT_V */
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#define BITP_ASTAT_V 24 /* Overflow Flag */
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#define BITP_ASTAT_AV1S 19 /* Sticky Overflow Flag 1 */
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#define BITP_ASTAT_AV1 18 /* Overflow Flag 1 */
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#define BITP_ASTAT_AV0S 17 /* Sticky Overflow Flag 0 */
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#define BITP_ASTAT_AV0 16 /* Overflow Flag 0 */
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#define BITP_ASTAT_AC1 13 /* Carry Flag 1 */
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#define BITP_ASTAT_AC0 12 /* Carry Flag 0 */
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#define BITP_ASTAT_RND_MOD 8 /* Rounding Mode */
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#define BITP_ASTAT_AQ 6 /* Quotient Bit */
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#define BITP_ASTAT_CC 5 /* Condition Code */
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#define BITP_ASTAT_V_COPY 3 /* Overflow Flag */
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#define BITP_ASTAT_AC0_COPY 2 /* Carry Flag 0 */
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#define BITP_ASTAT_AN 1 /* Negative Flag */
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#define BITP_ASTAT_AZ 0 /* Zero Flag */
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#define BITM_ASTAT_VS (_ADI_MSK(0x02000000,uint32_t)) /* Sticky version of ASTAT_V */
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#define BITM_ASTAT_V (_ADI_MSK(0x01000000,uint32_t)) /* Overflow Flag */
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#define BITM_ASTAT_AV1S (_ADI_MSK(0x00080000,uint32_t)) /* Sticky Overflow Flag 1 */
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#define BITM_ASTAT_AV1 (_ADI_MSK(0x00040000,uint32_t)) /* Overflow Flag 1 */
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#define BITM_ASTAT_AV0S (_ADI_MSK(0x00020000,uint32_t)) /* Sticky Overflow Flag 0 */
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#define BITM_ASTAT_AV0 (_ADI_MSK(0x00010000,uint32_t)) /* Overflow Flag 0 */
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#define BITM_ASTAT_AC1 (_ADI_MSK(0x00002000,uint32_t)) /* Carry Flag 1 */
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#define BITM_ASTAT_AC0 (_ADI_MSK(0x00001000,uint32_t)) /* Carry Flag 0 */
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#define BITM_ASTAT_RND_MOD (_ADI_MSK(0x00000100,uint32_t)) /* Rounding Mode */
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#define BITM_ASTAT_AQ (_ADI_MSK(0x00000040,uint32_t)) /* Quotient Bit */
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#define BITM_ASTAT_CC (_ADI_MSK(0x00000020,uint32_t)) /* Condition Code */
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#define BITM_ASTAT_V_COPY (_ADI_MSK(0x00000008,uint32_t)) /* Overflow Flag */
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#define BITM_ASTAT_AC0_COPY (_ADI_MSK(0x00000004,uint32_t)) /* Carry Flag 0 */
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#define BITM_ASTAT_AN (_ADI_MSK(0x00000002,uint32_t)) /* Negative Flag */
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#define BITM_ASTAT_AZ (_ADI_MSK(0x00000001,uint32_t)) /* Zero Flag */
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/* ------------------------------------------------------------------------------------------------------------------------
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LT Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_LT_ADDR 1 /* Loop Top Address */
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#define BITP_LT_LSB 0
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#define BITM_LT_ADDR (_ADI_MSK(0xFFFFFFFE,uint32_t)) /* Loop Top Address */
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#define BITM_LT_LSB (_ADI_MSK(0x00000001,uint32_t))
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/* ------------------------------------------------------------------------------------------------------------------------
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SEQSTAT Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_SEQSTAT_NSPECABT 19 /* Nonspeculative access was aborted */
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#define BITP_SEQSTAT_HWERRCAUSE 14 /* Holds cause of last hardware error generated by the core */
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#define BITP_SEQSTAT_SFTRESET 13 /* Indicates whether the last reset was a software reset */
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#define BITP_SEQSTAT_ITESTABT 12 /* ITEST_COMMAND was aborted */
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#define BITP_SEQSTAT_DTESTABT 11 /* DTEST_COMMAND was aborted */
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#define BITP_SEQSTAT_SYSNMI 10 /* System NMI Input Active */
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#define BITP_SEQSTAT_PEIC 9 /* Parity Error on Instruction L1 Read for Core */
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#define BITP_SEQSTAT_PEDC 8 /* Parity Error on Data L1 Read for Core */
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#define BITP_SEQSTAT_PEIX 7 /* Parity Error on Instruction L1 Read for L2 Transfer */
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#define BITP_SEQSTAT_PEDX 6 /* Parity Error on Data L1 Read for L2 Transfer */
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#define BITP_SEQSTAT_EXCAUSE 0 /* Holds cause of last-executed exception */
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#define BITM_SEQSTAT_NSPECABT (_ADI_MSK(0x00080000,uint32_t)) /* Nonspeculative access was aborted */
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#define BITM_SEQSTAT_HWERRCAUSE (_ADI_MSK(0x0007C000,uint32_t)) /* Holds cause of last hardware error generated by the core */
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#define BITM_SEQSTAT_SFTRESET (_ADI_MSK(0x00002000,uint32_t)) /* Indicates whether the last reset was a software reset */
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#define BITM_SEQSTAT_ITESTABT (_ADI_MSK(0x00001000,uint32_t)) /* ITEST_COMMAND was aborted */
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#define BITM_SEQSTAT_DTESTABT (_ADI_MSK(0x00000800,uint32_t)) /* DTEST_COMMAND was aborted */
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#define BITM_SEQSTAT_SYSNMI (_ADI_MSK(0x00000400,uint32_t)) /* System NMI Input Active */
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#define BITM_SEQSTAT_PEIC (_ADI_MSK(0x00000200,uint32_t)) /* Parity Error on Instruction L1 Read for Core */
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#define BITM_SEQSTAT_PEDC (_ADI_MSK(0x00000100,uint32_t)) /* Parity Error on Data L1 Read for Core */
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#define BITM_SEQSTAT_PEIX (_ADI_MSK(0x00000080,uint32_t)) /* Parity Error on Instruction L1 Read for L2 Transfer */
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#define BITM_SEQSTAT_PEDX (_ADI_MSK(0x00000040,uint32_t)) /* Parity Error on Data L1 Read for L2 Transfer */
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#define BITM_SEQSTAT_EXCAUSE (_ADI_MSK(0x0000003F,uint32_t)) /* Holds cause of last-executed exception */
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#define ENUM_SEQSTAT_EXINST (_ADI_MSK(0x00000000,uint32_t)) /* EXCAUSE: EXCPT Instruction */
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#define ENUM_SEQSTAT_SSTEP (_ADI_MSK(0x00000010,uint32_t)) /* EXCAUSE: Single Step */
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#define ENUM_SEQSTAT_EMUTROV (_ADI_MSK(0x00000011,uint32_t)) /* EXCAUSE: Trace Buffer */
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#define ENUM_SEQSTAT_UNDEFINST (_ADI_MSK(0x00000021,uint32_t)) /* EXCAUSE: Undefined Instruction */
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#define ENUM_SEQSTAT_ILLCOMB (_ADI_MSK(0x00000022,uint32_t)) /* EXCAUSE: Illegal Combination */
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#define ENUM_SEQSTAT_DAGPROTVIOL (_ADI_MSK(0x00000023,uint32_t)) /* EXCAUSE: DAG Protection Violation */
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#define ENUM_SEQSTAT_DAGALGN (_ADI_MSK(0x00000024,uint32_t)) /* EXCAUSE: DAG Misaligned Access */
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#define ENUM_SEQSTAT_UNRECOVER (_ADI_MSK(0x00000025,uint32_t)) /* EXCAUSE: Unrecoverable Event */
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#define ENUM_SEQSTAT_DAGCPLBMISS (_ADI_MSK(0x00000026,uint32_t)) /* EXCAUSE: DAG CPLB Miss */
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#define ENUM_SEQSTAT_DAGMCPLBH (_ADI_MSK(0x00000027,uint32_t)) /* EXCAUSE: DAG Multiple CPLB Hits */
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#define ENUM_SEQSTAT_EMUWPMATCH (_ADI_MSK(0x00000028,uint32_t)) /* EXCAUSE: Watchpoint Match */
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#define ENUM_SEQSTAT_IFALGN (_ADI_MSK(0x0000002A,uint32_t)) /* EXCAUSE: I-Fetch Misaligned Access */
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#define ENUM_SEQSTAT_IFPROTVIOL (_ADI_MSK(0x0000002B,uint32_t)) /* EXCAUSE: I-Fetch Protection Violation */
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#define ENUM_SEQSTAT_IFCPLBMISS (_ADI_MSK(0x0000002C,uint32_t)) /* EXCAUSE: I-Fetch CPLB Miss */
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#define ENUM_SEQSTAT_IFMCPLBH (_ADI_MSK(0x0000002D,uint32_t)) /* EXCAUSE: I-Fetch Multiple CPLB Hits */
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#define ENUM_SEQSTAT_PROTVIOL (_ADI_MSK(0x0000002E,uint32_t)) /* EXCAUSE: Illegal use superv. res */
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/* ------------------------------------------------------------------------------------------------------------------------
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SYSCFG Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_SYSCFG_SNEN 2 /* Self-Nesting Interrupt Enable */
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#define BITP_SYSCFG_CCEN 1 /* Enable cycle counter */
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#define BITP_SYSCFG_SSSTEP 0 /* Supervisor single step */
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#define BITM_SYSCFG_SNEN (_ADI_MSK(0x00000004,uint32_t)) /* Self-Nesting Interrupt Enable */
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#define BITM_SYSCFG_CCEN (_ADI_MSK(0x00000002,uint32_t)) /* Enable cycle counter */
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#define BITM_SYSCFG_SSSTEP (_ADI_MSK(0x00000001,uint32_t)) /* Supervisor single step */
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/* ==================================================
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CNT Registers
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================================================== */
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/* =========================
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CNT0
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========================= */
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#define REG_CNT0_CFG 0xFFC00400 /* CNT0 Configuration Register */
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#define REG_CNT0_IMSK 0xFFC00404 /* CNT0 Interrupt Mask Register */
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#define REG_CNT0_STAT 0xFFC00408 /* CNT0 Status Register */
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#define REG_CNT0_CMD 0xFFC0040C /* CNT0 Command Register */
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#define REG_CNT0_DEBNCE 0xFFC00410 /* CNT0 Debounce Register */
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#define REG_CNT0_CNTR 0xFFC00414 /* CNT0 Counter Register */
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#define REG_CNT0_MAX 0xFFC00418 /* CNT0 Maximum Count Register */
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#define REG_CNT0_MIN 0xFFC0041C /* CNT0 Minimum Count Register */
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/* =========================
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CNT
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========================= */
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/* ------------------------------------------------------------------------------------------------------------------------
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CNT_CFG Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_CNT_CFG_INPDIS 15 /* CUD and CDG Pin Input Disable */
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#define BITP_CNT_CFG_BNDMODE 12 /* Boundary Register Mode */
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#define BITP_CNT_CFG_ZMZC 11 /* CZM Zeroes Counter Enable */
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#define BITP_CNT_CFG_CNTMODE 8 /* Counter Operating Mode */
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#define BITP_CNT_CFG_CZMINV 6 /* CZM Pin Polarity Invert */
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#define BITP_CNT_CFG_CUDINV 5 /* CUD Pin Polarity Invert */
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#define BITP_CNT_CFG_CDGINV 4 /* CDG Pin Polarity Invert */
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#define BITP_CNT_CFG_DEBEN 1 /* Debounce Enable */
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#define BITP_CNT_CFG_EN 0 /* Counter Enable */
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#define BITM_CNT_CFG_INPDIS (_ADI_MSK(0x00008000,uint16_t)) /* CUD and CDG Pin Input Disable */
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#define ENUM_CNT_CFG_NO_INPDIS (_ADI_MSK(0x00000000,uint16_t)) /* INPDIS: Enable */
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#define ENUM_CNT_CFG_INPDIS (_ADI_MSK(0x00008000,uint16_t)) /* INPDIS: Pin Input Disable */
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#define BITM_CNT_CFG_BNDMODE (_ADI_MSK(0x00003000,uint16_t)) /* Boundary Register Mode */
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#define ENUM_CNT_CFG_BNDMODE_BNDCOMP (_ADI_MSK(0x00000000,uint16_t)) /* BNDMODE: BND_COMP */
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#define ENUM_CNT_CFG_BNDMODE_BINENC (_ADI_MSK(0x00001000,uint16_t)) /* BNDMODE: BIN_ENC */
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#define ENUM_CNT_CFG_BNDMODE_BNDCAPT (_ADI_MSK(0x00002000,uint16_t)) /* BNDMODE: BND_CAPT */
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#define ENUM_CNT_CFG_BNDMODE_BNDAEXT (_ADI_MSK(0x00003000,uint16_t)) /* BNDMODE: BND_AEXT */
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#define BITM_CNT_CFG_ZMZC (_ADI_MSK(0x00000800,uint16_t)) /* CZM Zeroes Counter Enable */
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#define ENUM_CNT_CFG_ZMZC_DIS (_ADI_MSK(0x00000000,uint16_t)) /* ZMZC: Disable */
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#define ENUM_CNT_CFG_ZMZC_EN (_ADI_MSK(0x00000800,uint16_t)) /* ZMZC: Enable */
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#define BITM_CNT_CFG_CNTMODE (_ADI_MSK(0x00000700,uint16_t)) /* Counter Operating Mode */
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#define ENUM_CNT_CFG_CNTMODE_QUADENC (_ADI_MSK(0x00000000,uint16_t)) /* CNTMODE: QUAD_ENC */
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#define ENUM_CNT_CFG_CNTMODE_BINENC (_ADI_MSK(0x00000100,uint16_t)) /* CNTMODE: BIN_ENC */
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#define ENUM_CNT_CFG_CNTMODE_UDCNT (_ADI_MSK(0x00000200,uint16_t)) /* CNTMODE: UD_CNT */
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#define ENUM_CNT_CFG_CNTMODE_DIRCNT (_ADI_MSK(0x00000400,uint16_t)) /* CNTMODE: DIR_CNT */
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#define ENUM_CNT_CFG_CNTMODE_DIRTMR (_ADI_MSK(0x00000500,uint16_t)) /* CNTMODE: DIR_TMR */
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#define BITM_CNT_CFG_CZMINV (_ADI_MSK(0x00000040,uint16_t)) /* CZM Pin Polarity Invert */
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#define ENUM_CNT_CFG_CZMINV_AHI (_ADI_MSK(0x00000000,uint16_t)) /* CZMINV: Active High, Rising Edge */
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#define ENUM_CNT_CFG_CZMINV_ALO (_ADI_MSK(0x00000040,uint16_t)) /* CZMINV: Active Low, Falling Edge */
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#define BITM_CNT_CFG_CUDINV (_ADI_MSK(0x00000020,uint16_t)) /* CUD Pin Polarity Invert */
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#define ENUM_CNT_CFG_CUDINV_AHI (_ADI_MSK(0x00000000,uint16_t)) /* CUDINV: Active High, Rising Edge */
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#define ENUM_CNT_CFG_CUDINV_ALO (_ADI_MSK(0x00000020,uint16_t)) /* CUDINV: Active Low, Falling Edge */
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#define BITM_CNT_CFG_CDGINV (_ADI_MSK(0x00000010,uint16_t)) /* CDG Pin Polarity Invert */
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#define ENUM_CNT_CFG_CDGINV_AHI (_ADI_MSK(0x00000000,uint16_t)) /* CDGINV: Active High, Rising Edge */
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#define ENUM_CNT_CFG_CDGINV_ALO (_ADI_MSK(0x00000010,uint16_t)) /* CDGINV: Active Low, Falling Edge */
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#define BITM_CNT_CFG_DEBEN (_ADI_MSK(0x00000002,uint16_t)) /* Debounce Enable */
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#define ENUM_CNT_CFG_DEBDIS (_ADI_MSK(0x00000000,uint16_t)) /* DEBEN: Disable */
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#define ENUM_CNT_CFG_DEBEN (_ADI_MSK(0x00000002,uint16_t)) /* DEBEN: Enable */
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#define BITM_CNT_CFG_EN (_ADI_MSK(0x00000001,uint16_t)) /* Counter Enable */
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#define ENUM_CNT_CFG_CNTDIS (_ADI_MSK(0x00000000,uint16_t)) /* EN: Counter Disable */
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#define ENUM_CNT_CFG_CNTEN (_ADI_MSK(0x00000001,uint16_t)) /* EN: Counter Enable */
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/* ------------------------------------------------------------------------------------------------------------------------
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CNT_IMSK Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_CNT_IMSK_CZMZ 10 /* Counter Zeroed by Zero Marker Interrupt Enable */
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#define BITP_CNT_IMSK_CZME 9 /* Zero Marker Error Interrupt Enable */
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#define BITP_CNT_IMSK_CZM 8 /* CZM Pin / Pushbutton Interrupt Enable */
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#define BITP_CNT_IMSK_CZERO 7 /* CNT_CNTR Counts To Zero Interrupt Enable */
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#define BITP_CNT_IMSK_COV15 6 /* Bit 15 Overflow Interrupt Enable */
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#define BITP_CNT_IMSK_COV31 5 /* Bit 31 Overflow Interrupt Enable */
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#define BITP_CNT_IMSK_MAXC 4 /* Max Count Interrupt Enable */
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#define BITP_CNT_IMSK_MINC 3 /* Min Count Interrupt Enable */
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#define BITP_CNT_IMSK_DC 2 /* Downcount Interrupt enable */
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#define BITP_CNT_IMSK_UC 1 /* Upcount Interrupt Enable */
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#define BITP_CNT_IMSK_IC 0 /* Illegal Gray/Binary Code Interrupt Enable */
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#define BITM_CNT_IMSK_CZMZ (_ADI_MSK(0x00000400,uint16_t)) /* Counter Zeroed by Zero Marker Interrupt Enable */
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#define ENUM_CNT_IMSK_CZMZ_MSK (_ADI_MSK(0x00000000,uint16_t)) /* CZMZ: Mask Interrupt */
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#define ENUM_CNT_IMSK_CZMZ_UMSK (_ADI_MSK(0x00000400,uint16_t)) /* CZMZ: Unmask Interrupt */
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#define BITM_CNT_IMSK_CZME (_ADI_MSK(0x00000200,uint16_t)) /* Zero Marker Error Interrupt Enable */
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#define ENUM_CNT_IMSK_CZME_MSK (_ADI_MSK(0x00000000,uint16_t)) /* CZME: Mask Interrupt */
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#define ENUM_CNT_IMSK_CZME_UMSK (_ADI_MSK(0x00000200,uint16_t)) /* CZME: Unmask Interrupt */
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#define BITM_CNT_IMSK_CZM (_ADI_MSK(0x00000100,uint16_t)) /* CZM Pin / Pushbutton Interrupt Enable */
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#define ENUM_CNT_IMSK_CZM_MSK (_ADI_MSK(0x00000000,uint16_t)) /* CZM: Mask Interrupt */
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#define ENUM_CNT_IMSK_CZM_UMSK (_ADI_MSK(0x00000100,uint16_t)) /* CZM: Unmask Interrupt */
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#define BITM_CNT_IMSK_CZERO (_ADI_MSK(0x00000080,uint16_t)) /* CNT_CNTR Counts To Zero Interrupt Enable */
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#define ENUM_CNT_IMSK_CZERO_MSK (_ADI_MSK(0x00000000,uint16_t)) /* CZERO: Mask Interrupt */
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#define ENUM_CNT_IMSK_CZERO_UMSK (_ADI_MSK(0x00000080,uint16_t)) /* CZERO: Unmask Interrupt */
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#define BITM_CNT_IMSK_COV15 (_ADI_MSK(0x00000040,uint16_t)) /* Bit 15 Overflow Interrupt Enable */
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#define ENUM_CNT_IMSK_COV15_MSK (_ADI_MSK(0x00000000,uint16_t)) /* COV15: Mask Interrupt */
|
|
#define ENUM_CNT_IMSK_COV15_UMSK (_ADI_MSK(0x00000040,uint16_t)) /* COV15: Unmask Interrupt */
|
|
|
|
#define BITM_CNT_IMSK_COV31 (_ADI_MSK(0x00000020,uint16_t)) /* Bit 31 Overflow Interrupt Enable */
|
|
#define ENUM_CNT_IMSK_COV31_MSK (_ADI_MSK(0x00000000,uint16_t)) /* COV31: Mask Interrupt */
|
|
#define ENUM_CNT_IMSK_COV31_UMSK (_ADI_MSK(0x00000020,uint16_t)) /* COV31: Unmask Interrupt */
|
|
|
|
#define BITM_CNT_IMSK_MAXC (_ADI_MSK(0x00000010,uint16_t)) /* Max Count Interrupt Enable */
|
|
#define ENUM_CNT_IMSK_MAXC_MSK (_ADI_MSK(0x00000000,uint16_t)) /* MAXC: Mask Interrupt */
|
|
#define ENUM_CNT_IMSK_MAXC_UMSK (_ADI_MSK(0x00000010,uint16_t)) /* MAXC: Unmask Interrupt */
|
|
|
|
#define BITM_CNT_IMSK_MINC (_ADI_MSK(0x00000008,uint16_t)) /* Min Count Interrupt Enable */
|
|
#define ENUM_CNT_IMSK_MINC_MSK (_ADI_MSK(0x00000000,uint16_t)) /* MINC: Mask Interrupt */
|
|
#define ENUM_CNT_IMSK_MINC_UMSK (_ADI_MSK(0x00000008,uint16_t)) /* MINC: Unmask Interrupt */
|
|
|
|
#define BITM_CNT_IMSK_DC (_ADI_MSK(0x00000004,uint16_t)) /* Downcount Interrupt enable */
|
|
#define ENUM_CNT_IMSK_DC_MSK (_ADI_MSK(0x00000000,uint16_t)) /* DC: Mask Interrupt */
|
|
#define ENUM_CNT_IMSK_DC_UMSK (_ADI_MSK(0x00000004,uint16_t)) /* DC: Unmask Interrupt */
|
|
|
|
#define BITM_CNT_IMSK_UC (_ADI_MSK(0x00000002,uint16_t)) /* Upcount Interrupt Enable */
|
|
#define ENUM_CNT_IMSK_UC_MSK (_ADI_MSK(0x00000000,uint16_t)) /* UC: Mask Interrupt */
|
|
#define ENUM_CNT_IMSK_UC_UMSK (_ADI_MSK(0x00000002,uint16_t)) /* UC: Unmask Interrupt */
|
|
|
|
#define BITM_CNT_IMSK_IC (_ADI_MSK(0x00000001,uint16_t)) /* Illegal Gray/Binary Code Interrupt Enable */
|
|
#define ENUM_CNT_IMSK_IC_MSK (_ADI_MSK(0x00000000,uint16_t)) /* IC: Mask Interrupt */
|
|
#define ENUM_CNT_IMSK_IC_UMSK (_ADI_MSK(0x00000001,uint16_t)) /* IC: Unmask Interrupt */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CNT_STAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CNT_STAT_CZMZ 10 /* Counter Zeroed By Zero Marker interrupt */
|
|
#define BITP_CNT_STAT_CZME 9 /* Zero Marker Error interrupt */
|
|
#define BITP_CNT_STAT_CZM 8 /* CZM Pin/Pushbutton interrupt */
|
|
#define BITP_CNT_STAT_CZERO 7 /* CNT_CNTR Counts To Zero interrupt */
|
|
#define BITP_CNT_STAT_COV15 6 /* Bit 15 overflow interrupt */
|
|
#define BITP_CNT_STAT_COV31 5 /* Bit 31 overflow interrupt */
|
|
#define BITP_CNT_STAT_MAXC 4 /* Max interrupt */
|
|
#define BITP_CNT_STAT_MINC 3 /* Min interrupt */
|
|
#define BITP_CNT_STAT_DC 2 /* Downcount interrupt */
|
|
#define BITP_CNT_STAT_UC 1 /* Upcount interrupt */
|
|
#define BITP_CNT_STAT_IC 0 /* Illegal gray/binary code interrupt */
|
|
#define BITM_CNT_STAT_CZMZ (_ADI_MSK(0x00000400,uint16_t)) /* Counter Zeroed By Zero Marker interrupt */
|
|
#define BITM_CNT_STAT_CZME (_ADI_MSK(0x00000200,uint16_t)) /* Zero Marker Error interrupt */
|
|
#define BITM_CNT_STAT_CZM (_ADI_MSK(0x00000100,uint16_t)) /* CZM Pin/Pushbutton interrupt */
|
|
#define BITM_CNT_STAT_CZERO (_ADI_MSK(0x00000080,uint16_t)) /* CNT_CNTR Counts To Zero interrupt */
|
|
#define BITM_CNT_STAT_COV15 (_ADI_MSK(0x00000040,uint16_t)) /* Bit 15 overflow interrupt */
|
|
#define BITM_CNT_STAT_COV31 (_ADI_MSK(0x00000020,uint16_t)) /* Bit 31 overflow interrupt */
|
|
#define BITM_CNT_STAT_MAXC (_ADI_MSK(0x00000010,uint16_t)) /* Max interrupt */
|
|
#define BITM_CNT_STAT_MINC (_ADI_MSK(0x00000008,uint16_t)) /* Min interrupt */
|
|
#define BITM_CNT_STAT_DC (_ADI_MSK(0x00000004,uint16_t)) /* Downcount interrupt */
|
|
#define BITM_CNT_STAT_UC (_ADI_MSK(0x00000002,uint16_t)) /* Upcount interrupt */
|
|
#define BITM_CNT_STAT_IC (_ADI_MSK(0x00000001,uint16_t)) /* Illegal gray/binary code interrupt */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CNT_CMD Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CNT_CMD_W1ZMONCE 12 /* Write 1 Zero Marker Clear Once Enable */
|
|
#define BITP_CNT_CMD_W1LMAXMIN 10 /* Write 1 MAX copy from MIN */
|
|
#define BITP_CNT_CMD_W1LMAXCNT 9 /* Write 1 MAX capture from CNTR */
|
|
#define BITP_CNT_CMD_W1LMAXZERO 8 /* Write 1 MAX to zero */
|
|
#define BITP_CNT_CMD_W1LMINMAX 7 /* Write 1 MIN copy from MAX */
|
|
#define BITP_CNT_CMD_W1LMINCNT 5 /* Write 1 MIN capture from CNTR */
|
|
#define BITP_CNT_CMD_W1LMINZERO 4 /* Write 1 MIN to zero */
|
|
#define BITP_CNT_CMD_W1LCNTMAX 3 /* Write 1 CNTR load from MAX */
|
|
#define BITP_CNT_CMD_W1LCNTMIN 2 /* Write 1 CNTR load from MIN */
|
|
#define BITP_CNT_CMD_W1LCNTZERO 0 /* Write 1 CNTR to zero */
|
|
#define BITM_CNT_CMD_W1ZMONCE (_ADI_MSK(0x00001000,uint16_t)) /* Write 1 Zero Marker Clear Once Enable */
|
|
#define BITM_CNT_CMD_W1LMAXMIN (_ADI_MSK(0x00000400,uint16_t)) /* Write 1 MAX copy from MIN */
|
|
#define BITM_CNT_CMD_W1LMAXCNT (_ADI_MSK(0x00000200,uint16_t)) /* Write 1 MAX capture from CNTR */
|
|
#define BITM_CNT_CMD_W1LMAXZERO (_ADI_MSK(0x00000100,uint16_t)) /* Write 1 MAX to zero */
|
|
#define BITM_CNT_CMD_W1LMINMAX (_ADI_MSK(0x00000080,uint16_t)) /* Write 1 MIN copy from MAX */
|
|
#define BITM_CNT_CMD_W1LMINCNT (_ADI_MSK(0x00000020,uint16_t)) /* Write 1 MIN capture from CNTR */
|
|
#define BITM_CNT_CMD_W1LMINZERO (_ADI_MSK(0x00000010,uint16_t)) /* Write 1 MIN to zero */
|
|
#define BITM_CNT_CMD_W1LCNTMAX (_ADI_MSK(0x00000008,uint16_t)) /* Write 1 CNTR load from MAX */
|
|
#define BITM_CNT_CMD_W1LCNTMIN (_ADI_MSK(0x00000004,uint16_t)) /* Write 1 CNTR load from MIN */
|
|
#define BITM_CNT_CMD_W1LCNTZERO (_ADI_MSK(0x00000001,uint16_t)) /* Write 1 CNTR to zero */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CNT_DEBNCE Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CNT_DEBNCE_DPRESCALE 0 /* Debounce Prescale */
|
|
#define BITM_CNT_DEBNCE_DPRESCALE (_ADI_MSK(0x0000001F,uint16_t)) /* Debounce Prescale */
|
|
|
|
/* ==================================================
|
|
RSI Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
RSI0
|
|
========================= */
|
|
#define REG_RSI0_CTL 0xFFC00604 /* RSI0 Control Register */
|
|
#define REG_RSI0_ARG 0xFFC00608 /* RSI0 Argument Register */
|
|
#define REG_RSI0_CMD 0xFFC0060C /* RSI0 Command Register */
|
|
#define REG_RSI0_RESP_CMD 0xFFC00610 /* RSI0 Response Command Register */
|
|
#define REG_RSI0_RESP0 0xFFC00614 /* RSI0 Response 0 Register */
|
|
#define REG_RSI0_RESP1 0xFFC00618 /* RSI0 Response 1 Register */
|
|
#define REG_RSI0_RESP2 0xFFC0061C /* RSI0 Response 2 Register */
|
|
#define REG_RSI0_RESP3 0xFFC00620 /* RSI0 Response 3 Register */
|
|
#define REG_RSI0_DATA_TMR 0xFFC00624 /* RSI0 Data Timer Register */
|
|
#define REG_RSI0_DATA_LEN 0xFFC00628 /* RSI0 Data Length Register */
|
|
#define REG_RSI0_DATA_CTL 0xFFC0062C /* RSI0 Data Control Register */
|
|
#define REG_RSI0_DATA_CNT 0xFFC00630 /* RSI0 Data Count Register */
|
|
#define REG_RSI0_XFRSTAT 0xFFC00634 /* RSI0 Status Register */
|
|
#define REG_RSI0_XFRSTAT_CLR 0xFFC00638 /* RSI0 Status Clear Register */
|
|
#define REG_RSI0_XFR_IMSK0 0xFFC0063C /* RSI0 Interrupt 0 Mask Register */
|
|
#define REG_RSI0_XFR_IMSK1 0xFFC00640 /* RSI0 Interrupt 1 Mask Register */
|
|
#define REG_RSI0_FIFO_CNT 0xFFC00648 /* RSI0 FIFO Counter Register */
|
|
#define REG_RSI0_CEATA 0xFFC0064C /* RSI0 This register contains bit to dis CCS gen */
|
|
#define REG_RSI0_BOOT_TCNTR 0xFFC00650 /* RSI0 Boot Timing Counter Register */
|
|
#define REG_RSI0_BACK_TOUT 0xFFC00654 /* RSI0 Boot Acknowledge Timeout Register */
|
|
#define REG_RSI0_SLP_WKUP_TOUT 0xFFC00658 /* RSI0 Sleep Wakeup Timeout Register */
|
|
#define REG_RSI0_BLKSZ 0xFFC0065C /* RSI0 Block Size Register */
|
|
#define REG_RSI0_FIFO 0xFFC00680 /* RSI0 Data FIFO Register */
|
|
#define REG_RSI0_STAT0 0xFFC006C0 /* RSI0 Exception Status Register */
|
|
#define REG_RSI0_IMSK0 0xFFC006C4 /* RSI0 Exception Mask Register */
|
|
#define REG_RSI0_CFG 0xFFC006C8 /* RSI0 Configuration Register */
|
|
#define REG_RSI0_RD_WAIT 0xFFC006CC /* RSI0 Read Wait Enable Register */
|
|
#define REG_RSI0_PID0 0xFFC006D0 /* RSI0 Peripheral Identification Register */
|
|
#define REG_RSI0_PID1 0xFFC006D4 /* RSI0 Peripheral Identification Register */
|
|
#define REG_RSI0_PID2 0xFFC006D8 /* RSI0 Peripheral Identification Register */
|
|
#define REG_RSI0_PID3 0xFFC006DC /* RSI0 Peripheral Identification Register */
|
|
|
|
/* =========================
|
|
RSI
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
RSI_CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RSI_CTL_CARDTYPE 13 /* Type of Card */
|
|
#define BITP_RSI_CTL_BUSWID 11 /* Wide Bus Mode Enable */
|
|
#define BITP_RSI_CTL_BYPASS 10 /* Bypass clock divisor */
|
|
#define BITP_RSI_CTL_PWRSAVE 9 /* Power Save Enable */
|
|
#define BITP_RSI_CTL_CLKEN 8 /* RSI_CLK Bus Clock Enable */
|
|
#define BITP_RSI_CTL_CLKDIV 0 /* RSI_CLK Divisor */
|
|
#define BITM_RSI_CTL_CARDTYPE (_ADI_MSK(0x0000E000,uint16_t)) /* Type of Card */
|
|
#define BITM_RSI_CTL_BUSWID (_ADI_MSK(0x00001800,uint16_t)) /* Wide Bus Mode Enable */
|
|
#define BITM_RSI_CTL_BYPASS (_ADI_MSK(0x00000400,uint16_t)) /* Bypass clock divisor */
|
|
#define BITM_RSI_CTL_PWRSAVE (_ADI_MSK(0x00000200,uint16_t)) /* Power Save Enable */
|
|
#define BITM_RSI_CTL_CLKEN (_ADI_MSK(0x00000100,uint16_t)) /* RSI_CLK Bus Clock Enable */
|
|
#define BITM_RSI_CTL_CLKDIV (_ADI_MSK(0x000000FF,uint16_t)) /* RSI_CLK Divisor */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
RSI_CMD Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RSI_CMD_CHKBUSY 12 /* Check Busy Condition */
|
|
#define BITP_RSI_CMD_CRCDIS 11 /* Disable CRC Check */
|
|
#define BITP_RSI_CMD_EN 10 /* Command Enable */
|
|
#define BITP_RSI_CMD_PNDEN 9 /* Command Pending enabled */
|
|
#define BITP_RSI_CMD_IEN 8 /* Command Interrupt Enabled */
|
|
#define BITP_RSI_CMD_LRSP 7 /* Long Response */
|
|
#define BITP_RSI_CMD_RSP 6 /* Response */
|
|
#define BITP_RSI_CMD_IDX 0 /* Command Index */
|
|
#define BITM_RSI_CMD_CHKBUSY (_ADI_MSK(0x00001000,uint16_t)) /* Check Busy Condition */
|
|
#define BITM_RSI_CMD_CRCDIS (_ADI_MSK(0x00000800,uint16_t)) /* Disable CRC Check */
|
|
#define BITM_RSI_CMD_EN (_ADI_MSK(0x00000400,uint16_t)) /* Command Enable */
|
|
#define BITM_RSI_CMD_PNDEN (_ADI_MSK(0x00000200,uint16_t)) /* Command Pending enabled */
|
|
#define BITM_RSI_CMD_IEN (_ADI_MSK(0x00000100,uint16_t)) /* Command Interrupt Enabled */
|
|
#define BITM_RSI_CMD_LRSP (_ADI_MSK(0x00000080,uint16_t)) /* Long Response */
|
|
#define BITM_RSI_CMD_RSP (_ADI_MSK(0x00000040,uint16_t)) /* Response */
|
|
#define BITM_RSI_CMD_IDX (_ADI_MSK(0x0000003F,uint16_t)) /* Command Index */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
RSI_RESP_CMD Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RSI_RESP_CMD_VALUE 0 /* Response Command */
|
|
#define BITM_RSI_RESP_CMD_VALUE (_ADI_MSK(0x0000003F,uint16_t)) /* Response Command */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
RSI_DATA_CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RSI_DATA_CTL_CEATAIEN 9 /* Ceata Command Completion Interrupt Enable */
|
|
#define BITP_RSI_DATA_CTL_CEATAMODE 8 /* Ceata Mode enable */
|
|
#define BITP_RSI_DATA_CTL_DMAEN 3 /* Data Transfer DMA Enable */
|
|
#define BITP_RSI_DATA_CTL_DATMODE 2 /* Data Transfer Mode */
|
|
#define BITP_RSI_DATA_CTL_DATDIR 1 /* Data Transfer Direction */
|
|
#define BITP_RSI_DATA_CTL_DATEN 0 /* Data Transfer Enable */
|
|
#define BITM_RSI_DATA_CTL_CEATAIEN (_ADI_MSK(0x00000200,uint16_t)) /* Ceata Command Completion Interrupt Enable */
|
|
#define BITM_RSI_DATA_CTL_CEATAMODE (_ADI_MSK(0x00000100,uint16_t)) /* Ceata Mode enable */
|
|
#define BITM_RSI_DATA_CTL_DMAEN (_ADI_MSK(0x00000008,uint16_t)) /* Data Transfer DMA Enable */
|
|
#define BITM_RSI_DATA_CTL_DATMODE (_ADI_MSK(0x00000004,uint16_t)) /* Data Transfer Mode */
|
|
#define BITM_RSI_DATA_CTL_DATDIR (_ADI_MSK(0x00000002,uint16_t)) /* Data Transfer Direction */
|
|
#define BITM_RSI_DATA_CTL_DATEN (_ADI_MSK(0x00000001,uint16_t)) /* Data Transfer Enable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
RSI_XFRSTAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RSI_XFRSTAT_RXFIFORDY 21 /* Receive FIFO Available */
|
|
#define BITP_RSI_XFRSTAT_TXFIFORDY 20 /* Transmit FIFO Available */
|
|
#define BITP_RSI_XFRSTAT_RXFIFOZERO 19 /* Receive FIFO Empty */
|
|
#define BITP_RSI_XFRSTAT_TXFIFOZERO 18 /* Transmit FIFO Empty */
|
|
#define BITP_RSI_XFRSTAT_RXFIFOFULL 17 /* Receive FIFO Full */
|
|
#define BITP_RSI_XFRSTAT_TXFIFOFULL 16 /* Transmit FIFO Full */
|
|
#define BITP_RSI_XFRSTAT_RXFIFOSTAT 15 /* Receive FIFO Status */
|
|
#define BITP_RSI_XFRSTAT_TXFIFOSTAT 14 /* Transmit FIFO Status */
|
|
#define BITP_RSI_XFRSTAT_RXACT 13 /* Receive Active */
|
|
#define BITP_RSI_XFRSTAT_TXACT 12 /* Transmit Active */
|
|
#define BITP_RSI_XFRSTAT_CMDACT 11 /* Command Active */
|
|
#define BITP_RSI_XFRSTAT_DATBLKEND 10 /* Data Block End */
|
|
#define BITP_RSI_XFRSTAT_SBITERR 9 /* Start Bit Error */
|
|
#define BITP_RSI_XFRSTAT_DATEND 8 /* Data End */
|
|
#define BITP_RSI_XFRSTAT_CMDSENT 7 /* Command Sent */
|
|
#define BITP_RSI_XFRSTAT_RESPEND 6 /* Command Response End */
|
|
#define BITP_RSI_XFRSTAT_RXOVER 5 /* Receive Over run */
|
|
#define BITP_RSI_XFRSTAT_TXUNDR 4 /* Transmit Under run */
|
|
#define BITP_RSI_XFRSTAT_DATTO 3 /* Data Timeout */
|
|
#define BITP_RSI_XFRSTAT_CMDTO 2 /* CMD Timeout */
|
|
#define BITP_RSI_XFRSTAT_DATCRCFAIL 1 /* Data CRC Fail */
|
|
#define BITP_RSI_XFRSTAT_CMDCRCFAIL 0 /* CMD CRC Fail */
|
|
#define BITM_RSI_XFRSTAT_RXFIFORDY (_ADI_MSK(0x00200000,uint32_t)) /* Receive FIFO Available */
|
|
#define BITM_RSI_XFRSTAT_TXFIFORDY (_ADI_MSK(0x00100000,uint32_t)) /* Transmit FIFO Available */
|
|
#define BITM_RSI_XFRSTAT_RXFIFOZERO (_ADI_MSK(0x00080000,uint32_t)) /* Receive FIFO Empty */
|
|
#define BITM_RSI_XFRSTAT_TXFIFOZERO (_ADI_MSK(0x00040000,uint32_t)) /* Transmit FIFO Empty */
|
|
#define BITM_RSI_XFRSTAT_RXFIFOFULL (_ADI_MSK(0x00020000,uint32_t)) /* Receive FIFO Full */
|
|
#define BITM_RSI_XFRSTAT_TXFIFOFULL (_ADI_MSK(0x00010000,uint32_t)) /* Transmit FIFO Full */
|
|
#define BITM_RSI_XFRSTAT_RXFIFOSTAT (_ADI_MSK(0x00008000,uint32_t)) /* Receive FIFO Status */
|
|
#define BITM_RSI_XFRSTAT_TXFIFOSTAT (_ADI_MSK(0x00004000,uint32_t)) /* Transmit FIFO Status */
|
|
#define BITM_RSI_XFRSTAT_RXACT (_ADI_MSK(0x00002000,uint32_t)) /* Receive Active */
|
|
#define BITM_RSI_XFRSTAT_TXACT (_ADI_MSK(0x00001000,uint32_t)) /* Transmit Active */
|
|
#define BITM_RSI_XFRSTAT_CMDACT (_ADI_MSK(0x00000800,uint32_t)) /* Command Active */
|
|
#define BITM_RSI_XFRSTAT_DATBLKEND (_ADI_MSK(0x00000400,uint32_t)) /* Data Block End */
|
|
#define BITM_RSI_XFRSTAT_SBITERR (_ADI_MSK(0x00000200,uint32_t)) /* Start Bit Error */
|
|
#define BITM_RSI_XFRSTAT_DATEND (_ADI_MSK(0x00000100,uint32_t)) /* Data End */
|
|
#define BITM_RSI_XFRSTAT_CMDSENT (_ADI_MSK(0x00000080,uint32_t)) /* Command Sent */
|
|
#define BITM_RSI_XFRSTAT_RESPEND (_ADI_MSK(0x00000040,uint32_t)) /* Command Response End */
|
|
#define BITM_RSI_XFRSTAT_RXOVER (_ADI_MSK(0x00000020,uint32_t)) /* Receive Over run */
|
|
#define BITM_RSI_XFRSTAT_TXUNDR (_ADI_MSK(0x00000010,uint32_t)) /* Transmit Under run */
|
|
#define BITM_RSI_XFRSTAT_DATTO (_ADI_MSK(0x00000008,uint32_t)) /* Data Timeout */
|
|
#define BITM_RSI_XFRSTAT_CMDTO (_ADI_MSK(0x00000004,uint32_t)) /* CMD Timeout */
|
|
#define BITM_RSI_XFRSTAT_DATCRCFAIL (_ADI_MSK(0x00000002,uint32_t)) /* Data CRC Fail */
|
|
#define BITM_RSI_XFRSTAT_CMDCRCFAIL (_ADI_MSK(0x00000001,uint32_t)) /* CMD CRC Fail */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
RSI_XFRSTAT_CLR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RSI_XFRSTAT_CLR_DATBLKEND 10 /* Data Block End Status */
|
|
#define BITP_RSI_XFRSTAT_CLR_STRTBITERR 9 /* Start Bit Error Status */
|
|
#define BITP_RSI_XFRSTAT_CLR_DATEND 8 /* Data End Status */
|
|
#define BITP_RSI_XFRSTAT_CLR_CMDSENT 7 /* Command Sent Status */
|
|
#define BITP_RSI_XFRSTAT_CLR_RESPEND 6 /* Command Response End Status */
|
|
#define BITP_RSI_XFRSTAT_CLR_RXOVER 5 /* Receive Over run Status */
|
|
#define BITP_RSI_XFRSTAT_CLR_TXUNDR 4 /* Transmit Under run Status */
|
|
#define BITP_RSI_XFRSTAT_CLR_DATTO 3 /* Data Timeout Status */
|
|
#define BITP_RSI_XFRSTAT_CLR_CMDTO 2 /* CMD Timeout Status */
|
|
#define BITP_RSI_XFRSTAT_CLR_DATCRCFAIL 1 /* Data CRC Fail Status */
|
|
#define BITP_RSI_XFRSTAT_CLR_CMDCRCFAIL 0 /* CMD CRC Fail Status */
|
|
#define BITM_RSI_XFRSTAT_CLR_DATBLKEND (_ADI_MSK(0x00000400,uint16_t)) /* Data Block End Status */
|
|
#define BITM_RSI_XFRSTAT_CLR_STRTBITERR (_ADI_MSK(0x00000200,uint16_t)) /* Start Bit Error Status */
|
|
#define BITM_RSI_XFRSTAT_CLR_DATEND (_ADI_MSK(0x00000100,uint16_t)) /* Data End Status */
|
|
#define BITM_RSI_XFRSTAT_CLR_CMDSENT (_ADI_MSK(0x00000080,uint16_t)) /* Command Sent Status */
|
|
#define BITM_RSI_XFRSTAT_CLR_RESPEND (_ADI_MSK(0x00000040,uint16_t)) /* Command Response End Status */
|
|
#define BITM_RSI_XFRSTAT_CLR_RXOVER (_ADI_MSK(0x00000020,uint16_t)) /* Receive Over run Status */
|
|
#define BITM_RSI_XFRSTAT_CLR_TXUNDR (_ADI_MSK(0x00000010,uint16_t)) /* Transmit Under run Status */
|
|
#define BITM_RSI_XFRSTAT_CLR_DATTO (_ADI_MSK(0x00000008,uint16_t)) /* Data Timeout Status */
|
|
#define BITM_RSI_XFRSTAT_CLR_CMDTO (_ADI_MSK(0x00000004,uint16_t)) /* CMD Timeout Status */
|
|
#define BITM_RSI_XFRSTAT_CLR_DATCRCFAIL (_ADI_MSK(0x00000002,uint16_t)) /* Data CRC Fail Status */
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#define BITM_RSI_XFRSTAT_CLR_CMDCRCFAIL (_ADI_MSK(0x00000001,uint16_t)) /* CMD CRC Fail Status */
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
RSI_XFR_IMSK0 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RSI_XFR_IMSK0_RXFIFORDY 21 /* Enable Interrupt for Receive FIFO Available */
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#define BITP_RSI_XFR_IMSK0_TXFIFORDY 20 /* Enable Interrupt for Transmit FIFO Available */
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#define BITP_RSI_XFR_IMSK0_RXFIFOZERO 19 /* Enable Interrupt for Receive FIFO Empty */
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#define BITP_RSI_XFR_IMSK0_TXFIFOZERO 18 /* Enable Interrupt for Transmit FIFO Empty */
|
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#define BITP_RSI_XFR_IMSK0_RXFIFOFULL 17 /* Enable Interrupt for Receive FIFO Full */
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#define BITP_RSI_XFR_IMSK0_TXFIFOFULL 16 /* Enable Interrupt for Transmit FIFO Full */
|
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#define BITP_RSI_XFR_IMSK0_RXFIFOSTAT 15 /* Enable Interrupt for Receive FIFO Status */
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#define BITP_RSI_XFR_IMSK0_TXFIFOSTAT 14 /* Enable Interrupt for Transmit FIFO Status */
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#define BITP_RSI_XFR_IMSK0_RXACT 13 /* Enable Interrupt for Receive Active */
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#define BITP_RSI_XFR_IMSK0_TXACT 12 /* Enable Interrupt for Transmit Active */
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#define BITP_RSI_XFR_IMSK0_CMDACT 11 /* Enable Interrupt for Command Active */
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#define BITP_RSI_XFR_IMSK0_DATBLKEND 10 /* Enable Interrupt for Data Block End */
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#define BITP_RSI_XFR_IMSK0_STRTBITERR 9 /* Enable Interrupt for Start Bit Error */
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#define BITP_RSI_XFR_IMSK0_DATEND 8 /* Enable Interrupt for Data End */
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#define BITP_RSI_XFR_IMSK0_CMDSENT 7 /* Enable Interrupt for Command Sent */
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#define BITP_RSI_XFR_IMSK0_RESPEND 6 /* Enable Interrupt for Command Response End */
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#define BITP_RSI_XFR_IMSK0_RXOVER 5 /* Enable Interrupt for Receive Over run */
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#define BITP_RSI_XFR_IMSK0_TXUNDR 4 /* Enable Interrupt for Transmit Under run */
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#define BITP_RSI_XFR_IMSK0_DATTO 3 /* Enable Interrupt for Data Timeout */
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#define BITP_RSI_XFR_IMSK0_CMDTO 2 /* Enable Interrupt for CMD Timeout */
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#define BITP_RSI_XFR_IMSK0_DATCRCFAIL 1 /* Enable Interrupt for Data CRC Fail */
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#define BITP_RSI_XFR_IMSK0_CMDCRCFAIL 0 /* Enable Interrupt for CMD CRC Fail */
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#define BITM_RSI_XFR_IMSK0_RXFIFORDY (_ADI_MSK(0x00200000,uint32_t)) /* Enable Interrupt for Receive FIFO Available */
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#define BITM_RSI_XFR_IMSK0_TXFIFORDY (_ADI_MSK(0x00100000,uint32_t)) /* Enable Interrupt for Transmit FIFO Available */
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#define BITM_RSI_XFR_IMSK0_RXFIFOZERO (_ADI_MSK(0x00080000,uint32_t)) /* Enable Interrupt for Receive FIFO Empty */
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#define BITM_RSI_XFR_IMSK0_TXFIFOZERO (_ADI_MSK(0x00040000,uint32_t)) /* Enable Interrupt for Transmit FIFO Empty */
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#define BITM_RSI_XFR_IMSK0_RXFIFOFULL (_ADI_MSK(0x00020000,uint32_t)) /* Enable Interrupt for Receive FIFO Full */
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#define BITM_RSI_XFR_IMSK0_TXFIFOFULL (_ADI_MSK(0x00010000,uint32_t)) /* Enable Interrupt for Transmit FIFO Full */
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#define BITM_RSI_XFR_IMSK0_RXFIFOSTAT (_ADI_MSK(0x00008000,uint32_t)) /* Enable Interrupt for Receive FIFO Status */
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#define BITM_RSI_XFR_IMSK0_TXFIFOSTAT (_ADI_MSK(0x00004000,uint32_t)) /* Enable Interrupt for Transmit FIFO Status */
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#define BITM_RSI_XFR_IMSK0_RXACT (_ADI_MSK(0x00002000,uint32_t)) /* Enable Interrupt for Receive Active */
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#define BITM_RSI_XFR_IMSK0_TXACT (_ADI_MSK(0x00001000,uint32_t)) /* Enable Interrupt for Transmit Active */
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#define BITM_RSI_XFR_IMSK0_CMDACT (_ADI_MSK(0x00000800,uint32_t)) /* Enable Interrupt for Command Active */
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#define BITM_RSI_XFR_IMSK0_DATBLKEND (_ADI_MSK(0x00000400,uint32_t)) /* Enable Interrupt for Data Block End */
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#define BITM_RSI_XFR_IMSK0_STRTBITERR (_ADI_MSK(0x00000200,uint32_t)) /* Enable Interrupt for Start Bit Error */
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#define BITM_RSI_XFR_IMSK0_DATEND (_ADI_MSK(0x00000100,uint32_t)) /* Enable Interrupt for Data End */
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#define BITM_RSI_XFR_IMSK0_CMDSENT (_ADI_MSK(0x00000080,uint32_t)) /* Enable Interrupt for Command Sent */
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#define BITM_RSI_XFR_IMSK0_RESPEND (_ADI_MSK(0x00000040,uint32_t)) /* Enable Interrupt for Command Response End */
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#define BITM_RSI_XFR_IMSK0_RXOVER (_ADI_MSK(0x00000020,uint32_t)) /* Enable Interrupt for Receive Over run */
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#define BITM_RSI_XFR_IMSK0_TXUNDR (_ADI_MSK(0x00000010,uint32_t)) /* Enable Interrupt for Transmit Under run */
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#define BITM_RSI_XFR_IMSK0_DATTO (_ADI_MSK(0x00000008,uint32_t)) /* Enable Interrupt for Data Timeout */
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#define BITM_RSI_XFR_IMSK0_CMDTO (_ADI_MSK(0x00000004,uint32_t)) /* Enable Interrupt for CMD Timeout */
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#define BITM_RSI_XFR_IMSK0_DATCRCFAIL (_ADI_MSK(0x00000002,uint32_t)) /* Enable Interrupt for Data CRC Fail */
|
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#define BITM_RSI_XFR_IMSK0_CMDCRCFAIL (_ADI_MSK(0x00000001,uint32_t)) /* Enable Interrupt for CMD CRC Fail */
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|
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
RSI_XFR_IMSK1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RSI_XFR_IMSK1_RXFIFORDY 21 /* Enable Interrupt for Receive FIFO Available */
|
|
#define BITP_RSI_XFR_IMSK1_TXFIFORDY 20 /* Enable Interrupt for Transmit FIFO Available */
|
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#define BITP_RSI_XFR_IMSK1_RXFIFOZERO 19 /* Enable Interrupt for Receive FIFO Empty */
|
|
#define BITP_RSI_XFR_IMSK1_TXFIFOZERO 18 /* Enable Interrupt for Transmit FIFO Empty */
|
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#define BITP_RSI_XFR_IMSK1_RXFIFOFULL 17 /* Enable Interrupt for Receive FIFO Full */
|
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#define BITP_RSI_XFR_IMSK1_TXFIFOFULL 16 /* Enable Interrupt for Transmit FIFO Full */
|
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#define BITP_RSI_XFR_IMSK1_RXFIFOSTAT 15 /* Enable Interrupt for Receive FIFO Status */
|
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#define BITP_RSI_XFR_IMSK1_TXFIFOSTAT 14 /* Enable Interrupt for Transmit FIFO Status */
|
|
#define BITP_RSI_XFR_IMSK1_RXACT 13 /* Enable Interrupt for Receive Active */
|
|
#define BITP_RSI_XFR_IMSK1_TXACT 12 /* Enable Interrupt for Transmit Active */
|
|
#define BITP_RSI_XFR_IMSK1_CMDACT 11 /* Enable Interrupt for Command Active */
|
|
#define BITP_RSI_XFR_IMSK1_DATBLKEND 10 /* Enable Interrupt for Data Block End */
|
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#define BITP_RSI_XFR_IMSK1_STRTBITERR 9 /* Enable Interrupt for Start Bit Error */
|
|
#define BITP_RSI_XFR_IMSK1_DATEND 8 /* Enable Interrupt for Data End */
|
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#define BITP_RSI_XFR_IMSK1_CMDSENT 7 /* Enable Interrupt for Command Sent */
|
|
#define BITP_RSI_XFR_IMSK1_RESPEND 6 /* Enable Interrupt for Command Response End */
|
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#define BITP_RSI_XFR_IMSK1_RXOVER 5 /* Enable Interrupt for Receive Over run */
|
|
#define BITP_RSI_XFR_IMSK1_TXUNDR 4 /* Enable Interrupt for Transmit Under run */
|
|
#define BITP_RSI_XFR_IMSK1_DATTO 3 /* Enable Interrupt for Data Timeout */
|
|
#define BITP_RSI_XFR_IMSK1_CMDTO 2 /* Enable Interrupt for CMD Timeout */
|
|
#define BITP_RSI_XFR_IMSK1_DATCRCFAIL 1 /* Enable Interrupt for Data CRC Fail */
|
|
#define BITP_RSI_XFR_IMSK1_CMDCRCFAIL 0 /* Enable Interrupt for CMD CRC Fail */
|
|
#define BITM_RSI_XFR_IMSK1_RXFIFORDY (_ADI_MSK(0x00200000,uint32_t)) /* Enable Interrupt for Receive FIFO Available */
|
|
#define BITM_RSI_XFR_IMSK1_TXFIFORDY (_ADI_MSK(0x00100000,uint32_t)) /* Enable Interrupt for Transmit FIFO Available */
|
|
#define BITM_RSI_XFR_IMSK1_RXFIFOZERO (_ADI_MSK(0x00080000,uint32_t)) /* Enable Interrupt for Receive FIFO Empty */
|
|
#define BITM_RSI_XFR_IMSK1_TXFIFOZERO (_ADI_MSK(0x00040000,uint32_t)) /* Enable Interrupt for Transmit FIFO Empty */
|
|
#define BITM_RSI_XFR_IMSK1_RXFIFOFULL (_ADI_MSK(0x00020000,uint32_t)) /* Enable Interrupt for Receive FIFO Full */
|
|
#define BITM_RSI_XFR_IMSK1_TXFIFOFULL (_ADI_MSK(0x00010000,uint32_t)) /* Enable Interrupt for Transmit FIFO Full */
|
|
#define BITM_RSI_XFR_IMSK1_RXFIFOSTAT (_ADI_MSK(0x00008000,uint32_t)) /* Enable Interrupt for Receive FIFO Status */
|
|
#define BITM_RSI_XFR_IMSK1_TXFIFOSTAT (_ADI_MSK(0x00004000,uint32_t)) /* Enable Interrupt for Transmit FIFO Status */
|
|
#define BITM_RSI_XFR_IMSK1_RXACT (_ADI_MSK(0x00002000,uint32_t)) /* Enable Interrupt for Receive Active */
|
|
#define BITM_RSI_XFR_IMSK1_TXACT (_ADI_MSK(0x00001000,uint32_t)) /* Enable Interrupt for Transmit Active */
|
|
#define BITM_RSI_XFR_IMSK1_CMDACT (_ADI_MSK(0x00000800,uint32_t)) /* Enable Interrupt for Command Active */
|
|
#define BITM_RSI_XFR_IMSK1_DATBLKEND (_ADI_MSK(0x00000400,uint32_t)) /* Enable Interrupt for Data Block End */
|
|
#define BITM_RSI_XFR_IMSK1_STRTBITERR (_ADI_MSK(0x00000200,uint32_t)) /* Enable Interrupt for Start Bit Error */
|
|
#define BITM_RSI_XFR_IMSK1_DATEND (_ADI_MSK(0x00000100,uint32_t)) /* Enable Interrupt for Data End */
|
|
#define BITM_RSI_XFR_IMSK1_CMDSENT (_ADI_MSK(0x00000080,uint32_t)) /* Enable Interrupt for Command Sent */
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|
#define BITM_RSI_XFR_IMSK1_RESPEND (_ADI_MSK(0x00000040,uint32_t)) /* Enable Interrupt for Command Response End */
|
|
#define BITM_RSI_XFR_IMSK1_RXOVER (_ADI_MSK(0x00000020,uint32_t)) /* Enable Interrupt for Receive Over run */
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|
#define BITM_RSI_XFR_IMSK1_TXUNDR (_ADI_MSK(0x00000010,uint32_t)) /* Enable Interrupt for Transmit Under run */
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#define BITM_RSI_XFR_IMSK1_DATTO (_ADI_MSK(0x00000008,uint32_t)) /* Enable Interrupt for Data Timeout */
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#define BITM_RSI_XFR_IMSK1_CMDTO (_ADI_MSK(0x00000004,uint32_t)) /* Enable Interrupt for CMD Timeout */
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#define BITM_RSI_XFR_IMSK1_DATCRCFAIL (_ADI_MSK(0x00000002,uint32_t)) /* Enable Interrupt for Data CRC Fail */
|
|
#define BITM_RSI_XFR_IMSK1_CMDCRCFAIL (_ADI_MSK(0x00000001,uint32_t)) /* Enable Interrupt for CMD CRC Fail */
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|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
RSI_FIFO_CNT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RSI_FIFO_CNT_VALUE 0 /* FIFO Count */
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#define BITM_RSI_FIFO_CNT_VALUE (_ADI_MSK(0x00007FFF,uint16_t)) /* FIFO Count */
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|
|
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
RSI_CEATA Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RSI_CEATA_INT_DIS 0 /* CEATA Disable Interrupt */
|
|
#define BITM_RSI_CEATA_INT_DIS (_ADI_MSK(0x00000001,uint32_t)) /* CEATA Disable Interrupt */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
RSI_BOOT_TCNTR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RSI_BOOT_TCNTR_HOLD 8 /* Boot Hold Time */
|
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#define BITP_RSI_BOOT_TCNTR_SETUP 0 /* Boot Setup Time */
|
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#define BITM_RSI_BOOT_TCNTR_HOLD (_ADI_MSK(0x0000FF00,uint16_t)) /* Boot Hold Time */
|
|
#define BITM_RSI_BOOT_TCNTR_SETUP (_ADI_MSK(0x000000FF,uint16_t)) /* Boot Setup Time */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
RSI_BLKSZ Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RSI_BLKSZ_VALUE 0 /* Size of Each Block of Data */
|
|
#define BITM_RSI_BLKSZ_VALUE (_ADI_MSK(0x00001FFF,uint16_t)) /* Size of Each Block of Data */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
RSI_STAT0 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RSI_STAT0_BUSYMODE 31 /* Card is in Busy mode */
|
|
#define BITP_RSI_STAT0_SLPMODE 30 /* Card in Sleep Mode */
|
|
#define BITP_RSI_STAT0_CARDRDY 17 /* Card Ready */
|
|
#define BITP_RSI_STAT0_SLPWKPTOUT 16 /* Sleep Wakeup Timer Expired */
|
|
#define BITP_RSI_STAT0_WKPDONE 15 /* Card Entered Standby state */
|
|
#define BITP_RSI_STAT0_SLPDONE 14 /* Card Entered Sleep State */
|
|
#define BITP_RSI_STAT0_BACKDONE 13 /* Correct Boot Ack is received */
|
|
#define BITP_RSI_STAT0_BACKBAD 12 /* Boot Ack received is corrupted */
|
|
#define BITP_RSI_STAT0_BACKTO 11 /* Boot Acknowledge Timeout */
|
|
#define BITP_RSI_STAT0_BDATTO 10 /* Boot Data Timeout */
|
|
#define BITP_RSI_STAT0_BHOLDEXP 9 /* Boot Hold Time Expiry */
|
|
#define BITP_RSI_STAT0_BSETUPEXP 8 /* Boot Setup Time Expiry */
|
|
#define BITP_RSI_STAT0_CEATAINT 5 /* CEATA Interrupt */
|
|
#define BITP_RSI_STAT0_SDCARD 4 /* SD Card Detected */
|
|
#define BITP_RSI_STAT0_SDIOINT 1 /* SDIO Interrupt */
|
|
#define BITM_RSI_STAT0_BUSYMODE (_ADI_MSK(0x80000000,uint32_t)) /* Card is in Busy mode */
|
|
#define BITM_RSI_STAT0_SLPMODE (_ADI_MSK(0x40000000,uint32_t)) /* Card in Sleep Mode */
|
|
#define BITM_RSI_STAT0_CARDRDY (_ADI_MSK(0x00020000,uint32_t)) /* Card Ready */
|
|
#define BITM_RSI_STAT0_SLPWKPTOUT (_ADI_MSK(0x00010000,uint32_t)) /* Sleep Wakeup Timer Expired */
|
|
#define BITM_RSI_STAT0_WKPDONE (_ADI_MSK(0x00008000,uint32_t)) /* Card Entered Standby state */
|
|
#define BITM_RSI_STAT0_SLPDONE (_ADI_MSK(0x00004000,uint32_t)) /* Card Entered Sleep State */
|
|
#define BITM_RSI_STAT0_BACKDONE (_ADI_MSK(0x00002000,uint32_t)) /* Correct Boot Ack is received */
|
|
#define BITM_RSI_STAT0_BACKBAD (_ADI_MSK(0x00001000,uint32_t)) /* Boot Ack received is corrupted */
|
|
#define BITM_RSI_STAT0_BACKTO (_ADI_MSK(0x00000800,uint32_t)) /* Boot Acknowledge Timeout */
|
|
#define BITM_RSI_STAT0_BDATTO (_ADI_MSK(0x00000400,uint32_t)) /* Boot Data Timeout */
|
|
#define BITM_RSI_STAT0_BHOLDEXP (_ADI_MSK(0x00000200,uint32_t)) /* Boot Hold Time Expiry */
|
|
#define BITM_RSI_STAT0_BSETUPEXP (_ADI_MSK(0x00000100,uint32_t)) /* Boot Setup Time Expiry */
|
|
#define BITM_RSI_STAT0_CEATAINT (_ADI_MSK(0x00000020,uint32_t)) /* CEATA Interrupt */
|
|
#define BITM_RSI_STAT0_SDCARD (_ADI_MSK(0x00000010,uint32_t)) /* SD Card Detected */
|
|
#define BITM_RSI_STAT0_SDIOINT (_ADI_MSK(0x00000002,uint32_t)) /* SDIO Interrupt */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
RSI_IMSK0 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RSI_IMSK0_CARDRDY 17 /* Mask Interrupt for Card Ready */
|
|
#define BITP_RSI_IMSK0_SLPWKPTOUT 16 /* Mask Interrupt for Sleep Wakeup Timer Expired */
|
|
#define BITP_RSI_IMSK0_WKPDONE 15 /* Mask Interrupt for Card Entered Standby state */
|
|
#define BITP_RSI_IMSK0_SLPDONE 14 /* Mask Interrupt for Card Entered Sleep State */
|
|
#define BITP_RSI_IMSK0_BACKDONE 13 /* Mask Interrupt for Correct Boot Ack is received */
|
|
#define BITP_RSI_IMSK0_BACKBAD 12 /* Mask Interrupt for Boot Ack received is corrupted */
|
|
#define BITP_RSI_IMSK0_BACKTO 11 /* Mask Interrupt for Boot Acknowledge Timeout */
|
|
#define BITP_RSI_IMSK0_BDATTO 10 /* Mask Interrupt for Boot Data Timeout */
|
|
#define BITP_RSI_IMSK0_BHOLDEXP 9 /* Mask Interrupt for Boot Hold Time Expiry */
|
|
#define BITP_RSI_IMSK0_BSETUPEXP 8 /* Mask Interrupt for Boot Setup Time Expiry */
|
|
#define BITP_RSI_IMSK0_CEATAINT 5 /* Mask CEATA Interrupt */
|
|
#define BITP_RSI_IMSK0_SDCARD 4 /* Mask Interrupt for SD Card Detected */
|
|
#define BITP_RSI_IMSK0_SDIOINT 1 /* Mask SDIO Interrupt */
|
|
#define BITM_RSI_IMSK0_CARDRDY (_ADI_MSK(0x00020000,uint32_t)) /* Mask Interrupt for Card Ready */
|
|
#define BITM_RSI_IMSK0_SLPWKPTOUT (_ADI_MSK(0x00010000,uint32_t)) /* Mask Interrupt for Sleep Wakeup Timer Expired */
|
|
#define BITM_RSI_IMSK0_WKPDONE (_ADI_MSK(0x00008000,uint32_t)) /* Mask Interrupt for Card Entered Standby state */
|
|
#define BITM_RSI_IMSK0_SLPDONE (_ADI_MSK(0x00004000,uint32_t)) /* Mask Interrupt for Card Entered Sleep State */
|
|
#define BITM_RSI_IMSK0_BACKDONE (_ADI_MSK(0x00002000,uint32_t)) /* Mask Interrupt for Correct Boot Ack is received */
|
|
#define BITM_RSI_IMSK0_BACKBAD (_ADI_MSK(0x00001000,uint32_t)) /* Mask Interrupt for Boot Ack received is corrupted */
|
|
#define BITM_RSI_IMSK0_BACKTO (_ADI_MSK(0x00000800,uint32_t)) /* Mask Interrupt for Boot Acknowledge Timeout */
|
|
#define BITM_RSI_IMSK0_BDATTO (_ADI_MSK(0x00000400,uint32_t)) /* Mask Interrupt for Boot Data Timeout */
|
|
#define BITM_RSI_IMSK0_BHOLDEXP (_ADI_MSK(0x00000200,uint32_t)) /* Mask Interrupt for Boot Hold Time Expiry */
|
|
#define BITM_RSI_IMSK0_BSETUPEXP (_ADI_MSK(0x00000100,uint32_t)) /* Mask Interrupt for Boot Setup Time Expiry */
|
|
#define BITM_RSI_IMSK0_CEATAINT (_ADI_MSK(0x00000020,uint32_t)) /* Mask CEATA Interrupt */
|
|
#define BITM_RSI_IMSK0_SDCARD (_ADI_MSK(0x00000010,uint32_t)) /* Mask Interrupt for SD Card Detected */
|
|
#define BITM_RSI_IMSK0_SDIOINT (_ADI_MSK(0x00000002,uint32_t)) /* Mask SDIO Interrupt */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
RSI_CFG Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RSI_CFG_BACKEN 14 /* Boot Acknowledge enabled */
|
|
#define BITP_RSI_CFG_MMCBMODE 13 /* MMC Boot Mode select */
|
|
#define BITP_RSI_CFG_MMCBEN 12 /* MMC Boot Enabled */
|
|
#define BITP_RSI_CFG_OPENDRAIN 11 /* MC_CMD Output Control */
|
|
#define BITP_RSI_CFG_PWRON 9 /* 11 - RSI Enabled */
|
|
#define BITP_RSI_CFG_IEBYPDIS 8 /* Disabled IE Bypass */
|
|
#define BITP_RSI_CFG_DAT3PUP 6 /* Pull-Up SD_DAT3 */
|
|
#define BITP_RSI_CFG_DATPUP 5 /* Pull-Up SD_DAT */
|
|
#define BITP_RSI_CFG_RST 4 /* SDMMC Reset */
|
|
#define BITP_RSI_CFG_MWINEN 3 /* Moving Window Enable */
|
|
#define BITP_RSI_CFG_SD4EN 2 /* SDIO 4-Bit Enable */
|
|
#define BITP_RSI_CFG_CLKSEN 0 /* Clocks Enable */
|
|
#define BITM_RSI_CFG_BACKEN (_ADI_MSK(0x00004000,uint16_t)) /* Boot Acknowledge enabled */
|
|
#define BITM_RSI_CFG_MMCBMODE (_ADI_MSK(0x00002000,uint16_t)) /* MMC Boot Mode select */
|
|
#define BITM_RSI_CFG_MMCBEN (_ADI_MSK(0x00001000,uint16_t)) /* MMC Boot Enabled */
|
|
#define BITM_RSI_CFG_OPENDRAIN (_ADI_MSK(0x00000800,uint16_t)) /* MC_CMD Output Control */
|
|
#define BITM_RSI_CFG_PWRON (_ADI_MSK(0x00000600,uint16_t)) /* 11 - RSI Enabled */
|
|
#define BITM_RSI_CFG_IEBYPDIS (_ADI_MSK(0x00000100,uint16_t)) /* Disabled IE Bypass */
|
|
#define BITM_RSI_CFG_DAT3PUP (_ADI_MSK(0x00000040,uint16_t)) /* Pull-Up SD_DAT3 */
|
|
#define BITM_RSI_CFG_DATPUP (_ADI_MSK(0x00000020,uint16_t)) /* Pull-Up SD_DAT */
|
|
#define BITM_RSI_CFG_RST (_ADI_MSK(0x00000010,uint16_t)) /* SDMMC Reset */
|
|
#define BITM_RSI_CFG_MWINEN (_ADI_MSK(0x00000008,uint16_t)) /* Moving Window Enable */
|
|
#define BITM_RSI_CFG_SD4EN (_ADI_MSK(0x00000004,uint16_t)) /* SDIO 4-Bit Enable */
|
|
#define BITM_RSI_CFG_CLKSEN (_ADI_MSK(0x00000001,uint16_t)) /* Clocks Enable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
RSI_RD_WAIT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RSI_RD_WAIT_REQUEST 0 /* Read Wait Request */
|
|
#define BITM_RSI_RD_WAIT_REQUEST (_ADI_MSK(0x00000001,uint16_t)) /* Read Wait Request */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
RSI_PID0 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RSI_PID0_VALUE 0 /* Peripheral Identification */
|
|
#define BITM_RSI_PID0_VALUE (_ADI_MSK(0x000000FF,uint32_t)) /* Peripheral Identification */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
RSI_PID1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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|
#define BITP_RSI_PID1_VALUE 0 /* Peripheral Identification */
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#define BITM_RSI_PID1_VALUE (_ADI_MSK(0x000000FF,uint32_t)) /* Peripheral Identification */
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|
|
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
RSI_PID2 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RSI_PID2_VALUE 0 /* Peripheral Identification */
|
|
#define BITM_RSI_PID2_VALUE (_ADI_MSK(0x000000FF,uint32_t)) /* Peripheral Identification */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
RSI_PID3 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RSI_PID3_VALUE 0 /* Peripheral Identification */
|
|
#define BITM_RSI_PID3_VALUE (_ADI_MSK(0x000000FF,uint32_t)) /* Peripheral Identification */
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|
|
|
/* ==================================================
|
|
Controller Area Network Registers
|
|
================================================== */
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|
|
|
/* =========================
|
|
CAN0
|
|
========================= */
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|
#define REG_CAN0_MC1 0xFFC00A00 /* CAN0 Mailbox Configuration 1 Register */
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|
#define REG_CAN0_MD1 0xFFC00A04 /* CAN0 Mailbox Direction 1 Register */
|
|
#define REG_CAN0_TRS1 0xFFC00A08 /* CAN0 Transmission Request Set 1 Register */
|
|
#define REG_CAN0_TRR1 0xFFC00A0C /* CAN0 Transmission Request Reset 1 Register */
|
|
#define REG_CAN0_TA1 0xFFC00A10 /* CAN0 Transmission Acknowledge 1 Register */
|
|
#define REG_CAN0_AA1 0xFFC00A14 /* CAN0 Abort Acknowledge 1 Register */
|
|
#define REG_CAN0_RMP1 0xFFC00A18 /* CAN0 Receive Message Pending 1 Register */
|
|
#define REG_CAN0_RML1 0xFFC00A1C /* CAN0 Receive Message Lost 1 Register */
|
|
#define REG_CAN0_MBTIF1 0xFFC00A20 /* CAN0 Mailbox Transmit Interrupt Flag 1 Register */
|
|
#define REG_CAN0_MBRIF1 0xFFC00A24 /* CAN0 Mailbox Receive Interrupt Flag 1 Register */
|
|
#define REG_CAN0_MBIM1 0xFFC00A28 /* CAN0 Mailbox Interrupt Mask 1 Register */
|
|
#define REG_CAN0_RFH1 0xFFC00A2C /* CAN0 Remote Frame Handling 1 Register */
|
|
#define REG_CAN0_OPSS1 0xFFC00A30 /* CAN0 Overwrite Protection/Single Shot Transmission 1 Register */
|
|
#define REG_CAN0_MC2 0xFFC00A40 /* CAN0 Mailbox Configuration 2 Register */
|
|
#define REG_CAN0_MD2 0xFFC00A44 /* CAN0 Mailbox Direction 2 Register */
|
|
#define REG_CAN0_TRS2 0xFFC00A48 /* CAN0 Transmission Request Set 2 Register */
|
|
#define REG_CAN0_TRR2 0xFFC00A4C /* CAN0 Transmission Request Reset 2 Register */
|
|
#define REG_CAN0_TA2 0xFFC00A50 /* CAN0 Transmission Acknowledge 2 Register */
|
|
#define REG_CAN0_AA2 0xFFC00A54 /* CAN0 Abort Acknowledge 2 Register */
|
|
#define REG_CAN0_RMP2 0xFFC00A58 /* CAN0 Receive Message Pending 2 Register */
|
|
#define REG_CAN0_RML2 0xFFC00A5C /* CAN0 Receive Message Lost 2 Register */
|
|
#define REG_CAN0_MBTIF2 0xFFC00A60 /* CAN0 Mailbox Transmit Interrupt Flag 2 Register */
|
|
#define REG_CAN0_MBRIF2 0xFFC00A64 /* CAN0 Mailbox Receive Interrupt Flag 2 Register */
|
|
#define REG_CAN0_MBIM2 0xFFC00A68 /* CAN0 Mailbox Interrupt Mask 2 Register */
|
|
#define REG_CAN0_RFH2 0xFFC00A6C /* CAN0 Remote Frame Handling 2 Register */
|
|
#define REG_CAN0_OPSS2 0xFFC00A70 /* CAN0 Overwrite Protection/Single Shot Transmission 2 Register */
|
|
#define REG_CAN0_CLK 0xFFC00A80 /* CAN0 Clock Register */
|
|
#define REG_CAN0_TIMING 0xFFC00A84 /* CAN0 Timing Register */
|
|
#define REG_CAN0_DBG 0xFFC00A88 /* CAN0 Debug Register */
|
|
#define REG_CAN0_STAT 0xFFC00A8C /* CAN0 Status Register */
|
|
#define REG_CAN0_CEC 0xFFC00A90 /* CAN0 Error Counter Register */
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|
#define REG_CAN0_GIS 0xFFC00A94 /* CAN0 Global CAN Interrupt Status Register */
|
|
#define REG_CAN0_GIM 0xFFC00A98 /* CAN0 Global CAN Interrupt Mask Register */
|
|
#define REG_CAN0_GIF 0xFFC00A9C /* CAN0 Global CAN Interrupt Flag Register */
|
|
#define REG_CAN0_CTL 0xFFC00AA0 /* CAN0 CAN Master Control Register */
|
|
#define REG_CAN0_INT 0xFFC00AA4 /* CAN0 Interrupt Pending Register */
|
|
#define REG_CAN0_MBTD 0xFFC00AAC /* CAN0 Temporary Mailbox Disable Register */
|
|
#define REG_CAN0_EWR 0xFFC00AB0 /* CAN0 Error Counter Warning Level Register */
|
|
#define REG_CAN0_ESR 0xFFC00AB4 /* CAN0 Error Status Register */
|
|
#define REG_CAN0_UCCNT 0xFFC00AC4 /* CAN0 Universal Counter Register */
|
|
#define REG_CAN0_UCRC 0xFFC00AC8 /* CAN0 Universal Counter Reload/Capture Register */
|
|
#define REG_CAN0_UCCNF 0xFFC00ACC /* CAN0 Universal Counter Configuration Mode Register */
|
|
#define REG_CAN0_AM00L 0xFFC00B00 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM01L 0xFFC00B08 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM02L 0xFFC00B10 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM03L 0xFFC00B18 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM04L 0xFFC00B20 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM05L 0xFFC00B28 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM06L 0xFFC00B30 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM07L 0xFFC00B38 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM08L 0xFFC00B40 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM09L 0xFFC00B48 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM10L 0xFFC00B50 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM11L 0xFFC00B58 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM12L 0xFFC00B60 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM13L 0xFFC00B68 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM14L 0xFFC00B70 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM15L 0xFFC00B78 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM16L 0xFFC00B80 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM17L 0xFFC00B88 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM18L 0xFFC00B90 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM19L 0xFFC00B98 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM20L 0xFFC00BA0 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM21L 0xFFC00BA8 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM22L 0xFFC00BB0 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM23L 0xFFC00BB8 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM24L 0xFFC00BC0 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM25L 0xFFC00BC8 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM26L 0xFFC00BD0 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM27L 0xFFC00BD8 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM28L 0xFFC00BE0 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM29L 0xFFC00BE8 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM30L 0xFFC00BF0 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM31L 0xFFC00BF8 /* CAN0 Acceptance Mask (L) Register */
|
|
#define REG_CAN0_AM00H 0xFFC00B04 /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM01H 0xFFC00B0C /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM02H 0xFFC00B14 /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM03H 0xFFC00B1C /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM04H 0xFFC00B24 /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM05H 0xFFC00B2C /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM06H 0xFFC00B34 /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM07H 0xFFC00B3C /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM08H 0xFFC00B44 /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM09H 0xFFC00B4C /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM10H 0xFFC00B54 /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM11H 0xFFC00B5C /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM12H 0xFFC00B64 /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM13H 0xFFC00B6C /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM14H 0xFFC00B74 /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM15H 0xFFC00B7C /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM16H 0xFFC00B84 /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM17H 0xFFC00B8C /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM18H 0xFFC00B94 /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM19H 0xFFC00B9C /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM20H 0xFFC00BA4 /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM21H 0xFFC00BAC /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM22H 0xFFC00BB4 /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM23H 0xFFC00BBC /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM24H 0xFFC00BC4 /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM25H 0xFFC00BCC /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM26H 0xFFC00BD4 /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM27H 0xFFC00BDC /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM28H 0xFFC00BE4 /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM29H 0xFFC00BEC /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM30H 0xFFC00BF4 /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_AM31H 0xFFC00BFC /* CAN0 Acceptance Mask (H) Register */
|
|
#define REG_CAN0_MB00_DATA0 0xFFC00C00 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB01_DATA0 0xFFC00C20 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB02_DATA0 0xFFC00C40 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB03_DATA0 0xFFC00C60 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB04_DATA0 0xFFC00C80 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB05_DATA0 0xFFC00CA0 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB06_DATA0 0xFFC00CC0 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB07_DATA0 0xFFC00CE0 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB08_DATA0 0xFFC00D00 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB09_DATA0 0xFFC00D20 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB10_DATA0 0xFFC00D40 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB11_DATA0 0xFFC00D60 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB12_DATA0 0xFFC00D80 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB13_DATA0 0xFFC00DA0 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB14_DATA0 0xFFC00DC0 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB15_DATA0 0xFFC00DE0 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB16_DATA0 0xFFC00E00 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB17_DATA0 0xFFC00E20 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB18_DATA0 0xFFC00E40 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB19_DATA0 0xFFC00E60 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB20_DATA0 0xFFC00E80 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB21_DATA0 0xFFC00EA0 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB22_DATA0 0xFFC00EC0 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB23_DATA0 0xFFC00EE0 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB24_DATA0 0xFFC00F00 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB25_DATA0 0xFFC00F20 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB26_DATA0 0xFFC00F40 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB27_DATA0 0xFFC00F60 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB28_DATA0 0xFFC00F80 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB29_DATA0 0xFFC00FA0 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB30_DATA0 0xFFC00FC0 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB31_DATA0 0xFFC00FE0 /* CAN0 Mailbox Word 0 Register */
|
|
#define REG_CAN0_MB00_DATA1 0xFFC00C04 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB01_DATA1 0xFFC00C24 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB02_DATA1 0xFFC00C44 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB03_DATA1 0xFFC00C64 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB04_DATA1 0xFFC00C84 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB05_DATA1 0xFFC00CA4 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB06_DATA1 0xFFC00CC4 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB07_DATA1 0xFFC00CE4 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB08_DATA1 0xFFC00D04 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB09_DATA1 0xFFC00D24 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB10_DATA1 0xFFC00D44 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB11_DATA1 0xFFC00D64 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB12_DATA1 0xFFC00D84 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB13_DATA1 0xFFC00DA4 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB14_DATA1 0xFFC00DC4 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB15_DATA1 0xFFC00DE4 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB16_DATA1 0xFFC00E04 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB17_DATA1 0xFFC00E24 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB18_DATA1 0xFFC00E44 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB19_DATA1 0xFFC00E64 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB20_DATA1 0xFFC00E84 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB21_DATA1 0xFFC00EA4 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB22_DATA1 0xFFC00EC4 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB23_DATA1 0xFFC00EE4 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB24_DATA1 0xFFC00F04 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB25_DATA1 0xFFC00F24 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB26_DATA1 0xFFC00F44 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB27_DATA1 0xFFC00F64 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB28_DATA1 0xFFC00F84 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB29_DATA1 0xFFC00FA4 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB30_DATA1 0xFFC00FC4 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB31_DATA1 0xFFC00FE4 /* CAN0 Mailbox Word 1 Register */
|
|
#define REG_CAN0_MB00_DATA2 0xFFC00C08 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB01_DATA2 0xFFC00C28 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB02_DATA2 0xFFC00C48 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB03_DATA2 0xFFC00C68 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB04_DATA2 0xFFC00C88 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB05_DATA2 0xFFC00CA8 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB06_DATA2 0xFFC00CC8 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB07_DATA2 0xFFC00CE8 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB08_DATA2 0xFFC00D08 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB09_DATA2 0xFFC00D28 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB10_DATA2 0xFFC00D48 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB11_DATA2 0xFFC00D68 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB12_DATA2 0xFFC00D88 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB13_DATA2 0xFFC00DA8 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB14_DATA2 0xFFC00DC8 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB15_DATA2 0xFFC00DE8 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB16_DATA2 0xFFC00E08 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB17_DATA2 0xFFC00E28 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB18_DATA2 0xFFC00E48 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB19_DATA2 0xFFC00E68 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB20_DATA2 0xFFC00E88 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB21_DATA2 0xFFC00EA8 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB22_DATA2 0xFFC00EC8 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB23_DATA2 0xFFC00EE8 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB24_DATA2 0xFFC00F08 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB25_DATA2 0xFFC00F28 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB26_DATA2 0xFFC00F48 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB27_DATA2 0xFFC00F68 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB28_DATA2 0xFFC00F88 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB29_DATA2 0xFFC00FA8 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB30_DATA2 0xFFC00FC8 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB31_DATA2 0xFFC00FE8 /* CAN0 Mailbox Word 2 Register */
|
|
#define REG_CAN0_MB00_DATA3 0xFFC00C0C /* CAN0 Mailbox Word 3 Register */
|
|
#define REG_CAN0_MB01_DATA3 0xFFC00C2C /* CAN0 Mailbox Word 3 Register */
|
|
#define REG_CAN0_MB02_DATA3 0xFFC00C4C /* CAN0 Mailbox Word 3 Register */
|
|
#define REG_CAN0_MB03_DATA3 0xFFC00C6C /* CAN0 Mailbox Word 3 Register */
|
|
#define REG_CAN0_MB04_DATA3 0xFFC00C8C /* CAN0 Mailbox Word 3 Register */
|
|
#define REG_CAN0_MB05_DATA3 0xFFC00CAC /* CAN0 Mailbox Word 3 Register */
|
|
#define REG_CAN0_MB06_DATA3 0xFFC00CCC /* CAN0 Mailbox Word 3 Register */
|
|
#define REG_CAN0_MB07_DATA3 0xFFC00CEC /* CAN0 Mailbox Word 3 Register */
|
|
#define REG_CAN0_MB08_DATA3 0xFFC00D0C /* CAN0 Mailbox Word 3 Register */
|
|
#define REG_CAN0_MB09_DATA3 0xFFC00D2C /* CAN0 Mailbox Word 3 Register */
|
|
#define REG_CAN0_MB10_DATA3 0xFFC00D4C /* CAN0 Mailbox Word 3 Register */
|
|
#define REG_CAN0_MB11_DATA3 0xFFC00D6C /* CAN0 Mailbox Word 3 Register */
|
|
#define REG_CAN0_MB12_DATA3 0xFFC00D8C /* CAN0 Mailbox Word 3 Register */
|
|
#define REG_CAN0_MB13_DATA3 0xFFC00DAC /* CAN0 Mailbox Word 3 Register */
|
|
#define REG_CAN0_MB14_DATA3 0xFFC00DCC /* CAN0 Mailbox Word 3 Register */
|
|
#define REG_CAN0_MB15_DATA3 0xFFC00DEC /* CAN0 Mailbox Word 3 Register */
|
|
#define REG_CAN0_MB16_DATA3 0xFFC00E0C /* CAN0 Mailbox Word 3 Register */
|
|
#define REG_CAN0_MB17_DATA3 0xFFC00E2C /* CAN0 Mailbox Word 3 Register */
|
|
#define REG_CAN0_MB18_DATA3 0xFFC00E4C /* CAN0 Mailbox Word 3 Register */
|
|
#define REG_CAN0_MB19_DATA3 0xFFC00E6C /* CAN0 Mailbox Word 3 Register */
|
|
#define REG_CAN0_MB20_DATA3 0xFFC00E8C /* CAN0 Mailbox Word 3 Register */
|
|
#define REG_CAN0_MB21_DATA3 0xFFC00EAC /* CAN0 Mailbox Word 3 Register */
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|
#define REG_CAN0_MB22_DATA3 0xFFC00ECC /* CAN0 Mailbox Word 3 Register */
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#define REG_CAN0_MB23_DATA3 0xFFC00EEC /* CAN0 Mailbox Word 3 Register */
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#define REG_CAN0_MB24_DATA3 0xFFC00F0C /* CAN0 Mailbox Word 3 Register */
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#define REG_CAN0_MB25_DATA3 0xFFC00F2C /* CAN0 Mailbox Word 3 Register */
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#define REG_CAN0_MB26_DATA3 0xFFC00F4C /* CAN0 Mailbox Word 3 Register */
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#define REG_CAN0_MB27_DATA3 0xFFC00F6C /* CAN0 Mailbox Word 3 Register */
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|
#define REG_CAN0_MB28_DATA3 0xFFC00F8C /* CAN0 Mailbox Word 3 Register */
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|
#define REG_CAN0_MB29_DATA3 0xFFC00FAC /* CAN0 Mailbox Word 3 Register */
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#define REG_CAN0_MB30_DATA3 0xFFC00FCC /* CAN0 Mailbox Word 3 Register */
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#define REG_CAN0_MB31_DATA3 0xFFC00FEC /* CAN0 Mailbox Word 3 Register */
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#define REG_CAN0_MB00_LENGTH 0xFFC00C10 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB01_LENGTH 0xFFC00C30 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB02_LENGTH 0xFFC00C50 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB03_LENGTH 0xFFC00C70 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB04_LENGTH 0xFFC00C90 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB05_LENGTH 0xFFC00CB0 /* CAN0 Mailbox Length Register */
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|
#define REG_CAN0_MB06_LENGTH 0xFFC00CD0 /* CAN0 Mailbox Length Register */
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|
#define REG_CAN0_MB07_LENGTH 0xFFC00CF0 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB08_LENGTH 0xFFC00D10 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB09_LENGTH 0xFFC00D30 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB10_LENGTH 0xFFC00D50 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB11_LENGTH 0xFFC00D70 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB12_LENGTH 0xFFC00D90 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB13_LENGTH 0xFFC00DB0 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB14_LENGTH 0xFFC00DD0 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB15_LENGTH 0xFFC00DF0 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB16_LENGTH 0xFFC00E10 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB17_LENGTH 0xFFC00E30 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB18_LENGTH 0xFFC00E50 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB19_LENGTH 0xFFC00E70 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB20_LENGTH 0xFFC00E90 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB21_LENGTH 0xFFC00EB0 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB22_LENGTH 0xFFC00ED0 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB23_LENGTH 0xFFC00EF0 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB24_LENGTH 0xFFC00F10 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB25_LENGTH 0xFFC00F30 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB26_LENGTH 0xFFC00F50 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB27_LENGTH 0xFFC00F70 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB28_LENGTH 0xFFC00F90 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB29_LENGTH 0xFFC00FB0 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB30_LENGTH 0xFFC00FD0 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB31_LENGTH 0xFFC00FF0 /* CAN0 Mailbox Length Register */
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#define REG_CAN0_MB00_TIMESTAMP 0xFFC00C14 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB01_TIMESTAMP 0xFFC00C34 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB02_TIMESTAMP 0xFFC00C54 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB03_TIMESTAMP 0xFFC00C74 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB04_TIMESTAMP 0xFFC00C94 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB05_TIMESTAMP 0xFFC00CB4 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB06_TIMESTAMP 0xFFC00CD4 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB07_TIMESTAMP 0xFFC00CF4 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB08_TIMESTAMP 0xFFC00D14 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB09_TIMESTAMP 0xFFC00D34 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB10_TIMESTAMP 0xFFC00D54 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB11_TIMESTAMP 0xFFC00D74 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB12_TIMESTAMP 0xFFC00D94 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB13_TIMESTAMP 0xFFC00DB4 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB14_TIMESTAMP 0xFFC00DD4 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB15_TIMESTAMP 0xFFC00DF4 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB16_TIMESTAMP 0xFFC00E14 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB17_TIMESTAMP 0xFFC00E34 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB18_TIMESTAMP 0xFFC00E54 /* CAN0 Mailbox Timestamp Register */
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|
#define REG_CAN0_MB19_TIMESTAMP 0xFFC00E74 /* CAN0 Mailbox Timestamp Register */
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|
#define REG_CAN0_MB20_TIMESTAMP 0xFFC00E94 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB21_TIMESTAMP 0xFFC00EB4 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB22_TIMESTAMP 0xFFC00ED4 /* CAN0 Mailbox Timestamp Register */
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|
#define REG_CAN0_MB23_TIMESTAMP 0xFFC00EF4 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB24_TIMESTAMP 0xFFC00F14 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB25_TIMESTAMP 0xFFC00F34 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB26_TIMESTAMP 0xFFC00F54 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB27_TIMESTAMP 0xFFC00F74 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB28_TIMESTAMP 0xFFC00F94 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB29_TIMESTAMP 0xFFC00FB4 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB30_TIMESTAMP 0xFFC00FD4 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB31_TIMESTAMP 0xFFC00FF4 /* CAN0 Mailbox Timestamp Register */
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#define REG_CAN0_MB00_ID0 0xFFC00C18 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB01_ID0 0xFFC00C38 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB02_ID0 0xFFC00C58 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB03_ID0 0xFFC00C78 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB04_ID0 0xFFC00C98 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB05_ID0 0xFFC00CB8 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB06_ID0 0xFFC00CD8 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB07_ID0 0xFFC00CF8 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB08_ID0 0xFFC00D18 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB09_ID0 0xFFC00D38 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB10_ID0 0xFFC00D58 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB11_ID0 0xFFC00D78 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB12_ID0 0xFFC00D98 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB13_ID0 0xFFC00DB8 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB14_ID0 0xFFC00DD8 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB15_ID0 0xFFC00DF8 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB16_ID0 0xFFC00E18 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB17_ID0 0xFFC00E38 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB18_ID0 0xFFC00E58 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB19_ID0 0xFFC00E78 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB20_ID0 0xFFC00E98 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB21_ID0 0xFFC00EB8 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB22_ID0 0xFFC00ED8 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB23_ID0 0xFFC00EF8 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB24_ID0 0xFFC00F18 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB25_ID0 0xFFC00F38 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB26_ID0 0xFFC00F58 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB27_ID0 0xFFC00F78 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB28_ID0 0xFFC00F98 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB29_ID0 0xFFC00FB8 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB30_ID0 0xFFC00FD8 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB31_ID0 0xFFC00FF8 /* CAN0 Mailbox ID 0 Register */
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#define REG_CAN0_MB00_ID1 0xFFC00C1C /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB01_ID1 0xFFC00C3C /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB02_ID1 0xFFC00C5C /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB03_ID1 0xFFC00C7C /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB04_ID1 0xFFC00C9C /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB05_ID1 0xFFC00CBC /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB06_ID1 0xFFC00CDC /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB07_ID1 0xFFC00CFC /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB08_ID1 0xFFC00D1C /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB09_ID1 0xFFC00D3C /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB10_ID1 0xFFC00D5C /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB11_ID1 0xFFC00D7C /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB12_ID1 0xFFC00D9C /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB13_ID1 0xFFC00DBC /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB14_ID1 0xFFC00DDC /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB15_ID1 0xFFC00DFC /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB16_ID1 0xFFC00E1C /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB17_ID1 0xFFC00E3C /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB18_ID1 0xFFC00E5C /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB19_ID1 0xFFC00E7C /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB20_ID1 0xFFC00E9C /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB21_ID1 0xFFC00EBC /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB22_ID1 0xFFC00EDC /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB23_ID1 0xFFC00EFC /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB24_ID1 0xFFC00F1C /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB25_ID1 0xFFC00F3C /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB26_ID1 0xFFC00F5C /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB27_ID1 0xFFC00F7C /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB28_ID1 0xFFC00F9C /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB29_ID1 0xFFC00FBC /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB30_ID1 0xFFC00FDC /* CAN0 Mailbox ID 1 Register */
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#define REG_CAN0_MB31_ID1 0xFFC00FFC /* CAN0 Mailbox ID 1 Register */
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|
/* =========================
|
|
CAN
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_MC1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_CAN_MC1_MB00 0 /* Mailbox n Enable/Disable */
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#define BITP_CAN_MC1_MB01 1 /* Mailbox n Enable/Disable */
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#define BITP_CAN_MC1_MB02 2 /* Mailbox n Enable/Disable */
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#define BITP_CAN_MC1_MB03 3 /* Mailbox n Enable/Disable */
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#define BITP_CAN_MC1_MB04 4 /* Mailbox n Enable/Disable */
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#define BITP_CAN_MC1_MB05 5 /* Mailbox n Enable/Disable */
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#define BITP_CAN_MC1_MB06 6 /* Mailbox n Enable/Disable */
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#define BITP_CAN_MC1_MB07 7 /* Mailbox n Enable/Disable */
|
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#define BITP_CAN_MC1_MB08 8 /* Mailbox n Enable/Disable */
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#define BITP_CAN_MC1_MB09 9 /* Mailbox n Enable/Disable */
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#define BITP_CAN_MC1_MB10 10 /* Mailbox n Enable/Disable */
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#define BITP_CAN_MC1_MB11 11 /* Mailbox n Enable/Disable */
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#define BITP_CAN_MC1_MB12 12 /* Mailbox n Enable/Disable */
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#define BITP_CAN_MC1_MB13 13 /* Mailbox n Enable/Disable */
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#define BITP_CAN_MC1_MB14 14 /* Mailbox n Enable/Disable */
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#define BITP_CAN_MC1_MB15 15 /* Mailbox n Enable/Disable */
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#define BITM_CAN_MC1_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Enable/Disable */
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#define BITM_CAN_MC1_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Enable/Disable */
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#define BITM_CAN_MC1_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Enable/Disable */
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#define BITM_CAN_MC1_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Enable/Disable */
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#define BITM_CAN_MC1_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Enable/Disable */
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#define BITM_CAN_MC1_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Enable/Disable */
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|
#define BITM_CAN_MC1_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Enable/Disable */
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#define BITM_CAN_MC1_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Enable/Disable */
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|
#define BITM_CAN_MC1_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Enable/Disable */
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#define BITM_CAN_MC1_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Enable/Disable */
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#define BITM_CAN_MC1_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Enable/Disable */
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#define BITM_CAN_MC1_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Enable/Disable */
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#define BITM_CAN_MC1_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Enable/Disable */
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#define BITM_CAN_MC1_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Enable/Disable */
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#define BITM_CAN_MC1_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Enable/Disable */
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|
#define BITM_CAN_MC1_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Enable/Disable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_MD1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_MD1_MB00 0 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD1_MB01 1 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD1_MB02 2 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD1_MB03 3 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD1_MB04 4 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD1_MB05 5 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD1_MB06 6 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD1_MB07 7 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD1_MB08 8 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD1_MB09 9 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD1_MB10 10 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD1_MB11 11 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD1_MB12 12 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD1_MB13 13 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD1_MB14 14 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD1_MB15 15 /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD1_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD1_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD1_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD1_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD1_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD1_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD1_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD1_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD1_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD1_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD1_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD1_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD1_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD1_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD1_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD1_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_TRS1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_TRS1_MB00 0 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS1_MB01 1 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS1_MB02 2 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS1_MB03 3 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS1_MB04 4 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS1_MB05 5 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS1_MB06 6 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS1_MB07 7 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS1_MB08 8 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS1_MB09 9 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS1_MB10 10 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS1_MB11 11 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS1_MB12 12 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS1_MB13 13 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS1_MB14 14 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS1_MB15 15 /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS1_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS1_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS1_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS1_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS1_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS1_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS1_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS1_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS1_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS1_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS1_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS1_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS1_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS1_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS1_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS1_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Transmit Request */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_TRR1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_TRR1_MB00 0 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR1_MB01 1 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR1_MB02 2 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR1_MB03 3 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR1_MB04 4 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR1_MB05 5 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR1_MB06 6 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR1_MB07 7 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR1_MB08 8 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR1_MB09 9 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR1_MB10 10 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR1_MB11 11 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR1_MB12 12 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR1_MB13 13 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR1_MB14 14 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR1_MB15 15 /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR1_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR1_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR1_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR1_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR1_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR1_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR1_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR1_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR1_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR1_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR1_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR1_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR1_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR1_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR1_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR1_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Transmit Abort */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_TA1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_TA1_MB00 0 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA1_MB01 1 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA1_MB02 2 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA1_MB03 3 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA1_MB04 4 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA1_MB05 5 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA1_MB06 6 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA1_MB07 7 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA1_MB08 8 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA1_MB09 9 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA1_MB10 10 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA1_MB11 11 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA1_MB12 12 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA1_MB13 13 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA1_MB14 14 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA1_MB15 15 /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA1_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA1_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA1_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA1_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA1_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA1_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA1_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA1_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA1_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA1_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA1_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA1_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA1_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA1_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA1_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA1_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_AA1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_AA1_MB00 0 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA1_MB01 1 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA1_MB02 2 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA1_MB03 3 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA1_MB04 4 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA1_MB05 5 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA1_MB06 6 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA1_MB07 7 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA1_MB08 8 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA1_MB09 9 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA1_MB10 10 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA1_MB11 11 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA1_MB12 12 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA1_MB13 13 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA1_MB14 14 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA1_MB15 15 /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA1_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA1_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA1_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA1_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA1_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Abort Acknowledge */
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|
#define BITM_CAN_AA1_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA1_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA1_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA1_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Abort Acknowledge */
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|
#define BITM_CAN_AA1_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA1_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA1_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA1_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA1_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA1_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA1_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_RMP1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_RMP1_MB00 0 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP1_MB01 1 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP1_MB02 2 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP1_MB03 3 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP1_MB04 4 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP1_MB05 5 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP1_MB06 6 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP1_MB07 7 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP1_MB08 8 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP1_MB09 9 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP1_MB10 10 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP1_MB11 11 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP1_MB12 12 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP1_MB13 13 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP1_MB14 14 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP1_MB15 15 /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP1_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP1_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP1_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP1_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP1_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP1_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP1_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP1_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP1_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP1_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP1_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP1_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP1_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP1_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP1_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP1_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Message Pending */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_RML1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_RML1_MB00 0 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML1_MB01 1 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML1_MB02 2 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML1_MB03 3 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML1_MB04 4 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML1_MB05 5 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML1_MB06 6 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML1_MB07 7 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML1_MB08 8 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML1_MB09 9 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML1_MB10 10 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML1_MB11 11 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML1_MB12 12 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML1_MB13 13 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML1_MB14 14 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML1_MB15 15 /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML1_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML1_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML1_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML1_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML1_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML1_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML1_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML1_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML1_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML1_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML1_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML1_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML1_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML1_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML1_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML1_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Message Lost */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_MBTIF1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_MBTIF1_MB00 0 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF1_MB01 1 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF1_MB02 2 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF1_MB03 3 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF1_MB04 4 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF1_MB05 5 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF1_MB06 6 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF1_MB07 7 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF1_MB08 8 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF1_MB09 9 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF1_MB10 10 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF1_MB11 11 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF1_MB12 12 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF1_MB13 13 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF1_MB14 14 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF1_MB15 15 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF1_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF1_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF1_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF1_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF1_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF1_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF1_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF1_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF1_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF1_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF1_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF1_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF1_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF1_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF1_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF1_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_MBRIF1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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|
#define BITP_CAN_MBRIF1_MB00 0 /* Mailbox n Receive Interrupt Pending */
|
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#define BITP_CAN_MBRIF1_MB01 1 /* Mailbox n Receive Interrupt Pending */
|
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#define BITP_CAN_MBRIF1_MB02 2 /* Mailbox n Receive Interrupt Pending */
|
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#define BITP_CAN_MBRIF1_MB03 3 /* Mailbox n Receive Interrupt Pending */
|
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#define BITP_CAN_MBRIF1_MB04 4 /* Mailbox n Receive Interrupt Pending */
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|
#define BITP_CAN_MBRIF1_MB05 5 /* Mailbox n Receive Interrupt Pending */
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#define BITP_CAN_MBRIF1_MB06 6 /* Mailbox n Receive Interrupt Pending */
|
|
#define BITP_CAN_MBRIF1_MB07 7 /* Mailbox n Receive Interrupt Pending */
|
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#define BITP_CAN_MBRIF1_MB08 8 /* Mailbox n Receive Interrupt Pending */
|
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#define BITP_CAN_MBRIF1_MB09 9 /* Mailbox n Receive Interrupt Pending */
|
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#define BITP_CAN_MBRIF1_MB10 10 /* Mailbox n Receive Interrupt Pending */
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#define BITP_CAN_MBRIF1_MB11 11 /* Mailbox n Receive Interrupt Pending */
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#define BITP_CAN_MBRIF1_MB12 12 /* Mailbox n Receive Interrupt Pending */
|
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#define BITP_CAN_MBRIF1_MB13 13 /* Mailbox n Receive Interrupt Pending */
|
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#define BITP_CAN_MBRIF1_MB14 14 /* Mailbox n Receive Interrupt Pending */
|
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#define BITP_CAN_MBRIF1_MB15 15 /* Mailbox n Receive Interrupt Pending */
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#define BITM_CAN_MBRIF1_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Receive Interrupt Pending */
|
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#define BITM_CAN_MBRIF1_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Receive Interrupt Pending */
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#define BITM_CAN_MBRIF1_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Receive Interrupt Pending */
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#define BITM_CAN_MBRIF1_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Receive Interrupt Pending */
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#define BITM_CAN_MBRIF1_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Receive Interrupt Pending */
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#define BITM_CAN_MBRIF1_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Receive Interrupt Pending */
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#define BITM_CAN_MBRIF1_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Receive Interrupt Pending */
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#define BITM_CAN_MBRIF1_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Receive Interrupt Pending */
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#define BITM_CAN_MBRIF1_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Receive Interrupt Pending */
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#define BITM_CAN_MBRIF1_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Receive Interrupt Pending */
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|
#define BITM_CAN_MBRIF1_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Receive Interrupt Pending */
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#define BITM_CAN_MBRIF1_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Receive Interrupt Pending */
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#define BITM_CAN_MBRIF1_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Receive Interrupt Pending */
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#define BITM_CAN_MBRIF1_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Receive Interrupt Pending */
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#define BITM_CAN_MBRIF1_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Receive Interrupt Pending */
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#define BITM_CAN_MBRIF1_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Receive Interrupt Pending */
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|
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_MBIM1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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|
#define BITP_CAN_MBIM1_MB00 0 /* Mailbox n Transmit and Receive Interrupt Enable */
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#define BITP_CAN_MBIM1_MB01 1 /* Mailbox n Transmit and Receive Interrupt Enable */
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#define BITP_CAN_MBIM1_MB02 2 /* Mailbox n Transmit and Receive Interrupt Enable */
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#define BITP_CAN_MBIM1_MB03 3 /* Mailbox n Transmit and Receive Interrupt Enable */
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#define BITP_CAN_MBIM1_MB04 4 /* Mailbox n Transmit and Receive Interrupt Enable */
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#define BITP_CAN_MBIM1_MB05 5 /* Mailbox n Transmit and Receive Interrupt Enable */
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|
#define BITP_CAN_MBIM1_MB06 6 /* Mailbox n Transmit and Receive Interrupt Enable */
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#define BITP_CAN_MBIM1_MB07 7 /* Mailbox n Transmit and Receive Interrupt Enable */
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#define BITP_CAN_MBIM1_MB08 8 /* Mailbox n Transmit and Receive Interrupt Enable */
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|
#define BITP_CAN_MBIM1_MB09 9 /* Mailbox n Transmit and Receive Interrupt Enable */
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|
#define BITP_CAN_MBIM1_MB10 10 /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITP_CAN_MBIM1_MB11 11 /* Mailbox n Transmit and Receive Interrupt Enable */
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|
#define BITP_CAN_MBIM1_MB12 12 /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITP_CAN_MBIM1_MB13 13 /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITP_CAN_MBIM1_MB14 14 /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITP_CAN_MBIM1_MB15 15 /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM1_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
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#define BITM_CAN_MBIM1_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
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#define BITM_CAN_MBIM1_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM1_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM1_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM1_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM1_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
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|
#define BITM_CAN_MBIM1_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
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|
#define BITM_CAN_MBIM1_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM1_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM1_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
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|
#define BITM_CAN_MBIM1_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM1_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
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|
#define BITM_CAN_MBIM1_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM1_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM1_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_RFH1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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|
#define BITP_CAN_RFH1_MB00 0 /* Mailbox n Remote Frame Handling Enable */
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#define BITP_CAN_RFH1_MB01 1 /* Mailbox n Remote Frame Handling Enable */
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|
#define BITP_CAN_RFH1_MB02 2 /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITP_CAN_RFH1_MB03 3 /* Mailbox n Remote Frame Handling Enable */
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|
#define BITP_CAN_RFH1_MB04 4 /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITP_CAN_RFH1_MB05 5 /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITP_CAN_RFH1_MB06 6 /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITP_CAN_RFH1_MB07 7 /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITP_CAN_RFH1_MB08 8 /* Mailbox n Remote Frame Handling Enable */
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#define BITP_CAN_RFH1_MB09 9 /* Mailbox n Remote Frame Handling Enable */
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#define BITP_CAN_RFH1_MB10 10 /* Mailbox n Remote Frame Handling Enable */
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|
#define BITP_CAN_RFH1_MB11 11 /* Mailbox n Remote Frame Handling Enable */
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#define BITP_CAN_RFH1_MB12 12 /* Mailbox n Remote Frame Handling Enable */
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#define BITP_CAN_RFH1_MB13 13 /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITP_CAN_RFH1_MB14 14 /* Mailbox n Remote Frame Handling Enable */
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|
#define BITP_CAN_RFH1_MB15 15 /* Mailbox n Remote Frame Handling Enable */
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#define BITM_CAN_RFH1_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
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|
#define BITM_CAN_RFH1_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
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|
#define BITM_CAN_RFH1_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
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#define BITM_CAN_RFH1_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
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#define BITM_CAN_RFH1_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
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#define BITM_CAN_RFH1_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
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#define BITM_CAN_RFH1_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
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#define BITM_CAN_RFH1_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
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#define BITM_CAN_RFH1_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
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#define BITM_CAN_RFH1_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
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#define BITM_CAN_RFH1_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
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#define BITM_CAN_RFH1_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
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#define BITM_CAN_RFH1_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
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#define BITM_CAN_RFH1_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
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#define BITM_CAN_RFH1_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
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#define BITM_CAN_RFH1_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
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|
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_OPSS1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_CAN_OPSS1_MB00 0 /* Mailbox n Overwrite Protection Enable */
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#define BITP_CAN_OPSS1_MB01 1 /* Mailbox n Overwrite Protection Enable */
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#define BITP_CAN_OPSS1_MB02 2 /* Mailbox n Overwrite Protection Enable */
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#define BITP_CAN_OPSS1_MB03 3 /* Mailbox n Overwrite Protection Enable */
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#define BITP_CAN_OPSS1_MB04 4 /* Mailbox n Overwrite Protection Enable */
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#define BITP_CAN_OPSS1_MB05 5 /* Mailbox n Overwrite Protection Enable */
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#define BITP_CAN_OPSS1_MB06 6 /* Mailbox n Overwrite Protection Enable */
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#define BITP_CAN_OPSS1_MB07 7 /* Mailbox n Overwrite Protection Enable */
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#define BITP_CAN_OPSS1_MB08 8 /* Mailbox n Overwrite Protection Enable */
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#define BITP_CAN_OPSS1_MB09 9 /* Mailbox n Overwrite Protection Enable */
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#define BITP_CAN_OPSS1_MB10 10 /* Mailbox n Overwrite Protection Enable */
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#define BITP_CAN_OPSS1_MB11 11 /* Mailbox n Overwrite Protection Enable */
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#define BITP_CAN_OPSS1_MB12 12 /* Mailbox n Overwrite Protection Enable */
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#define BITP_CAN_OPSS1_MB13 13 /* Mailbox n Overwrite Protection Enable */
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#define BITP_CAN_OPSS1_MB14 14 /* Mailbox n Overwrite Protection Enable */
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#define BITP_CAN_OPSS1_MB15 15 /* Mailbox n Overwrite Protection Enable */
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#define BITM_CAN_OPSS1_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Overwrite Protection Enable */
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#define BITM_CAN_OPSS1_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Overwrite Protection Enable */
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#define BITM_CAN_OPSS1_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Overwrite Protection Enable */
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#define BITM_CAN_OPSS1_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Overwrite Protection Enable */
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#define BITM_CAN_OPSS1_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Overwrite Protection Enable */
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#define BITM_CAN_OPSS1_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Overwrite Protection Enable */
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#define BITM_CAN_OPSS1_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Overwrite Protection Enable */
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#define BITM_CAN_OPSS1_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Overwrite Protection Enable */
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#define BITM_CAN_OPSS1_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Overwrite Protection Enable */
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#define BITM_CAN_OPSS1_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Overwrite Protection Enable */
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#define BITM_CAN_OPSS1_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Overwrite Protection Enable */
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#define BITM_CAN_OPSS1_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Overwrite Protection Enable */
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#define BITM_CAN_OPSS1_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Overwrite Protection Enable */
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#define BITM_CAN_OPSS1_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Overwrite Protection Enable */
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#define BITM_CAN_OPSS1_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Overwrite Protection Enable */
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|
#define BITM_CAN_OPSS1_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Overwrite Protection Enable */
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|
|
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_MC2 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_MC2_MB00 0 /* Mailbox n Enable/Disable */
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#define BITP_CAN_MC2_MB01 1 /* Mailbox n Enable/Disable */
|
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#define BITP_CAN_MC2_MB02 2 /* Mailbox n Enable/Disable */
|
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#define BITP_CAN_MC2_MB03 3 /* Mailbox n Enable/Disable */
|
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#define BITP_CAN_MC2_MB04 4 /* Mailbox n Enable/Disable */
|
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#define BITP_CAN_MC2_MB05 5 /* Mailbox n Enable/Disable */
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#define BITP_CAN_MC2_MB06 6 /* Mailbox n Enable/Disable */
|
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#define BITP_CAN_MC2_MB07 7 /* Mailbox n Enable/Disable */
|
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#define BITP_CAN_MC2_MB08 8 /* Mailbox n Enable/Disable */
|
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#define BITP_CAN_MC2_MB09 9 /* Mailbox n Enable/Disable */
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#define BITP_CAN_MC2_MB10 10 /* Mailbox n Enable/Disable */
|
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#define BITP_CAN_MC2_MB11 11 /* Mailbox n Enable/Disable */
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#define BITP_CAN_MC2_MB12 12 /* Mailbox n Enable/Disable */
|
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#define BITP_CAN_MC2_MB13 13 /* Mailbox n Enable/Disable */
|
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#define BITP_CAN_MC2_MB14 14 /* Mailbox n Enable/Disable */
|
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#define BITP_CAN_MC2_MB15 15 /* Mailbox n Enable/Disable */
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#define BITM_CAN_MC2_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Enable/Disable */
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#define BITM_CAN_MC2_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Enable/Disable */
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#define BITM_CAN_MC2_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Enable/Disable */
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#define BITM_CAN_MC2_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Enable/Disable */
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#define BITM_CAN_MC2_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Enable/Disable */
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#define BITM_CAN_MC2_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Enable/Disable */
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#define BITM_CAN_MC2_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Enable/Disable */
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|
#define BITM_CAN_MC2_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Enable/Disable */
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#define BITM_CAN_MC2_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Enable/Disable */
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#define BITM_CAN_MC2_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Enable/Disable */
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#define BITM_CAN_MC2_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Enable/Disable */
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#define BITM_CAN_MC2_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Enable/Disable */
|
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#define BITM_CAN_MC2_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Enable/Disable */
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|
#define BITM_CAN_MC2_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Enable/Disable */
|
|
#define BITM_CAN_MC2_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Enable/Disable */
|
|
#define BITM_CAN_MC2_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Enable/Disable */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_MD2 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_MD2_MB00 0 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD2_MB01 1 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD2_MB02 2 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD2_MB03 3 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD2_MB04 4 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD2_MB05 5 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD2_MB06 6 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD2_MB07 7 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD2_MB08 8 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD2_MB09 9 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD2_MB10 10 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD2_MB11 11 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD2_MB12 12 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD2_MB13 13 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD2_MB14 14 /* Mailbox n Transmit/Receive */
|
|
#define BITP_CAN_MD2_MB15 15 /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD2_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD2_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD2_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD2_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD2_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD2_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD2_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD2_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD2_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD2_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD2_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD2_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD2_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD2_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD2_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
#define BITM_CAN_MD2_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Transmit/Receive */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_TRS2 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_TRS2_MB00 0 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS2_MB01 1 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS2_MB02 2 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS2_MB03 3 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS2_MB04 4 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS2_MB05 5 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS2_MB06 6 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS2_MB07 7 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS2_MB08 8 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS2_MB09 9 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS2_MB10 10 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS2_MB11 11 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS2_MB12 12 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS2_MB13 13 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS2_MB14 14 /* Mailbox n Transmit Request */
|
|
#define BITP_CAN_TRS2_MB15 15 /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS2_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS2_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS2_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS2_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS2_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS2_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS2_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS2_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS2_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS2_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS2_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS2_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS2_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS2_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS2_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Transmit Request */
|
|
#define BITM_CAN_TRS2_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Transmit Request */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_TRR2 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_TRR2_MB00 0 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR2_MB01 1 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR2_MB02 2 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR2_MB03 3 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR2_MB04 4 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR2_MB05 5 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR2_MB06 6 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR2_MB07 7 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR2_MB08 8 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR2_MB09 9 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR2_MB10 10 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR2_MB11 11 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR2_MB12 12 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR2_MB13 13 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR2_MB14 14 /* Mailbox n Transmit Abort */
|
|
#define BITP_CAN_TRR2_MB15 15 /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR2_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR2_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR2_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR2_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR2_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR2_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR2_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR2_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR2_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR2_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR2_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR2_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR2_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR2_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR2_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Transmit Abort */
|
|
#define BITM_CAN_TRR2_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Transmit Abort */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_TA2 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_TA2_MB00 0 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA2_MB01 1 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA2_MB02 2 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA2_MB03 3 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA2_MB04 4 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA2_MB05 5 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA2_MB06 6 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA2_MB07 7 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA2_MB08 8 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA2_MB09 9 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA2_MB10 10 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA2_MB11 11 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA2_MB12 12 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA2_MB13 13 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA2_MB14 14 /* Mailbox n Transmit Acknowledge */
|
|
#define BITP_CAN_TA2_MB15 15 /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA2_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA2_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA2_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA2_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA2_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA2_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA2_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA2_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA2_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA2_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA2_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA2_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA2_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA2_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA2_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
#define BITM_CAN_TA2_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Transmit Acknowledge */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_AA2 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_AA2_MB00 0 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA2_MB01 1 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA2_MB02 2 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA2_MB03 3 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA2_MB04 4 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA2_MB05 5 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA2_MB06 6 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA2_MB07 7 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA2_MB08 8 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA2_MB09 9 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA2_MB10 10 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA2_MB11 11 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA2_MB12 12 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA2_MB13 13 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA2_MB14 14 /* Mailbox n Abort Acknowledge */
|
|
#define BITP_CAN_AA2_MB15 15 /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA2_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA2_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA2_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA2_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA2_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA2_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA2_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA2_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA2_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA2_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA2_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA2_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA2_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA2_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA2_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
#define BITM_CAN_AA2_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Abort Acknowledge */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_RMP2 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_RMP2_MB00 0 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP2_MB01 1 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP2_MB02 2 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP2_MB03 3 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP2_MB04 4 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP2_MB05 5 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP2_MB06 6 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP2_MB07 7 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP2_MB08 8 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP2_MB09 9 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP2_MB10 10 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP2_MB11 11 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP2_MB12 12 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP2_MB13 13 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP2_MB14 14 /* Mailbox n Message Pending */
|
|
#define BITP_CAN_RMP2_MB15 15 /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP2_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP2_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP2_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP2_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP2_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP2_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP2_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP2_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP2_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP2_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP2_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP2_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP2_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP2_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP2_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Message Pending */
|
|
#define BITM_CAN_RMP2_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Message Pending */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_RML2 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_RML2_MB00 0 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML2_MB01 1 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML2_MB02 2 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML2_MB03 3 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML2_MB04 4 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML2_MB05 5 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML2_MB06 6 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML2_MB07 7 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML2_MB08 8 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML2_MB09 9 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML2_MB10 10 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML2_MB11 11 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML2_MB12 12 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML2_MB13 13 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML2_MB14 14 /* Mailbox n Message Lost */
|
|
#define BITP_CAN_RML2_MB15 15 /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML2_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML2_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML2_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML2_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML2_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML2_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML2_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML2_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML2_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML2_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML2_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML2_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML2_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML2_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML2_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Message Lost */
|
|
#define BITM_CAN_RML2_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Message Lost */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_MBTIF2 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_MBTIF2_MB00 0 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF2_MB01 1 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF2_MB02 2 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF2_MB03 3 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF2_MB04 4 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF2_MB05 5 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF2_MB06 6 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF2_MB07 7 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF2_MB08 8 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF2_MB09 9 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF2_MB10 10 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF2_MB11 11 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF2_MB12 12 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF2_MB13 13 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF2_MB14 14 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITP_CAN_MBTIF2_MB15 15 /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF2_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF2_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF2_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF2_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF2_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF2_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF2_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF2_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF2_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF2_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF2_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF2_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF2_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF2_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF2_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
#define BITM_CAN_MBTIF2_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Transmit Interrupt Pending */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_MBRIF2 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_MBRIF2_MB00 0 /* Mailbox n Receive Interrupt Pending */
|
|
#define BITP_CAN_MBRIF2_MB01 1 /* Mailbox n Receive Interrupt Pending */
|
|
#define BITP_CAN_MBRIF2_MB02 2 /* Mailbox n Receive Interrupt Pending */
|
|
#define BITP_CAN_MBRIF2_MB03 3 /* Mailbox n Receive Interrupt Pending */
|
|
#define BITP_CAN_MBRIF2_MB04 4 /* Mailbox n Receive Interrupt Pending */
|
|
#define BITP_CAN_MBRIF2_MB05 5 /* Mailbox n Receive Interrupt Pending */
|
|
#define BITP_CAN_MBRIF2_MB06 6 /* Mailbox n Receive Interrupt Pending */
|
|
#define BITP_CAN_MBRIF2_MB07 7 /* Mailbox n Receive Interrupt Pending */
|
|
#define BITP_CAN_MBRIF2_MB08 8 /* Mailbox n Receive Interrupt Pending */
|
|
#define BITP_CAN_MBRIF2_MB09 9 /* Mailbox n Receive Interrupt Pending */
|
|
#define BITP_CAN_MBRIF2_MB10 10 /* Mailbox n Receive Interrupt Pending */
|
|
#define BITP_CAN_MBRIF2_MB11 11 /* Mailbox n Receive Interrupt Pending */
|
|
#define BITP_CAN_MBRIF2_MB12 12 /* Mailbox n Receive Interrupt Pending */
|
|
#define BITP_CAN_MBRIF2_MB13 13 /* Mailbox n Receive Interrupt Pending */
|
|
#define BITP_CAN_MBRIF2_MB14 14 /* Mailbox n Receive Interrupt Pending */
|
|
#define BITP_CAN_MBRIF2_MB15 15 /* Mailbox n Receive Interrupt Pending */
|
|
#define BITM_CAN_MBRIF2_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Receive Interrupt Pending */
|
|
#define BITM_CAN_MBRIF2_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Receive Interrupt Pending */
|
|
#define BITM_CAN_MBRIF2_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Receive Interrupt Pending */
|
|
#define BITM_CAN_MBRIF2_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Receive Interrupt Pending */
|
|
#define BITM_CAN_MBRIF2_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Receive Interrupt Pending */
|
|
#define BITM_CAN_MBRIF2_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Receive Interrupt Pending */
|
|
#define BITM_CAN_MBRIF2_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Receive Interrupt Pending */
|
|
#define BITM_CAN_MBRIF2_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Receive Interrupt Pending */
|
|
#define BITM_CAN_MBRIF2_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Receive Interrupt Pending */
|
|
#define BITM_CAN_MBRIF2_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Receive Interrupt Pending */
|
|
#define BITM_CAN_MBRIF2_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Receive Interrupt Pending */
|
|
#define BITM_CAN_MBRIF2_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Receive Interrupt Pending */
|
|
#define BITM_CAN_MBRIF2_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Receive Interrupt Pending */
|
|
#define BITM_CAN_MBRIF2_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Receive Interrupt Pending */
|
|
#define BITM_CAN_MBRIF2_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Receive Interrupt Pending */
|
|
#define BITM_CAN_MBRIF2_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Receive Interrupt Pending */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_MBIM2 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_MBIM2_MB00 0 /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITP_CAN_MBIM2_MB01 1 /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITP_CAN_MBIM2_MB02 2 /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITP_CAN_MBIM2_MB03 3 /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITP_CAN_MBIM2_MB04 4 /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITP_CAN_MBIM2_MB05 5 /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITP_CAN_MBIM2_MB06 6 /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITP_CAN_MBIM2_MB07 7 /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITP_CAN_MBIM2_MB08 8 /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITP_CAN_MBIM2_MB09 9 /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITP_CAN_MBIM2_MB10 10 /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITP_CAN_MBIM2_MB11 11 /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITP_CAN_MBIM2_MB12 12 /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITP_CAN_MBIM2_MB13 13 /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITP_CAN_MBIM2_MB14 14 /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITP_CAN_MBIM2_MB15 15 /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM2_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM2_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM2_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM2_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM2_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM2_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM2_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM2_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM2_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM2_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM2_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM2_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM2_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM2_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM2_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
#define BITM_CAN_MBIM2_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Transmit and Receive Interrupt Enable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_RFH2 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_RFH2_MB00 0 /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITP_CAN_RFH2_MB01 1 /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITP_CAN_RFH2_MB02 2 /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITP_CAN_RFH2_MB03 3 /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITP_CAN_RFH2_MB04 4 /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITP_CAN_RFH2_MB05 5 /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITP_CAN_RFH2_MB06 6 /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITP_CAN_RFH2_MB07 7 /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITP_CAN_RFH2_MB08 8 /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITP_CAN_RFH2_MB09 9 /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITP_CAN_RFH2_MB10 10 /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITP_CAN_RFH2_MB11 11 /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITP_CAN_RFH2_MB12 12 /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITP_CAN_RFH2_MB13 13 /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITP_CAN_RFH2_MB14 14 /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITP_CAN_RFH2_MB15 15 /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITM_CAN_RFH2_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITM_CAN_RFH2_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITM_CAN_RFH2_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITM_CAN_RFH2_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITM_CAN_RFH2_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITM_CAN_RFH2_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITM_CAN_RFH2_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITM_CAN_RFH2_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITM_CAN_RFH2_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITM_CAN_RFH2_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITM_CAN_RFH2_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITM_CAN_RFH2_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITM_CAN_RFH2_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITM_CAN_RFH2_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITM_CAN_RFH2_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
|
|
#define BITM_CAN_RFH2_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Remote Frame Handling Enable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_OPSS2 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_OPSS2_MB00 0 /* Mailbox n Overwrite Protection Enable */
|
|
#define BITP_CAN_OPSS2_MB01 1 /* Mailbox n Overwrite Protection Enable */
|
|
#define BITP_CAN_OPSS2_MB02 2 /* Mailbox n Overwrite Protection Enable */
|
|
#define BITP_CAN_OPSS2_MB03 3 /* Mailbox n Overwrite Protection Enable */
|
|
#define BITP_CAN_OPSS2_MB04 4 /* Mailbox n Overwrite Protection Enable */
|
|
#define BITP_CAN_OPSS2_MB05 5 /* Mailbox n Overwrite Protection Enable */
|
|
#define BITP_CAN_OPSS2_MB06 6 /* Mailbox n Overwrite Protection Enable */
|
|
#define BITP_CAN_OPSS2_MB07 7 /* Mailbox n Overwrite Protection Enable */
|
|
#define BITP_CAN_OPSS2_MB08 8 /* Mailbox n Overwrite Protection Enable */
|
|
#define BITP_CAN_OPSS2_MB09 9 /* Mailbox n Overwrite Protection Enable */
|
|
#define BITP_CAN_OPSS2_MB10 10 /* Mailbox n Overwrite Protection Enable */
|
|
#define BITP_CAN_OPSS2_MB11 11 /* Mailbox n Overwrite Protection Enable */
|
|
#define BITP_CAN_OPSS2_MB12 12 /* Mailbox n Overwrite Protection Enable */
|
|
#define BITP_CAN_OPSS2_MB13 13 /* Mailbox n Overwrite Protection Enable */
|
|
#define BITP_CAN_OPSS2_MB14 14 /* Mailbox n Overwrite Protection Enable */
|
|
#define BITP_CAN_OPSS2_MB15 15 /* Mailbox n Overwrite Protection Enable */
|
|
#define BITM_CAN_OPSS2_MB00 (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox n Overwrite Protection Enable */
|
|
#define BITM_CAN_OPSS2_MB01 (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox n Overwrite Protection Enable */
|
|
#define BITM_CAN_OPSS2_MB02 (_ADI_MSK(0x00000004,uint16_t)) /* Mailbox n Overwrite Protection Enable */
|
|
#define BITM_CAN_OPSS2_MB03 (_ADI_MSK(0x00000008,uint16_t)) /* Mailbox n Overwrite Protection Enable */
|
|
#define BITM_CAN_OPSS2_MB04 (_ADI_MSK(0x00000010,uint16_t)) /* Mailbox n Overwrite Protection Enable */
|
|
#define BITM_CAN_OPSS2_MB05 (_ADI_MSK(0x00000020,uint16_t)) /* Mailbox n Overwrite Protection Enable */
|
|
#define BITM_CAN_OPSS2_MB06 (_ADI_MSK(0x00000040,uint16_t)) /* Mailbox n Overwrite Protection Enable */
|
|
#define BITM_CAN_OPSS2_MB07 (_ADI_MSK(0x00000080,uint16_t)) /* Mailbox n Overwrite Protection Enable */
|
|
#define BITM_CAN_OPSS2_MB08 (_ADI_MSK(0x00000100,uint16_t)) /* Mailbox n Overwrite Protection Enable */
|
|
#define BITM_CAN_OPSS2_MB09 (_ADI_MSK(0x00000200,uint16_t)) /* Mailbox n Overwrite Protection Enable */
|
|
#define BITM_CAN_OPSS2_MB10 (_ADI_MSK(0x00000400,uint16_t)) /* Mailbox n Overwrite Protection Enable */
|
|
#define BITM_CAN_OPSS2_MB11 (_ADI_MSK(0x00000800,uint16_t)) /* Mailbox n Overwrite Protection Enable */
|
|
#define BITM_CAN_OPSS2_MB12 (_ADI_MSK(0x00001000,uint16_t)) /* Mailbox n Overwrite Protection Enable */
|
|
#define BITM_CAN_OPSS2_MB13 (_ADI_MSK(0x00002000,uint16_t)) /* Mailbox n Overwrite Protection Enable */
|
|
#define BITM_CAN_OPSS2_MB14 (_ADI_MSK(0x00004000,uint16_t)) /* Mailbox n Overwrite Protection Enable */
|
|
#define BITM_CAN_OPSS2_MB15 (_ADI_MSK(0x00008000,uint16_t)) /* Mailbox n Overwrite Protection Enable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_CLK Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_CLK_BRP 0 /* Bit Rate Prescaler */
|
|
#define BITM_CAN_CLK_BRP (_ADI_MSK(0x000003FF,uint16_t)) /* Bit Rate Prescaler */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_TIMING Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_TIMING_SJW 8 /* Synchronization Jump Width */
|
|
#define BITP_CAN_TIMING_SAM 7 /* Sampling */
|
|
#define BITP_CAN_TIMING_TSEG2 4 /* Time Segment 2 */
|
|
#define BITP_CAN_TIMING_TSEG1 0 /* Time Segment 1 */
|
|
#define BITM_CAN_TIMING_SJW (_ADI_MSK(0x00000300,uint16_t)) /* Synchronization Jump Width */
|
|
#define BITM_CAN_TIMING_SAM (_ADI_MSK(0x00000080,uint16_t)) /* Sampling */
|
|
#define BITM_CAN_TIMING_TSEG2 (_ADI_MSK(0x00000070,uint16_t)) /* Time Segment 2 */
|
|
#define BITM_CAN_TIMING_TSEG1 (_ADI_MSK(0x0000000F,uint16_t)) /* Time Segment 1 */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_DBG Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_DBG_CDE 15 /* CAN Debug Mode Enable */
|
|
#define BITP_CAN_DBG_MRB 5 /* Mode Read Back */
|
|
#define BITP_CAN_DBG_MAA 4 /* Mode Auto Acknowledge */
|
|
#define BITP_CAN_DBG_DIL 3 /* Disable Internal Loop */
|
|
#define BITP_CAN_DBG_DTO 2 /* Disable Tx Output Pin */
|
|
#define BITP_CAN_DBG_DRI 1 /* Disable Receive Input Pin */
|
|
#define BITP_CAN_DBG_DEC 0 /* Disable Transmit and Receive Error Counters */
|
|
#define BITM_CAN_DBG_CDE (_ADI_MSK(0x00008000,uint16_t)) /* CAN Debug Mode Enable */
|
|
#define BITM_CAN_DBG_MRB (_ADI_MSK(0x00000020,uint16_t)) /* Mode Read Back */
|
|
#define BITM_CAN_DBG_MAA (_ADI_MSK(0x00000010,uint16_t)) /* Mode Auto Acknowledge */
|
|
#define BITM_CAN_DBG_DIL (_ADI_MSK(0x00000008,uint16_t)) /* Disable Internal Loop */
|
|
#define BITM_CAN_DBG_DTO (_ADI_MSK(0x00000004,uint16_t)) /* Disable Tx Output Pin */
|
|
#define BITM_CAN_DBG_DRI (_ADI_MSK(0x00000002,uint16_t)) /* Disable Receive Input Pin */
|
|
#define BITM_CAN_DBG_DEC (_ADI_MSK(0x00000001,uint16_t)) /* Disable Transmit and Receive Error Counters */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_STAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_STAT_REC 15 /* Receive Mode */
|
|
#define BITP_CAN_STAT_TRM 14 /* Transmit Mode */
|
|
#define BITP_CAN_STAT_MBPTR 8 /* Mailbox Pointer */
|
|
#define BITP_CAN_STAT_CCA 7 /* CAN Configuration Mode Acknowledge */
|
|
#define BITP_CAN_STAT_CSA 6 /* CAN Suspend Mode Acknowledge */
|
|
#define BITP_CAN_STAT_EBO 3 /* CAN Error Bus Off Mode */
|
|
#define BITP_CAN_STAT_EP 2 /* CAN Error Passive Mode */
|
|
#define BITP_CAN_STAT_WR 1 /* CAN Receive Warning Flag */
|
|
#define BITP_CAN_STAT_WT 0 /* CAN Transmit Warning Flag */
|
|
#define BITM_CAN_STAT_REC (_ADI_MSK(0x00008000,uint16_t)) /* Receive Mode */
|
|
#define BITM_CAN_STAT_TRM (_ADI_MSK(0x00004000,uint16_t)) /* Transmit Mode */
|
|
#define BITM_CAN_STAT_MBPTR (_ADI_MSK(0x00001F00,uint16_t)) /* Mailbox Pointer */
|
|
#define BITM_CAN_STAT_CCA (_ADI_MSK(0x00000080,uint16_t)) /* CAN Configuration Mode Acknowledge */
|
|
#define BITM_CAN_STAT_CSA (_ADI_MSK(0x00000040,uint16_t)) /* CAN Suspend Mode Acknowledge */
|
|
#define BITM_CAN_STAT_EBO (_ADI_MSK(0x00000008,uint16_t)) /* CAN Error Bus Off Mode */
|
|
#define BITM_CAN_STAT_EP (_ADI_MSK(0x00000004,uint16_t)) /* CAN Error Passive Mode */
|
|
#define BITM_CAN_STAT_WR (_ADI_MSK(0x00000002,uint16_t)) /* CAN Receive Warning Flag */
|
|
#define BITM_CAN_STAT_WT (_ADI_MSK(0x00000001,uint16_t)) /* CAN Transmit Warning Flag */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_CEC Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_CEC_TXECNT 8 /* Transmit Error Counter */
|
|
#define BITP_CAN_CEC_RXECNT 0 /* Receive Error Counter */
|
|
#define BITM_CAN_CEC_TXECNT (_ADI_MSK(0x0000FF00,uint16_t)) /* Transmit Error Counter */
|
|
#define BITM_CAN_CEC_RXECNT (_ADI_MSK(0x000000FF,uint16_t)) /* Receive Error Counter */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_GIS Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_GIS_ADIS 10 /* Access Denied Interrupt Status */
|
|
#define BITP_CAN_GIS_UCEIS 8 /* Universal Counter Exceeded Interrupt Status */
|
|
#define BITP_CAN_GIS_RMLIS 7 /* Receive Message Lost Interrupt Status */
|
|
#define BITP_CAN_GIS_AAIS 6 /* Abort Acknowledge Interrupt Status */
|
|
#define BITP_CAN_GIS_UIAIS 5 /* Unimplemented Address Interrupt Status */
|
|
#define BITP_CAN_GIS_WUIS 4 /* Wake Up Interrupt Status */
|
|
#define BITP_CAN_GIS_BOIS 3 /* Bus Off Interrupt Status */
|
|
#define BITP_CAN_GIS_EPIS 2 /* Error Passive Interrupt Status */
|
|
#define BITP_CAN_GIS_EWRIS 1 /* Error Warning Receive Interrupt Status */
|
|
#define BITP_CAN_GIS_EWTIS 0 /* Error Warning Transmit Interrupt Status */
|
|
#define BITM_CAN_GIS_ADIS (_ADI_MSK(0x00000400,uint16_t)) /* Access Denied Interrupt Status */
|
|
#define BITM_CAN_GIS_UCEIS (_ADI_MSK(0x00000100,uint16_t)) /* Universal Counter Exceeded Interrupt Status */
|
|
#define BITM_CAN_GIS_RMLIS (_ADI_MSK(0x00000080,uint16_t)) /* Receive Message Lost Interrupt Status */
|
|
#define BITM_CAN_GIS_AAIS (_ADI_MSK(0x00000040,uint16_t)) /* Abort Acknowledge Interrupt Status */
|
|
#define BITM_CAN_GIS_UIAIS (_ADI_MSK(0x00000020,uint16_t)) /* Unimplemented Address Interrupt Status */
|
|
#define BITM_CAN_GIS_WUIS (_ADI_MSK(0x00000010,uint16_t)) /* Wake Up Interrupt Status */
|
|
#define BITM_CAN_GIS_BOIS (_ADI_MSK(0x00000008,uint16_t)) /* Bus Off Interrupt Status */
|
|
#define BITM_CAN_GIS_EPIS (_ADI_MSK(0x00000004,uint16_t)) /* Error Passive Interrupt Status */
|
|
#define BITM_CAN_GIS_EWRIS (_ADI_MSK(0x00000002,uint16_t)) /* Error Warning Receive Interrupt Status */
|
|
#define BITM_CAN_GIS_EWTIS (_ADI_MSK(0x00000001,uint16_t)) /* Error Warning Transmit Interrupt Status */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_GIM Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_GIM_ADIM 10 /* Access Denied Interrupt Mask */
|
|
#define BITP_CAN_GIM_UCEIM 8 /* Universal Counter Exceeded Interrupt Mask */
|
|
#define BITP_CAN_GIM_RMLIM 7 /* Receive Message Lost Interrupt Mask */
|
|
#define BITP_CAN_GIM_AAIM 6 /* Abort Acknowledge Interrupt Mask */
|
|
#define BITP_CAN_GIM_UIAIM 5 /* Unimplemented Address Interrupt Mask */
|
|
#define BITP_CAN_GIM_WUIM 4 /* Wake Up Interrupt Mask */
|
|
#define BITP_CAN_GIM_BOIM 3 /* Bus Off Interrupt Mask */
|
|
#define BITP_CAN_GIM_EPIM 2 /* Error Passive Interrupt Mask */
|
|
#define BITP_CAN_GIM_EWRIM 1 /* Error Warning Receive Interrupt Mask */
|
|
#define BITP_CAN_GIM_EWTIM 0 /* Error Warning Transmit Interrupt Mask */
|
|
#define BITM_CAN_GIM_ADIM (_ADI_MSK(0x00000400,uint16_t)) /* Access Denied Interrupt Mask */
|
|
#define BITM_CAN_GIM_UCEIM (_ADI_MSK(0x00000100,uint16_t)) /* Universal Counter Exceeded Interrupt Mask */
|
|
#define BITM_CAN_GIM_RMLIM (_ADI_MSK(0x00000080,uint16_t)) /* Receive Message Lost Interrupt Mask */
|
|
#define BITM_CAN_GIM_AAIM (_ADI_MSK(0x00000040,uint16_t)) /* Abort Acknowledge Interrupt Mask */
|
|
#define BITM_CAN_GIM_UIAIM (_ADI_MSK(0x00000020,uint16_t)) /* Unimplemented Address Interrupt Mask */
|
|
#define BITM_CAN_GIM_WUIM (_ADI_MSK(0x00000010,uint16_t)) /* Wake Up Interrupt Mask */
|
|
#define BITM_CAN_GIM_BOIM (_ADI_MSK(0x00000008,uint16_t)) /* Bus Off Interrupt Mask */
|
|
#define BITM_CAN_GIM_EPIM (_ADI_MSK(0x00000004,uint16_t)) /* Error Passive Interrupt Mask */
|
|
#define BITM_CAN_GIM_EWRIM (_ADI_MSK(0x00000002,uint16_t)) /* Error Warning Receive Interrupt Mask */
|
|
#define BITM_CAN_GIM_EWTIM (_ADI_MSK(0x00000001,uint16_t)) /* Error Warning Transmit Interrupt Mask */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_GIF Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_GIF_ADIF 10 /* Access Denied Interrupt Flag */
|
|
#define BITP_CAN_GIF_UCEIF 8 /* Universal Counter Exceeded Interrupt Flag */
|
|
#define BITP_CAN_GIF_RMLIF 7 /* Receive Message Lost Interrupt Flag */
|
|
#define BITP_CAN_GIF_AAIF 6 /* Abort Acknowledge Interrupt Flag */
|
|
#define BITP_CAN_GIF_UIAIF 5 /* Unimplemented Address Interrupt Flag */
|
|
#define BITP_CAN_GIF_WUIF 4 /* Wake Up Interrupt Flag */
|
|
#define BITP_CAN_GIF_BOIF 3 /* Bus Off Interrupt Flag */
|
|
#define BITP_CAN_GIF_EPIF 2 /* Error Passive Interrupt Flag */
|
|
#define BITP_CAN_GIF_EWRIF 1 /* Error Warning Receive Interrupt Flag */
|
|
#define BITP_CAN_GIF_EWTIF 0 /* Error Warning Transmit Interrupt Flag */
|
|
#define BITM_CAN_GIF_ADIF (_ADI_MSK(0x00000400,uint16_t)) /* Access Denied Interrupt Flag */
|
|
#define BITM_CAN_GIF_UCEIF (_ADI_MSK(0x00000100,uint16_t)) /* Universal Counter Exceeded Interrupt Flag */
|
|
#define BITM_CAN_GIF_RMLIF (_ADI_MSK(0x00000080,uint16_t)) /* Receive Message Lost Interrupt Flag */
|
|
#define BITM_CAN_GIF_AAIF (_ADI_MSK(0x00000040,uint16_t)) /* Abort Acknowledge Interrupt Flag */
|
|
#define BITM_CAN_GIF_UIAIF (_ADI_MSK(0x00000020,uint16_t)) /* Unimplemented Address Interrupt Flag */
|
|
#define BITM_CAN_GIF_WUIF (_ADI_MSK(0x00000010,uint16_t)) /* Wake Up Interrupt Flag */
|
|
#define BITM_CAN_GIF_BOIF (_ADI_MSK(0x00000008,uint16_t)) /* Bus Off Interrupt Flag */
|
|
#define BITM_CAN_GIF_EPIF (_ADI_MSK(0x00000004,uint16_t)) /* Error Passive Interrupt Flag */
|
|
#define BITM_CAN_GIF_EWRIF (_ADI_MSK(0x00000002,uint16_t)) /* Error Warning Receive Interrupt Flag */
|
|
#define BITM_CAN_GIF_EWTIF (_ADI_MSK(0x00000001,uint16_t)) /* Error Warning Transmit Interrupt Flag */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_CTL_CCR 7 /* CAN Configuration Mode Request */
|
|
#define BITP_CAN_CTL_CSR 6 /* CAN Suspend Mode Request */
|
|
#define BITP_CAN_CTL_SMR 5 /* Sleep Mode Request */
|
|
#define BITP_CAN_CTL_WBA 4 /* Wake Up on CAN Bus Activity */
|
|
#define BITP_CAN_CTL_ABO 2 /* Auto Bus On */
|
|
#define BITP_CAN_CTL_DNM 1 /* Device Net Mode */
|
|
#define BITP_CAN_CTL_SRS 0 /* Software Reset */
|
|
#define BITM_CAN_CTL_CCR (_ADI_MSK(0x00000080,uint16_t)) /* CAN Configuration Mode Request */
|
|
#define BITM_CAN_CTL_CSR (_ADI_MSK(0x00000040,uint16_t)) /* CAN Suspend Mode Request */
|
|
#define BITM_CAN_CTL_SMR (_ADI_MSK(0x00000020,uint16_t)) /* Sleep Mode Request */
|
|
#define BITM_CAN_CTL_WBA (_ADI_MSK(0x00000010,uint16_t)) /* Wake Up on CAN Bus Activity */
|
|
#define BITM_CAN_CTL_ABO (_ADI_MSK(0x00000004,uint16_t)) /* Auto Bus On */
|
|
#define BITM_CAN_CTL_DNM (_ADI_MSK(0x00000002,uint16_t)) /* Device Net Mode */
|
|
#define BITM_CAN_CTL_SRS (_ADI_MSK(0x00000001,uint16_t)) /* Software Reset */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_INT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_INT_CANRX 7 /* Serial Input From Transceiver */
|
|
#define BITP_CAN_INT_CANTX 6 /* Serial Input To Transceiver */
|
|
#define BITP_CAN_INT_SMACK 3 /* Sleep Mode Acknowledge */
|
|
#define BITP_CAN_INT_GIRQ 2 /* Global CAN Interrupt Output */
|
|
#define BITP_CAN_INT_MBTIRQ 1 /* Mailbox Transmit Interrupt Output */
|
|
#define BITP_CAN_INT_MBRIRQ 0 /* Mailbox Receive Interrupt Output */
|
|
#define BITM_CAN_INT_CANRX (_ADI_MSK(0x00000080,uint16_t)) /* Serial Input From Transceiver */
|
|
#define BITM_CAN_INT_CANTX (_ADI_MSK(0x00000040,uint16_t)) /* Serial Input To Transceiver */
|
|
#define BITM_CAN_INT_SMACK (_ADI_MSK(0x00000008,uint16_t)) /* Sleep Mode Acknowledge */
|
|
#define BITM_CAN_INT_GIRQ (_ADI_MSK(0x00000004,uint16_t)) /* Global CAN Interrupt Output */
|
|
#define BITM_CAN_INT_MBTIRQ (_ADI_MSK(0x00000002,uint16_t)) /* Mailbox Transmit Interrupt Output */
|
|
#define BITM_CAN_INT_MBRIRQ (_ADI_MSK(0x00000001,uint16_t)) /* Mailbox Receive Interrupt Output */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_MBTD Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_MBTD_TDR 7 /* Temporary Disable Request */
|
|
#define BITP_CAN_MBTD_TDA 6 /* Temporary Disable Acknowledge */
|
|
#define BITP_CAN_MBTD_TDPTR 0 /* Temporary Disable Pointer */
|
|
#define BITM_CAN_MBTD_TDR (_ADI_MSK(0x00000080,uint16_t)) /* Temporary Disable Request */
|
|
#define BITM_CAN_MBTD_TDA (_ADI_MSK(0x00000040,uint16_t)) /* Temporary Disable Acknowledge */
|
|
#define BITM_CAN_MBTD_TDPTR (_ADI_MSK(0x0000001F,uint16_t)) /* Temporary Disable Pointer */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_EWR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_EWR_EWLTEC 8 /* Transmit Error Warning Limit */
|
|
#define BITP_CAN_EWR_EWLREC 0 /* Receive Error Warning Limit */
|
|
#define BITM_CAN_EWR_EWLTEC (_ADI_MSK(0x0000FF00,uint16_t)) /* Transmit Error Warning Limit */
|
|
#define BITM_CAN_EWR_EWLREC (_ADI_MSK(0x000000FF,uint16_t)) /* Receive Error Warning Limit */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_ESR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_ESR_FER 7 /* Form Error */
|
|
#define BITP_CAN_ESR_BEF 6 /* Bit Error Flag */
|
|
#define BITP_CAN_ESR_SAO 5 /* Stuck at Dominant */
|
|
#define BITP_CAN_ESR_CRCE 4 /* CRC Error */
|
|
#define BITP_CAN_ESR_SER 3 /* Stuff Bit Error */
|
|
#define BITP_CAN_ESR_ACKE 2 /* Acknowledge Error */
|
|
#define BITM_CAN_ESR_FER (_ADI_MSK(0x00000080,uint16_t)) /* Form Error */
|
|
#define BITM_CAN_ESR_BEF (_ADI_MSK(0x00000040,uint16_t)) /* Bit Error Flag */
|
|
#define BITM_CAN_ESR_SAO (_ADI_MSK(0x00000020,uint16_t)) /* Stuck at Dominant */
|
|
#define BITM_CAN_ESR_CRCE (_ADI_MSK(0x00000010,uint16_t)) /* CRC Error */
|
|
#define BITM_CAN_ESR_SER (_ADI_MSK(0x00000008,uint16_t)) /* Stuff Bit Error */
|
|
#define BITM_CAN_ESR_ACKE (_ADI_MSK(0x00000004,uint16_t)) /* Acknowledge Error */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_UCCNF Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_UCCNF_UCE 7 /* Universal Counter Enable */
|
|
#define BITP_CAN_UCCNF_UCCT 6 /* Universal Counter CAN Trigger */
|
|
#define BITP_CAN_UCCNF_UCRC 5 /* Universal Counter Reload/Clear */
|
|
#define BITP_CAN_UCCNF_UCCNF 0 /* Universal Counter Configuration */
|
|
#define BITM_CAN_UCCNF_UCE (_ADI_MSK(0x00000080,uint16_t)) /* Universal Counter Enable */
|
|
#define BITM_CAN_UCCNF_UCCT (_ADI_MSK(0x00000040,uint16_t)) /* Universal Counter CAN Trigger */
|
|
#define BITM_CAN_UCCNF_UCRC (_ADI_MSK(0x00000020,uint16_t)) /* Universal Counter Reload/Clear */
|
|
#define BITM_CAN_UCCNF_UCCNF (_ADI_MSK(0x0000000F,uint16_t)) /* Universal Counter Configuration */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_AMnH Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_AMH_FDF 15 /* Filter on Delay Field */
|
|
#define BITP_CAN_AMH_FMD 14 /* Full Mask Data */
|
|
#define BITP_CAN_AMH_AMIDE 13 /* Acceptance Mask Identifier Extension */
|
|
#define BITP_CAN_AMH_BASEID 2 /* Base Identifier */
|
|
#define BITP_CAN_AMH_EXTID 0 /* Extended Identifier */
|
|
#define BITM_CAN_AMH_FDF (_ADI_MSK(0x00008000,uint16_t)) /* Filter on Delay Field */
|
|
#define BITM_CAN_AMH_FMD (_ADI_MSK(0x00004000,uint16_t)) /* Full Mask Data */
|
|
#define BITM_CAN_AMH_AMIDE (_ADI_MSK(0x00002000,uint16_t)) /* Acceptance Mask Identifier Extension */
|
|
#define BITM_CAN_AMH_BASEID (_ADI_MSK(0x00001FFC,uint16_t)) /* Base Identifier */
|
|
#define BITM_CAN_AMH_EXTID (_ADI_MSK(0x00000003,uint16_t)) /* Extended Identifier */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_MBn_DATA0 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_MB_DATA0_DFB6 8 /* Data Field Byte 6 */
|
|
#define BITP_CAN_MB_DATA0_DFB7 0 /* Data Field Byte 7 */
|
|
#define BITM_CAN_MB_DATA0_DFB6 (_ADI_MSK(0x0000FF00,uint16_t)) /* Data Field Byte 6 */
|
|
#define BITM_CAN_MB_DATA0_DFB7 (_ADI_MSK(0x000000FF,uint16_t)) /* Data Field Byte 7 */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_MBn_DATA1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_MB_DATA1_DFB4 8 /* Data Field Byte 4 */
|
|
#define BITP_CAN_MB_DATA1_DFB5 0 /* Data Field Byte 5 */
|
|
#define BITM_CAN_MB_DATA1_DFB4 (_ADI_MSK(0x0000FF00,uint16_t)) /* Data Field Byte 4 */
|
|
#define BITM_CAN_MB_DATA1_DFB5 (_ADI_MSK(0x000000FF,uint16_t)) /* Data Field Byte 5 */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_MBn_DATA2 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_MB_DATA2_DFB2 8 /* Data Field Byte 2 */
|
|
#define BITP_CAN_MB_DATA2_DFB3 0 /* Data Field Byte 3 */
|
|
#define BITM_CAN_MB_DATA2_DFB2 (_ADI_MSK(0x0000FF00,uint16_t)) /* Data Field Byte 2 */
|
|
#define BITM_CAN_MB_DATA2_DFB3 (_ADI_MSK(0x000000FF,uint16_t)) /* Data Field Byte 3 */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_MBn_DATA3 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_MB_DATA3_DFB0 8 /* Data Field Byte 0 */
|
|
#define BITP_CAN_MB_DATA3_DFB1 0 /* Data Field Byte 1 */
|
|
#define BITM_CAN_MB_DATA3_DFB0 (_ADI_MSK(0x0000FF00,uint16_t)) /* Data Field Byte 0 */
|
|
#define BITM_CAN_MB_DATA3_DFB1 (_ADI_MSK(0x000000FF,uint16_t)) /* Data Field Byte 1 */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_MBn_LENGTH Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_MB_LENGTH_DLC 0 /* Data Length Code */
|
|
#define BITM_CAN_MB_LENGTH_DLC (_ADI_MSK(0x0000000F,uint16_t)) /* Data Length Code */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CAN_MBn_ID1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CAN_MB_ID1_AME 15 /* Acceptance Mask Enable */
|
|
#define BITP_CAN_MB_ID1_RTR 14 /* Remote Transmission Request */
|
|
#define BITP_CAN_MB_ID1_IDE 13 /* Identifier Extension */
|
|
#define BITP_CAN_MB_ID1_BASEID 2 /* Base Identifier */
|
|
#define BITP_CAN_MB_ID1_EXTID 0 /* Extended Identifier */
|
|
#define BITM_CAN_MB_ID1_AME (_ADI_MSK(0x00008000,uint16_t)) /* Acceptance Mask Enable */
|
|
#define BITM_CAN_MB_ID1_RTR (_ADI_MSK(0x00004000,uint16_t)) /* Remote Transmission Request */
|
|
#define BITM_CAN_MB_ID1_IDE (_ADI_MSK(0x00002000,uint16_t)) /* Identifier Extension */
|
|
#define BITM_CAN_MB_ID1_BASEID (_ADI_MSK(0x00001FFC,uint16_t)) /* Base Identifier */
|
|
#define BITM_CAN_MB_ID1_EXTID (_ADI_MSK(0x00000003,uint16_t)) /* Extended Identifier */
|
|
|
|
/* ==================================================
|
|
Link Port Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
LP0
|
|
========================= */
|
|
#define REG_LP0_CTL 0xFFC01000 /* LP0 Control Register */
|
|
#define REG_LP0_STAT 0xFFC01004 /* LP0 Status Register */
|
|
#define REG_LP0_DIV 0xFFC01008 /* LP0 Clock Divider Value */
|
|
#define REG_LP0_TX 0xFFC01010 /* LP0 Transmit Buffer */
|
|
#define REG_LP0_RX 0xFFC01014 /* LP0 Receive Buffer */
|
|
#define REG_LP0_TXIN_SHDW 0xFFC01018 /* LP0 Shadow Input Transmit Buffer */
|
|
#define REG_LP0_TXOUT_SHDW 0xFFC0101C /* LP0 Shadow Output Transmit Buffer */
|
|
|
|
/* =========================
|
|
LP1
|
|
========================= */
|
|
#define REG_LP1_CTL 0xFFC01100 /* LP1 Control Register */
|
|
#define REG_LP1_STAT 0xFFC01104 /* LP1 Status Register */
|
|
#define REG_LP1_DIV 0xFFC01108 /* LP1 Clock Divider Value */
|
|
#define REG_LP1_TX 0xFFC01110 /* LP1 Transmit Buffer */
|
|
#define REG_LP1_RX 0xFFC01114 /* LP1 Receive Buffer */
|
|
#define REG_LP1_TXIN_SHDW 0xFFC01118 /* LP1 Shadow Input Transmit Buffer */
|
|
#define REG_LP1_TXOUT_SHDW 0xFFC0111C /* LP1 Shadow Output Transmit Buffer */
|
|
|
|
/* =========================
|
|
LP2
|
|
========================= */
|
|
#define REG_LP2_CTL 0xFFC01200 /* LP2 Control Register */
|
|
#define REG_LP2_STAT 0xFFC01204 /* LP2 Status Register */
|
|
#define REG_LP2_DIV 0xFFC01208 /* LP2 Clock Divider Value */
|
|
#define REG_LP2_TX 0xFFC01210 /* LP2 Transmit Buffer */
|
|
#define REG_LP2_RX 0xFFC01214 /* LP2 Receive Buffer */
|
|
#define REG_LP2_TXIN_SHDW 0xFFC01218 /* LP2 Shadow Input Transmit Buffer */
|
|
#define REG_LP2_TXOUT_SHDW 0xFFC0121C /* LP2 Shadow Output Transmit Buffer */
|
|
|
|
/* =========================
|
|
LP3
|
|
========================= */
|
|
#define REG_LP3_CTL 0xFFC01300 /* LP3 Control Register */
|
|
#define REG_LP3_STAT 0xFFC01304 /* LP3 Status Register */
|
|
#define REG_LP3_DIV 0xFFC01308 /* LP3 Clock Divider Value */
|
|
#define REG_LP3_TX 0xFFC01310 /* LP3 Transmit Buffer */
|
|
#define REG_LP3_RX 0xFFC01314 /* LP3 Receive Buffer */
|
|
#define REG_LP3_TXIN_SHDW 0xFFC01318 /* LP3 Shadow Input Transmit Buffer */
|
|
#define REG_LP3_TXOUT_SHDW 0xFFC0131C /* LP3 Shadow Output Transmit Buffer */
|
|
|
|
/* =========================
|
|
LP
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
LP_CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_LP_CTL_ITMSK 11 /* Receive FIFO Overflow Interrupt Mask */
|
|
#define BITP_LP_CTL_RRQMSK 9 /* Receive Request Interrupt Mask */
|
|
#define BITP_LP_CTL_TRQMSK 8 /* Transmit Request Interrupt Mask */
|
|
#define BITP_LP_CTL_TRAN 3 /* Transfer Direction */
|
|
#define BITP_LP_CTL_EN 0 /* Enable */
|
|
|
|
#define BITM_LP_CTL_ITMSK (_ADI_MSK(0x00000800,uint32_t)) /* Receive FIFO Overflow Interrupt Mask */
|
|
#define ENUM_LP_CTL_RX_OVF_DIS (_ADI_MSK(0x00000000,uint32_t)) /* ITMSK: Mask */
|
|
#define ENUM_LP_CTL_RX_OVF_EN (_ADI_MSK(0x00000800,uint32_t)) /* ITMSK: Unmask */
|
|
|
|
#define BITM_LP_CTL_RRQMSK (_ADI_MSK(0x00000200,uint32_t)) /* Receive Request Interrupt Mask */
|
|
#define ENUM_LP_CTL_RRQ_DIS (_ADI_MSK(0x00000000,uint32_t)) /* RRQMSK: Mask */
|
|
#define ENUM_LP_CTL_RRQ_EN (_ADI_MSK(0x00000200,uint32_t)) /* RRQMSK: Unmask */
|
|
|
|
#define BITM_LP_CTL_TRQMSK (_ADI_MSK(0x00000100,uint32_t)) /* Transmit Request Interrupt Mask */
|
|
#define ENUM_LP_CTL_TRQ_DIS (_ADI_MSK(0x00000000,uint32_t)) /* TRQMSK: Mask */
|
|
#define ENUM_LP_CTL_TRQ_EN (_ADI_MSK(0x00000100,uint32_t)) /* TRQMSK: Unmask */
|
|
|
|
#define BITM_LP_CTL_TRAN (_ADI_MSK(0x00000008,uint32_t)) /* Transfer Direction */
|
|
#define ENUM_LP_CTL_RX (_ADI_MSK(0x00000000,uint32_t)) /* TRAN: Receive */
|
|
#define ENUM_LP_CTL_TX (_ADI_MSK(0x00000008,uint32_t)) /* TRAN: Transmit */
|
|
|
|
#define BITM_LP_CTL_EN (_ADI_MSK(0x00000001,uint32_t)) /* Enable */
|
|
#define ENUM_LP_CTL_DIS (_ADI_MSK(0x00000000,uint32_t)) /* EN: Disable */
|
|
#define ENUM_LP_CTL_EN (_ADI_MSK(0x00000001,uint32_t)) /* EN: Enable linkport */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
LP_STAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_LP_STAT_LPBS 8 /* Bus Status */
|
|
#define BITP_LP_STAT_LERR 7 /* Buffer Pack Error Status */
|
|
#define BITP_LP_STAT_FFST 4 /* FIFO Status */
|
|
#define BITP_LP_STAT_LPIT 3 /* Receive FIFO Overflow Interrupt */
|
|
#define BITP_LP_STAT_LRRQ 1 /* Receive Request */
|
|
#define BITP_LP_STAT_LTRQ 0 /* Transmit Request */
|
|
|
|
#define BITM_LP_STAT_LPBS (_ADI_MSK(0x00000100,uint32_t)) /* Bus Status */
|
|
#define ENUM_LP_STAT_IDLE (_ADI_MSK(0x00000000,uint32_t)) /* LPBS: Bus is Idle */
|
|
#define ENUM_LP_STAT_BUSY (_ADI_MSK(0x00000100,uint32_t)) /* LPBS: Bus Busy */
|
|
|
|
#define BITM_LP_STAT_LERR (_ADI_MSK(0x00000080,uint32_t)) /* Buffer Pack Error Status */
|
|
#define ENUM_LP_STAT_PACK_DONE (_ADI_MSK(0x00000000,uint32_t)) /* LERR: Packing Complete */
|
|
#define ENUM_LP_STAT_PACK_PROG (_ADI_MSK(0x00000080,uint32_t)) /* LERR: Packing Incomplete */
|
|
|
|
#define BITM_LP_STAT_FFST (_ADI_MSK(0x00000070,uint32_t)) /* FIFO Status */
|
|
#define ENUM_LP_STAT_RX0_TX0 (_ADI_MSK(0x00000000,uint32_t)) /* FFST: TX - Empty; RX -Empty */
|
|
#define ENUM_LP_STAT_RX1_TXR (_ADI_MSK(0x00000010,uint32_t)) /* FFST: TX - reserved ; RX - One Word */
|
|
#define ENUM_LP_STAT_RX2_TXR (_ADI_MSK(0x00000020,uint32_t)) /* FFST: TX - reserved; RX - Two Word */
|
|
#define ENUM_LP_STAT_RX3_TXR (_ADI_MSK(0x00000030,uint32_t)) /* FFST: TX - reserved; RX - Three Word */
|
|
#define ENUM_LP_STAT_RX4_TX1 (_ADI_MSK(0x00000040,uint32_t)) /* FFST: TX - One Word; RX - Four word */
|
|
#define ENUM_LP_STAT_RXR1_TXR1 (_ADI_MSK(0x00000050,uint32_t)) /* FFST: TX - Reserved; RX - Reserved */
|
|
#define ENUM_LP_STAT_RXR2_TXR2 (_ADI_MSK(0x00000060,uint32_t)) /* FFST: TX - FIFO Full; RX - Reserved */
|
|
#define ENUM_LP_STAT_RXR3_TXR3 (_ADI_MSK(0x00000070,uint32_t)) /* FFST: TX - Reserved; RX - Reserved */
|
|
#define BITM_LP_STAT_LPIT (_ADI_MSK(0x00000008,uint32_t)) /* Receive FIFO Overflow Interrupt */
|
|
#define BITM_LP_STAT_LRRQ (_ADI_MSK(0x00000002,uint32_t)) /* Receive Request */
|
|
#define BITM_LP_STAT_LTRQ (_ADI_MSK(0x00000001,uint32_t)) /* Transmit Request */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
LP_DIV Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_LP_DIV_VALUE 0 /* Divisor Value */
|
|
#define BITM_LP_DIV_VALUE (_ADI_MSK(0x000000FF,uint32_t)) /* Divisor Value */
|
|
|
|
/* ==================================================
|
|
General Purpose Timer Block Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
TIMER0
|
|
========================= */
|
|
#define REG_TIMER0_REVID 0xFFC01400 /* TIMER0 Revision ID Register */
|
|
#define REG_TIMER0_RUN 0xFFC01404 /* TIMER0 Run Register */
|
|
#define REG_TIMER0_RUN_SET 0xFFC01408 /* TIMER0 Run Set Register */
|
|
#define REG_TIMER0_RUN_CLR 0xFFC0140C /* TIMER0 Run Clear Register */
|
|
#define REG_TIMER0_STOP_CFG 0xFFC01410 /* TIMER0 Stop Configuration Register */
|
|
#define REG_TIMER0_STOP_CFG_SET 0xFFC01414 /* TIMER0 Stop Configuration Set Register */
|
|
#define REG_TIMER0_STOP_CFG_CLR 0xFFC01418 /* TIMER0 Stop Configuration Clear Register */
|
|
#define REG_TIMER0_DATA_IMSK 0xFFC0141C /* TIMER0 Data Interrupt Mask Register */
|
|
#define REG_TIMER0_STAT_IMSK 0xFFC01420 /* TIMER0 Status Interrupt Mask Register */
|
|
#define REG_TIMER0_TRG_MSK 0xFFC01424 /* TIMER0 Trigger Master Mask Register */
|
|
#define REG_TIMER0_TRG_IE 0xFFC01428 /* TIMER0 Trigger Slave Enable Register */
|
|
#define REG_TIMER0_DATA_ILAT 0xFFC0142C /* TIMER0 Data Interrupt Latch Register */
|
|
#define REG_TIMER0_STAT_ILAT 0xFFC01430 /* TIMER0 Status Interrupt Latch Register */
|
|
#define REG_TIMER0_ERR_TYPE 0xFFC01434 /* TIMER0 Error Type Status Register */
|
|
#define REG_TIMER0_BCAST_PER 0xFFC01438 /* TIMER0 Broadcast Period Register */
|
|
#define REG_TIMER0_BCAST_WID 0xFFC0143C /* TIMER0 Broadcast Width Register */
|
|
#define REG_TIMER0_BCAST_DLY 0xFFC01440 /* TIMER0 Broadcast Delay Register */
|
|
#define REG_TIMER0_TMR0_CFG 0xFFC01460 /* TIMER0 Timer n Configuration Register */
|
|
#define REG_TIMER0_TMR1_CFG 0xFFC01480 /* TIMER0 Timer n Configuration Register */
|
|
#define REG_TIMER0_TMR2_CFG 0xFFC014A0 /* TIMER0 Timer n Configuration Register */
|
|
#define REG_TIMER0_TMR3_CFG 0xFFC014C0 /* TIMER0 Timer n Configuration Register */
|
|
#define REG_TIMER0_TMR4_CFG 0xFFC014E0 /* TIMER0 Timer n Configuration Register */
|
|
#define REG_TIMER0_TMR5_CFG 0xFFC01500 /* TIMER0 Timer n Configuration Register */
|
|
#define REG_TIMER0_TMR6_CFG 0xFFC01520 /* TIMER0 Timer n Configuration Register */
|
|
#define REG_TIMER0_TMR7_CFG 0xFFC01540 /* TIMER0 Timer n Configuration Register */
|
|
#define REG_TIMER0_TMR0_CNT 0xFFC01464 /* TIMER0 Timer n Counter Register */
|
|
#define REG_TIMER0_TMR1_CNT 0xFFC01484 /* TIMER0 Timer n Counter Register */
|
|
#define REG_TIMER0_TMR2_CNT 0xFFC014A4 /* TIMER0 Timer n Counter Register */
|
|
#define REG_TIMER0_TMR3_CNT 0xFFC014C4 /* TIMER0 Timer n Counter Register */
|
|
#define REG_TIMER0_TMR4_CNT 0xFFC014E4 /* TIMER0 Timer n Counter Register */
|
|
#define REG_TIMER0_TMR5_CNT 0xFFC01504 /* TIMER0 Timer n Counter Register */
|
|
#define REG_TIMER0_TMR6_CNT 0xFFC01524 /* TIMER0 Timer n Counter Register */
|
|
#define REG_TIMER0_TMR7_CNT 0xFFC01544 /* TIMER0 Timer n Counter Register */
|
|
#define REG_TIMER0_TMR0_PER 0xFFC01468 /* TIMER0 Timer n Period Register */
|
|
#define REG_TIMER0_TMR1_PER 0xFFC01488 /* TIMER0 Timer n Period Register */
|
|
#define REG_TIMER0_TMR2_PER 0xFFC014A8 /* TIMER0 Timer n Period Register */
|
|
#define REG_TIMER0_TMR3_PER 0xFFC014C8 /* TIMER0 Timer n Period Register */
|
|
#define REG_TIMER0_TMR4_PER 0xFFC014E8 /* TIMER0 Timer n Period Register */
|
|
#define REG_TIMER0_TMR5_PER 0xFFC01508 /* TIMER0 Timer n Period Register */
|
|
#define REG_TIMER0_TMR6_PER 0xFFC01528 /* TIMER0 Timer n Period Register */
|
|
#define REG_TIMER0_TMR7_PER 0xFFC01548 /* TIMER0 Timer n Period Register */
|
|
#define REG_TIMER0_TMR0_WID 0xFFC0146C /* TIMER0 Timer n Width Register */
|
|
#define REG_TIMER0_TMR1_WID 0xFFC0148C /* TIMER0 Timer n Width Register */
|
|
#define REG_TIMER0_TMR2_WID 0xFFC014AC /* TIMER0 Timer n Width Register */
|
|
#define REG_TIMER0_TMR3_WID 0xFFC014CC /* TIMER0 Timer n Width Register */
|
|
#define REG_TIMER0_TMR4_WID 0xFFC014EC /* TIMER0 Timer n Width Register */
|
|
#define REG_TIMER0_TMR5_WID 0xFFC0150C /* TIMER0 Timer n Width Register */
|
|
#define REG_TIMER0_TMR6_WID 0xFFC0152C /* TIMER0 Timer n Width Register */
|
|
#define REG_TIMER0_TMR7_WID 0xFFC0154C /* TIMER0 Timer n Width Register */
|
|
#define REG_TIMER0_TMR0_DLY 0xFFC01470 /* TIMER0 Timer n Delay Register */
|
|
#define REG_TIMER0_TMR1_DLY 0xFFC01490 /* TIMER0 Timer n Delay Register */
|
|
#define REG_TIMER0_TMR2_DLY 0xFFC014B0 /* TIMER0 Timer n Delay Register */
|
|
#define REG_TIMER0_TMR3_DLY 0xFFC014D0 /* TIMER0 Timer n Delay Register */
|
|
#define REG_TIMER0_TMR4_DLY 0xFFC014F0 /* TIMER0 Timer n Delay Register */
|
|
#define REG_TIMER0_TMR5_DLY 0xFFC01510 /* TIMER0 Timer n Delay Register */
|
|
#define REG_TIMER0_TMR6_DLY 0xFFC01530 /* TIMER0 Timer n Delay Register */
|
|
#define REG_TIMER0_TMR7_DLY 0xFFC01550 /* TIMER0 Timer n Delay Register */
|
|
|
|
/* =========================
|
|
TIMER
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TIMER_REVID Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TIMER_REVID_MAJOR 4 /* Major Revision ID */
|
|
#define BITP_TIMER_REVID_REV 0 /* Incremental Revision ID */
|
|
#define BITM_TIMER_REVID_MAJOR (_ADI_MSK(0x000000F0,uint16_t)) /* Major Revision ID */
|
|
#define BITM_TIMER_REVID_REV (_ADI_MSK(0x0000000F,uint16_t)) /* Incremental Revision ID */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TIMER_RUN Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TIMER_RUN_TMR00 0 /* Start/Stop Timer n */
|
|
#define BITP_TIMER_RUN_TMR01 1 /* Start/Stop Timer n */
|
|
#define BITP_TIMER_RUN_TMR02 2 /* Start/Stop Timer n */
|
|
#define BITP_TIMER_RUN_TMR03 3 /* Start/Stop Timer n */
|
|
#define BITP_TIMER_RUN_TMR04 4 /* Start/Stop Timer n */
|
|
#define BITP_TIMER_RUN_TMR05 5 /* Start/Stop Timer n */
|
|
#define BITP_TIMER_RUN_TMR06 6 /* Start/Stop Timer n */
|
|
#define BITP_TIMER_RUN_TMR07 7 /* Start/Stop Timer n */
|
|
#define BITM_TIMER_RUN_TMR00 (_ADI_MSK(0x00000001,uint16_t)) /* Start/Stop Timer n */
|
|
#define BITM_TIMER_RUN_TMR01 (_ADI_MSK(0x00000002,uint16_t)) /* Start/Stop Timer n */
|
|
#define BITM_TIMER_RUN_TMR02 (_ADI_MSK(0x00000004,uint16_t)) /* Start/Stop Timer n */
|
|
#define BITM_TIMER_RUN_TMR03 (_ADI_MSK(0x00000008,uint16_t)) /* Start/Stop Timer n */
|
|
#define BITM_TIMER_RUN_TMR04 (_ADI_MSK(0x00000010,uint16_t)) /* Start/Stop Timer n */
|
|
#define BITM_TIMER_RUN_TMR05 (_ADI_MSK(0x00000020,uint16_t)) /* Start/Stop Timer n */
|
|
#define BITM_TIMER_RUN_TMR06 (_ADI_MSK(0x00000040,uint16_t)) /* Start/Stop Timer n */
|
|
#define BITM_TIMER_RUN_TMR07 (_ADI_MSK(0x00000080,uint16_t)) /* Start/Stop Timer n */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TIMER_RUN_SET Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TIMER_RUN_SET_TMR00 0 /* RUN Set Alias */
|
|
#define BITP_TIMER_RUN_SET_TMR01 1 /* RUN Set Alias */
|
|
#define BITP_TIMER_RUN_SET_TMR02 2 /* RUN Set Alias */
|
|
#define BITP_TIMER_RUN_SET_TMR03 3 /* RUN Set Alias */
|
|
#define BITP_TIMER_RUN_SET_TMR04 4 /* RUN Set Alias */
|
|
#define BITP_TIMER_RUN_SET_TMR05 5 /* RUN Set Alias */
|
|
#define BITP_TIMER_RUN_SET_TMR06 6 /* RUN Set Alias */
|
|
#define BITP_TIMER_RUN_SET_TMR07 7 /* RUN Set Alias */
|
|
#define BITM_TIMER_RUN_SET_TMR00 (_ADI_MSK(0x00000001,uint16_t)) /* RUN Set Alias */
|
|
#define BITM_TIMER_RUN_SET_TMR01 (_ADI_MSK(0x00000002,uint16_t)) /* RUN Set Alias */
|
|
#define BITM_TIMER_RUN_SET_TMR02 (_ADI_MSK(0x00000004,uint16_t)) /* RUN Set Alias */
|
|
#define BITM_TIMER_RUN_SET_TMR03 (_ADI_MSK(0x00000008,uint16_t)) /* RUN Set Alias */
|
|
#define BITM_TIMER_RUN_SET_TMR04 (_ADI_MSK(0x00000010,uint16_t)) /* RUN Set Alias */
|
|
#define BITM_TIMER_RUN_SET_TMR05 (_ADI_MSK(0x00000020,uint16_t)) /* RUN Set Alias */
|
|
#define BITM_TIMER_RUN_SET_TMR06 (_ADI_MSK(0x00000040,uint16_t)) /* RUN Set Alias */
|
|
#define BITM_TIMER_RUN_SET_TMR07 (_ADI_MSK(0x00000080,uint16_t)) /* RUN Set Alias */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TIMER_RUN_CLR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TIMER_RUN_CLR_TMR00 0 /* RUN Clear Alias */
|
|
#define BITP_TIMER_RUN_CLR_TMR01 1 /* RUN Clear Alias */
|
|
#define BITP_TIMER_RUN_CLR_TMR02 2 /* RUN Clear Alias */
|
|
#define BITP_TIMER_RUN_CLR_TMR03 3 /* RUN Clear Alias */
|
|
#define BITP_TIMER_RUN_CLR_TMR04 4 /* RUN Clear Alias */
|
|
#define BITP_TIMER_RUN_CLR_TMR05 5 /* RUN Clear Alias */
|
|
#define BITP_TIMER_RUN_CLR_TMR06 6 /* RUN Clear Alias */
|
|
#define BITP_TIMER_RUN_CLR_TMR07 7 /* RUN Clear Alias */
|
|
#define BITM_TIMER_RUN_CLR_TMR00 (_ADI_MSK(0x00000001,uint16_t)) /* RUN Clear Alias */
|
|
#define BITM_TIMER_RUN_CLR_TMR01 (_ADI_MSK(0x00000002,uint16_t)) /* RUN Clear Alias */
|
|
#define BITM_TIMER_RUN_CLR_TMR02 (_ADI_MSK(0x00000004,uint16_t)) /* RUN Clear Alias */
|
|
#define BITM_TIMER_RUN_CLR_TMR03 (_ADI_MSK(0x00000008,uint16_t)) /* RUN Clear Alias */
|
|
#define BITM_TIMER_RUN_CLR_TMR04 (_ADI_MSK(0x00000010,uint16_t)) /* RUN Clear Alias */
|
|
#define BITM_TIMER_RUN_CLR_TMR05 (_ADI_MSK(0x00000020,uint16_t)) /* RUN Clear Alias */
|
|
#define BITM_TIMER_RUN_CLR_TMR06 (_ADI_MSK(0x00000040,uint16_t)) /* RUN Clear Alias */
|
|
#define BITM_TIMER_RUN_CLR_TMR07 (_ADI_MSK(0x00000080,uint16_t)) /* RUN Clear Alias */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TIMER_STOP_CFG Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TIMER_STOP_CFG_TMR00 0 /* Stop Mode Select */
|
|
#define BITP_TIMER_STOP_CFG_TMR01 1 /* Stop Mode Select */
|
|
#define BITP_TIMER_STOP_CFG_TMR02 2 /* Stop Mode Select */
|
|
#define BITP_TIMER_STOP_CFG_TMR03 3 /* Stop Mode Select */
|
|
#define BITP_TIMER_STOP_CFG_TMR04 4 /* Stop Mode Select */
|
|
#define BITP_TIMER_STOP_CFG_TMR05 5 /* Stop Mode Select */
|
|
#define BITP_TIMER_STOP_CFG_TMR06 6 /* Stop Mode Select */
|
|
#define BITP_TIMER_STOP_CFG_TMR07 7 /* Stop Mode Select */
|
|
#define BITM_TIMER_STOP_CFG_TMR00 (_ADI_MSK(0x00000001,uint16_t)) /* Stop Mode Select */
|
|
#define BITM_TIMER_STOP_CFG_TMR01 (_ADI_MSK(0x00000002,uint16_t)) /* Stop Mode Select */
|
|
#define BITM_TIMER_STOP_CFG_TMR02 (_ADI_MSK(0x00000004,uint16_t)) /* Stop Mode Select */
|
|
#define BITM_TIMER_STOP_CFG_TMR03 (_ADI_MSK(0x00000008,uint16_t)) /* Stop Mode Select */
|
|
#define BITM_TIMER_STOP_CFG_TMR04 (_ADI_MSK(0x00000010,uint16_t)) /* Stop Mode Select */
|
|
#define BITM_TIMER_STOP_CFG_TMR05 (_ADI_MSK(0x00000020,uint16_t)) /* Stop Mode Select */
|
|
#define BITM_TIMER_STOP_CFG_TMR06 (_ADI_MSK(0x00000040,uint16_t)) /* Stop Mode Select */
|
|
#define BITM_TIMER_STOP_CFG_TMR07 (_ADI_MSK(0x00000080,uint16_t)) /* Stop Mode Select */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TIMER_STOP_CFG_SET Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TIMER_STOP_CFG_SET_TMR00 0 /* STOP_CFG Set Alias */
|
|
#define BITP_TIMER_STOP_CFG_SET_TMR01 1 /* STOP_CFG Set Alias */
|
|
#define BITP_TIMER_STOP_CFG_SET_TMR02 2 /* STOP_CFG Set Alias */
|
|
#define BITP_TIMER_STOP_CFG_SET_TMR03 3 /* STOP_CFG Set Alias */
|
|
#define BITP_TIMER_STOP_CFG_SET_TMR04 4 /* STOP_CFG Set Alias */
|
|
#define BITP_TIMER_STOP_CFG_SET_TMR05 5 /* STOP_CFG Set Alias */
|
|
#define BITP_TIMER_STOP_CFG_SET_TMR06 6 /* STOP_CFG Set Alias */
|
|
#define BITP_TIMER_STOP_CFG_SET_TMR07 7 /* STOP_CFG Set Alias */
|
|
#define BITM_TIMER_STOP_CFG_SET_TMR00 (_ADI_MSK(0x00000001,uint16_t)) /* STOP_CFG Set Alias */
|
|
#define BITM_TIMER_STOP_CFG_SET_TMR01 (_ADI_MSK(0x00000002,uint16_t)) /* STOP_CFG Set Alias */
|
|
#define BITM_TIMER_STOP_CFG_SET_TMR02 (_ADI_MSK(0x00000004,uint16_t)) /* STOP_CFG Set Alias */
|
|
#define BITM_TIMER_STOP_CFG_SET_TMR03 (_ADI_MSK(0x00000008,uint16_t)) /* STOP_CFG Set Alias */
|
|
#define BITM_TIMER_STOP_CFG_SET_TMR04 (_ADI_MSK(0x00000010,uint16_t)) /* STOP_CFG Set Alias */
|
|
#define BITM_TIMER_STOP_CFG_SET_TMR05 (_ADI_MSK(0x00000020,uint16_t)) /* STOP_CFG Set Alias */
|
|
#define BITM_TIMER_STOP_CFG_SET_TMR06 (_ADI_MSK(0x00000040,uint16_t)) /* STOP_CFG Set Alias */
|
|
#define BITM_TIMER_STOP_CFG_SET_TMR07 (_ADI_MSK(0x00000080,uint16_t)) /* STOP_CFG Set Alias */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TIMER_STOP_CFG_CLR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TIMER_STOP_CFG_CLR_TMR00 0 /* STOP_CFG Clear Alias */
|
|
#define BITP_TIMER_STOP_CFG_CLR_TMR01 1 /* STOP_CFG Clear Alias */
|
|
#define BITP_TIMER_STOP_CFG_CLR_TMR02 2 /* STOP_CFG Clear Alias */
|
|
#define BITP_TIMER_STOP_CFG_CLR_TMR03 3 /* STOP_CFG Clear Alias */
|
|
#define BITP_TIMER_STOP_CFG_CLR_TMR04 4 /* STOP_CFG Clear Alias */
|
|
#define BITP_TIMER_STOP_CFG_CLR_TMR05 5 /* STOP_CFG Clear Alias */
|
|
#define BITP_TIMER_STOP_CFG_CLR_TMR06 6 /* STOP_CFG Clear Alias */
|
|
#define BITP_TIMER_STOP_CFG_CLR_TMR07 7 /* STOP_CFG Clear Alias */
|
|
#define BITM_TIMER_STOP_CFG_CLR_TMR00 (_ADI_MSK(0x00000001,uint16_t)) /* STOP_CFG Clear Alias */
|
|
#define BITM_TIMER_STOP_CFG_CLR_TMR01 (_ADI_MSK(0x00000002,uint16_t)) /* STOP_CFG Clear Alias */
|
|
#define BITM_TIMER_STOP_CFG_CLR_TMR02 (_ADI_MSK(0x00000004,uint16_t)) /* STOP_CFG Clear Alias */
|
|
#define BITM_TIMER_STOP_CFG_CLR_TMR03 (_ADI_MSK(0x00000008,uint16_t)) /* STOP_CFG Clear Alias */
|
|
#define BITM_TIMER_STOP_CFG_CLR_TMR04 (_ADI_MSK(0x00000010,uint16_t)) /* STOP_CFG Clear Alias */
|
|
#define BITM_TIMER_STOP_CFG_CLR_TMR05 (_ADI_MSK(0x00000020,uint16_t)) /* STOP_CFG Clear Alias */
|
|
#define BITM_TIMER_STOP_CFG_CLR_TMR06 (_ADI_MSK(0x00000040,uint16_t)) /* STOP_CFG Clear Alias */
|
|
#define BITM_TIMER_STOP_CFG_CLR_TMR07 (_ADI_MSK(0x00000080,uint16_t)) /* STOP_CFG Clear Alias */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TIMER_DATA_IMSK Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TIMER_DATA_IMSK_TMR00 0 /* Data Interrupt Mask */
|
|
#define BITP_TIMER_DATA_IMSK_TMR01 1 /* Data Interrupt Mask */
|
|
#define BITP_TIMER_DATA_IMSK_TMR02 2 /* Data Interrupt Mask */
|
|
#define BITP_TIMER_DATA_IMSK_TMR03 3 /* Data Interrupt Mask */
|
|
#define BITP_TIMER_DATA_IMSK_TMR04 4 /* Data Interrupt Mask */
|
|
#define BITP_TIMER_DATA_IMSK_TMR05 5 /* Data Interrupt Mask */
|
|
#define BITP_TIMER_DATA_IMSK_TMR06 6 /* Data Interrupt Mask */
|
|
#define BITP_TIMER_DATA_IMSK_TMR07 7 /* Data Interrupt Mask */
|
|
#define BITM_TIMER_DATA_IMSK_TMR00 (_ADI_MSK(0x00000001,uint16_t)) /* Data Interrupt Mask */
|
|
#define BITM_TIMER_DATA_IMSK_TMR01 (_ADI_MSK(0x00000002,uint16_t)) /* Data Interrupt Mask */
|
|
#define BITM_TIMER_DATA_IMSK_TMR02 (_ADI_MSK(0x00000004,uint16_t)) /* Data Interrupt Mask */
|
|
#define BITM_TIMER_DATA_IMSK_TMR03 (_ADI_MSK(0x00000008,uint16_t)) /* Data Interrupt Mask */
|
|
#define BITM_TIMER_DATA_IMSK_TMR04 (_ADI_MSK(0x00000010,uint16_t)) /* Data Interrupt Mask */
|
|
#define BITM_TIMER_DATA_IMSK_TMR05 (_ADI_MSK(0x00000020,uint16_t)) /* Data Interrupt Mask */
|
|
#define BITM_TIMER_DATA_IMSK_TMR06 (_ADI_MSK(0x00000040,uint16_t)) /* Data Interrupt Mask */
|
|
#define BITM_TIMER_DATA_IMSK_TMR07 (_ADI_MSK(0x00000080,uint16_t)) /* Data Interrupt Mask */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TIMER_STAT_IMSK Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TIMER_STAT_IMSK_TMR00 0 /* Status Interrupt Mask */
|
|
#define BITP_TIMER_STAT_IMSK_TMR01 1 /* Status Interrupt Mask */
|
|
#define BITP_TIMER_STAT_IMSK_TMR02 2 /* Status Interrupt Mask */
|
|
#define BITP_TIMER_STAT_IMSK_TMR03 3 /* Status Interrupt Mask */
|
|
#define BITP_TIMER_STAT_IMSK_TMR04 4 /* Status Interrupt Mask */
|
|
#define BITP_TIMER_STAT_IMSK_TMR05 5 /* Status Interrupt Mask */
|
|
#define BITP_TIMER_STAT_IMSK_TMR06 6 /* Status Interrupt Mask */
|
|
#define BITP_TIMER_STAT_IMSK_TMR07 7 /* Status Interrupt Mask */
|
|
#define BITM_TIMER_STAT_IMSK_TMR00 (_ADI_MSK(0x00000001,uint16_t)) /* Status Interrupt Mask */
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#define BITM_TIMER_STAT_IMSK_TMR01 (_ADI_MSK(0x00000002,uint16_t)) /* Status Interrupt Mask */
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#define BITM_TIMER_STAT_IMSK_TMR02 (_ADI_MSK(0x00000004,uint16_t)) /* Status Interrupt Mask */
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#define BITM_TIMER_STAT_IMSK_TMR03 (_ADI_MSK(0x00000008,uint16_t)) /* Status Interrupt Mask */
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#define BITM_TIMER_STAT_IMSK_TMR04 (_ADI_MSK(0x00000010,uint16_t)) /* Status Interrupt Mask */
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#define BITM_TIMER_STAT_IMSK_TMR05 (_ADI_MSK(0x00000020,uint16_t)) /* Status Interrupt Mask */
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#define BITM_TIMER_STAT_IMSK_TMR06 (_ADI_MSK(0x00000040,uint16_t)) /* Status Interrupt Mask */
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#define BITM_TIMER_STAT_IMSK_TMR07 (_ADI_MSK(0x00000080,uint16_t)) /* Status Interrupt Mask */
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/* ------------------------------------------------------------------------------------------------------------------------
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TIMER_TRG_MSK Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_TIMER_TRG_MSK_TMR00 0 /* Trigger Output Mask */
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#define BITP_TIMER_TRG_MSK_TMR01 1 /* Trigger Output Mask */
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#define BITP_TIMER_TRG_MSK_TMR02 2 /* Trigger Output Mask */
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#define BITP_TIMER_TRG_MSK_TMR03 3 /* Trigger Output Mask */
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#define BITP_TIMER_TRG_MSK_TMR04 4 /* Trigger Output Mask */
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#define BITP_TIMER_TRG_MSK_TMR05 5 /* Trigger Output Mask */
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#define BITP_TIMER_TRG_MSK_TMR06 6 /* Trigger Output Mask */
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#define BITP_TIMER_TRG_MSK_TMR07 7 /* Trigger Output Mask */
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#define BITM_TIMER_TRG_MSK_TMR00 (_ADI_MSK(0x00000001,uint16_t)) /* Trigger Output Mask */
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#define BITM_TIMER_TRG_MSK_TMR01 (_ADI_MSK(0x00000002,uint16_t)) /* Trigger Output Mask */
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#define BITM_TIMER_TRG_MSK_TMR02 (_ADI_MSK(0x00000004,uint16_t)) /* Trigger Output Mask */
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#define BITM_TIMER_TRG_MSK_TMR03 (_ADI_MSK(0x00000008,uint16_t)) /* Trigger Output Mask */
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#define BITM_TIMER_TRG_MSK_TMR04 (_ADI_MSK(0x00000010,uint16_t)) /* Trigger Output Mask */
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#define BITM_TIMER_TRG_MSK_TMR05 (_ADI_MSK(0x00000020,uint16_t)) /* Trigger Output Mask */
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#define BITM_TIMER_TRG_MSK_TMR06 (_ADI_MSK(0x00000040,uint16_t)) /* Trigger Output Mask */
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#define BITM_TIMER_TRG_MSK_TMR07 (_ADI_MSK(0x00000080,uint16_t)) /* Trigger Output Mask */
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/* ------------------------------------------------------------------------------------------------------------------------
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TIMER_TRG_IE Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_TIMER_TRG_IE_TMR00 0 /* Trigger Input Enable */
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#define BITP_TIMER_TRG_IE_TMR01 1 /* Trigger Input Enable */
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#define BITP_TIMER_TRG_IE_TMR02 2 /* Trigger Input Enable */
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#define BITP_TIMER_TRG_IE_TMR03 3 /* Trigger Input Enable */
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#define BITP_TIMER_TRG_IE_TMR04 4 /* Trigger Input Enable */
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#define BITP_TIMER_TRG_IE_TMR05 5 /* Trigger Input Enable */
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#define BITP_TIMER_TRG_IE_TMR06 6 /* Trigger Input Enable */
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#define BITP_TIMER_TRG_IE_TMR07 7 /* Trigger Input Enable */
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#define BITM_TIMER_TRG_IE_TMR00 (_ADI_MSK(0x00000001,uint16_t)) /* Trigger Input Enable */
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#define BITM_TIMER_TRG_IE_TMR01 (_ADI_MSK(0x00000002,uint16_t)) /* Trigger Input Enable */
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#define BITM_TIMER_TRG_IE_TMR02 (_ADI_MSK(0x00000004,uint16_t)) /* Trigger Input Enable */
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#define BITM_TIMER_TRG_IE_TMR03 (_ADI_MSK(0x00000008,uint16_t)) /* Trigger Input Enable */
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#define BITM_TIMER_TRG_IE_TMR04 (_ADI_MSK(0x00000010,uint16_t)) /* Trigger Input Enable */
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#define BITM_TIMER_TRG_IE_TMR05 (_ADI_MSK(0x00000020,uint16_t)) /* Trigger Input Enable */
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#define BITM_TIMER_TRG_IE_TMR06 (_ADI_MSK(0x00000040,uint16_t)) /* Trigger Input Enable */
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#define BITM_TIMER_TRG_IE_TMR07 (_ADI_MSK(0x00000080,uint16_t)) /* Trigger Input Enable */
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/* ------------------------------------------------------------------------------------------------------------------------
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TIMER_DATA_ILAT Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_TIMER_DATA_ILAT_TMR00 0 /* Data Interrupt Latch */
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#define BITP_TIMER_DATA_ILAT_TMR01 1 /* Data Interrupt Latch */
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#define BITP_TIMER_DATA_ILAT_TMR02 2 /* Data Interrupt Latch */
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#define BITP_TIMER_DATA_ILAT_TMR03 3 /* Data Interrupt Latch */
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#define BITP_TIMER_DATA_ILAT_TMR04 4 /* Data Interrupt Latch */
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#define BITP_TIMER_DATA_ILAT_TMR05 5 /* Data Interrupt Latch */
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#define BITP_TIMER_DATA_ILAT_TMR06 6 /* Data Interrupt Latch */
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#define BITP_TIMER_DATA_ILAT_TMR07 7 /* Data Interrupt Latch */
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#define BITM_TIMER_DATA_ILAT_TMR00 (_ADI_MSK(0x00000001,uint16_t)) /* Data Interrupt Latch */
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#define BITM_TIMER_DATA_ILAT_TMR01 (_ADI_MSK(0x00000002,uint16_t)) /* Data Interrupt Latch */
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#define BITM_TIMER_DATA_ILAT_TMR02 (_ADI_MSK(0x00000004,uint16_t)) /* Data Interrupt Latch */
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#define BITM_TIMER_DATA_ILAT_TMR03 (_ADI_MSK(0x00000008,uint16_t)) /* Data Interrupt Latch */
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#define BITM_TIMER_DATA_ILAT_TMR04 (_ADI_MSK(0x00000010,uint16_t)) /* Data Interrupt Latch */
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#define BITM_TIMER_DATA_ILAT_TMR05 (_ADI_MSK(0x00000020,uint16_t)) /* Data Interrupt Latch */
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#define BITM_TIMER_DATA_ILAT_TMR06 (_ADI_MSK(0x00000040,uint16_t)) /* Data Interrupt Latch */
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#define BITM_TIMER_DATA_ILAT_TMR07 (_ADI_MSK(0x00000080,uint16_t)) /* Data Interrupt Latch */
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/* ------------------------------------------------------------------------------------------------------------------------
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TIMER_STAT_ILAT Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_TIMER_STAT_ILAT_TMR00 0 /* Status Interrupt Latch */
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#define BITP_TIMER_STAT_ILAT_TMR01 1 /* Status Interrupt Latch */
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#define BITP_TIMER_STAT_ILAT_TMR02 2 /* Status Interrupt Latch */
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#define BITP_TIMER_STAT_ILAT_TMR03 3 /* Status Interrupt Latch */
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#define BITP_TIMER_STAT_ILAT_TMR04 4 /* Status Interrupt Latch */
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#define BITP_TIMER_STAT_ILAT_TMR05 5 /* Status Interrupt Latch */
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#define BITP_TIMER_STAT_ILAT_TMR06 6 /* Status Interrupt Latch */
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#define BITP_TIMER_STAT_ILAT_TMR07 7 /* Status Interrupt Latch */
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#define BITM_TIMER_STAT_ILAT_TMR00 (_ADI_MSK(0x00000001,uint16_t)) /* Status Interrupt Latch */
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#define BITM_TIMER_STAT_ILAT_TMR01 (_ADI_MSK(0x00000002,uint16_t)) /* Status Interrupt Latch */
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#define BITM_TIMER_STAT_ILAT_TMR02 (_ADI_MSK(0x00000004,uint16_t)) /* Status Interrupt Latch */
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#define BITM_TIMER_STAT_ILAT_TMR03 (_ADI_MSK(0x00000008,uint16_t)) /* Status Interrupt Latch */
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#define BITM_TIMER_STAT_ILAT_TMR04 (_ADI_MSK(0x00000010,uint16_t)) /* Status Interrupt Latch */
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#define BITM_TIMER_STAT_ILAT_TMR05 (_ADI_MSK(0x00000020,uint16_t)) /* Status Interrupt Latch */
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#define BITM_TIMER_STAT_ILAT_TMR06 (_ADI_MSK(0x00000040,uint16_t)) /* Status Interrupt Latch */
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#define BITM_TIMER_STAT_ILAT_TMR07 (_ADI_MSK(0x00000080,uint16_t)) /* Status Interrupt Latch */
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/* ------------------------------------------------------------------------------------------------------------------------
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TIMER_ERR_TYPE Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_TIMER_ERR_TYPE_TERR7 14 /* Error type for Timer 7 */
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#define BITP_TIMER_ERR_TYPE_TERR6 12 /* Error type for Timer 6 */
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#define BITP_TIMER_ERR_TYPE_TERR5 10 /* Error type for Timer 5 */
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#define BITP_TIMER_ERR_TYPE_TERR4 8 /* Error type for Timer 4 */
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#define BITP_TIMER_ERR_TYPE_TERR3 6 /* Error type for Timer 3 */
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#define BITP_TIMER_ERR_TYPE_TERR2 4 /* Error type for Timer 2 */
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#define BITP_TIMER_ERR_TYPE_TERR1 2 /* Error type for Timer 1 */
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#define BITP_TIMER_ERR_TYPE_TERR0 0 /* Error type for Timer 0 */
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#define BITM_TIMER_ERR_TYPE_TERR7 (_ADI_MSK(0x0000C000,uint32_t)) /* Error type for Timer 7 */
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#define ENUM_TIMER_ERR_TYPE_NO_ERR7 (_ADI_MSK(0x00000000,uint32_t)) /* TERR7: No Error */
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#define ENUM_TIMER_ERR_TYPE_CNTOVF7 (_ADI_MSK(0x00004000,uint32_t)) /* TERR7: Counter Overflow Error */
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#define ENUM_TIMER_ERR_TYPE_PERPRG7 (_ADI_MSK(0x00008000,uint32_t)) /* TERR7: PER Register Programming Error */
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#define ENUM_TIMER_ERR_TYPE_PULSEPRG7 (_ADI_MSK(0x0000C000,uint32_t)) /* TERR7: WID or DLY Register Programming Error */
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#define BITM_TIMER_ERR_TYPE_TERR6 (_ADI_MSK(0x00003000,uint32_t)) /* Error type for Timer 6 */
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#define ENUM_TIMER_ERR_TYPE_NO_ERR6 (_ADI_MSK(0x00000000,uint32_t)) /* TERR6: No Error */
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#define ENUM_TIMER_ERR_TYPE_CNTOVF6 (_ADI_MSK(0x00001000,uint32_t)) /* TERR6: Counter Overflow Error */
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#define ENUM_TIMER_ERR_TYPE_PERPRG6 (_ADI_MSK(0x00002000,uint32_t)) /* TERR6: PER Register Programming Error */
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#define ENUM_TIMER_ERR_TYPE_PULSEPRG6 (_ADI_MSK(0x00003000,uint32_t)) /* TERR6: WID or DLY Register Programming Error */
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#define BITM_TIMER_ERR_TYPE_TERR5 (_ADI_MSK(0x00000C00,uint32_t)) /* Error type for Timer 5 */
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#define ENUM_TIMER_ERR_TYPE_NO_ERR5 (_ADI_MSK(0x00000000,uint32_t)) /* TERR5: No Error */
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#define ENUM_TIMER_ERR_TYPE_CNTOVF5 (_ADI_MSK(0x00000400,uint32_t)) /* TERR5: Counter Overflow Error */
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#define ENUM_TIMER_ERR_TYPE_PERPRG5 (_ADI_MSK(0x00000800,uint32_t)) /* TERR5: PER Register Programming Error */
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#define ENUM_TIMER_ERR_TYPE_PULSEPRG5 (_ADI_MSK(0x00000C00,uint32_t)) /* TERR5: WID or DLY Register Programming Error */
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#define BITM_TIMER_ERR_TYPE_TERR4 (_ADI_MSK(0x00000300,uint32_t)) /* Error type for Timer 4 */
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#define ENUM_TIMER_ERR_TYPE_NO_ERR4 (_ADI_MSK(0x00000000,uint32_t)) /* TERR4: No Error */
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#define ENUM_TIMER_ERR_TYPE_CNTOVF4 (_ADI_MSK(0x00000100,uint32_t)) /* TERR4: Counter Overflow Error */
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#define ENUM_TIMER_ERR_TYPE_PERPRG4 (_ADI_MSK(0x00000200,uint32_t)) /* TERR4: PER Register Programming Error */
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#define ENUM_TIMER_ERR_TYPE_PULSEPRG4 (_ADI_MSK(0x00000300,uint32_t)) /* TERR4: WID or DLY Register Programming Error */
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#define BITM_TIMER_ERR_TYPE_TERR3 (_ADI_MSK(0x000000C0,uint32_t)) /* Error type for Timer 3 */
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#define ENUM_TIMER_ERR_TYPE_NO_ERR3 (_ADI_MSK(0x00000000,uint32_t)) /* TERR3: No Error */
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#define ENUM_TIMER_ERR_TYPE_CNTOVF3 (_ADI_MSK(0x00000040,uint32_t)) /* TERR3: Counter Overflow Error */
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#define ENUM_TIMER_ERR_TYPE_PERPRG3 (_ADI_MSK(0x00000080,uint32_t)) /* TERR3: PER Register Programming Error */
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#define ENUM_TIMER_ERR_TYPE_PULSEPRG3 (_ADI_MSK(0x000000C0,uint32_t)) /* TERR3: WID or DLY Register Programming Error */
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#define BITM_TIMER_ERR_TYPE_TERR2 (_ADI_MSK(0x00000030,uint32_t)) /* Error type for Timer 2 */
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#define ENUM_TIMER_ERR_TYPE_NO_ERR2 (_ADI_MSK(0x00000000,uint32_t)) /* TERR2: No Error */
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#define ENUM_TIMER_ERR_TYPE_CNTOVF2 (_ADI_MSK(0x00000010,uint32_t)) /* TERR2: Counter Overflow Error */
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#define ENUM_TIMER_ERR_TYPE_PERPRG2 (_ADI_MSK(0x00000020,uint32_t)) /* TERR2: PER Register Programming Error */
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#define ENUM_TIMER_ERR_TYPE_PULSEPRG2 (_ADI_MSK(0x00000030,uint32_t)) /* TERR2: WID or DLY Register Programming Error */
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#define BITM_TIMER_ERR_TYPE_TERR1 (_ADI_MSK(0x0000000C,uint32_t)) /* Error type for Timer 1 */
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#define ENUM_TIMER_ERR_TYPE_NO_ERR1 (_ADI_MSK(0x00000000,uint32_t)) /* TERR1: No Error */
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#define ENUM_TIMER_ERR_TYPE_CNTOVF1 (_ADI_MSK(0x00000004,uint32_t)) /* TERR1: Counter Overflow Error */
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#define ENUM_TIMER_ERR_TYPE_PERPRG1 (_ADI_MSK(0x00000008,uint32_t)) /* TERR1: PER Register Programming Error */
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#define ENUM_TIMER_ERR_TYPE_PULSEPRG1 (_ADI_MSK(0x0000000C,uint32_t)) /* TERR1: WID or DLY Register Programming Error */
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#define BITM_TIMER_ERR_TYPE_TERR0 (_ADI_MSK(0x00000003,uint32_t)) /* Error type for Timer 0 */
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#define ENUM_TIMER_ERR_TYPE_NO_ERR0 (_ADI_MSK(0x00000000,uint32_t)) /* TERR0: No Error */
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#define ENUM_TIMER_ERR_TYPE_CNTOVF0 (_ADI_MSK(0x00000001,uint32_t)) /* TERR0: Counter Overflow Error */
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#define ENUM_TIMER_ERR_TYPE_PERPRG0 (_ADI_MSK(0x00000002,uint32_t)) /* TERR0: PER Register Programming Error */
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#define ENUM_TIMER_ERR_TYPE_PULSEPRG0 (_ADI_MSK(0x00000003,uint32_t)) /* TERR0: WID or DLY Register Programming Error */
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/* ------------------------------------------------------------------------------------------------------------------------
|
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TIMER_TMR_CFG Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_TIMER_TMR_CFG_EMURUN 15 /* Run Timer (Counter) During Emulation */
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#define BITP_TIMER_TMR_CFG_BPEREN 14 /* Broadcast Period Enable */
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#define BITP_TIMER_TMR_CFG_BWIDEN 13 /* Broadcast Width Enable */
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#define BITP_TIMER_TMR_CFG_BDLYEN 12 /* Broadcast Delay Enable */
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#define BITP_TIMER_TMR_CFG_OUTDIS 11 /* Output Disable */
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#define BITP_TIMER_TMR_CFG_TINSEL 10 /* Timer Input Select (for WIDCAP, WATCHDOG, PININT modes) */
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#define BITP_TIMER_TMR_CFG_CLKSEL 8 /* Clock Select */
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#define BITP_TIMER_TMR_CFG_PULSEHI 7 /* Polarity Response Select */
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#define BITP_TIMER_TMR_CFG_SLAVETRIG 6 /* Slave Trigger Response */
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#define BITP_TIMER_TMR_CFG_IRQMODE 4 /* Interrupt Modes */
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#define BITP_TIMER_TMR_CFG_TMODE 0 /* Timer Mode Select */
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#define BITM_TIMER_TMR_CFG_EMURUN (_ADI_MSK(0x00008000,uint16_t)) /* Run Timer (Counter) During Emulation */
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#define ENUM_TIMER_TMR_CFG_EMU_NOCNT (_ADI_MSK(0x00000000,uint16_t)) /* EMURUN: Stop Timer During Emulation */
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#define ENUM_TIMER_TMR_CFG_EMU_CNT (_ADI_MSK(0x00008000,uint16_t)) /* EMURUN: Run Timer During Emulation */
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#define BITM_TIMER_TMR_CFG_BPEREN (_ADI_MSK(0x00004000,uint16_t)) /* Broadcast Period Enable */
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#define ENUM_TIMER_TMR_CFG_BCASTPER_DIS (_ADI_MSK(0x00000000,uint16_t)) /* BPEREN: Disable Broadcast to PER Register */
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#define ENUM_TIMER_TMR_CFG_BCASTPER_EN (_ADI_MSK(0x00004000,uint16_t)) /* BPEREN: Enable Broadcast to PER Register */
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#define BITM_TIMER_TMR_CFG_BWIDEN (_ADI_MSK(0x00002000,uint16_t)) /* Broadcast Width Enable */
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#define ENUM_TIMER_TMR_CFG_BCASTWID_DIS (_ADI_MSK(0x00000000,uint16_t)) /* BWIDEN: Disable Broadcast to WID Register */
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#define ENUM_TIMER_TMR_CFG_BCASTWID_EN (_ADI_MSK(0x00002000,uint16_t)) /* BWIDEN: Enable Broadcast to WID Register */
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#define BITM_TIMER_TMR_CFG_BDLYEN (_ADI_MSK(0x00001000,uint16_t)) /* Broadcast Delay Enable */
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#define ENUM_TIMER_TMR_CFG_BCASTDLY_DIS (_ADI_MSK(0x00000000,uint16_t)) /* BDLYEN: Disable Broadcast to DLY Register */
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#define ENUM_TIMER_TMR_CFG_BCASTDLY_EN (_ADI_MSK(0x00001000,uint16_t)) /* BDLYEN: Enable Broadcast to DLY Register */
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#define BITM_TIMER_TMR_CFG_OUTDIS (_ADI_MSK(0x00000800,uint16_t)) /* Output Disable */
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#define ENUM_TIMER_TMR_CFG_PADOUT_EN (_ADI_MSK(0x00000000,uint16_t)) /* OUTDIS: Enable TMR pin output buffer */
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#define ENUM_TIMER_TMR_CFG_PADOUT_DIS (_ADI_MSK(0x00000800,uint16_t)) /* OUTDIS: Disable TMR pin output buffer */
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#define BITM_TIMER_TMR_CFG_TINSEL (_ADI_MSK(0x00000400,uint16_t)) /* Timer Input Select (for WIDCAP, WATCHDOG, PININT modes) */
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#define ENUM_TIMER_TMR_CFG_TINSEL_TMR (_ADI_MSK(0x00000000,uint16_t)) /* TINSEL: Use TMR pin input */
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#define ENUM_TIMER_TMR_CFG_TINSEL_AUX (_ADI_MSK(0x00000400,uint16_t)) /* TINSEL: Use TMR Alternate Capture Input */
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#define BITM_TIMER_TMR_CFG_CLKSEL (_ADI_MSK(0x00000300,uint16_t)) /* Clock Select */
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#define ENUM_TIMER_TMR_CFG_CLKSEL_SCLK (_ADI_MSK(0x00000000,uint16_t)) /* CLKSEL: Use SCLK */
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#define ENUM_TIMER_TMR_CFG_CLKSEL_ALT0 (_ADI_MSK(0x00000100,uint16_t)) /* CLKSEL: Use TMR_ALT_CLK0 as the TMR clock */
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#define ENUM_TIMER_TMR_CFG_CLKSEL_ALT1 (_ADI_MSK(0x00000300,uint16_t)) /* CLKSEL: Use TMR_ALT_CLK1 as the TMR clock */
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#define BITM_TIMER_TMR_CFG_PULSEHI (_ADI_MSK(0x00000080,uint16_t)) /* Polarity Response Select */
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#define ENUM_TIMER_TMR_CFG_NEG_EDGE (_ADI_MSK(0x00000000,uint16_t)) /* PULSEHI: Negative Response/Pulse */
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#define ENUM_TIMER_TMR_CFG_POS_EDGE (_ADI_MSK(0x00000080,uint16_t)) /* PULSEHI: Positive Response/Pulse */
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#define BITM_TIMER_TMR_CFG_SLAVETRIG (_ADI_MSK(0x00000040,uint16_t)) /* Slave Trigger Response */
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#define ENUM_TIMER_TMR_CFG_TRIGSTOP (_ADI_MSK(0x00000000,uint16_t)) /* SLAVETRIG: Pulse stops timer if it is running */
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#define ENUM_TIMER_TMR_CFG_TRIGSTART (_ADI_MSK(0x00000040,uint16_t)) /* SLAVETRIG: Pulse starts timer if it is stopped */
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#define BITM_TIMER_TMR_CFG_IRQMODE (_ADI_MSK(0x00000030,uint16_t)) /* Interrupt Modes */
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#define ENUM_TIMER_TMR_CFG_IRQMODE0 (_ADI_MSK(0x00000000,uint16_t)) /* IRQMODE: Active Edge Mode */
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#define ENUM_TIMER_TMR_CFG_IRQMODE1 (_ADI_MSK(0x00000010,uint16_t)) /* IRQMODE: Delay Expired Mode */
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#define ENUM_TIMER_TMR_CFG_IRQMODE2 (_ADI_MSK(0x00000020,uint16_t)) /* IRQMODE: Width Plus Delay Expired Mode */
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#define ENUM_TIMER_TMR_CFG_IRQMODE3 (_ADI_MSK(0x00000030,uint16_t)) /* IRQMODE: Period Expired Mode */
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#define BITM_TIMER_TMR_CFG_TMODE (_ADI_MSK(0x0000000F,uint16_t)) /* Timer Mode Select */
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#define ENUM_TIMER_TMR_CFG_IDLE_MODE (_ADI_MSK(0x00000000,uint16_t)) /* TMODE: Idle Mode */
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#define ENUM_TIMER_TMR_CFG_WIDCAP0_MODE (_ADI_MSK(0x0000000A,uint16_t)) /* TMODE: Width Capture Asserted Mode */
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#define ENUM_TIMER_TMR_CFG_WIDCAP1_MODE (_ADI_MSK(0x0000000B,uint16_t)) /* TMODE: Width Capture Deasserted Mode */
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#define ENUM_TIMER_TMR_CFG_PWMCONT_MODE (_ADI_MSK(0x0000000C,uint16_t)) /* TMODE: Continuous PWMOUT mode */
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#define ENUM_TIMER_TMR_CFG_PWMSING_MODE (_ADI_MSK(0x0000000D,uint16_t)) /* TMODE: Single pulse PWMOUT mode */
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#define ENUM_TIMER_TMR_CFG_EXTCLK_MODE (_ADI_MSK(0x0000000E,uint16_t)) /* TMODE: EXTCLK mode */
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#define ENUM_TIMER_TMR_CFG_PININT_MODE (_ADI_MSK(0x0000000F,uint16_t)) /* TMODE: PININT (pin interrupt) mode */
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#define ENUM_TIMER_TMR_CFG_WDPER_MODE (_ADI_MSK(0x00000008,uint16_t)) /* TMODE: Period Watchdog Mode */
|
|
#define ENUM_TIMER_TMR_CFG_WDWID_MODE (_ADI_MSK(0x00000009,uint16_t)) /* TMODE: Width Watchdog Mode */
|
|
|
|
/* ==================================================
|
|
Cyclic Redundancy Check Unit Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
CRC0
|
|
========================= */
|
|
#define REG_CRC0_CTL 0xFFC01C00 /* CRC0 Control Register */
|
|
#define REG_CRC0_DCNT 0xFFC01C04 /* CRC0 Data Word Count Register */
|
|
#define REG_CRC0_DCNTRLD 0xFFC01C08 /* CRC0 Data Word Count Reload Register */
|
|
#define REG_CRC0_COMP 0xFFC01C14 /* CRC0 Data Compare Register */
|
|
#define REG_CRC0_FILLVAL 0xFFC01C18 /* CRC0 Fill Value Register */
|
|
#define REG_CRC0_DFIFO 0xFFC01C1C /* CRC0 Data FIFO Register */
|
|
#define REG_CRC0_INEN 0xFFC01C20 /* CRC0 Interrupt Enable Register */
|
|
#define REG_CRC0_INEN_SET 0xFFC01C24 /* CRC0 Interrupt Enable Set Register */
|
|
#define REG_CRC0_INEN_CLR 0xFFC01C28 /* CRC0 Interrupt Enable Clear Register */
|
|
#define REG_CRC0_POLY 0xFFC01C2C /* CRC0 Polynomial Register */
|
|
#define REG_CRC0_STAT 0xFFC01C40 /* CRC0 Status Register */
|
|
#define REG_CRC0_DCNTCAP 0xFFC01C44 /* CRC0 Data Count Capture Register */
|
|
#define REG_CRC0_RESULT_FIN 0xFFC01C4C /* CRC0 CRC Final Result Register */
|
|
#define REG_CRC0_RESULT_CUR 0xFFC01C50 /* CRC0 CRC Current Result Register */
|
|
#define REG_CRC0_REVID 0xFFC01C60 /* CRC0 Revision ID Register */
|
|
|
|
/* =========================
|
|
CRC1
|
|
========================= */
|
|
#define REG_CRC1_CTL 0xFFC01D00 /* CRC1 Control Register */
|
|
#define REG_CRC1_DCNT 0xFFC01D04 /* CRC1 Data Word Count Register */
|
|
#define REG_CRC1_DCNTRLD 0xFFC01D08 /* CRC1 Data Word Count Reload Register */
|
|
#define REG_CRC1_COMP 0xFFC01D14 /* CRC1 Data Compare Register */
|
|
#define REG_CRC1_FILLVAL 0xFFC01D18 /* CRC1 Fill Value Register */
|
|
#define REG_CRC1_DFIFO 0xFFC01D1C /* CRC1 Data FIFO Register */
|
|
#define REG_CRC1_INEN 0xFFC01D20 /* CRC1 Interrupt Enable Register */
|
|
#define REG_CRC1_INEN_SET 0xFFC01D24 /* CRC1 Interrupt Enable Set Register */
|
|
#define REG_CRC1_INEN_CLR 0xFFC01D28 /* CRC1 Interrupt Enable Clear Register */
|
|
#define REG_CRC1_POLY 0xFFC01D2C /* CRC1 Polynomial Register */
|
|
#define REG_CRC1_STAT 0xFFC01D40 /* CRC1 Status Register */
|
|
#define REG_CRC1_DCNTCAP 0xFFC01D44 /* CRC1 Data Count Capture Register */
|
|
#define REG_CRC1_RESULT_FIN 0xFFC01D4C /* CRC1 CRC Final Result Register */
|
|
#define REG_CRC1_RESULT_CUR 0xFFC01D50 /* CRC1 CRC Current Result Register */
|
|
#define REG_CRC1_REVID 0xFFC01D60 /* CRC1 Revision ID Register */
|
|
|
|
/* =========================
|
|
CRC
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CRC_CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CRC_CTL_CMPMIRR 22 /* COMPARE Register Mirroring */
|
|
#define BITP_CRC_CTL_POLYMIRR 21 /* Polynomial Register Mirroring */
|
|
#define BITP_CRC_CTL_RSLTMIRR 20 /* Result Register Mirroring */
|
|
#define BITP_CRC_CTL_FDSEL 19 /* FIFO Data Select */
|
|
#define BITP_CRC_CTL_W16SWP 18 /* Word16 Swapping */
|
|
#define BITP_CRC_CTL_BYTMIRR 17 /* Byte Mirroring */
|
|
#define BITP_CRC_CTL_BITMIRR 16 /* Bit Mirroring */
|
|
#define BITP_CRC_CTL_IRRSTALL 13 /* Intermediate Result Ready Stall */
|
|
#define BITP_CRC_CTL_OBRSTALL 12 /* Output Buffer Ready Stall */
|
|
#define BITP_CRC_CTL_AUTOCLRF 9 /* Auto Clear to One */
|
|
#define BITP_CRC_CTL_AUTOCLRZ 8 /* Auto Clear to Zero */
|
|
#define BITP_CRC_CTL_OPMODE 4 /* Operation Mode */
|
|
#define BITP_CRC_CTL_BLKEN 0 /* Block Enable */
|
|
#define BITM_CRC_CTL_CMPMIRR (_ADI_MSK(0x00400000,uint32_t)) /* COMPARE Register Mirroring */
|
|
#define BITM_CRC_CTL_POLYMIRR (_ADI_MSK(0x00200000,uint32_t)) /* Polynomial Register Mirroring */
|
|
#define BITM_CRC_CTL_RSLTMIRR (_ADI_MSK(0x00100000,uint32_t)) /* Result Register Mirroring */
|
|
#define BITM_CRC_CTL_FDSEL (_ADI_MSK(0x00080000,uint32_t)) /* FIFO Data Select */
|
|
#define BITM_CRC_CTL_W16SWP (_ADI_MSK(0x00040000,uint32_t)) /* Word16 Swapping */
|
|
#define BITM_CRC_CTL_BYTMIRR (_ADI_MSK(0x00020000,uint32_t)) /* Byte Mirroring */
|
|
#define BITM_CRC_CTL_BITMIRR (_ADI_MSK(0x00010000,uint32_t)) /* Bit Mirroring */
|
|
#define BITM_CRC_CTL_IRRSTALL (_ADI_MSK(0x00002000,uint32_t)) /* Intermediate Result Ready Stall */
|
|
#define BITM_CRC_CTL_OBRSTALL (_ADI_MSK(0x00001000,uint32_t)) /* Output Buffer Ready Stall */
|
|
#define BITM_CRC_CTL_AUTOCLRF (_ADI_MSK(0x00000200,uint32_t)) /* Auto Clear to One */
|
|
#define BITM_CRC_CTL_AUTOCLRZ (_ADI_MSK(0x00000100,uint32_t)) /* Auto Clear to Zero */
|
|
#define BITM_CRC_CTL_OPMODE (_ADI_MSK(0x000000F0,uint32_t)) /* Operation Mode */
|
|
#define BITM_CRC_CTL_BLKEN (_ADI_MSK(0x00000001,uint32_t)) /* Block Enable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CRC_INEN Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CRC_INEN_DCNTEXP 4 /* Data Count Expired (Status) Interrupt Enable */
|
|
#define BITP_CRC_INEN_CMPERR 1 /* Compare Error Interrupt Enable */
|
|
|
|
#define BITM_CRC_INEN_DCNTEXP (_ADI_MSK(0x00000010,uint32_t)) /* Data Count Expired (Status) Interrupt Enable */
|
|
#define ENUM_CRC_INEN_DCNTEXP_MSK (_ADI_MSK(0x00000000,uint32_t)) /* DCNTEXP: Disable (mask) interrupt */
|
|
#define ENUM_CRC_INEN_DCNTEXP_UMSK (_ADI_MSK(0x00000010,uint32_t)) /* DCNTEXP: Enable (unmask) interrupt */
|
|
|
|
#define BITM_CRC_INEN_CMPERR (_ADI_MSK(0x00000002,uint32_t)) /* Compare Error Interrupt Enable */
|
|
#define ENUM_CRC_INEN_CMPERR_MSK (_ADI_MSK(0x00000000,uint32_t)) /* CMPERR: Disable (mask) interrupt */
|
|
#define ENUM_CRC_INEN_CMPERR_UMSK (_ADI_MSK(0x00000002,uint32_t)) /* CMPERR: Enable (unmask) interrupt */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CRC_INEN_SET Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CRC_INEN_SET_DCNTEXP 4 /* Data Count Expired (Status) Interrupt Enable Set */
|
|
#define BITP_CRC_INEN_SET_CMPERR 1 /* Compare Error Interrupt Enable Set */
|
|
#define BITM_CRC_INEN_SET_DCNTEXP (_ADI_MSK(0x00000010,uint32_t)) /* Data Count Expired (Status) Interrupt Enable Set */
|
|
#define BITM_CRC_INEN_SET_CMPERR (_ADI_MSK(0x00000002,uint32_t)) /* Compare Error Interrupt Enable Set */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CRC_INEN_CLR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CRC_INEN_CLR_DCNTEXP 4 /* Data Count Expired (Status) Interrupt Enable Clear */
|
|
#define BITP_CRC_INEN_CLR_CMPERR 1 /* Compare Error Interrupt Enable Clear */
|
|
#define BITM_CRC_INEN_CLR_DCNTEXP (_ADI_MSK(0x00000010,uint32_t)) /* Data Count Expired (Status) Interrupt Enable Clear */
|
|
#define BITM_CRC_INEN_CLR_CMPERR (_ADI_MSK(0x00000002,uint32_t)) /* Compare Error Interrupt Enable Clear */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CRC_STAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CRC_STAT_FSTAT 20 /* FIFO Status */
|
|
#define BITP_CRC_STAT_LUTDONE 19 /* Look Up Table Done */
|
|
#define BITP_CRC_STAT_IRR 18 /* Intermediate Result Ready */
|
|
#define BITP_CRC_STAT_OBR 17 /* Output Buffer Ready */
|
|
#define BITP_CRC_STAT_IBR 16 /* Input Buffer Ready */
|
|
#define BITP_CRC_STAT_DCNTEXP 4 /* Data Count Expired */
|
|
#define BITP_CRC_STAT_CMPERR 1 /* Compare Error */
|
|
#define BITM_CRC_STAT_FSTAT (_ADI_MSK(0x00700000,uint32_t)) /* FIFO Status */
|
|
#define BITM_CRC_STAT_LUTDONE (_ADI_MSK(0x00080000,uint32_t)) /* Look Up Table Done */
|
|
#define BITM_CRC_STAT_IRR (_ADI_MSK(0x00040000,uint32_t)) /* Intermediate Result Ready */
|
|
#define BITM_CRC_STAT_OBR (_ADI_MSK(0x00020000,uint32_t)) /* Output Buffer Ready */
|
|
#define BITM_CRC_STAT_IBR (_ADI_MSK(0x00010000,uint32_t)) /* Input Buffer Ready */
|
|
#define BITM_CRC_STAT_DCNTEXP (_ADI_MSK(0x00000010,uint32_t)) /* Data Count Expired */
|
|
#define BITM_CRC_STAT_CMPERR (_ADI_MSK(0x00000002,uint32_t)) /* Compare Error */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CRC_REVID Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CRC_REVID_MAJOR 4 /* Major Revision ID */
|
|
#define BITP_CRC_REVID_REV 0 /* Incremental Revision ID */
|
|
#define BITM_CRC_REVID_MAJOR (_ADI_MSK(0x000000F0,uint32_t)) /* Major Revision ID */
|
|
#define BITM_CRC_REVID_REV (_ADI_MSK(0x0000000F,uint32_t)) /* Incremental Revision ID */
|
|
|
|
/* ==================================================
|
|
2-Wire Interface Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
TWI0
|
|
========================= */
|
|
#define REG_TWI0_CLKDIV 0xFFC01E00 /* TWI0 SCL Clock Divider Register */
|
|
#define REG_TWI0_CTL 0xFFC01E04 /* TWI0 Control Register */
|
|
#define REG_TWI0_SLVCTL 0xFFC01E08 /* TWI0 Slave Mode Control Register */
|
|
#define REG_TWI0_SLVSTAT 0xFFC01E0C /* TWI0 Slave Mode Status Register */
|
|
#define REG_TWI0_SLVADDR 0xFFC01E10 /* TWI0 Slave Mode Address Register */
|
|
#define REG_TWI0_MSTRCTL 0xFFC01E14 /* TWI0 Master Mode Control Registers */
|
|
#define REG_TWI0_MSTRSTAT 0xFFC01E18 /* TWI0 Master Mode Status Register */
|
|
#define REG_TWI0_MSTRADDR 0xFFC01E1C /* TWI0 Master Mode Address Register */
|
|
#define REG_TWI0_ISTAT 0xFFC01E20 /* TWI0 Interrupt Status Register */
|
|
#define REG_TWI0_IMSK 0xFFC01E24 /* TWI0 Interrupt Mask Register */
|
|
#define REG_TWI0_FIFOCTL 0xFFC01E28 /* TWI0 FIFO Control Register */
|
|
#define REG_TWI0_FIFOSTAT 0xFFC01E2C /* TWI0 FIFO Status Register */
|
|
#define REG_TWI0_TXDATA8 0xFFC01E80 /* TWI0 Tx Data Single-Byte Register */
|
|
#define REG_TWI0_TXDATA16 0xFFC01E84 /* TWI0 Tx Data Double-Byte Register */
|
|
#define REG_TWI0_RXDATA8 0xFFC01E88 /* TWI0 Rx Data Single-Byte Register */
|
|
#define REG_TWI0_RXDATA16 0xFFC01E8C /* TWI0 Rx Data Double-Byte Register */
|
|
|
|
/* =========================
|
|
TWI1
|
|
========================= */
|
|
#define REG_TWI1_CLKDIV 0xFFC01F00 /* TWI1 SCL Clock Divider Register */
|
|
#define REG_TWI1_CTL 0xFFC01F04 /* TWI1 Control Register */
|
|
#define REG_TWI1_SLVCTL 0xFFC01F08 /* TWI1 Slave Mode Control Register */
|
|
#define REG_TWI1_SLVSTAT 0xFFC01F0C /* TWI1 Slave Mode Status Register */
|
|
#define REG_TWI1_SLVADDR 0xFFC01F10 /* TWI1 Slave Mode Address Register */
|
|
#define REG_TWI1_MSTRCTL 0xFFC01F14 /* TWI1 Master Mode Control Registers */
|
|
#define REG_TWI1_MSTRSTAT 0xFFC01F18 /* TWI1 Master Mode Status Register */
|
|
#define REG_TWI1_MSTRADDR 0xFFC01F1C /* TWI1 Master Mode Address Register */
|
|
#define REG_TWI1_ISTAT 0xFFC01F20 /* TWI1 Interrupt Status Register */
|
|
#define REG_TWI1_IMSK 0xFFC01F24 /* TWI1 Interrupt Mask Register */
|
|
#define REG_TWI1_FIFOCTL 0xFFC01F28 /* TWI1 FIFO Control Register */
|
|
#define REG_TWI1_FIFOSTAT 0xFFC01F2C /* TWI1 FIFO Status Register */
|
|
#define REG_TWI1_TXDATA8 0xFFC01F80 /* TWI1 Tx Data Single-Byte Register */
|
|
#define REG_TWI1_TXDATA16 0xFFC01F84 /* TWI1 Tx Data Double-Byte Register */
|
|
#define REG_TWI1_RXDATA8 0xFFC01F88 /* TWI1 Rx Data Single-Byte Register */
|
|
#define REG_TWI1_RXDATA16 0xFFC01F8C /* TWI1 Rx Data Double-Byte Register */
|
|
|
|
/* =========================
|
|
TWI
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TWI_CLKDIV Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TWI_CLKDIV_CLKHI 8 /* SCL Clock High Periods */
|
|
#define BITP_TWI_CLKDIV_CLKLO 0 /* SCL Clock Low Periods */
|
|
#define BITM_TWI_CLKDIV_CLKHI (_ADI_MSK(0x0000FF00,uint16_t)) /* SCL Clock High Periods */
|
|
#define BITM_TWI_CLKDIV_CLKLO (_ADI_MSK(0x000000FF,uint16_t)) /* SCL Clock Low Periods */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TWI_CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TWI_CTL_SCCB 9 /* SCCB Compatibility */
|
|
#define BITP_TWI_CTL_EN 7 /* Enable Module */
|
|
#define BITP_TWI_CTL_PRESCALE 0 /* SCLK Prescale Value */
|
|
|
|
#define BITM_TWI_CTL_SCCB (_ADI_MSK(0x00000200,uint16_t)) /* SCCB Compatibility */
|
|
#define ENUM_TWI_CTL_SCCB_DIS (_ADI_MSK(0x00000000,uint16_t)) /* SCCB: Disable SCCB compatibility */
|
|
#define ENUM_TWI_CTL_SCCB_EN (_ADI_MSK(0x00000200,uint16_t)) /* SCCB: Enable SCCB compatibility */
|
|
|
|
#define BITM_TWI_CTL_EN (_ADI_MSK(0x00000080,uint16_t)) /* Enable Module */
|
|
#define ENUM_TWI_CTL_DIS (_ADI_MSK(0x00000000,uint16_t)) /* EN: Disable */
|
|
#define ENUM_TWI_CTL_EN (_ADI_MSK(0x00000080,uint16_t)) /* EN: Enable */
|
|
#define BITM_TWI_CTL_PRESCALE (_ADI_MSK(0x0000007F,uint16_t)) /* SCLK Prescale Value */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TWI_SLVCTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TWI_SLVCTL_GEN 4 /* General Call Enable */
|
|
#define BITP_TWI_SLVCTL_NAK 3 /* Not Acknowledge */
|
|
#define BITP_TWI_SLVCTL_TDVAL 2 /* Transmit Data Valid for Slave */
|
|
#define BITP_TWI_SLVCTL_EN 0 /* Enable Slave Mode */
|
|
|
|
#define BITM_TWI_SLVCTL_GEN (_ADI_MSK(0x00000010,uint16_t)) /* General Call Enable */
|
|
#define ENUM_TWI_SLVCTL_GDIS (_ADI_MSK(0x00000000,uint16_t)) /* GEN: Disable General Call Matching */
|
|
#define ENUM_TWI_SLVCTL_GEN (_ADI_MSK(0x00000010,uint16_t)) /* GEN: Enable General Call Matching */
|
|
|
|
#define BITM_TWI_SLVCTL_NAK (_ADI_MSK(0x00000008,uint16_t)) /* Not Acknowledge */
|
|
#define ENUM_TWI_SLVCTL_ACKGEN (_ADI_MSK(0x00000000,uint16_t)) /* NAK: Generate ACK */
|
|
#define ENUM_TWI_SLVCTL_NAKGEN (_ADI_MSK(0x00000008,uint16_t)) /* NAK: Generate NAK */
|
|
|
|
#define BITM_TWI_SLVCTL_TDVAL (_ADI_MSK(0x00000004,uint16_t)) /* Transmit Data Valid for Slave */
|
|
#define ENUM_TWI_SLVCTL_INVALID (_ADI_MSK(0x00000000,uint16_t)) /* TDVAL: Data Invalid for Slave Tx */
|
|
#define ENUM_TWI_SLVCTL_VALID (_ADI_MSK(0x00000004,uint16_t)) /* TDVAL: Data Valid for Slave Tx */
|
|
|
|
#define BITM_TWI_SLVCTL_EN (_ADI_MSK(0x00000001,uint16_t)) /* Enable Slave Mode */
|
|
#define ENUM_TWI_SLVCTL_DIS (_ADI_MSK(0x00000000,uint16_t)) /* EN: Disable */
|
|
#define ENUM_TWI_SLVCTL_EN (_ADI_MSK(0x00000001,uint16_t)) /* EN: Enable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TWI_SLVSTAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TWI_SLVSTAT_GCALL 1 /* General Call */
|
|
#define BITP_TWI_SLVSTAT_DIR 0 /* Transfer Direction for Slave */
|
|
|
|
#define BITM_TWI_SLVSTAT_GCALL (_ADI_MSK(0x00000002,uint16_t)) /* General Call */
|
|
#define ENUM_TWI_SLVSTAT_NO (_ADI_MSK(0x00000000,uint16_t)) /* GCALL: Not a General Call Address */
|
|
#define ENUM_TWI_SLVSTAT_YES (_ADI_MSK(0x00000002,uint16_t)) /* GCALL: General Call Address */
|
|
|
|
#define BITM_TWI_SLVSTAT_DIR (_ADI_MSK(0x00000001,uint16_t)) /* Transfer Direction for Slave */
|
|
#define ENUM_TWI_SLVSTAT_RX (_ADI_MSK(0x00000000,uint16_t)) /* DIR: Slave Receive */
|
|
#define ENUM_TWI_SLVSTAT_TX (_ADI_MSK(0x00000001,uint16_t)) /* DIR: Slave Transmit */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TWI_SLVADDR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TWI_SLVADDR_ADDR 0 /* Slave Mode Address */
|
|
#define BITM_TWI_SLVADDR_ADDR (_ADI_MSK(0x0000007F,uint16_t)) /* Slave Mode Address */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TWI_MSTRCTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TWI_MSTRCTL_SCLOVR 15 /* Serial Clock Override */
|
|
#define BITP_TWI_MSTRCTL_SDAOVR 14 /* Serial Data Override */
|
|
#define BITP_TWI_MSTRCTL_DCNT 6 /* Data Transfer Count */
|
|
#define BITP_TWI_MSTRCTL_RSTART 5 /* Repeat Start */
|
|
#define BITP_TWI_MSTRCTL_STOP 4 /* Issue Stop Condition */
|
|
#define BITP_TWI_MSTRCTL_FAST 3 /* Fast Mode */
|
|
#define BITP_TWI_MSTRCTL_DIR 2 /* Transfer Direction for Master */
|
|
#define BITP_TWI_MSTRCTL_EN 0 /* Enable Master Mode */
|
|
|
|
#define BITM_TWI_MSTRCTL_SCLOVR (_ADI_MSK(0x00008000,uint16_t)) /* Serial Clock Override */
|
|
#define ENUM_TWI_MSTRCTL_SCLNORM (_ADI_MSK(0x00000000,uint16_t)) /* SCLOVR: Permit Normal SCL Operation */
|
|
#define ENUM_TWI_MSTRCTL_SCLOVER (_ADI_MSK(0x00008000,uint16_t)) /* SCLOVR: Override Normal SCL Operation */
|
|
|
|
#define BITM_TWI_MSTRCTL_SDAOVR (_ADI_MSK(0x00004000,uint16_t)) /* Serial Data Override */
|
|
#define ENUM_TWI_MSTRCTL_SDANORM (_ADI_MSK(0x00000000,uint16_t)) /* SDAOVR: Permit Normal SDA Operation */
|
|
#define ENUM_TWI_MSTRCTL_SDAOVER (_ADI_MSK(0x00004000,uint16_t)) /* SDAOVR: Override Normal SDA Operation */
|
|
#define BITM_TWI_MSTRCTL_DCNT (_ADI_MSK(0x00003FC0,uint16_t)) /* Data Transfer Count */
|
|
|
|
#define BITM_TWI_MSTRCTL_RSTART (_ADI_MSK(0x00000020,uint16_t)) /* Repeat Start */
|
|
#define ENUM_TWI_MSTRCTL_END (_ADI_MSK(0x00000000,uint16_t)) /* RSTART: Disable Repeat Start */
|
|
#define ENUM_TWI_MSTRCTL_RPT (_ADI_MSK(0x00000020,uint16_t)) /* RSTART: Enable Repeat Start */
|
|
|
|
#define BITM_TWI_MSTRCTL_STOP (_ADI_MSK(0x00000010,uint16_t)) /* Issue Stop Condition */
|
|
#define ENUM_TWI_MSTRCTL_NORM (_ADI_MSK(0x00000000,uint16_t)) /* STOP: Permit Normal Operation */
|
|
#define ENUM_TWI_MSTRCTL_STOP (_ADI_MSK(0x00000010,uint16_t)) /* STOP: Issue Stop */
|
|
|
|
#define BITM_TWI_MSTRCTL_FAST (_ADI_MSK(0x00000008,uint16_t)) /* Fast Mode */
|
|
#define ENUM_TWI_MSTRCTL_NORM (_ADI_MSK(0x00000000,uint16_t)) /* FAST: Select Standard Mode */
|
|
#define ENUM_TWI_MSTRCTL_FAST (_ADI_MSK(0x00000008,uint16_t)) /* FAST: Select Fast Mode */
|
|
|
|
#define BITM_TWI_MSTRCTL_DIR (_ADI_MSK(0x00000004,uint16_t)) /* Transfer Direction for Master */
|
|
#define ENUM_TWI_MSTRCTL_TX (_ADI_MSK(0x00000000,uint16_t)) /* DIR: Master Transmit */
|
|
#define ENUM_TWI_MSTRCTL_RX (_ADI_MSK(0x00000004,uint16_t)) /* DIR: Master Receive */
|
|
|
|
#define BITM_TWI_MSTRCTL_EN (_ADI_MSK(0x00000001,uint16_t)) /* Enable Master Mode */
|
|
#define ENUM_TWI_MSTRCTL_DIS (_ADI_MSK(0x00000000,uint16_t)) /* EN: Disable */
|
|
#define ENUM_TWI_MSTRCTL_EN (_ADI_MSK(0x00000001,uint16_t)) /* EN: Enable */
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/* ------------------------------------------------------------------------------------------------------------------------
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TWI_MSTRSTAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_TWI_MSTRSTAT_BUSBUSY 8 /* Bus Busy */
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#define BITP_TWI_MSTRSTAT_SCLSEN 7 /* Serial Clock Sense */
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#define BITP_TWI_MSTRSTAT_SDASEN 6 /* Serial Data Sense */
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#define BITP_TWI_MSTRSTAT_BUFWRERR 5 /* Buffer Write Error */
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#define BITP_TWI_MSTRSTAT_BUFRDERR 4 /* Buffer Read Error */
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#define BITP_TWI_MSTRSTAT_DNAK 3 /* Data Not Acknowledged */
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#define BITP_TWI_MSTRSTAT_ANAK 2 /* Address Not Acknowledged */
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#define BITP_TWI_MSTRSTAT_LOSTARB 1 /* Lost Arbitration */
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#define BITP_TWI_MSTRSTAT_MPROG 0 /* Master Transfer in Progress */
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#define BITM_TWI_MSTRSTAT_BUSBUSY (_ADI_MSK(0x00000100,uint16_t)) /* Bus Busy */
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#define ENUM_TWI_MSTRSTAT_FREE (_ADI_MSK(0x00000000,uint16_t)) /* BUSBUSY: Bus Free */
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#define ENUM_TWI_MSTRSTAT_BUSY (_ADI_MSK(0x00000100,uint16_t)) /* BUSBUSY: Bus Busy */
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#define BITM_TWI_MSTRSTAT_SCLSEN (_ADI_MSK(0x00000080,uint16_t)) /* Serial Clock Sense */
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#define ENUM_TWI_MSTRSTAT_SCLSEN_NO (_ADI_MSK(0x00000000,uint16_t)) /* SCLSEN: SCL Inactive "One" */
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#define ENUM_TWI_MSTRSTAT_SCLSEN_YES (_ADI_MSK(0x00000080,uint16_t)) /* SCLSEN: SCL Active "Zero" */
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#define BITM_TWI_MSTRSTAT_SDASEN (_ADI_MSK(0x00000040,uint16_t)) /* Serial Data Sense */
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#define ENUM_TWI_MSTRSTAT_SDASEN_NO (_ADI_MSK(0x00000000,uint16_t)) /* SDASEN: SDA Inactive "One" */
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#define ENUM_TWI_MSTRSTAT_SDASEN_YES (_ADI_MSK(0x00000040,uint16_t)) /* SDASEN: SDA Active "Zero" */
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#define BITM_TWI_MSTRSTAT_BUFWRERR (_ADI_MSK(0x00000020,uint16_t)) /* Buffer Write Error */
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#define ENUM_TWI_MSTRSTAT_BUFWRERR_NO (_ADI_MSK(0x00000000,uint16_t)) /* BUFWRERR: No Status */
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#define ENUM_TWI_MSTRSTAT_BUFWRERR_YES (_ADI_MSK(0x00000020,uint16_t)) /* BUFWRERR: Buffer Write Error */
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#define BITM_TWI_MSTRSTAT_BUFRDERR (_ADI_MSK(0x00000010,uint16_t)) /* Buffer Read Error */
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#define ENUM_TWI_MSTRSTAT_BUFRDERR_NO (_ADI_MSK(0x00000000,uint16_t)) /* BUFRDERR: No Status */
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#define ENUM_TWI_MSTRSTAT_BUFRDERR_YES (_ADI_MSK(0x00000010,uint16_t)) /* BUFRDERR: Buffer Read Error */
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#define BITM_TWI_MSTRSTAT_DNAK (_ADI_MSK(0x00000008,uint16_t)) /* Data Not Acknowledged */
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#define ENUM_TWI_MSTRSTAT_DNAK_NO (_ADI_MSK(0x00000000,uint16_t)) /* DNAK: No Status */
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#define ENUM_TWI_MSTRSTAT_DNAK_YES (_ADI_MSK(0x00000008,uint16_t)) /* DNAK: Data NAK */
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#define BITM_TWI_MSTRSTAT_ANAK (_ADI_MSK(0x00000004,uint16_t)) /* Address Not Acknowledged */
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#define ENUM_TWI_MSTRSTAT_ANAK_NO (_ADI_MSK(0x00000000,uint16_t)) /* ANAK: No Status */
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#define ENUM_TWI_MSTRSTAT_ANAK_YES (_ADI_MSK(0x00000004,uint16_t)) /* ANAK: Address NAK */
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#define BITM_TWI_MSTRSTAT_LOSTARB (_ADI_MSK(0x00000002,uint16_t)) /* Lost Arbitration */
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#define ENUM_TWI_MSTRSTAT_LOSTARB_NO (_ADI_MSK(0x00000000,uint16_t)) /* LOSTARB: No Status */
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#define ENUM_TWI_MSTRSTAT_LOSTARB_YES (_ADI_MSK(0x00000002,uint16_t)) /* LOSTARB: Lost Arbitration */
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#define BITM_TWI_MSTRSTAT_MPROG (_ADI_MSK(0x00000001,uint16_t)) /* Master Transfer in Progress */
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#define ENUM_TWI_MSTRSTAT_MPROG_NO (_ADI_MSK(0x00000000,uint16_t)) /* MPROG: No Status */
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#define ENUM_TWI_MSTRSTAT_MPROG_YES (_ADI_MSK(0x00000001,uint16_t)) /* MPROG: Master Transfer in Progress */
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/* ------------------------------------------------------------------------------------------------------------------------
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TWI_MSTRADDR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_TWI_MSTRADDR_ADDR 0 /* Master Mode Address */
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#define BITM_TWI_MSTRADDR_ADDR (_ADI_MSK(0x0000007F,uint16_t)) /* Master Mode Address */
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/* ------------------------------------------------------------------------------------------------------------------------
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TWI_ISTAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_TWI_ISTAT_SCLI 15 /* Serial Clock Interrupt */
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#define BITP_TWI_ISTAT_SDAI 14 /* Serial Data Interrupt */
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#define BITP_TWI_ISTAT_RXSERV 7 /* Rx FIFO Service */
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#define BITP_TWI_ISTAT_TXSERV 6 /* Tx FIFO Service */
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#define BITP_TWI_ISTAT_MERR 5 /* Master Transfer Error */
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#define BITP_TWI_ISTAT_MCOMP 4 /* Master Transfer Complete */
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#define BITP_TWI_ISTAT_SOVF 3 /* Slave Overflow */
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#define BITP_TWI_ISTAT_SERR 2 /* Slave Transfer Error */
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#define BITP_TWI_ISTAT_SCOMP 1 /* Slave Transfer Complete */
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#define BITP_TWI_ISTAT_SINIT 0 /* Slave Transfer Initiated */
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#define BITM_TWI_ISTAT_SCLI (_ADI_MSK(0x00008000,uint16_t)) /* Serial Clock Interrupt */
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#define ENUM_TWI_ISTAT_SCLI_NO (_ADI_MSK(0x00000000,uint16_t)) /* SCLI: No Interrupt */
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#define ENUM_TWI_ISTAT_SCLI_YES (_ADI_MSK(0x00008000,uint16_t)) /* SCLI: Interrupt Detected */
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#define BITM_TWI_ISTAT_SDAI (_ADI_MSK(0x00004000,uint16_t)) /* Serial Data Interrupt */
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#define ENUM_TWI_ISTAT_SDAI_NO (_ADI_MSK(0x00000000,uint16_t)) /* SDAI: No Interrupt */
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#define ENUM_TWI_ISTAT_SDAI_YES (_ADI_MSK(0x00004000,uint16_t)) /* SDAI: Interrupt Detected */
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#define BITM_TWI_ISTAT_RXSERV (_ADI_MSK(0x00000080,uint16_t)) /* Rx FIFO Service */
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#define ENUM_TWI_ISTAT_RXSERV_NO (_ADI_MSK(0x00000000,uint16_t)) /* RXSERV: No Interrupt */
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#define ENUM_TWI_ISTAT_RXSERV_YES (_ADI_MSK(0x00000080,uint16_t)) /* RXSERV: Interrupt Detected */
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#define BITM_TWI_ISTAT_TXSERV (_ADI_MSK(0x00000040,uint16_t)) /* Tx FIFO Service */
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#define ENUM_TWI_ISTAT_TXSERV_NO (_ADI_MSK(0x00000000,uint16_t)) /* TXSERV: No Interrupt */
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#define ENUM_TWI_ISTAT_TXSERV_YES (_ADI_MSK(0x00000040,uint16_t)) /* TXSERV: Interrupt Detected */
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#define BITM_TWI_ISTAT_MERR (_ADI_MSK(0x00000020,uint16_t)) /* Master Transfer Error */
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#define ENUM_TWI_ISTAT_MERR_NO (_ADI_MSK(0x00000000,uint16_t)) /* MERR: No Interrupt */
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#define ENUM_TWI_ISTAT_MERR_YES (_ADI_MSK(0x00000020,uint16_t)) /* MERR: Interrupt Detected */
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#define BITM_TWI_ISTAT_MCOMP (_ADI_MSK(0x00000010,uint16_t)) /* Master Transfer Complete */
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#define ENUM_TWI_ISTAT_MCOMP_NO (_ADI_MSK(0x00000000,uint16_t)) /* MCOMP: No Interrupt */
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#define ENUM_TWI_ISTAT_MCOMP_YES (_ADI_MSK(0x00000010,uint16_t)) /* MCOMP: Interrupt Detected */
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#define BITM_TWI_ISTAT_SOVF (_ADI_MSK(0x00000008,uint16_t)) /* Slave Overflow */
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#define ENUM_TWI_ISTAT_SOVF_NO (_ADI_MSK(0x00000000,uint16_t)) /* SOVF: No Interrupt */
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#define ENUM_TWI_ISTAT_SOVF_YES (_ADI_MSK(0x00000008,uint16_t)) /* SOVF: Interrupt Detected */
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#define BITM_TWI_ISTAT_SERR (_ADI_MSK(0x00000004,uint16_t)) /* Slave Transfer Error */
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#define ENUM_TWI_ISTAT_SERR_NO (_ADI_MSK(0x00000000,uint16_t)) /* SERR: No Interrupt */
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#define ENUM_TWI_ISTAT_SERR_YES (_ADI_MSK(0x00000004,uint16_t)) /* SERR: Interrupt Detected */
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#define BITM_TWI_ISTAT_SCOMP (_ADI_MSK(0x00000002,uint16_t)) /* Slave Transfer Complete */
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#define ENUM_TWI_ISTAT_SCOMP_NO (_ADI_MSK(0x00000000,uint16_t)) /* SCOMP: No Interrupt */
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#define ENUM_TWI_ISTAT_SCOMP_YES (_ADI_MSK(0x00000002,uint16_t)) /* SCOMP: Interrupt Detected */
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#define BITM_TWI_ISTAT_SINIT (_ADI_MSK(0x00000001,uint16_t)) /* Slave Transfer Initiated */
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#define ENUM_TWI_ISTAT_SINIT_NO (_ADI_MSK(0x00000000,uint16_t)) /* SINIT: No Interrupt */
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#define ENUM_TWI_ISTAT_SINIT_YES (_ADI_MSK(0x00000001,uint16_t)) /* SINIT: Interrupt Detected */
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|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TWI_IMSK Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TWI_IMSK_SCLI 15 /* Serial Clock Interrupt Mask */
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#define BITP_TWI_IMSK_SDAI 14 /* Serial Data Interrupt Mask */
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#define BITP_TWI_IMSK_RXSERV 7 /* Rx FIFO Service Interrupt Mask */
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#define BITP_TWI_IMSK_TXSERV 6 /* Tx FIFO Service Interrupt Mask */
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#define BITP_TWI_IMSK_MERR 5 /* Master Transfer Error Interrupt Mask */
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#define BITP_TWI_IMSK_MCOMP 4 /* Master Transfer Complete Interrupt Mask */
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#define BITP_TWI_IMSK_SOVF 3 /* Slave Overflow Interrupt Mask */
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#define BITP_TWI_IMSK_SERR 2 /* Slave Transfer Error Interrupt Mask */
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#define BITP_TWI_IMSK_SCOMP 1 /* Slave Transfer Complete Interrupt Mask */
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#define BITP_TWI_IMSK_SINIT 0 /* Slave Transfer Initiated Interrupt Mask */
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#define BITM_TWI_IMSK_SCLI (_ADI_MSK(0x00008000,uint16_t)) /* Serial Clock Interrupt Mask */
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#define ENUM_TWI_IMSK_SCLI_MSK (_ADI_MSK(0x00000000,uint16_t)) /* SCLI: Mask (Disable) Interrupt */
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#define ENUM_TWI_IMSK_SCLI_UMSK (_ADI_MSK(0x00008000,uint16_t)) /* SCLI: Unmask (Enable) Interrupt */
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#define BITM_TWI_IMSK_SDAI (_ADI_MSK(0x00004000,uint16_t)) /* Serial Data Interrupt Mask */
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#define ENUM_TWI_IMSK_SDAI_MSK (_ADI_MSK(0x00000000,uint16_t)) /* SDAI: Mask (Disable) Interrupt */
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#define ENUM_TWI_IMSK_SDAI_UMSK (_ADI_MSK(0x00004000,uint16_t)) /* SDAI: Unmask (Enable) Interrupt */
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#define BITM_TWI_IMSK_RXSERV (_ADI_MSK(0x00000080,uint16_t)) /* Rx FIFO Service Interrupt Mask */
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#define ENUM_TWI_IMSK_RXSERV_MSK (_ADI_MSK(0x00000000,uint16_t)) /* RXSERV: Mask (Disable) Interrupt */
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#define ENUM_TWI_IMSK_RXSERV_UMSK (_ADI_MSK(0x00000080,uint16_t)) /* RXSERV: Unmask (Enable) Interrupt */
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#define BITM_TWI_IMSK_TXSERV (_ADI_MSK(0x00000040,uint16_t)) /* Tx FIFO Service Interrupt Mask */
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#define ENUM_TWI_IMSK_TXSERV_MSK (_ADI_MSK(0x00000000,uint16_t)) /* TXSERV: Mask (Disable) Interrupt */
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#define ENUM_TWI_IMSK_TXSERV_UMSK (_ADI_MSK(0x00000040,uint16_t)) /* TXSERV: Unmask (Enable) Interrupt */
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#define BITM_TWI_IMSK_MERR (_ADI_MSK(0x00000020,uint16_t)) /* Master Transfer Error Interrupt Mask */
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#define ENUM_TWI_IMSK_MERR_MSK (_ADI_MSK(0x00000000,uint16_t)) /* MERR: Mask (Disable) Interrupt */
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#define ENUM_TWI_IMSK_MERR_UMSK (_ADI_MSK(0x00000020,uint16_t)) /* MERR: Unmask (Enable) Interrupt */
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#define BITM_TWI_IMSK_MCOMP (_ADI_MSK(0x00000010,uint16_t)) /* Master Transfer Complete Interrupt Mask */
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#define ENUM_TWI_IMSK_MCOMP_MSK (_ADI_MSK(0x00000000,uint16_t)) /* MCOMP: Mask (Disable) Interrupt */
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#define ENUM_TWI_IMSK_MCOMP_UMSK (_ADI_MSK(0x00000010,uint16_t)) /* MCOMP: Unmask (Enable) Interrupt */
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#define BITM_TWI_IMSK_SOVF (_ADI_MSK(0x00000008,uint16_t)) /* Slave Overflow Interrupt Mask */
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#define ENUM_TWI_IMSK_SOVF_MSK (_ADI_MSK(0x00000000,uint16_t)) /* SOVF: Mask (Disable) Interrupt */
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#define ENUM_TWI_IMSK_SOVF_UMSK (_ADI_MSK(0x00000008,uint16_t)) /* SOVF: Unmask (Enable) Interrupt */
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#define BITM_TWI_IMSK_SERR (_ADI_MSK(0x00000004,uint16_t)) /* Slave Transfer Error Interrupt Mask */
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#define ENUM_TWI_IMSK_SERR_MSK (_ADI_MSK(0x00000000,uint16_t)) /* SERR: Mask (Disable) Interrupt */
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#define ENUM_TWI_IMSK_SERR_UMSK (_ADI_MSK(0x00000004,uint16_t)) /* SERR: Unmask (Enable) Interrupt */
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#define BITM_TWI_IMSK_SCOMP (_ADI_MSK(0x00000002,uint16_t)) /* Slave Transfer Complete Interrupt Mask */
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#define ENUM_TWI_IMSK_SCOMP_MSK (_ADI_MSK(0x00000000,uint16_t)) /* SCOMP: Mask (Disable) Interrupt */
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#define ENUM_TWI_IMSK_SCOMP_UMSK (_ADI_MSK(0x00000002,uint16_t)) /* SCOMP: Unmask (Enable) Interrupt */
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#define BITM_TWI_IMSK_SINIT (_ADI_MSK(0x00000001,uint16_t)) /* Slave Transfer Initiated Interrupt Mask */
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#define ENUM_TWI_IMSK_SINIT_MSK (_ADI_MSK(0x00000000,uint16_t)) /* SINIT: Mask (Disable) Interrupt */
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#define ENUM_TWI_IMSK_SINIT_UMSK (_ADI_MSK(0x00000001,uint16_t)) /* SINIT: Unmask (Enable) Interrupt */
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|
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
TWI_FIFOCTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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|
#define BITP_TWI_FIFOCTL_RXILEN 3 /* Rx Buffer Interrupt Length */
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#define BITP_TWI_FIFOCTL_TXILEN 2 /* Tx Buffer Interrupt Length */
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#define BITP_TWI_FIFOCTL_RXFLUSH 1 /* Rx Buffer Flush */
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#define BITP_TWI_FIFOCTL_TXFLUSH 0 /* Tx Buffer Flush */
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#define BITM_TWI_FIFOCTL_RXILEN (_ADI_MSK(0x00000008,uint16_t)) /* Rx Buffer Interrupt Length */
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#define ENUM_TWI_FIFOCTL_RXONEBYTE (_ADI_MSK(0x00000000,uint16_t)) /* RXILEN: RXSERVI on 1 or 2 Bytes in FIFO */
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#define ENUM_TWI_FIFOCTL_RXTWOBYTE (_ADI_MSK(0x00000008,uint16_t)) /* RXILEN: RXSERVI on 2 Bytes in FIFO */
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#define BITM_TWI_FIFOCTL_TXILEN (_ADI_MSK(0x00000004,uint16_t)) /* Tx Buffer Interrupt Length */
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#define ENUM_TWI_FIFOCTL_TXONEBYTE (_ADI_MSK(0x00000000,uint16_t)) /* TXILEN: TXSERVI on 1 Byte of FIFO Empty */
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#define ENUM_TWI_FIFOCTL_TXTWOBYTE (_ADI_MSK(0x00000004,uint16_t)) /* TXILEN: TXSERVI on 2 Bytes of FIFO Empty */
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#define BITM_TWI_FIFOCTL_RXFLUSH (_ADI_MSK(0x00000002,uint16_t)) /* Rx Buffer Flush */
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#define ENUM_TWI_FIFOCTL_RXNORM (_ADI_MSK(0x00000000,uint16_t)) /* RXFLUSH: Normal Operation of Rx Buffer */
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#define ENUM_TWI_FIFOCTL_RXFLUSH (_ADI_MSK(0x00000002,uint16_t)) /* RXFLUSH: Flush Rx Buffer */
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#define BITM_TWI_FIFOCTL_TXFLUSH (_ADI_MSK(0x00000001,uint16_t)) /* Tx Buffer Flush */
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#define ENUM_TWI_FIFOCTL_TXNORM (_ADI_MSK(0x00000000,uint16_t)) /* TXFLUSH: Normal Operation of Tx Buffer */
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#define ENUM_TWI_FIFOCTL_TXFLUSH (_ADI_MSK(0x00000001,uint16_t)) /* TXFLUSH: Flush Tx Buffer */
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|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TWI_FIFOSTAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TWI_FIFOSTAT_RXSTAT 2 /* Rx FIFO Status */
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|
#define BITP_TWI_FIFOSTAT_TXSTAT 0 /* Tx FIFO Status */
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|
#define BITM_TWI_FIFOSTAT_RXSTAT (_ADI_MSK(0x0000000C,uint16_t)) /* Rx FIFO Status */
|
|
#define BITM_TWI_FIFOSTAT_TXSTAT (_ADI_MSK(0x00000003,uint16_t)) /* Tx FIFO Status */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TWI_TXDATA8 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TWI_TXDATA8_VALUE 0 /* Tx Data 8-Bit Value */
|
|
#define BITM_TWI_TXDATA8_VALUE (_ADI_MSK(0x000000FF,uint16_t)) /* Tx Data 8-Bit Value */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TWI_RXDATA8 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TWI_RXDATA8_VALUE 0 /* Rx Data 8-Bit Value */
|
|
#define BITM_TWI_RXDATA8_VALUE (_ADI_MSK(0x000000FF,uint16_t)) /* Rx Data 8-Bit Value */
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|
|
|
/* ==================================================
|
|
UART Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
UART0
|
|
========================= */
|
|
#define REG_UART0_REVID 0xFFC02000 /* UART0 Revision ID Register */
|
|
#define REG_UART0_CTL 0xFFC02004 /* UART0 Control Register */
|
|
#define REG_UART0_STAT 0xFFC02008 /* UART0 Status Register */
|
|
#define REG_UART0_SCR 0xFFC0200C /* UART0 Scratch Register */
|
|
#define REG_UART0_CLK 0xFFC02010 /* UART0 Clock Rate Register */
|
|
#define REG_UART0_IMSK 0xFFC02014 /* UART0 Interrupt Mask Register */
|
|
#define REG_UART0_IMSK_SET 0xFFC02018 /* UART0 Interrupt Mask Set Register */
|
|
#define REG_UART0_IMSK_CLR 0xFFC0201C /* UART0 Interrupt Mask Clear Register */
|
|
#define REG_UART0_RBR 0xFFC02020 /* UART0 Receive Buffer Register */
|
|
#define REG_UART0_THR 0xFFC02024 /* UART0 Transmit Hold Register */
|
|
#define REG_UART0_TAIP 0xFFC02028 /* UART0 Transmit Address/Insert Pulse Register */
|
|
#define REG_UART0_TSR 0xFFC0202C /* UART0 Transmit Shift Register */
|
|
#define REG_UART0_RSR 0xFFC02030 /* UART0 Receive Shift Register */
|
|
#define REG_UART0_TXCNT 0xFFC02034 /* UART0 Transmit Counter Register */
|
|
#define REG_UART0_RXCNT 0xFFC02038 /* UART0 Receive Counter Register */
|
|
|
|
/* =========================
|
|
UART1
|
|
========================= */
|
|
#define REG_UART1_REVID 0xFFC02400 /* UART1 Revision ID Register */
|
|
#define REG_UART1_CTL 0xFFC02404 /* UART1 Control Register */
|
|
#define REG_UART1_STAT 0xFFC02408 /* UART1 Status Register */
|
|
#define REG_UART1_SCR 0xFFC0240C /* UART1 Scratch Register */
|
|
#define REG_UART1_CLK 0xFFC02410 /* UART1 Clock Rate Register */
|
|
#define REG_UART1_IMSK 0xFFC02414 /* UART1 Interrupt Mask Register */
|
|
#define REG_UART1_IMSK_SET 0xFFC02418 /* UART1 Interrupt Mask Set Register */
|
|
#define REG_UART1_IMSK_CLR 0xFFC0241C /* UART1 Interrupt Mask Clear Register */
|
|
#define REG_UART1_RBR 0xFFC02420 /* UART1 Receive Buffer Register */
|
|
#define REG_UART1_THR 0xFFC02424 /* UART1 Transmit Hold Register */
|
|
#define REG_UART1_TAIP 0xFFC02428 /* UART1 Transmit Address/Insert Pulse Register */
|
|
#define REG_UART1_TSR 0xFFC0242C /* UART1 Transmit Shift Register */
|
|
#define REG_UART1_RSR 0xFFC02430 /* UART1 Receive Shift Register */
|
|
#define REG_UART1_TXCNT 0xFFC02434 /* UART1 Transmit Counter Register */
|
|
#define REG_UART1_RXCNT 0xFFC02438 /* UART1 Receive Counter Register */
|
|
|
|
/* =========================
|
|
UART
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
UART_REVID Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_UART_REVID_MAJOR 4 /* Major Version */
|
|
#define BITP_UART_REVID_REV 0 /* Incremental Version */
|
|
#define BITM_UART_REVID_MAJOR (_ADI_MSK(0x000000F0,uint32_t)) /* Major Version */
|
|
#define BITM_UART_REVID_REV (_ADI_MSK(0x0000000F,uint32_t)) /* Incremental Version */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
UART_CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_UART_CTL_RFRT 30 /* Receive FIFO RTS Threshold */
|
|
#define BITP_UART_CTL_RFIT 29 /* Receive FIFO IRQ Threshold */
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#define BITP_UART_CTL_ACTS 28 /* Automatic CTS */
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#define BITP_UART_CTL_ARTS 27 /* Automatic RTS */
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#define BITP_UART_CTL_XOFF 26 /* Transmitter off */
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#define BITP_UART_CTL_MRTS 25 /* Manual Request to Send */
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#define BITP_UART_CTL_TPOLC 24 /* IrDA TX Polarity Change */
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#define BITP_UART_CTL_RPOLC 23 /* IrDA RX Polarity Change */
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#define BITP_UART_CTL_FCPOL 22 /* Flow Control Pin Polarity */
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#define BITP_UART_CTL_SB 19 /* Set Break */
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#define BITP_UART_CTL_FFE 18 /* Force Framing Error on Transmit */
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#define BITP_UART_CTL_FPE 17 /* Force Parity Error on Transmit */
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#define BITP_UART_CTL_STP 16 /* Sticky Parity */
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#define BITP_UART_CTL_EPS 15 /* Even Parity Select */
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#define BITP_UART_CTL_PEN 14 /* Parity Enable */
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#define BITP_UART_CTL_STBH 13 /* Stop Bits (Half Bit Time) */
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#define BITP_UART_CTL_STB 12 /* Stop Bits */
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#define BITP_UART_CTL_WLS 8 /* Word Length Select */
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#define BITP_UART_CTL_MOD 4 /* Mode of Operation */
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#define BITP_UART_CTL_LOOP_EN 1 /* Loopback Enable */
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#define BITP_UART_CTL_EN 0 /* Enable UART */
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#define BITM_UART_CTL_RFRT (_ADI_MSK(0x40000000,uint32_t)) /* Receive FIFO RTS Threshold */
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#define ENUM_UART_CTL_RX_RTS_TH4 (_ADI_MSK(0x00000000,uint32_t)) /* RFRT: De-assert RTS if RX FIFO word count > 4; assert if <= 4 */
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#define ENUM_UART_CTL_RX_RTS_TH7 (_ADI_MSK(0x40000000,uint32_t)) /* RFRT: De-assert RTS if RX FIFO word count > 7; assert if <= 7 */
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#define BITM_UART_CTL_RFIT (_ADI_MSK(0x20000000,uint32_t)) /* Receive FIFO IRQ Threshold */
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#define ENUM_UART_CTL_RX_IRQ_TH4 (_ADI_MSK(0x00000000,uint32_t)) /* RFIT: Set RFCS=1 if RX FIFO count >= 4 */
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#define ENUM_UART_CTL_RX_IRQ_TH7 (_ADI_MSK(0x20000000,uint32_t)) /* RFIT: Set RFCS=1 if RX FIFO count >= 7 */
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#define BITM_UART_CTL_ACTS (_ADI_MSK(0x10000000,uint32_t)) /* Automatic CTS */
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#define ENUM_UART_CTL_CTS_MAN (_ADI_MSK(0x00000000,uint32_t)) /* ACTS: Disable TX handshaking protocol */
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#define ENUM_UART_CTL_CTS_AUTO (_ADI_MSK(0x10000000,uint32_t)) /* ACTS: Enable TX handshaking protocol */
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#define BITM_UART_CTL_ARTS (_ADI_MSK(0x08000000,uint32_t)) /* Automatic RTS */
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#define ENUM_UART_CTL_RTS_MAN (_ADI_MSK(0x00000000,uint32_t)) /* ARTS: Disable RX handshaking protocol. */
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#define ENUM_UART_CTL_RTS_AUTO (_ADI_MSK(0x08000000,uint32_t)) /* ARTS: Enable RX handshaking protocol. */
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#define BITM_UART_CTL_XOFF (_ADI_MSK(0x04000000,uint32_t)) /* Transmitter off */
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#define ENUM_UART_CTL_TX_ON (_ADI_MSK(0x00000000,uint32_t)) /* XOFF: Transmission ON, if ACTS=0 */
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#define ENUM_UART_CTL_TX_OFF (_ADI_MSK(0x04000000,uint32_t)) /* XOFF: Transmission OFF, if ACTS=0 */
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#define BITM_UART_CTL_MRTS (_ADI_MSK(0x02000000,uint32_t)) /* Manual Request to Send */
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#define ENUM_UART_CTL_RTS_DEASSERT (_ADI_MSK(0x00000000,uint32_t)) /* MRTS: De-assert RTS pin when ARTS=0 */
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#define ENUM_UART_CTL_RTS_ASSERT (_ADI_MSK(0x02000000,uint32_t)) /* MRTS: Assert RTS pin when ARTS=0 */
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#define BITM_UART_CTL_TPOLC (_ADI_MSK(0x01000000,uint32_t)) /* IrDA TX Polarity Change */
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#define ENUM_UART_CTL_TPOLC_LO (_ADI_MSK(0x00000000,uint32_t)) /* TPOLC: Active-low TX polarity setting */
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#define ENUM_UART_CTL_TPOLC_HI (_ADI_MSK(0x01000000,uint32_t)) /* TPOLC: Active-high TX polarity setting */
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#define BITM_UART_CTL_RPOLC (_ADI_MSK(0x00800000,uint32_t)) /* IrDA RX Polarity Change */
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#define ENUM_UART_CTL_RPOLC_LO (_ADI_MSK(0x00000000,uint32_t)) /* RPOLC: Active-low RX polarity setting */
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#define ENUM_UART_CTL_RPOLC_HI (_ADI_MSK(0x00800000,uint32_t)) /* RPOLC: Active-high RX polarity setting */
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#define BITM_UART_CTL_FCPOL (_ADI_MSK(0x00400000,uint32_t)) /* Flow Control Pin Polarity */
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#define ENUM_UART_CTL_FCPOL_LO (_ADI_MSK(0x00000000,uint32_t)) /* FCPOL: Active low CTS/RTS */
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#define ENUM_UART_CTL_FCPOL_HI (_ADI_MSK(0x00400000,uint32_t)) /* FCPOL: Active high CTS/RTS */
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#define BITM_UART_CTL_SB (_ADI_MSK(0x00080000,uint32_t)) /* Set Break */
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#define ENUM_UART_CTL_NORM_BREAK (_ADI_MSK(0x00000000,uint32_t)) /* SB: No force */
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#define ENUM_UART_CTL_FORCE_BREAK (_ADI_MSK(0x00080000,uint32_t)) /* SB: Force TX pin to 0 */
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#define BITM_UART_CTL_FFE (_ADI_MSK(0x00040000,uint32_t)) /* Force Framing Error on Transmit */
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#define ENUM_UART_CTL_NORM_FRM_ERR (_ADI_MSK(0x00000000,uint32_t)) /* FFE: Normal operation */
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#define ENUM_UART_CTL_FORCE_FRM_ERR (_ADI_MSK(0x00040000,uint32_t)) /* FFE: Force error */
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#define BITM_UART_CTL_FPE (_ADI_MSK(0x00020000,uint32_t)) /* Force Parity Error on Transmit */
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#define ENUM_UART_CTL_NORM_PARITY_ERR (_ADI_MSK(0x00000000,uint32_t)) /* FPE: Normal operation */
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#define ENUM_UART_CTL_FORCE_PARITY_ERR (_ADI_MSK(0x00020000,uint32_t)) /* FPE: Force parity error */
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#define BITM_UART_CTL_STP (_ADI_MSK(0x00010000,uint32_t)) /* Sticky Parity */
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#define ENUM_UART_CTL_NORM_PARITY (_ADI_MSK(0x00000000,uint32_t)) /* STP: No Forced Parity */
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#define ENUM_UART_CTL_STICKY_PARITY (_ADI_MSK(0x00010000,uint32_t)) /* STP: Force (Stick) Parity to Defined Value (if PEN=1) */
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#define BITM_UART_CTL_EPS (_ADI_MSK(0x00008000,uint32_t)) /* Even Parity Select */
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#define ENUM_UART_CTL_ODD_PARITY (_ADI_MSK(0x00000000,uint32_t)) /* EPS: Odd parity */
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#define ENUM_UART_CTL_EVEN_PARITY (_ADI_MSK(0x00008000,uint32_t)) /* EPS: Even parity */
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#define BITM_UART_CTL_PEN (_ADI_MSK(0x00004000,uint32_t)) /* Parity Enable */
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#define ENUM_UART_CTL_PARITY_DIS (_ADI_MSK(0x00000000,uint32_t)) /* PEN: Disable */
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#define ENUM_UART_CTL_PARITY_EN (_ADI_MSK(0x00004000,uint32_t)) /* PEN: Enable parity transmit and check */
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#define BITM_UART_CTL_STBH (_ADI_MSK(0x00002000,uint32_t)) /* Stop Bits (Half Bit Time) */
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#define ENUM_UART_CTL_NO_EXTRA_STBH (_ADI_MSK(0x00000000,uint32_t)) /* STBH: 0 half-bit-time stop bit */
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#define ENUM_UART_CTL_1_EXTRA_STBH (_ADI_MSK(0x00002000,uint32_t)) /* STBH: 1 half-bit-time stop bit */
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#define BITM_UART_CTL_STB (_ADI_MSK(0x00001000,uint32_t)) /* Stop Bits */
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#define ENUM_UART_CTL_NO_EXTRA_STB (_ADI_MSK(0x00000000,uint32_t)) /* STB: 1 stop bit */
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#define ENUM_UART_CTL_1_EXTRA_STB (_ADI_MSK(0x00001000,uint32_t)) /* STB: 2 stop bits */
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#define BITM_UART_CTL_WLS (_ADI_MSK(0x00000300,uint32_t)) /* Word Length Select */
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#define ENUM_UART_CTL_WL5BITS (_ADI_MSK(0x00000000,uint32_t)) /* WLS: 5-bit Word */
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#define ENUM_UART_CTL_WL6BITS (_ADI_MSK(0x00000100,uint32_t)) /* WLS: 6-bit Word */
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#define ENUM_UART_CTL_WL7BITS (_ADI_MSK(0x00000200,uint32_t)) /* WLS: 7-bit Word */
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#define ENUM_UART_CTL_WL8BITS (_ADI_MSK(0x00000300,uint32_t)) /* WLS: 8-bit Word */
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#define BITM_UART_CTL_MOD (_ADI_MSK(0x00000030,uint32_t)) /* Mode of Operation */
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#define ENUM_UART_CTL_UART_MODE (_ADI_MSK(0x00000000,uint32_t)) /* MOD: UART Mode */
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#define ENUM_UART_CTL_MDB_MODE (_ADI_MSK(0x00000010,uint32_t)) /* MOD: MDB Mode */
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#define ENUM_UART_CTL_IRDA_MODE (_ADI_MSK(0x00000020,uint32_t)) /* MOD: IrDA SIR Mode */
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#define BITM_UART_CTL_LOOP_EN (_ADI_MSK(0x00000002,uint32_t)) /* Loopback Enable */
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#define ENUM_UART_CTL_LOOP_DIS (_ADI_MSK(0x00000000,uint32_t)) /* LOOP_EN: Disable */
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#define ENUM_UART_CTL_LOOP_EN (_ADI_MSK(0x00000002,uint32_t)) /* LOOP_EN: Enable */
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#define BITM_UART_CTL_EN (_ADI_MSK(0x00000001,uint32_t)) /* Enable UART */
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#define ENUM_UART_CTL_CLK_DIS (_ADI_MSK(0x00000000,uint32_t)) /* EN: Disable */
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#define ENUM_UART_CTL_CLK_EN (_ADI_MSK(0x00000001,uint32_t)) /* EN: Enable */
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/* ------------------------------------------------------------------------------------------------------------------------
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UART_STAT Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_UART_STAT_RFCS 17 /* Receive FIFO Count Status */
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#define BITP_UART_STAT_CTS 16 /* Clear to Send */
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#define BITP_UART_STAT_SCTS 12 /* Sticky CTS */
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#define BITP_UART_STAT_RO 11 /* Reception On-going */
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#define BITP_UART_STAT_ADDR 10 /* Address Bit Status */
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#define BITP_UART_STAT_ASTKY 9 /* Address Sticky */
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#define BITP_UART_STAT_TFI 8 /* Transmission Finished Indicator */
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#define BITP_UART_STAT_TEMT 7 /* TSR and THR Empty */
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#define BITP_UART_STAT_THRE 5 /* Transmit Hold Register Empty */
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#define BITP_UART_STAT_BI 4 /* Break Indicator */
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#define BITP_UART_STAT_FE 3 /* Framing Error */
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#define BITP_UART_STAT_PE 2 /* Parity Error */
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#define BITP_UART_STAT_OE 1 /* Overrun Error */
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#define BITP_UART_STAT_DR 0 /* Data Ready */
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#define BITM_UART_STAT_RFCS (_ADI_MSK(0x00020000,uint32_t)) /* Receive FIFO Count Status */
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#define ENUM_UART_STAT_RFCS_LO (_ADI_MSK(0x00000000,uint32_t)) /* RFCS: RX FIFO has less than 4 (7) entries when RFIT=0 (1) */
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#define ENUM_UART_STAT_RFCS_HI (_ADI_MSK(0x00020000,uint32_t)) /* RFCS: RX FIFO has at least 4 (7) entries when RFIT=0 (1) */
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#define BITM_UART_STAT_CTS (_ADI_MSK(0x00010000,uint32_t)) /* Clear to Send */
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#define ENUM_UART_STAT_CTS_LO (_ADI_MSK(0x00000000,uint32_t)) /* CTS: Not clear to send (External device not ready to receive) */
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#define ENUM_UART_STAT_CTS_HI (_ADI_MSK(0x00010000,uint32_t)) /* CTS: Clear to send (External device ready to receive) */
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#define BITM_UART_STAT_SCTS (_ADI_MSK(0x00001000,uint32_t)) /* Sticky CTS */
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#define ENUM_UART_STAT_CTS_LO_STKY (_ADI_MSK(0x00000000,uint32_t)) /* SCTS: CTS has not transitioned from low to high */
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#define ENUM_UART_STAT_CTS_HI_STKY (_ADI_MSK(0x00001000,uint32_t)) /* SCTS: CTS has transitioned from low to high */
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#define BITM_UART_STAT_RO (_ADI_MSK(0x00000800,uint32_t)) /* Reception On-going */
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#define ENUM_UART_STAT_NO_RX_PROGRESS (_ADI_MSK(0x00000000,uint32_t)) /* RO: No data reception in progress */
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#define ENUM_UART_STAT_RX_PROGRESS (_ADI_MSK(0x00000800,uint32_t)) /* RO: Data reception in progress */
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#define BITM_UART_STAT_ADDR (_ADI_MSK(0x00000400,uint32_t)) /* Address Bit Status */
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#define ENUM_UART_STAT_ADDR_LO (_ADI_MSK(0x00000000,uint32_t)) /* ADDR: Address bit is low */
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#define ENUM_UART_STAT_ADDR_HI (_ADI_MSK(0x00000400,uint32_t)) /* ADDR: Address bit is high */
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#define BITM_UART_STAT_ASTKY (_ADI_MSK(0x00000200,uint32_t)) /* Address Sticky */
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#define ENUM_UART_STAT_ADDR_LO_STKY (_ADI_MSK(0x00000000,uint32_t)) /* ASTKY: ADDR bit has not been set */
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#define ENUM_UART_STAT_ADDR_HI_STKY (_ADI_MSK(0x00000200,uint32_t)) /* ASTKY: ADDR bit has been set */
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#define BITM_UART_STAT_TFI (_ADI_MSK(0x00000100,uint32_t)) /* Transmission Finished Indicator */
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#define ENUM_UART_STAT_TX_NOT_DONE (_ADI_MSK(0x00000000,uint32_t)) /* TFI: TEMT did not transition from 0 to 1 */
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#define ENUM_UART_STAT_TX_DONE (_ADI_MSK(0x00000100,uint32_t)) /* TFI: TEMT transition from 0 to 1 */
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#define BITM_UART_STAT_TEMT (_ADI_MSK(0x00000080,uint32_t)) /* TSR and THR Empty */
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#define ENUM_UART_STAT_TX_NOT_EMPTY (_ADI_MSK(0x00000000,uint32_t)) /* TEMT: Not empty TSR/THR */
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#define ENUM_UART_STAT_TX_EMPTY (_ADI_MSK(0x00000080,uint32_t)) /* TEMT: TSR/THR Empty */
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#define BITM_UART_STAT_THRE (_ADI_MSK(0x00000020,uint32_t)) /* Transmit Hold Register Empty */
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#define ENUM_UART_STAT_THR_NOT_EMPTY (_ADI_MSK(0x00000000,uint32_t)) /* THRE: Not empty THR/TAIP */
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#define ENUM_UART_STAT_THR_EMPTY (_ADI_MSK(0x00000020,uint32_t)) /* THRE: Empty THR/TAIP */
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#define BITM_UART_STAT_BI (_ADI_MSK(0x00000010,uint32_t)) /* Break Indicator */
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#define ENUM_UART_STAT_NO_BREAK_INT (_ADI_MSK(0x00000000,uint32_t)) /* BI: No break interrupt */
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#define ENUM_UART_STAT_BREAK_INT (_ADI_MSK(0x00000010,uint32_t)) /* BI: Break interrupt */
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#define BITM_UART_STAT_FE (_ADI_MSK(0x00000008,uint32_t)) /* Framing Error */
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#define ENUM_UART_STAT_NO_FRAMING_ERR (_ADI_MSK(0x00000000,uint32_t)) /* FE: No error */
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#define ENUM_UART_STAT_FRAMING_ERR (_ADI_MSK(0x00000008,uint32_t)) /* FE: Invalid stop bit error */
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#define BITM_UART_STAT_PE (_ADI_MSK(0x00000004,uint32_t)) /* Parity Error */
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#define ENUM_UART_STAT_NO_PARITY_ERR (_ADI_MSK(0x00000000,uint32_t)) /* PE: No parity error */
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#define ENUM_UART_STAT_PARITY_ERR (_ADI_MSK(0x00000004,uint32_t)) /* PE: Parity error */
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#define BITM_UART_STAT_OE (_ADI_MSK(0x00000002,uint32_t)) /* Overrun Error */
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#define ENUM_UART_STAT_NO_OVR_ERR (_ADI_MSK(0x00000000,uint32_t)) /* OE: No overrun */
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#define ENUM_UART_STAT_OVR_ERR (_ADI_MSK(0x00000002,uint32_t)) /* OE: Overrun error */
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#define BITM_UART_STAT_DR (_ADI_MSK(0x00000001,uint32_t)) /* Data Ready */
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#define ENUM_UART_STAT_NO_DATA (_ADI_MSK(0x00000000,uint32_t)) /* DR: No new data */
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#define ENUM_UART_STAT_NEW_DATA (_ADI_MSK(0x00000001,uint32_t)) /* DR: New data in RBR */
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/* ------------------------------------------------------------------------------------------------------------------------
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UART_SCR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_UART_SCR_VALUE 0 /* Stored 8-bit Data */
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#define BITM_UART_SCR_VALUE (_ADI_MSK(0x000000FF,uint32_t)) /* Stored 8-bit Data */
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/* ------------------------------------------------------------------------------------------------------------------------
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UART_CLK Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_UART_CLK_EDBO 31 /* Enable Divide By One */
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#define BITP_UART_CLK_DIV 0 /* Divisor */
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#define BITM_UART_CLK_EDBO (_ADI_MSK(0x80000000,uint32_t)) /* Enable Divide By One */
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#define ENUM_UART_CLK_DIS_DIV_BY_ONE (_ADI_MSK(0x00000000,uint32_t)) /* EDBO: Bit clock prescaler = 16 */
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#define ENUM_UART_CLK_EN_DIV_BY_ONE (_ADI_MSK(0x80000000,uint32_t)) /* EDBO: Bit clock prescaler = 1 */
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#define BITM_UART_CLK_DIV (_ADI_MSK(0x0000FFFF,uint32_t)) /* Divisor */
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/* ------------------------------------------------------------------------------------------------------------------------
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|
UART_IMSK Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_UART_IMSK_ETXS 9 /* Enable TX to Status Interrupt Mask Status */
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#define BITP_UART_IMSK_ERXS 8 /* Enable RX to Status Interrupt Mask Status */
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#define BITP_UART_IMSK_EAWI 7 /* Enable Address Word Interrupt Mask Status */
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#define BITP_UART_IMSK_ERFCI 6 /* Enable Receive FIFO Count Interrupt Mask Status */
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#define BITP_UART_IMSK_ETFI 5 /* Enable Transmission Finished Interrupt Mask Status */
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#define BITP_UART_IMSK_EDTPTI 4 /* Enable DMA TX Peripheral Trigerred Interrupt Mask Status */
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#define BITP_UART_IMSK_EDSSI 3 /* Enable Modem Status Interrupt Mask Status */
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#define BITP_UART_IMSK_ELSI 2 /* Enable Line Status Interrupt Mask Status */
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#define BITP_UART_IMSK_ETBEI 1 /* Enable Transmit Buffer Empty Interrupt Mask Status */
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#define BITP_UART_IMSK_ERBFI 0 /* Enable Receive Buffer Full Interrupt Mask Status */
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#define BITM_UART_IMSK_ETXS (_ADI_MSK(0x00000200,uint32_t)) /* Enable TX to Status Interrupt Mask Status */
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#define ENUM_UART_ETXS_LO (_ADI_MSK(0x00000000,uint32_t)) /* ETXS: Interrupt is masked */
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#define ENUM_UART_ETXS_HI (_ADI_MSK(0x00000200,uint32_t)) /* ETXS: Interrupt is unmasked */
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#define BITM_UART_IMSK_ERXS (_ADI_MSK(0x00000100,uint32_t)) /* Enable RX to Status Interrupt Mask Status */
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#define ENUM_UART_ERXS_LO (_ADI_MSK(0x00000000,uint32_t)) /* ERXS: Interrupt is masked */
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#define ENUM_UART_ERXS_HI (_ADI_MSK(0x00000100,uint32_t)) /* ERXS: Interrupt is unmasked */
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#define BITM_UART_IMSK_EAWI (_ADI_MSK(0x00000080,uint32_t)) /* Enable Address Word Interrupt Mask Status */
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#define ENUM_UART_EAWI_LO (_ADI_MSK(0x00000000,uint32_t)) /* EAWI: Interrupt is masked */
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#define ENUM_UART_EAWI_HI (_ADI_MSK(0x00000080,uint32_t)) /* EAWI: Interrupt is unmasked */
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#define BITM_UART_IMSK_ERFCI (_ADI_MSK(0x00000040,uint32_t)) /* Enable Receive FIFO Count Interrupt Mask Status */
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#define ENUM_UART_ERFCI_LO (_ADI_MSK(0x00000000,uint32_t)) /* ERFCI: Interrupt is masked */
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#define ENUM_UART_ERFCI_HI (_ADI_MSK(0x00000040,uint32_t)) /* ERFCI: Interrupt is unmasked */
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#define BITM_UART_IMSK_ETFI (_ADI_MSK(0x00000020,uint32_t)) /* Enable Transmission Finished Interrupt Mask Status */
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#define ENUM_UART_ETFI_LO (_ADI_MSK(0x00000000,uint32_t)) /* ETFI: Interrupt is masked */
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#define ENUM_UART_ETFI_HI (_ADI_MSK(0x00000020,uint32_t)) /* ETFI: Interrupt is unmasked */
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#define BITM_UART_IMSK_EDTPTI (_ADI_MSK(0x00000010,uint32_t)) /* Enable DMA TX Peripheral Trigerred Interrupt Mask Status */
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#define ENUM_UART_EDTPTI_LO (_ADI_MSK(0x00000000,uint32_t)) /* EDTPTI: Interrupt is masked */
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#define ENUM_UART_EDTPTI_HI (_ADI_MSK(0x00000010,uint32_t)) /* EDTPTI: Interrupt is unmasked */
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#define BITM_UART_IMSK_EDSSI (_ADI_MSK(0x00000008,uint32_t)) /* Enable Modem Status Interrupt Mask Status */
|
|
#define ENUM_UART_EDSSI_LO (_ADI_MSK(0x00000000,uint32_t)) /* EDSSI: Interrupt is masked */
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#define ENUM_UART_EDSSI_HI (_ADI_MSK(0x00000008,uint32_t)) /* EDSSI: Interrupt is unmasked */
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#define BITM_UART_IMSK_ELSI (_ADI_MSK(0x00000004,uint32_t)) /* Enable Line Status Interrupt Mask Status */
|
|
#define ENUM_UART_ELSI_LO (_ADI_MSK(0x00000000,uint32_t)) /* ELSI: Interrupt is masked */
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#define ENUM_UART_ELSI_HI (_ADI_MSK(0x00000004,uint32_t)) /* ELSI: Interrupt is unmasked */
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#define BITM_UART_IMSK_ETBEI (_ADI_MSK(0x00000002,uint32_t)) /* Enable Transmit Buffer Empty Interrupt Mask Status */
|
|
#define ENUM_UART_ETBEI_LO (_ADI_MSK(0x00000000,uint32_t)) /* ETBEI: Interrupt is masked */
|
|
#define ENUM_UART_ETBEI_HI (_ADI_MSK(0x00000002,uint32_t)) /* ETBEI: Interrupt is unmasked */
|
|
|
|
#define BITM_UART_IMSK_ERBFI (_ADI_MSK(0x00000001,uint32_t)) /* Enable Receive Buffer Full Interrupt Mask Status */
|
|
#define ENUM_UART_ERBFI_LO (_ADI_MSK(0x00000000,uint32_t)) /* ERBFI: Interrupt is masked */
|
|
#define ENUM_UART_ERBFI_HI (_ADI_MSK(0x00000001,uint32_t)) /* ERBFI: Interrupt is unmasked */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
UART_IMSK_SET Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_UART_IMSK_SET_ETXS 9 /* Enable TX to Status Interrupt Mask Set */
|
|
#define BITP_UART_IMSK_SET_ERXS 8 /* Enable RX to Status Interrupt Mask Set */
|
|
#define BITP_UART_IMSK_SET_EAWI 7 /* Enable Address Word Interrupt Mask Set */
|
|
#define BITP_UART_IMSK_SET_ERFCI 6 /* Enable Receive FIFO Count Interrupt Mask Set */
|
|
#define BITP_UART_IMSK_SET_ETFI 5 /* Enable Transmission Finished Interrupt Mask Set */
|
|
#define BITP_UART_IMSK_SET_EDTPTI 4 /* Enable DMA TX Peripheral Triggered Interrupt Mask Set */
|
|
#define BITP_UART_IMSK_SET_EDSSI 3 /* Enable Modem Status Interrupt Mask Set */
|
|
#define BITP_UART_IMSK_SET_ELSI 2 /* Enable Line Status Interrupt Mask Set */
|
|
#define BITP_UART_IMSK_SET_ETBEI 1 /* Enable Transmit Buffer Empty Interrupt Mask Set */
|
|
#define BITP_UART_IMSK_SET_ERBFI 0 /* Enable Receive Buffer Full Interrupt Mask Set */
|
|
|
|
/* The fields and enumerations for UART_IMSK_SET are also in UART - see the common set of ENUM_UART_* #defines located with register UART_IMSK */
|
|
|
|
#define BITM_UART_IMSK_SET_ETXS (_ADI_MSK(0x00000200,uint32_t)) /* Enable TX to Status Interrupt Mask Set */
|
|
#define BITM_UART_IMSK_SET_ERXS (_ADI_MSK(0x00000100,uint32_t)) /* Enable RX to Status Interrupt Mask Set */
|
|
#define BITM_UART_IMSK_SET_EAWI (_ADI_MSK(0x00000080,uint32_t)) /* Enable Address Word Interrupt Mask Set */
|
|
#define BITM_UART_IMSK_SET_ERFCI (_ADI_MSK(0x00000040,uint32_t)) /* Enable Receive FIFO Count Interrupt Mask Set */
|
|
#define BITM_UART_IMSK_SET_ETFI (_ADI_MSK(0x00000020,uint32_t)) /* Enable Transmission Finished Interrupt Mask Set */
|
|
#define BITM_UART_IMSK_SET_EDTPTI (_ADI_MSK(0x00000010,uint32_t)) /* Enable DMA TX Peripheral Triggered Interrupt Mask Set */
|
|
#define BITM_UART_IMSK_SET_EDSSI (_ADI_MSK(0x00000008,uint32_t)) /* Enable Modem Status Interrupt Mask Set */
|
|
#define BITM_UART_IMSK_SET_ELSI (_ADI_MSK(0x00000004,uint32_t)) /* Enable Line Status Interrupt Mask Set */
|
|
#define BITM_UART_IMSK_SET_ETBEI (_ADI_MSK(0x00000002,uint32_t)) /* Enable Transmit Buffer Empty Interrupt Mask Set */
|
|
#define BITM_UART_IMSK_SET_ERBFI (_ADI_MSK(0x00000001,uint32_t)) /* Enable Receive Buffer Full Interrupt Mask Set */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
UART_IMSK_CLR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_UART_IMSK_CLR_ETXS 9 /* Enable TX to Status Interrupt Mask Clear */
|
|
#define BITP_UART_IMSK_CLR_ERXS 8 /* Enable RX to Status Interrupt Mask Clear */
|
|
#define BITP_UART_IMSK_CLR_EAWI 7 /* Enable Address Word Interrupt Mask Clear */
|
|
#define BITP_UART_IMSK_CLR_ERFCI 6 /* Enable Receive FIFO Count Interrupt Mask Clear */
|
|
#define BITP_UART_IMSK_CLR_ETFI 5 /* Enable Transmission Finished Interrupt Mask Clear */
|
|
#define BITP_UART_IMSK_CLR_EDTPTI 4 /* Enable DMA TX Peripheral Triggered Interrupt Mask Clear */
|
|
#define BITP_UART_IMSK_CLR_EDSSI 3 /* Enable Modem Status Interrupt Mask Clear */
|
|
#define BITP_UART_IMSK_CLR_ELSI 2 /* Enable Line Status Interrupt Mask Clear */
|
|
#define BITP_UART_IMSK_CLR_ETBEI 1 /* Enable Transmit Buffer Empty Interrupt Mask Clear */
|
|
#define BITP_UART_IMSK_CLR_ERBFI 0 /* Enable Receive Buffer Full Interrupt Mask Clear */
|
|
|
|
/* The fields and enumerations for UART_IMSK_CLR are also in UART - see the common set of ENUM_UART_* #defines located with register UART_IMSK */
|
|
|
|
#define BITM_UART_IMSK_CLR_ETXS (_ADI_MSK(0x00000200,uint32_t)) /* Enable TX to Status Interrupt Mask Clear */
|
|
#define BITM_UART_IMSK_CLR_ERXS (_ADI_MSK(0x00000100,uint32_t)) /* Enable RX to Status Interrupt Mask Clear */
|
|
#define BITM_UART_IMSK_CLR_EAWI (_ADI_MSK(0x00000080,uint32_t)) /* Enable Address Word Interrupt Mask Clear */
|
|
#define BITM_UART_IMSK_CLR_ERFCI (_ADI_MSK(0x00000040,uint32_t)) /* Enable Receive FIFO Count Interrupt Mask Clear */
|
|
#define BITM_UART_IMSK_CLR_ETFI (_ADI_MSK(0x00000020,uint32_t)) /* Enable Transmission Finished Interrupt Mask Clear */
|
|
#define BITM_UART_IMSK_CLR_EDTPTI (_ADI_MSK(0x00000010,uint32_t)) /* Enable DMA TX Peripheral Triggered Interrupt Mask Clear */
|
|
#define BITM_UART_IMSK_CLR_EDSSI (_ADI_MSK(0x00000008,uint32_t)) /* Enable Modem Status Interrupt Mask Clear */
|
|
#define BITM_UART_IMSK_CLR_ELSI (_ADI_MSK(0x00000004,uint32_t)) /* Enable Line Status Interrupt Mask Clear */
|
|
#define BITM_UART_IMSK_CLR_ETBEI (_ADI_MSK(0x00000002,uint32_t)) /* Enable Transmit Buffer Empty Interrupt Mask Clear */
|
|
#define BITM_UART_IMSK_CLR_ERBFI (_ADI_MSK(0x00000001,uint32_t)) /* Enable Receive Buffer Full Interrupt Mask Clear */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
UART_RBR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_UART_RBR_VALUE 0 /* 8-bit data */
|
|
#define BITM_UART_RBR_VALUE (_ADI_MSK(0x000000FF,uint32_t)) /* 8-bit data */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
UART_THR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_UART_THR_VALUE 0 /* 8 bit data */
|
|
#define BITM_UART_THR_VALUE (_ADI_MSK(0x000000FF,uint32_t)) /* 8 bit data */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
UART_TAIP Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_UART_TAIP_VALUE 0 /* 8-bit data */
|
|
#define BITM_UART_TAIP_VALUE (_ADI_MSK(0x000000FF,uint32_t)) /* 8-bit data */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
UART_TSR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_UART_TSR_VALUE 0 /* Contents of TSR */
|
|
#define BITM_UART_TSR_VALUE (_ADI_MSK(0x000007FF,uint32_t)) /* Contents of TSR */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
UART_RSR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_UART_RSR_VALUE 0 /* Contents of RSR */
|
|
#define BITM_UART_RSR_VALUE (_ADI_MSK(0x000003FF,uint32_t)) /* Contents of RSR */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
UART_TXCNT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_UART_TXCNT_VALUE 0 /* 16-bit Counter Value */
|
|
#define BITM_UART_TXCNT_VALUE (_ADI_MSK(0x0000FFFF,uint32_t)) /* 16-bit Counter Value */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
UART_RXCNT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_UART_RXCNT_VALUE 0 /* 16-bit Counter Value */
|
|
#define BITM_UART_RXCNT_VALUE (_ADI_MSK(0x0000FFFF,uint32_t)) /* 16-bit Counter Value */
|
|
|
|
/* ==================================================
|
|
General Purpose Input/Output Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
PORTA
|
|
========================= */
|
|
#define REG_PORTA_FER 0xFFC03000 /* PORTA Port x Function Enable Register */
|
|
#define REG_PORTA_FER_SET 0xFFC03004 /* PORTA Port x Function Enable Set Register */
|
|
#define REG_PORTA_FER_CLR 0xFFC03008 /* PORTA Port x Function Enable Clear Register */
|
|
#define REG_PORTA_DATA 0xFFC0300C /* PORTA Port x GPIO Data Register */
|
|
#define REG_PORTA_DATA_SET 0xFFC03010 /* PORTA Port x GPIO Data Set Register */
|
|
#define REG_PORTA_DATA_CLR 0xFFC03014 /* PORTA Port x GPIO Data Clear Register */
|
|
#define REG_PORTA_DIR 0xFFC03018 /* PORTA Port x GPIO Direction Register */
|
|
#define REG_PORTA_DIR_SET 0xFFC0301C /* PORTA Port x GPIO Direction Set Register */
|
|
#define REG_PORTA_DIR_CLR 0xFFC03020 /* PORTA Port x GPIO Direction Clear Register */
|
|
#define REG_PORTA_INEN 0xFFC03024 /* PORTA Port x GPIO Input Enable Register */
|
|
#define REG_PORTA_INEN_SET 0xFFC03028 /* PORTA Port x GPIO Input Enable Set Register */
|
|
#define REG_PORTA_INEN_CLR 0xFFC0302C /* PORTA Port x GPIO Input Enable Clear Register */
|
|
#define REG_PORTA_MUX 0xFFC03030 /* PORTA Port x Multiplexer Control Register */
|
|
#define REG_PORTA_DATA_TGL 0xFFC03034 /* PORTA Port x GPIO Input Enable Toggle Register */
|
|
#define REG_PORTA_POL 0xFFC03038 /* PORTA Port x GPIO Polarity Invert Register */
|
|
#define REG_PORTA_POL_SET 0xFFC0303C /* PORTA Port x GPIO Polarity Invert Set Register */
|
|
#define REG_PORTA_POL_CLR 0xFFC03040 /* PORTA Port x GPIO Polarity Invert Clear Register */
|
|
#define REG_PORTA_LOCK 0xFFC03044 /* PORTA Port x GPIO Lock Register */
|
|
#define REG_PORTA_REVID 0xFFC0307C /* PORTA Port x GPIO Revision ID */
|
|
|
|
/* =========================
|
|
PORTB
|
|
========================= */
|
|
#define REG_PORTB_FER 0xFFC03080 /* PORTB Port x Function Enable Register */
|
|
#define REG_PORTB_FER_SET 0xFFC03084 /* PORTB Port x Function Enable Set Register */
|
|
#define REG_PORTB_FER_CLR 0xFFC03088 /* PORTB Port x Function Enable Clear Register */
|
|
#define REG_PORTB_DATA 0xFFC0308C /* PORTB Port x GPIO Data Register */
|
|
#define REG_PORTB_DATA_SET 0xFFC03090 /* PORTB Port x GPIO Data Set Register */
|
|
#define REG_PORTB_DATA_CLR 0xFFC03094 /* PORTB Port x GPIO Data Clear Register */
|
|
#define REG_PORTB_DIR 0xFFC03098 /* PORTB Port x GPIO Direction Register */
|
|
#define REG_PORTB_DIR_SET 0xFFC0309C /* PORTB Port x GPIO Direction Set Register */
|
|
#define REG_PORTB_DIR_CLR 0xFFC030A0 /* PORTB Port x GPIO Direction Clear Register */
|
|
#define REG_PORTB_INEN 0xFFC030A4 /* PORTB Port x GPIO Input Enable Register */
|
|
#define REG_PORTB_INEN_SET 0xFFC030A8 /* PORTB Port x GPIO Input Enable Set Register */
|
|
#define REG_PORTB_INEN_CLR 0xFFC030AC /* PORTB Port x GPIO Input Enable Clear Register */
|
|
#define REG_PORTB_MUX 0xFFC030B0 /* PORTB Port x Multiplexer Control Register */
|
|
#define REG_PORTB_DATA_TGL 0xFFC030B4 /* PORTB Port x GPIO Input Enable Toggle Register */
|
|
#define REG_PORTB_POL 0xFFC030B8 /* PORTB Port x GPIO Polarity Invert Register */
|
|
#define REG_PORTB_POL_SET 0xFFC030BC /* PORTB Port x GPIO Polarity Invert Set Register */
|
|
#define REG_PORTB_POL_CLR 0xFFC030C0 /* PORTB Port x GPIO Polarity Invert Clear Register */
|
|
#define REG_PORTB_LOCK 0xFFC030C4 /* PORTB Port x GPIO Lock Register */
|
|
#define REG_PORTB_REVID 0xFFC030FC /* PORTB Port x GPIO Revision ID */
|
|
|
|
/* =========================
|
|
PORTC
|
|
========================= */
|
|
#define REG_PORTC_FER 0xFFC03100 /* PORTC Port x Function Enable Register */
|
|
#define REG_PORTC_FER_SET 0xFFC03104 /* PORTC Port x Function Enable Set Register */
|
|
#define REG_PORTC_FER_CLR 0xFFC03108 /* PORTC Port x Function Enable Clear Register */
|
|
#define REG_PORTC_DATA 0xFFC0310C /* PORTC Port x GPIO Data Register */
|
|
#define REG_PORTC_DATA_SET 0xFFC03110 /* PORTC Port x GPIO Data Set Register */
|
|
#define REG_PORTC_DATA_CLR 0xFFC03114 /* PORTC Port x GPIO Data Clear Register */
|
|
#define REG_PORTC_DIR 0xFFC03118 /* PORTC Port x GPIO Direction Register */
|
|
#define REG_PORTC_DIR_SET 0xFFC0311C /* PORTC Port x GPIO Direction Set Register */
|
|
#define REG_PORTC_DIR_CLR 0xFFC03120 /* PORTC Port x GPIO Direction Clear Register */
|
|
#define REG_PORTC_INEN 0xFFC03124 /* PORTC Port x GPIO Input Enable Register */
|
|
#define REG_PORTC_INEN_SET 0xFFC03128 /* PORTC Port x GPIO Input Enable Set Register */
|
|
#define REG_PORTC_INEN_CLR 0xFFC0312C /* PORTC Port x GPIO Input Enable Clear Register */
|
|
#define REG_PORTC_MUX 0xFFC03130 /* PORTC Port x Multiplexer Control Register */
|
|
#define REG_PORTC_DATA_TGL 0xFFC03134 /* PORTC Port x GPIO Input Enable Toggle Register */
|
|
#define REG_PORTC_POL 0xFFC03138 /* PORTC Port x GPIO Polarity Invert Register */
|
|
#define REG_PORTC_POL_SET 0xFFC0313C /* PORTC Port x GPIO Polarity Invert Set Register */
|
|
#define REG_PORTC_POL_CLR 0xFFC03140 /* PORTC Port x GPIO Polarity Invert Clear Register */
|
|
#define REG_PORTC_LOCK 0xFFC03144 /* PORTC Port x GPIO Lock Register */
|
|
#define REG_PORTC_REVID 0xFFC0317C /* PORTC Port x GPIO Revision ID */
|
|
|
|
/* =========================
|
|
PORTD
|
|
========================= */
|
|
#define REG_PORTD_FER 0xFFC03180 /* PORTD Port x Function Enable Register */
|
|
#define REG_PORTD_FER_SET 0xFFC03184 /* PORTD Port x Function Enable Set Register */
|
|
#define REG_PORTD_FER_CLR 0xFFC03188 /* PORTD Port x Function Enable Clear Register */
|
|
#define REG_PORTD_DATA 0xFFC0318C /* PORTD Port x GPIO Data Register */
|
|
#define REG_PORTD_DATA_SET 0xFFC03190 /* PORTD Port x GPIO Data Set Register */
|
|
#define REG_PORTD_DATA_CLR 0xFFC03194 /* PORTD Port x GPIO Data Clear Register */
|
|
#define REG_PORTD_DIR 0xFFC03198 /* PORTD Port x GPIO Direction Register */
|
|
#define REG_PORTD_DIR_SET 0xFFC0319C /* PORTD Port x GPIO Direction Set Register */
|
|
#define REG_PORTD_DIR_CLR 0xFFC031A0 /* PORTD Port x GPIO Direction Clear Register */
|
|
#define REG_PORTD_INEN 0xFFC031A4 /* PORTD Port x GPIO Input Enable Register */
|
|
#define REG_PORTD_INEN_SET 0xFFC031A8 /* PORTD Port x GPIO Input Enable Set Register */
|
|
#define REG_PORTD_INEN_CLR 0xFFC031AC /* PORTD Port x GPIO Input Enable Clear Register */
|
|
#define REG_PORTD_MUX 0xFFC031B0 /* PORTD Port x Multiplexer Control Register */
|
|
#define REG_PORTD_DATA_TGL 0xFFC031B4 /* PORTD Port x GPIO Input Enable Toggle Register */
|
|
#define REG_PORTD_POL 0xFFC031B8 /* PORTD Port x GPIO Polarity Invert Register */
|
|
#define REG_PORTD_POL_SET 0xFFC031BC /* PORTD Port x GPIO Polarity Invert Set Register */
|
|
#define REG_PORTD_POL_CLR 0xFFC031C0 /* PORTD Port x GPIO Polarity Invert Clear Register */
|
|
#define REG_PORTD_LOCK 0xFFC031C4 /* PORTD Port x GPIO Lock Register */
|
|
#define REG_PORTD_REVID 0xFFC031FC /* PORTD Port x GPIO Revision ID */
|
|
|
|
/* =========================
|
|
PORTE
|
|
========================= */
|
|
#define REG_PORTE_FER 0xFFC03200 /* PORTE Port x Function Enable Register */
|
|
#define REG_PORTE_FER_SET 0xFFC03204 /* PORTE Port x Function Enable Set Register */
|
|
#define REG_PORTE_FER_CLR 0xFFC03208 /* PORTE Port x Function Enable Clear Register */
|
|
#define REG_PORTE_DATA 0xFFC0320C /* PORTE Port x GPIO Data Register */
|
|
#define REG_PORTE_DATA_SET 0xFFC03210 /* PORTE Port x GPIO Data Set Register */
|
|
#define REG_PORTE_DATA_CLR 0xFFC03214 /* PORTE Port x GPIO Data Clear Register */
|
|
#define REG_PORTE_DIR 0xFFC03218 /* PORTE Port x GPIO Direction Register */
|
|
#define REG_PORTE_DIR_SET 0xFFC0321C /* PORTE Port x GPIO Direction Set Register */
|
|
#define REG_PORTE_DIR_CLR 0xFFC03220 /* PORTE Port x GPIO Direction Clear Register */
|
|
#define REG_PORTE_INEN 0xFFC03224 /* PORTE Port x GPIO Input Enable Register */
|
|
#define REG_PORTE_INEN_SET 0xFFC03228 /* PORTE Port x GPIO Input Enable Set Register */
|
|
#define REG_PORTE_INEN_CLR 0xFFC0322C /* PORTE Port x GPIO Input Enable Clear Register */
|
|
#define REG_PORTE_MUX 0xFFC03230 /* PORTE Port x Multiplexer Control Register */
|
|
#define REG_PORTE_DATA_TGL 0xFFC03234 /* PORTE Port x GPIO Input Enable Toggle Register */
|
|
#define REG_PORTE_POL 0xFFC03238 /* PORTE Port x GPIO Polarity Invert Register */
|
|
#define REG_PORTE_POL_SET 0xFFC0323C /* PORTE Port x GPIO Polarity Invert Set Register */
|
|
#define REG_PORTE_POL_CLR 0xFFC03240 /* PORTE Port x GPIO Polarity Invert Clear Register */
|
|
#define REG_PORTE_LOCK 0xFFC03244 /* PORTE Port x GPIO Lock Register */
|
|
#define REG_PORTE_REVID 0xFFC0327C /* PORTE Port x GPIO Revision ID */
|
|
|
|
/* =========================
|
|
PORTF
|
|
========================= */
|
|
#define REG_PORTF_FER 0xFFC03280 /* PORTF Port x Function Enable Register */
|
|
#define REG_PORTF_FER_SET 0xFFC03284 /* PORTF Port x Function Enable Set Register */
|
|
#define REG_PORTF_FER_CLR 0xFFC03288 /* PORTF Port x Function Enable Clear Register */
|
|
#define REG_PORTF_DATA 0xFFC0328C /* PORTF Port x GPIO Data Register */
|
|
#define REG_PORTF_DATA_SET 0xFFC03290 /* PORTF Port x GPIO Data Set Register */
|
|
#define REG_PORTF_DATA_CLR 0xFFC03294 /* PORTF Port x GPIO Data Clear Register */
|
|
#define REG_PORTF_DIR 0xFFC03298 /* PORTF Port x GPIO Direction Register */
|
|
#define REG_PORTF_DIR_SET 0xFFC0329C /* PORTF Port x GPIO Direction Set Register */
|
|
#define REG_PORTF_DIR_CLR 0xFFC032A0 /* PORTF Port x GPIO Direction Clear Register */
|
|
#define REG_PORTF_INEN 0xFFC032A4 /* PORTF Port x GPIO Input Enable Register */
|
|
#define REG_PORTF_INEN_SET 0xFFC032A8 /* PORTF Port x GPIO Input Enable Set Register */
|
|
#define REG_PORTF_INEN_CLR 0xFFC032AC /* PORTF Port x GPIO Input Enable Clear Register */
|
|
#define REG_PORTF_MUX 0xFFC032B0 /* PORTF Port x Multiplexer Control Register */
|
|
#define REG_PORTF_DATA_TGL 0xFFC032B4 /* PORTF Port x GPIO Input Enable Toggle Register */
|
|
#define REG_PORTF_POL 0xFFC032B8 /* PORTF Port x GPIO Polarity Invert Register */
|
|
#define REG_PORTF_POL_SET 0xFFC032BC /* PORTF Port x GPIO Polarity Invert Set Register */
|
|
#define REG_PORTF_POL_CLR 0xFFC032C0 /* PORTF Port x GPIO Polarity Invert Clear Register */
|
|
#define REG_PORTF_LOCK 0xFFC032C4 /* PORTF Port x GPIO Lock Register */
|
|
#define REG_PORTF_REVID 0xFFC032FC /* PORTF Port x GPIO Revision ID */
|
|
|
|
/* =========================
|
|
PORTG
|
|
========================= */
|
|
#define REG_PORTG_FER 0xFFC03300 /* PORTG Port x Function Enable Register */
|
|
#define REG_PORTG_FER_SET 0xFFC03304 /* PORTG Port x Function Enable Set Register */
|
|
#define REG_PORTG_FER_CLR 0xFFC03308 /* PORTG Port x Function Enable Clear Register */
|
|
#define REG_PORTG_DATA 0xFFC0330C /* PORTG Port x GPIO Data Register */
|
|
#define REG_PORTG_DATA_SET 0xFFC03310 /* PORTG Port x GPIO Data Set Register */
|
|
#define REG_PORTG_DATA_CLR 0xFFC03314 /* PORTG Port x GPIO Data Clear Register */
|
|
#define REG_PORTG_DIR 0xFFC03318 /* PORTG Port x GPIO Direction Register */
|
|
#define REG_PORTG_DIR_SET 0xFFC0331C /* PORTG Port x GPIO Direction Set Register */
|
|
#define REG_PORTG_DIR_CLR 0xFFC03320 /* PORTG Port x GPIO Direction Clear Register */
|
|
#define REG_PORTG_INEN 0xFFC03324 /* PORTG Port x GPIO Input Enable Register */
|
|
#define REG_PORTG_INEN_SET 0xFFC03328 /* PORTG Port x GPIO Input Enable Set Register */
|
|
#define REG_PORTG_INEN_CLR 0xFFC0332C /* PORTG Port x GPIO Input Enable Clear Register */
|
|
#define REG_PORTG_MUX 0xFFC03330 /* PORTG Port x Multiplexer Control Register */
|
|
#define REG_PORTG_DATA_TGL 0xFFC03334 /* PORTG Port x GPIO Input Enable Toggle Register */
|
|
#define REG_PORTG_POL 0xFFC03338 /* PORTG Port x GPIO Polarity Invert Register */
|
|
#define REG_PORTG_POL_SET 0xFFC0333C /* PORTG Port x GPIO Polarity Invert Set Register */
|
|
#define REG_PORTG_POL_CLR 0xFFC03340 /* PORTG Port x GPIO Polarity Invert Clear Register */
|
|
#define REG_PORTG_LOCK 0xFFC03344 /* PORTG Port x GPIO Lock Register */
|
|
#define REG_PORTG_REVID 0xFFC0337C /* PORTG Port x GPIO Revision ID */
|
|
|
|
/* =========================
|
|
PORT
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PORT_FER Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PORT_FER_PX15 15 /* Port x Bit 15 Mode */
|
|
#define BITP_PORT_FER_PX14 14 /* Port x Bit 14 Mode */
|
|
#define BITP_PORT_FER_PX13 13 /* Port x Bit 13 Mode */
|
|
#define BITP_PORT_FER_PX12 12 /* Port x Bit 12 Mode */
|
|
#define BITP_PORT_FER_PX11 11 /* Port x Bit 11 Mode */
|
|
#define BITP_PORT_FER_PX10 10 /* Port x Bit 10 Mode */
|
|
#define BITP_PORT_FER_PX9 9 /* Port x Bit 9 Mode */
|
|
#define BITP_PORT_FER_PX8 8 /* Port x Bit 8 Mode */
|
|
#define BITP_PORT_FER_PX7 7 /* Port x Bit 7 Mode */
|
|
#define BITP_PORT_FER_PX6 6 /* Port x Bit 6 Mode */
|
|
#define BITP_PORT_FER_PX5 5 /* Port x Bit 5 Mode */
|
|
#define BITP_PORT_FER_PX4 4 /* Port x Bit 4 Mode */
|
|
#define BITP_PORT_FER_PX3 3 /* Port x Bit 3 Mode */
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#define BITP_PORT_FER_PX2 2 /* Port x Bit 2 Mode */
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#define BITP_PORT_FER_PX1 1 /* Port x Bit 1 Mode */
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#define BITP_PORT_FER_PX0 0 /* Port x Bit 0 Mode */
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#define BITM_PORT_FER_PX15 (_ADI_MSK(0x00008000,uint32_t)) /* Port x Bit 15 Mode */
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#define BITM_PORT_FER_PX14 (_ADI_MSK(0x00004000,uint32_t)) /* Port x Bit 14 Mode */
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#define BITM_PORT_FER_PX13 (_ADI_MSK(0x00002000,uint32_t)) /* Port x Bit 13 Mode */
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#define BITM_PORT_FER_PX12 (_ADI_MSK(0x00001000,uint32_t)) /* Port x Bit 12 Mode */
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#define BITM_PORT_FER_PX11 (_ADI_MSK(0x00000800,uint32_t)) /* Port x Bit 11 Mode */
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#define BITM_PORT_FER_PX10 (_ADI_MSK(0x00000400,uint32_t)) /* Port x Bit 10 Mode */
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#define BITM_PORT_FER_PX9 (_ADI_MSK(0x00000200,uint32_t)) /* Port x Bit 9 Mode */
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#define BITM_PORT_FER_PX8 (_ADI_MSK(0x00000100,uint32_t)) /* Port x Bit 8 Mode */
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#define BITM_PORT_FER_PX7 (_ADI_MSK(0x00000080,uint32_t)) /* Port x Bit 7 Mode */
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#define BITM_PORT_FER_PX6 (_ADI_MSK(0x00000040,uint32_t)) /* Port x Bit 6 Mode */
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#define BITM_PORT_FER_PX5 (_ADI_MSK(0x00000020,uint32_t)) /* Port x Bit 5 Mode */
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#define BITM_PORT_FER_PX4 (_ADI_MSK(0x00000010,uint32_t)) /* Port x Bit 4 Mode */
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#define BITM_PORT_FER_PX3 (_ADI_MSK(0x00000008,uint32_t)) /* Port x Bit 3 Mode */
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#define BITM_PORT_FER_PX2 (_ADI_MSK(0x00000004,uint32_t)) /* Port x Bit 2 Mode */
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#define BITM_PORT_FER_PX1 (_ADI_MSK(0x00000002,uint32_t)) /* Port x Bit 1 Mode */
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#define BITM_PORT_FER_PX0 (_ADI_MSK(0x00000001,uint32_t)) /* Port x Bit 0 Mode */
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|
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
PORT_FER_SET Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_PORT_FER_SET_PX15 15 /* Port x Bit 15 Mode Set */
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#define BITP_PORT_FER_SET_PX14 14 /* Port x Bit 14 Mode Set */
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#define BITP_PORT_FER_SET_PX13 13 /* Port x Bit 13 Mode Set */
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#define BITP_PORT_FER_SET_PX12 12 /* Port x Bit 12 Mode Set */
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#define BITP_PORT_FER_SET_PX11 11 /* Port x Bit 11 Mode Set */
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#define BITP_PORT_FER_SET_PX10 10 /* Port x Bit 10 Mode Set */
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#define BITP_PORT_FER_SET_PX9 9 /* Port x Bit 9 Mode Set */
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#define BITP_PORT_FER_SET_PX8 8 /* Port x Bit 8 Mode Set */
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#define BITP_PORT_FER_SET_PX7 7 /* Port x Bit 7 Mode Set */
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#define BITP_PORT_FER_SET_PX6 6 /* Port x Bit 6 Mode Set */
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#define BITP_PORT_FER_SET_PX5 5 /* Port x Bit 5 Mode Set */
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#define BITP_PORT_FER_SET_PX4 4 /* Port x Bit 4 Mode Set */
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#define BITP_PORT_FER_SET_PX3 3 /* Port x Bit 3 Mode Set */
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#define BITP_PORT_FER_SET_PX2 2 /* Port x Bit 2 Mode Set */
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#define BITP_PORT_FER_SET_PX1 1 /* Port x Bit 1 Mode Set */
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#define BITP_PORT_FER_SET_PX0 0 /* Port x Bit 0 Mode Set */
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#define BITM_PORT_FER_SET_PX15 (_ADI_MSK(0x00008000,uint32_t)) /* Port x Bit 15 Mode Set */
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#define BITM_PORT_FER_SET_PX14 (_ADI_MSK(0x00004000,uint32_t)) /* Port x Bit 14 Mode Set */
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#define BITM_PORT_FER_SET_PX13 (_ADI_MSK(0x00002000,uint32_t)) /* Port x Bit 13 Mode Set */
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#define BITM_PORT_FER_SET_PX12 (_ADI_MSK(0x00001000,uint32_t)) /* Port x Bit 12 Mode Set */
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#define BITM_PORT_FER_SET_PX11 (_ADI_MSK(0x00000800,uint32_t)) /* Port x Bit 11 Mode Set */
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#define BITM_PORT_FER_SET_PX10 (_ADI_MSK(0x00000400,uint32_t)) /* Port x Bit 10 Mode Set */
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#define BITM_PORT_FER_SET_PX9 (_ADI_MSK(0x00000200,uint32_t)) /* Port x Bit 9 Mode Set */
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#define BITM_PORT_FER_SET_PX8 (_ADI_MSK(0x00000100,uint32_t)) /* Port x Bit 8 Mode Set */
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#define BITM_PORT_FER_SET_PX7 (_ADI_MSK(0x00000080,uint32_t)) /* Port x Bit 7 Mode Set */
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#define BITM_PORT_FER_SET_PX6 (_ADI_MSK(0x00000040,uint32_t)) /* Port x Bit 6 Mode Set */
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#define BITM_PORT_FER_SET_PX5 (_ADI_MSK(0x00000020,uint32_t)) /* Port x Bit 5 Mode Set */
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#define BITM_PORT_FER_SET_PX4 (_ADI_MSK(0x00000010,uint32_t)) /* Port x Bit 4 Mode Set */
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#define BITM_PORT_FER_SET_PX3 (_ADI_MSK(0x00000008,uint32_t)) /* Port x Bit 3 Mode Set */
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#define BITM_PORT_FER_SET_PX2 (_ADI_MSK(0x00000004,uint32_t)) /* Port x Bit 2 Mode Set */
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#define BITM_PORT_FER_SET_PX1 (_ADI_MSK(0x00000002,uint32_t)) /* Port x Bit 1 Mode Set */
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#define BITM_PORT_FER_SET_PX0 (_ADI_MSK(0x00000001,uint32_t)) /* Port x Bit 0 Mode Set */
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|
|
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
PORT_FER_CLR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PORT_FER_CLR_PX15 15 /* Port x Bit 15 Mode Clear */
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#define BITP_PORT_FER_CLR_PX14 14 /* Port x Bit 14 Mode Clear */
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#define BITP_PORT_FER_CLR_PX13 13 /* Port x Bit 13 Mode Clear */
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#define BITP_PORT_FER_CLR_PX12 12 /* Port x Bit 12 Mode Clear */
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#define BITP_PORT_FER_CLR_PX11 11 /* Port x Bit 11 Mode Clear */
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#define BITP_PORT_FER_CLR_PX10 10 /* Port x Bit 10 Mode Clear */
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#define BITP_PORT_FER_CLR_PX9 9 /* Port x Bit 9 Mode Clear */
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#define BITP_PORT_FER_CLR_PX8 8 /* Port x Bit 8 Mode Clear */
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|
#define BITP_PORT_FER_CLR_PX7 7 /* Port x Bit 7 Mode Clear */
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#define BITP_PORT_FER_CLR_PX6 6 /* Port x Bit 6 Mode Clear */
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#define BITP_PORT_FER_CLR_PX5 5 /* Port x Bit 5 Mode Clear */
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#define BITP_PORT_FER_CLR_PX4 4 /* Port x Bit 4 Mode Clear */
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#define BITP_PORT_FER_CLR_PX3 3 /* Port x Bit 3 Mode Clear */
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#define BITP_PORT_FER_CLR_PX2 2 /* Port x Bit 2 Mode Clear */
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|
#define BITP_PORT_FER_CLR_PX1 1 /* Port x Bit 1 Mode Clear */
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|
#define BITP_PORT_FER_CLR_PX0 0 /* Port x Bit 0 Mode Clear */
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|
#define BITM_PORT_FER_CLR_PX15 (_ADI_MSK(0x00008000,uint32_t)) /* Port x Bit 15 Mode Clear */
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|
#define BITM_PORT_FER_CLR_PX14 (_ADI_MSK(0x00004000,uint32_t)) /* Port x Bit 14 Mode Clear */
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|
#define BITM_PORT_FER_CLR_PX13 (_ADI_MSK(0x00002000,uint32_t)) /* Port x Bit 13 Mode Clear */
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|
#define BITM_PORT_FER_CLR_PX12 (_ADI_MSK(0x00001000,uint32_t)) /* Port x Bit 12 Mode Clear */
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|
#define BITM_PORT_FER_CLR_PX11 (_ADI_MSK(0x00000800,uint32_t)) /* Port x Bit 11 Mode Clear */
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|
#define BITM_PORT_FER_CLR_PX10 (_ADI_MSK(0x00000400,uint32_t)) /* Port x Bit 10 Mode Clear */
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|
#define BITM_PORT_FER_CLR_PX9 (_ADI_MSK(0x00000200,uint32_t)) /* Port x Bit 9 Mode Clear */
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|
#define BITM_PORT_FER_CLR_PX8 (_ADI_MSK(0x00000100,uint32_t)) /* Port x Bit 8 Mode Clear */
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|
#define BITM_PORT_FER_CLR_PX7 (_ADI_MSK(0x00000080,uint32_t)) /* Port x Bit 7 Mode Clear */
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#define BITM_PORT_FER_CLR_PX6 (_ADI_MSK(0x00000040,uint32_t)) /* Port x Bit 6 Mode Clear */
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|
#define BITM_PORT_FER_CLR_PX5 (_ADI_MSK(0x00000020,uint32_t)) /* Port x Bit 5 Mode Clear */
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|
#define BITM_PORT_FER_CLR_PX4 (_ADI_MSK(0x00000010,uint32_t)) /* Port x Bit 4 Mode Clear */
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|
#define BITM_PORT_FER_CLR_PX3 (_ADI_MSK(0x00000008,uint32_t)) /* Port x Bit 3 Mode Clear */
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|
#define BITM_PORT_FER_CLR_PX2 (_ADI_MSK(0x00000004,uint32_t)) /* Port x Bit 2 Mode Clear */
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|
#define BITM_PORT_FER_CLR_PX1 (_ADI_MSK(0x00000002,uint32_t)) /* Port x Bit 1 Mode Clear */
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|
#define BITM_PORT_FER_CLR_PX0 (_ADI_MSK(0x00000001,uint32_t)) /* Port x Bit 0 Mode Clear */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PORT_DATA Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PORT_DATA_PX15 15 /* Port x Bit 15 Data */
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|
#define BITP_PORT_DATA_PX14 14 /* Port x Bit 14 Data */
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|
#define BITP_PORT_DATA_PX13 13 /* Port x Bit 13 Data */
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|
#define BITP_PORT_DATA_PX12 12 /* Port x Bit 12 Data */
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|
#define BITP_PORT_DATA_PX11 11 /* Port x Bit 11 Data */
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#define BITP_PORT_DATA_PX10 10 /* Port x Bit 10 Data */
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|
#define BITP_PORT_DATA_PX9 9 /* Port x Bit 9 Data */
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|
#define BITP_PORT_DATA_PX8 8 /* Port x Bit 8 Data */
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|
#define BITP_PORT_DATA_PX7 7 /* Port x Bit 7 Data */
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|
#define BITP_PORT_DATA_PX6 6 /* Port x Bit 6 Data */
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|
#define BITP_PORT_DATA_PX5 5 /* Port x Bit 5 Data */
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|
#define BITP_PORT_DATA_PX4 4 /* Port x Bit 4 Data */
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#define BITP_PORT_DATA_PX3 3 /* Port x Bit 3 Data */
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|
#define BITP_PORT_DATA_PX2 2 /* Port x Bit 2 Data */
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#define BITP_PORT_DATA_PX1 1 /* Port x Bit 1 Data */
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#define BITP_PORT_DATA_PX0 0 /* Port x Bit 0 Data */
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#define BITM_PORT_DATA_PX15 (_ADI_MSK(0x00008000,uint32_t)) /* Port x Bit 15 Data */
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#define BITM_PORT_DATA_PX14 (_ADI_MSK(0x00004000,uint32_t)) /* Port x Bit 14 Data */
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|
#define BITM_PORT_DATA_PX13 (_ADI_MSK(0x00002000,uint32_t)) /* Port x Bit 13 Data */
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#define BITM_PORT_DATA_PX12 (_ADI_MSK(0x00001000,uint32_t)) /* Port x Bit 12 Data */
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#define BITM_PORT_DATA_PX11 (_ADI_MSK(0x00000800,uint32_t)) /* Port x Bit 11 Data */
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#define BITM_PORT_DATA_PX10 (_ADI_MSK(0x00000400,uint32_t)) /* Port x Bit 10 Data */
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#define BITM_PORT_DATA_PX9 (_ADI_MSK(0x00000200,uint32_t)) /* Port x Bit 9 Data */
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#define BITM_PORT_DATA_PX8 (_ADI_MSK(0x00000100,uint32_t)) /* Port x Bit 8 Data */
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#define BITM_PORT_DATA_PX7 (_ADI_MSK(0x00000080,uint32_t)) /* Port x Bit 7 Data */
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#define BITM_PORT_DATA_PX6 (_ADI_MSK(0x00000040,uint32_t)) /* Port x Bit 6 Data */
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|
#define BITM_PORT_DATA_PX5 (_ADI_MSK(0x00000020,uint32_t)) /* Port x Bit 5 Data */
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#define BITM_PORT_DATA_PX4 (_ADI_MSK(0x00000010,uint32_t)) /* Port x Bit 4 Data */
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#define BITM_PORT_DATA_PX3 (_ADI_MSK(0x00000008,uint32_t)) /* Port x Bit 3 Data */
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|
#define BITM_PORT_DATA_PX2 (_ADI_MSK(0x00000004,uint32_t)) /* Port x Bit 2 Data */
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|
#define BITM_PORT_DATA_PX1 (_ADI_MSK(0x00000002,uint32_t)) /* Port x Bit 1 Data */
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#define BITM_PORT_DATA_PX0 (_ADI_MSK(0x00000001,uint32_t)) /* Port x Bit 0 Data */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PORT_DATA_SET Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PORT_DATA_SET_PX15 15 /* Port x Bit 15 Data Set */
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#define BITP_PORT_DATA_SET_PX14 14 /* Port x Bit 14 Data Set */
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|
#define BITP_PORT_DATA_SET_PX13 13 /* Port x Bit 13 Data Set */
|
|
#define BITP_PORT_DATA_SET_PX12 12 /* Port x Bit 12 Data Set */
|
|
#define BITP_PORT_DATA_SET_PX11 11 /* Port x Bit 11 Data Set */
|
|
#define BITP_PORT_DATA_SET_PX10 10 /* Port x Bit 10 Data Set */
|
|
#define BITP_PORT_DATA_SET_PX9 9 /* Port x Bit 9 Data Set */
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#define BITP_PORT_DATA_SET_PX8 8 /* Port x Bit 8 Data Set */
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|
#define BITP_PORT_DATA_SET_PX7 7 /* Port x Bit 7 Data Set */
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#define BITP_PORT_DATA_SET_PX6 6 /* Port x Bit 6 Data Set */
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#define BITP_PORT_DATA_SET_PX5 5 /* Port x Bit 5 Data Set */
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|
#define BITP_PORT_DATA_SET_PX4 4 /* Port x Bit 4 Data Set */
|
|
#define BITP_PORT_DATA_SET_PX3 3 /* Port x Bit 3 Data Set */
|
|
#define BITP_PORT_DATA_SET_PX2 2 /* Port x Bit 2 Data Set */
|
|
#define BITP_PORT_DATA_SET_PX1 1 /* Port x Bit 1 Data Set */
|
|
#define BITP_PORT_DATA_SET_PX0 0 /* Port x Bit 0 Data Set */
|
|
#define BITM_PORT_DATA_SET_PX15 (_ADI_MSK(0x00008000,uint32_t)) /* Port x Bit 15 Data Set */
|
|
#define BITM_PORT_DATA_SET_PX14 (_ADI_MSK(0x00004000,uint32_t)) /* Port x Bit 14 Data Set */
|
|
#define BITM_PORT_DATA_SET_PX13 (_ADI_MSK(0x00002000,uint32_t)) /* Port x Bit 13 Data Set */
|
|
#define BITM_PORT_DATA_SET_PX12 (_ADI_MSK(0x00001000,uint32_t)) /* Port x Bit 12 Data Set */
|
|
#define BITM_PORT_DATA_SET_PX11 (_ADI_MSK(0x00000800,uint32_t)) /* Port x Bit 11 Data Set */
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|
#define BITM_PORT_DATA_SET_PX10 (_ADI_MSK(0x00000400,uint32_t)) /* Port x Bit 10 Data Set */
|
|
#define BITM_PORT_DATA_SET_PX9 (_ADI_MSK(0x00000200,uint32_t)) /* Port x Bit 9 Data Set */
|
|
#define BITM_PORT_DATA_SET_PX8 (_ADI_MSK(0x00000100,uint32_t)) /* Port x Bit 8 Data Set */
|
|
#define BITM_PORT_DATA_SET_PX7 (_ADI_MSK(0x00000080,uint32_t)) /* Port x Bit 7 Data Set */
|
|
#define BITM_PORT_DATA_SET_PX6 (_ADI_MSK(0x00000040,uint32_t)) /* Port x Bit 6 Data Set */
|
|
#define BITM_PORT_DATA_SET_PX5 (_ADI_MSK(0x00000020,uint32_t)) /* Port x Bit 5 Data Set */
|
|
#define BITM_PORT_DATA_SET_PX4 (_ADI_MSK(0x00000010,uint32_t)) /* Port x Bit 4 Data Set */
|
|
#define BITM_PORT_DATA_SET_PX3 (_ADI_MSK(0x00000008,uint32_t)) /* Port x Bit 3 Data Set */
|
|
#define BITM_PORT_DATA_SET_PX2 (_ADI_MSK(0x00000004,uint32_t)) /* Port x Bit 2 Data Set */
|
|
#define BITM_PORT_DATA_SET_PX1 (_ADI_MSK(0x00000002,uint32_t)) /* Port x Bit 1 Data Set */
|
|
#define BITM_PORT_DATA_SET_PX0 (_ADI_MSK(0x00000001,uint32_t)) /* Port x Bit 0 Data Set */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PORT_DATA_CLR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PORT_DATA_CLR_PX15 15 /* Port x Bit 15 Data Clear */
|
|
#define BITP_PORT_DATA_CLR_PX14 14 /* Port x Bit 14 Data Clear */
|
|
#define BITP_PORT_DATA_CLR_PX13 13 /* Port x Bit 13 Data Clear */
|
|
#define BITP_PORT_DATA_CLR_PX12 12 /* Port x Bit 12 Data Clear */
|
|
#define BITP_PORT_DATA_CLR_PX11 11 /* Port x Bit 11 Data Clear */
|
|
#define BITP_PORT_DATA_CLR_PX10 10 /* Port x Bit 10 Data Clear */
|
|
#define BITP_PORT_DATA_CLR_PX9 9 /* Port x Bit 9 Data Clear */
|
|
#define BITP_PORT_DATA_CLR_PX8 8 /* Port x Bit 8 Data Clear */
|
|
#define BITP_PORT_DATA_CLR_PX7 7 /* Port x Bit 7 Data Clear */
|
|
#define BITP_PORT_DATA_CLR_PX6 6 /* Port x Bit 6 Data Clear */
|
|
#define BITP_PORT_DATA_CLR_PX5 5 /* Port x Bit 5 Data Clear */
|
|
#define BITP_PORT_DATA_CLR_PX4 4 /* Port x Bit 4 Data Clear */
|
|
#define BITP_PORT_DATA_CLR_PX3 3 /* Port x Bit 3 Data Clear */
|
|
#define BITP_PORT_DATA_CLR_PX2 2 /* Port x Bit 2 Data Clear */
|
|
#define BITP_PORT_DATA_CLR_PX1 1 /* Port x Bit 1 Data Clear */
|
|
#define BITP_PORT_DATA_CLR_PX0 0 /* Port x Bit 0 Data Clear */
|
|
#define BITM_PORT_DATA_CLR_PX15 (_ADI_MSK(0x00008000,uint32_t)) /* Port x Bit 15 Data Clear */
|
|
#define BITM_PORT_DATA_CLR_PX14 (_ADI_MSK(0x00004000,uint32_t)) /* Port x Bit 14 Data Clear */
|
|
#define BITM_PORT_DATA_CLR_PX13 (_ADI_MSK(0x00002000,uint32_t)) /* Port x Bit 13 Data Clear */
|
|
#define BITM_PORT_DATA_CLR_PX12 (_ADI_MSK(0x00001000,uint32_t)) /* Port x Bit 12 Data Clear */
|
|
#define BITM_PORT_DATA_CLR_PX11 (_ADI_MSK(0x00000800,uint32_t)) /* Port x Bit 11 Data Clear */
|
|
#define BITM_PORT_DATA_CLR_PX10 (_ADI_MSK(0x00000400,uint32_t)) /* Port x Bit 10 Data Clear */
|
|
#define BITM_PORT_DATA_CLR_PX9 (_ADI_MSK(0x00000200,uint32_t)) /* Port x Bit 9 Data Clear */
|
|
#define BITM_PORT_DATA_CLR_PX8 (_ADI_MSK(0x00000100,uint32_t)) /* Port x Bit 8 Data Clear */
|
|
#define BITM_PORT_DATA_CLR_PX7 (_ADI_MSK(0x00000080,uint32_t)) /* Port x Bit 7 Data Clear */
|
|
#define BITM_PORT_DATA_CLR_PX6 (_ADI_MSK(0x00000040,uint32_t)) /* Port x Bit 6 Data Clear */
|
|
#define BITM_PORT_DATA_CLR_PX5 (_ADI_MSK(0x00000020,uint32_t)) /* Port x Bit 5 Data Clear */
|
|
#define BITM_PORT_DATA_CLR_PX4 (_ADI_MSK(0x00000010,uint32_t)) /* Port x Bit 4 Data Clear */
|
|
#define BITM_PORT_DATA_CLR_PX3 (_ADI_MSK(0x00000008,uint32_t)) /* Port x Bit 3 Data Clear */
|
|
#define BITM_PORT_DATA_CLR_PX2 (_ADI_MSK(0x00000004,uint32_t)) /* Port x Bit 2 Data Clear */
|
|
#define BITM_PORT_DATA_CLR_PX1 (_ADI_MSK(0x00000002,uint32_t)) /* Port x Bit 1 Data Clear */
|
|
#define BITM_PORT_DATA_CLR_PX0 (_ADI_MSK(0x00000001,uint32_t)) /* Port x Bit 0 Data Clear */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PORT_DIR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PORT_DIR_PX15 15 /* Port x Bit 15 Direction */
|
|
#define BITP_PORT_DIR_PX14 14 /* Port x Bit 14 Direction */
|
|
#define BITP_PORT_DIR_PX13 13 /* Port x Bit 13 Direction */
|
|
#define BITP_PORT_DIR_PX12 12 /* Port x Bit 12 Direction */
|
|
#define BITP_PORT_DIR_PX11 11 /* Port x Bit 11 Direction */
|
|
#define BITP_PORT_DIR_PX10 10 /* Port x Bit 10 Direction */
|
|
#define BITP_PORT_DIR_PX9 9 /* Port x Bit 9 Direction */
|
|
#define BITP_PORT_DIR_PX8 8 /* Port x Bit 8 Direction */
|
|
#define BITP_PORT_DIR_PX7 7 /* Port x Bit 7 Direction */
|
|
#define BITP_PORT_DIR_PX6 6 /* Port x Bit 6 Direction */
|
|
#define BITP_PORT_DIR_PX5 5 /* Port x Bit 5 Direction */
|
|
#define BITP_PORT_DIR_PX4 4 /* Port x Bit 4 Direction */
|
|
#define BITP_PORT_DIR_PX3 3 /* Port x Bit 3 Direction */
|
|
#define BITP_PORT_DIR_PX2 2 /* Port x Bit 2 Direction */
|
|
#define BITP_PORT_DIR_PX1 1 /* Port x Bit 1 Direction */
|
|
#define BITP_PORT_DIR_PX0 0 /* Port x Bit 0 Direction */
|
|
#define BITM_PORT_DIR_PX15 (_ADI_MSK(0x00008000,uint32_t)) /* Port x Bit 15 Direction */
|
|
#define BITM_PORT_DIR_PX14 (_ADI_MSK(0x00004000,uint32_t)) /* Port x Bit 14 Direction */
|
|
#define BITM_PORT_DIR_PX13 (_ADI_MSK(0x00002000,uint32_t)) /* Port x Bit 13 Direction */
|
|
#define BITM_PORT_DIR_PX12 (_ADI_MSK(0x00001000,uint32_t)) /* Port x Bit 12 Direction */
|
|
#define BITM_PORT_DIR_PX11 (_ADI_MSK(0x00000800,uint32_t)) /* Port x Bit 11 Direction */
|
|
#define BITM_PORT_DIR_PX10 (_ADI_MSK(0x00000400,uint32_t)) /* Port x Bit 10 Direction */
|
|
#define BITM_PORT_DIR_PX9 (_ADI_MSK(0x00000200,uint32_t)) /* Port x Bit 9 Direction */
|
|
#define BITM_PORT_DIR_PX8 (_ADI_MSK(0x00000100,uint32_t)) /* Port x Bit 8 Direction */
|
|
#define BITM_PORT_DIR_PX7 (_ADI_MSK(0x00000080,uint32_t)) /* Port x Bit 7 Direction */
|
|
#define BITM_PORT_DIR_PX6 (_ADI_MSK(0x00000040,uint32_t)) /* Port x Bit 6 Direction */
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|
#define BITM_PORT_DIR_PX5 (_ADI_MSK(0x00000020,uint32_t)) /* Port x Bit 5 Direction */
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#define BITM_PORT_DIR_PX4 (_ADI_MSK(0x00000010,uint32_t)) /* Port x Bit 4 Direction */
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#define BITM_PORT_DIR_PX3 (_ADI_MSK(0x00000008,uint32_t)) /* Port x Bit 3 Direction */
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#define BITM_PORT_DIR_PX2 (_ADI_MSK(0x00000004,uint32_t)) /* Port x Bit 2 Direction */
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#define BITM_PORT_DIR_PX1 (_ADI_MSK(0x00000002,uint32_t)) /* Port x Bit 1 Direction */
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#define BITM_PORT_DIR_PX0 (_ADI_MSK(0x00000001,uint32_t)) /* Port x Bit 0 Direction */
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|
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
PORT_DIR_SET Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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|
#define BITP_PORT_DIR_SET_PX15 15 /* Port x Bit 15 Direction Set */
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#define BITP_PORT_DIR_SET_PX14 14 /* Port x Bit 14 Direction Set */
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#define BITP_PORT_DIR_SET_PX13 13 /* Port x Bit 13 Direction Set */
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#define BITP_PORT_DIR_SET_PX12 12 /* Port x Bit 12 Direction Set */
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#define BITP_PORT_DIR_SET_PX11 11 /* Port x Bit 11 Direction Set */
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#define BITP_PORT_DIR_SET_PX10 10 /* Port x Bit 10 Direction Set */
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#define BITP_PORT_DIR_SET_PX9 9 /* Port x Bit 9 Direction Set */
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#define BITP_PORT_DIR_SET_PX8 8 /* Port x Bit 8 Direction Set */
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#define BITP_PORT_DIR_SET_PX7 7 /* Port x Bit 7 Direction Set */
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#define BITP_PORT_DIR_SET_PX6 6 /* Port x Bit 6 Direction Set */
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#define BITP_PORT_DIR_SET_PX5 5 /* Port x Bit 5 Direction Set */
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#define BITP_PORT_DIR_SET_PX4 4 /* Port x Bit 4 Direction Set */
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#define BITP_PORT_DIR_SET_PX3 3 /* Port x Bit 3 Direction Set */
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#define BITP_PORT_DIR_SET_PX2 2 /* Port x Bit 2 Direction Set */
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#define BITP_PORT_DIR_SET_PX1 1 /* Port x Bit 1 Direction Set */
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#define BITP_PORT_DIR_SET_PX0 0 /* Port x Bit 0 Direction Set */
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#define BITM_PORT_DIR_SET_PX15 (_ADI_MSK(0x00008000,uint32_t)) /* Port x Bit 15 Direction Set */
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#define BITM_PORT_DIR_SET_PX14 (_ADI_MSK(0x00004000,uint32_t)) /* Port x Bit 14 Direction Set */
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#define BITM_PORT_DIR_SET_PX13 (_ADI_MSK(0x00002000,uint32_t)) /* Port x Bit 13 Direction Set */
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#define BITM_PORT_DIR_SET_PX12 (_ADI_MSK(0x00001000,uint32_t)) /* Port x Bit 12 Direction Set */
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#define BITM_PORT_DIR_SET_PX11 (_ADI_MSK(0x00000800,uint32_t)) /* Port x Bit 11 Direction Set */
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#define BITM_PORT_DIR_SET_PX10 (_ADI_MSK(0x00000400,uint32_t)) /* Port x Bit 10 Direction Set */
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#define BITM_PORT_DIR_SET_PX9 (_ADI_MSK(0x00000200,uint32_t)) /* Port x Bit 9 Direction Set */
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#define BITM_PORT_DIR_SET_PX8 (_ADI_MSK(0x00000100,uint32_t)) /* Port x Bit 8 Direction Set */
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#define BITM_PORT_DIR_SET_PX7 (_ADI_MSK(0x00000080,uint32_t)) /* Port x Bit 7 Direction Set */
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#define BITM_PORT_DIR_SET_PX6 (_ADI_MSK(0x00000040,uint32_t)) /* Port x Bit 6 Direction Set */
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#define BITM_PORT_DIR_SET_PX5 (_ADI_MSK(0x00000020,uint32_t)) /* Port x Bit 5 Direction Set */
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#define BITM_PORT_DIR_SET_PX4 (_ADI_MSK(0x00000010,uint32_t)) /* Port x Bit 4 Direction Set */
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#define BITM_PORT_DIR_SET_PX3 (_ADI_MSK(0x00000008,uint32_t)) /* Port x Bit 3 Direction Set */
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#define BITM_PORT_DIR_SET_PX2 (_ADI_MSK(0x00000004,uint32_t)) /* Port x Bit 2 Direction Set */
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#define BITM_PORT_DIR_SET_PX1 (_ADI_MSK(0x00000002,uint32_t)) /* Port x Bit 1 Direction Set */
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#define BITM_PORT_DIR_SET_PX0 (_ADI_MSK(0x00000001,uint32_t)) /* Port x Bit 0 Direction Set */
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|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PORT_DIR_CLR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PORT_DIR_CLR_PX15 15 /* Port x Bit 15 Direction Clear */
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#define BITP_PORT_DIR_CLR_PX14 14 /* Port x Bit 14 Direction Clear */
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#define BITP_PORT_DIR_CLR_PX13 13 /* Port x Bit 13 Direction Clear */
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#define BITP_PORT_DIR_CLR_PX12 12 /* Port x Bit 12 Direction Clear */
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#define BITP_PORT_DIR_CLR_PX11 11 /* Port x Bit 11 Direction Clear */
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#define BITP_PORT_DIR_CLR_PX10 10 /* Port x Bit 10 Direction Clear */
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#define BITP_PORT_DIR_CLR_PX9 9 /* Port x Bit 9 Direction Clear */
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#define BITP_PORT_DIR_CLR_PX8 8 /* Port x Bit 8 Direction Clear */
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#define BITP_PORT_DIR_CLR_PX7 7 /* Port x Bit 7 Direction Clear */
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#define BITP_PORT_DIR_CLR_PX6 6 /* Port x Bit 6 Direction Clear */
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#define BITP_PORT_DIR_CLR_PX5 5 /* Port x Bit 5 Direction Clear */
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#define BITP_PORT_DIR_CLR_PX4 4 /* Port x Bit 4 Direction Clear */
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#define BITP_PORT_DIR_CLR_PX3 3 /* Port x Bit 3 Direction Clear */
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#define BITP_PORT_DIR_CLR_PX2 2 /* Port x Bit 2 Direction Clear */
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#define BITP_PORT_DIR_CLR_PX1 1 /* Port x Bit 1 Direction Clear */
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#define BITP_PORT_DIR_CLR_PX0 0 /* Port x Bit 0 Direction Clear */
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|
#define BITM_PORT_DIR_CLR_PX15 (_ADI_MSK(0x00008000,uint32_t)) /* Port x Bit 15 Direction Clear */
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|
#define BITM_PORT_DIR_CLR_PX14 (_ADI_MSK(0x00004000,uint32_t)) /* Port x Bit 14 Direction Clear */
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|
#define BITM_PORT_DIR_CLR_PX13 (_ADI_MSK(0x00002000,uint32_t)) /* Port x Bit 13 Direction Clear */
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|
#define BITM_PORT_DIR_CLR_PX12 (_ADI_MSK(0x00001000,uint32_t)) /* Port x Bit 12 Direction Clear */
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|
#define BITM_PORT_DIR_CLR_PX11 (_ADI_MSK(0x00000800,uint32_t)) /* Port x Bit 11 Direction Clear */
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|
#define BITM_PORT_DIR_CLR_PX10 (_ADI_MSK(0x00000400,uint32_t)) /* Port x Bit 10 Direction Clear */
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|
#define BITM_PORT_DIR_CLR_PX9 (_ADI_MSK(0x00000200,uint32_t)) /* Port x Bit 9 Direction Clear */
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|
#define BITM_PORT_DIR_CLR_PX8 (_ADI_MSK(0x00000100,uint32_t)) /* Port x Bit 8 Direction Clear */
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|
#define BITM_PORT_DIR_CLR_PX7 (_ADI_MSK(0x00000080,uint32_t)) /* Port x Bit 7 Direction Clear */
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|
#define BITM_PORT_DIR_CLR_PX6 (_ADI_MSK(0x00000040,uint32_t)) /* Port x Bit 6 Direction Clear */
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|
#define BITM_PORT_DIR_CLR_PX5 (_ADI_MSK(0x00000020,uint32_t)) /* Port x Bit 5 Direction Clear */
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|
#define BITM_PORT_DIR_CLR_PX4 (_ADI_MSK(0x00000010,uint32_t)) /* Port x Bit 4 Direction Clear */
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|
#define BITM_PORT_DIR_CLR_PX3 (_ADI_MSK(0x00000008,uint32_t)) /* Port x Bit 3 Direction Clear */
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#define BITM_PORT_DIR_CLR_PX2 (_ADI_MSK(0x00000004,uint32_t)) /* Port x Bit 2 Direction Clear */
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|
#define BITM_PORT_DIR_CLR_PX1 (_ADI_MSK(0x00000002,uint32_t)) /* Port x Bit 1 Direction Clear */
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|
#define BITM_PORT_DIR_CLR_PX0 (_ADI_MSK(0x00000001,uint32_t)) /* Port x Bit 0 Direction Clear */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PORT_INEN Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PORT_INEN_PX15 15 /* Port x Bit 15 Input Enable */
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|
#define BITP_PORT_INEN_PX14 14 /* Port x Bit 14 Input Enable */
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|
#define BITP_PORT_INEN_PX13 13 /* Port x Bit 13 Input Enable */
|
|
#define BITP_PORT_INEN_PX12 12 /* Port x Bit 12 Input Enable */
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|
#define BITP_PORT_INEN_PX11 11 /* Port x Bit 11 Input Enable */
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|
#define BITP_PORT_INEN_PX10 10 /* Port x Bit 10 Input Enable */
|
|
#define BITP_PORT_INEN_PX9 9 /* Port x Bit 9 Input Enable */
|
|
#define BITP_PORT_INEN_PX8 8 /* Port x Bit 8 Input Enable */
|
|
#define BITP_PORT_INEN_PX7 7 /* Port x Bit 7 Input Enable */
|
|
#define BITP_PORT_INEN_PX6 6 /* Port x Bit 6 Input Enable */
|
|
#define BITP_PORT_INEN_PX5 5 /* Port x Bit 5 Input Enable */
|
|
#define BITP_PORT_INEN_PX4 4 /* Port x Bit 4 Input Enable */
|
|
#define BITP_PORT_INEN_PX3 3 /* Port x Bit 3 Input Enable */
|
|
#define BITP_PORT_INEN_PX2 2 /* Port x Bit 2 Input Enable */
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|
#define BITP_PORT_INEN_PX1 1 /* Port x Bit 1 Input Enable */
|
|
#define BITP_PORT_INEN_PX0 0 /* Port x Bit 0 Input Enable */
|
|
#define BITM_PORT_INEN_PX15 (_ADI_MSK(0x00008000,uint32_t)) /* Port x Bit 15 Input Enable */
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|
#define BITM_PORT_INEN_PX14 (_ADI_MSK(0x00004000,uint32_t)) /* Port x Bit 14 Input Enable */
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|
#define BITM_PORT_INEN_PX13 (_ADI_MSK(0x00002000,uint32_t)) /* Port x Bit 13 Input Enable */
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|
#define BITM_PORT_INEN_PX12 (_ADI_MSK(0x00001000,uint32_t)) /* Port x Bit 12 Input Enable */
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|
#define BITM_PORT_INEN_PX11 (_ADI_MSK(0x00000800,uint32_t)) /* Port x Bit 11 Input Enable */
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|
#define BITM_PORT_INEN_PX10 (_ADI_MSK(0x00000400,uint32_t)) /* Port x Bit 10 Input Enable */
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|
#define BITM_PORT_INEN_PX9 (_ADI_MSK(0x00000200,uint32_t)) /* Port x Bit 9 Input Enable */
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|
#define BITM_PORT_INEN_PX8 (_ADI_MSK(0x00000100,uint32_t)) /* Port x Bit 8 Input Enable */
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|
#define BITM_PORT_INEN_PX7 (_ADI_MSK(0x00000080,uint32_t)) /* Port x Bit 7 Input Enable */
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#define BITM_PORT_INEN_PX6 (_ADI_MSK(0x00000040,uint32_t)) /* Port x Bit 6 Input Enable */
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#define BITM_PORT_INEN_PX5 (_ADI_MSK(0x00000020,uint32_t)) /* Port x Bit 5 Input Enable */
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|
#define BITM_PORT_INEN_PX4 (_ADI_MSK(0x00000010,uint32_t)) /* Port x Bit 4 Input Enable */
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|
#define BITM_PORT_INEN_PX3 (_ADI_MSK(0x00000008,uint32_t)) /* Port x Bit 3 Input Enable */
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#define BITM_PORT_INEN_PX2 (_ADI_MSK(0x00000004,uint32_t)) /* Port x Bit 2 Input Enable */
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|
#define BITM_PORT_INEN_PX1 (_ADI_MSK(0x00000002,uint32_t)) /* Port x Bit 1 Input Enable */
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#define BITM_PORT_INEN_PX0 (_ADI_MSK(0x00000001,uint32_t)) /* Port x Bit 0 Input Enable */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PORT_INEN_SET Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PORT_INEN_SET_PX15 15 /* Port x Bit 15 Input Enable Set */
|
|
#define BITP_PORT_INEN_SET_PX14 14 /* Port x Bit 14 Input Enable Set */
|
|
#define BITP_PORT_INEN_SET_PX13 13 /* Port x Bit 13 Input Enable Set */
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|
#define BITP_PORT_INEN_SET_PX12 12 /* Port x Bit 12 Input Enable Set */
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|
#define BITP_PORT_INEN_SET_PX11 11 /* Port x Bit 11 Input Enable Set */
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#define BITP_PORT_INEN_SET_PX10 10 /* Port x Bit 10 Input Enable Set */
|
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#define BITP_PORT_INEN_SET_PX9 9 /* Port x Bit 9 Input Enable Set */
|
|
#define BITP_PORT_INEN_SET_PX8 8 /* Port x Bit 8 Input Enable Set */
|
|
#define BITP_PORT_INEN_SET_PX7 7 /* Port x Bit 7 Input Enable Set */
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#define BITP_PORT_INEN_SET_PX6 6 /* Port x Bit 6 Input Enable Set */
|
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#define BITP_PORT_INEN_SET_PX5 5 /* Port x Bit 5 Input Enable Set */
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|
#define BITP_PORT_INEN_SET_PX4 4 /* Port x Bit 4 Input Enable Set */
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|
#define BITP_PORT_INEN_SET_PX3 3 /* Port x Bit 3 Input Enable Set */
|
|
#define BITP_PORT_INEN_SET_PX2 2 /* Port x Bit 2 Input Enable Set */
|
|
#define BITP_PORT_INEN_SET_PX1 1 /* Port x Bit 1 Input Enable Set */
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|
#define BITP_PORT_INEN_SET_PX0 0 /* Port x Bit 0 Input Enable Set */
|
|
#define BITM_PORT_INEN_SET_PX15 (_ADI_MSK(0x00008000,uint32_t)) /* Port x Bit 15 Input Enable Set */
|
|
#define BITM_PORT_INEN_SET_PX14 (_ADI_MSK(0x00004000,uint32_t)) /* Port x Bit 14 Input Enable Set */
|
|
#define BITM_PORT_INEN_SET_PX13 (_ADI_MSK(0x00002000,uint32_t)) /* Port x Bit 13 Input Enable Set */
|
|
#define BITM_PORT_INEN_SET_PX12 (_ADI_MSK(0x00001000,uint32_t)) /* Port x Bit 12 Input Enable Set */
|
|
#define BITM_PORT_INEN_SET_PX11 (_ADI_MSK(0x00000800,uint32_t)) /* Port x Bit 11 Input Enable Set */
|
|
#define BITM_PORT_INEN_SET_PX10 (_ADI_MSK(0x00000400,uint32_t)) /* Port x Bit 10 Input Enable Set */
|
|
#define BITM_PORT_INEN_SET_PX9 (_ADI_MSK(0x00000200,uint32_t)) /* Port x Bit 9 Input Enable Set */
|
|
#define BITM_PORT_INEN_SET_PX8 (_ADI_MSK(0x00000100,uint32_t)) /* Port x Bit 8 Input Enable Set */
|
|
#define BITM_PORT_INEN_SET_PX7 (_ADI_MSK(0x00000080,uint32_t)) /* Port x Bit 7 Input Enable Set */
|
|
#define BITM_PORT_INEN_SET_PX6 (_ADI_MSK(0x00000040,uint32_t)) /* Port x Bit 6 Input Enable Set */
|
|
#define BITM_PORT_INEN_SET_PX5 (_ADI_MSK(0x00000020,uint32_t)) /* Port x Bit 5 Input Enable Set */
|
|
#define BITM_PORT_INEN_SET_PX4 (_ADI_MSK(0x00000010,uint32_t)) /* Port x Bit 4 Input Enable Set */
|
|
#define BITM_PORT_INEN_SET_PX3 (_ADI_MSK(0x00000008,uint32_t)) /* Port x Bit 3 Input Enable Set */
|
|
#define BITM_PORT_INEN_SET_PX2 (_ADI_MSK(0x00000004,uint32_t)) /* Port x Bit 2 Input Enable Set */
|
|
#define BITM_PORT_INEN_SET_PX1 (_ADI_MSK(0x00000002,uint32_t)) /* Port x Bit 1 Input Enable Set */
|
|
#define BITM_PORT_INEN_SET_PX0 (_ADI_MSK(0x00000001,uint32_t)) /* Port x Bit 0 Input Enable Set */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PORT_INEN_CLR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PORT_INEN_CLR_PX15 15 /* Port x Bit 15 Input Enable Clear */
|
|
#define BITP_PORT_INEN_CLR_PX14 14 /* Port x Bit 14 Input Enable Clear */
|
|
#define BITP_PORT_INEN_CLR_PX13 13 /* Port x Bit 13 Input Enable Clear */
|
|
#define BITP_PORT_INEN_CLR_PX12 12 /* Port x Bit 12 Input Enable Clear */
|
|
#define BITP_PORT_INEN_CLR_PX11 11 /* Port x Bit 11 Input Enable Clear */
|
|
#define BITP_PORT_INEN_CLR_PX10 10 /* Port x Bit 10 Input Enable Clear */
|
|
#define BITP_PORT_INEN_CLR_PX9 9 /* Port x Bit 9 Input Enable Clear */
|
|
#define BITP_PORT_INEN_CLR_PX8 8 /* Port x Bit 8 Input Enable Clear */
|
|
#define BITP_PORT_INEN_CLR_PX7 7 /* Port x Bit 7 Input Enable Clear */
|
|
#define BITP_PORT_INEN_CLR_PX6 6 /* Port x Bit 6 Input Enable Clear */
|
|
#define BITP_PORT_INEN_CLR_PX5 5 /* Port x Bit 5 Input Enable Clear */
|
|
#define BITP_PORT_INEN_CLR_PX4 4 /* Port x Bit 4 Input Enable Clear */
|
|
#define BITP_PORT_INEN_CLR_PX3 3 /* Port x Bit 3 Input Enable Clear */
|
|
#define BITP_PORT_INEN_CLR_PX2 2 /* Port x Bit 2 Input Enable Clear */
|
|
#define BITP_PORT_INEN_CLR_PX1 1 /* Port x Bit 1 Input Enable Clear */
|
|
#define BITP_PORT_INEN_CLR_PX0 0 /* Port x Bit 0 Input Enable Clear */
|
|
#define BITM_PORT_INEN_CLR_PX15 (_ADI_MSK(0x00008000,uint32_t)) /* Port x Bit 15 Input Enable Clear */
|
|
#define BITM_PORT_INEN_CLR_PX14 (_ADI_MSK(0x00004000,uint32_t)) /* Port x Bit 14 Input Enable Clear */
|
|
#define BITM_PORT_INEN_CLR_PX13 (_ADI_MSK(0x00002000,uint32_t)) /* Port x Bit 13 Input Enable Clear */
|
|
#define BITM_PORT_INEN_CLR_PX12 (_ADI_MSK(0x00001000,uint32_t)) /* Port x Bit 12 Input Enable Clear */
|
|
#define BITM_PORT_INEN_CLR_PX11 (_ADI_MSK(0x00000800,uint32_t)) /* Port x Bit 11 Input Enable Clear */
|
|
#define BITM_PORT_INEN_CLR_PX10 (_ADI_MSK(0x00000400,uint32_t)) /* Port x Bit 10 Input Enable Clear */
|
|
#define BITM_PORT_INEN_CLR_PX9 (_ADI_MSK(0x00000200,uint32_t)) /* Port x Bit 9 Input Enable Clear */
|
|
#define BITM_PORT_INEN_CLR_PX8 (_ADI_MSK(0x00000100,uint32_t)) /* Port x Bit 8 Input Enable Clear */
|
|
#define BITM_PORT_INEN_CLR_PX7 (_ADI_MSK(0x00000080,uint32_t)) /* Port x Bit 7 Input Enable Clear */
|
|
#define BITM_PORT_INEN_CLR_PX6 (_ADI_MSK(0x00000040,uint32_t)) /* Port x Bit 6 Input Enable Clear */
|
|
#define BITM_PORT_INEN_CLR_PX5 (_ADI_MSK(0x00000020,uint32_t)) /* Port x Bit 5 Input Enable Clear */
|
|
#define BITM_PORT_INEN_CLR_PX4 (_ADI_MSK(0x00000010,uint32_t)) /* Port x Bit 4 Input Enable Clear */
|
|
#define BITM_PORT_INEN_CLR_PX3 (_ADI_MSK(0x00000008,uint32_t)) /* Port x Bit 3 Input Enable Clear */
|
|
#define BITM_PORT_INEN_CLR_PX2 (_ADI_MSK(0x00000004,uint32_t)) /* Port x Bit 2 Input Enable Clear */
|
|
#define BITM_PORT_INEN_CLR_PX1 (_ADI_MSK(0x00000002,uint32_t)) /* Port x Bit 1 Input Enable Clear */
|
|
#define BITM_PORT_INEN_CLR_PX0 (_ADI_MSK(0x00000001,uint32_t)) /* Port x Bit 0 Input Enable Clear */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PORT_MUX Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PORT_MUX_MUX15 30 /* Mux for Port x Bit 15 */
|
|
#define BITP_PORT_MUX_MUX14 28 /* Mux for Port x Bit 14 */
|
|
#define BITP_PORT_MUX_MUX13 26 /* Mux for Port x Bit 13 */
|
|
#define BITP_PORT_MUX_MUX12 24 /* Mux for Port x Bit 12 */
|
|
#define BITP_PORT_MUX_MUX11 22 /* Mux for Port x Bit 11 */
|
|
#define BITP_PORT_MUX_MUX10 20 /* Mux for Port x Bit 10 */
|
|
#define BITP_PORT_MUX_MUX9 18 /* Mux for Port x Bit 9 */
|
|
#define BITP_PORT_MUX_MUX8 16 /* Mux for Port x Bit 8 */
|
|
#define BITP_PORT_MUX_MUX7 14 /* Mux for Port x Bit 7 */
|
|
#define BITP_PORT_MUX_MUX6 12 /* Mux for Port x Bit 6 */
|
|
#define BITP_PORT_MUX_MUX5 10 /* Mux for Port x Bit 5 */
|
|
#define BITP_PORT_MUX_MUX4 8 /* Mux for Port x Bit 4 */
|
|
#define BITP_PORT_MUX_MUX3 6 /* Mux for Port x Bit 3 */
|
|
#define BITP_PORT_MUX_MUX2 4 /* Mux for Port x Bit 2 */
|
|
#define BITP_PORT_MUX_MUX1 2 /* Mux for Port x Bit 1 */
|
|
#define BITP_PORT_MUX_MUX0 0 /* Mux for Port x Bit 0 */
|
|
#define BITM_PORT_MUX_MUX15 (_ADI_MSK(0xC0000000,uint32_t)) /* Mux for Port x Bit 15 */
|
|
#define BITM_PORT_MUX_MUX14 (_ADI_MSK(0x30000000,uint32_t)) /* Mux for Port x Bit 14 */
|
|
#define BITM_PORT_MUX_MUX13 (_ADI_MSK(0x0C000000,uint32_t)) /* Mux for Port x Bit 13 */
|
|
#define BITM_PORT_MUX_MUX12 (_ADI_MSK(0x03000000,uint32_t)) /* Mux for Port x Bit 12 */
|
|
#define BITM_PORT_MUX_MUX11 (_ADI_MSK(0x00C00000,uint32_t)) /* Mux for Port x Bit 11 */
|
|
#define BITM_PORT_MUX_MUX10 (_ADI_MSK(0x00300000,uint32_t)) /* Mux for Port x Bit 10 */
|
|
#define BITM_PORT_MUX_MUX9 (_ADI_MSK(0x000C0000,uint32_t)) /* Mux for Port x Bit 9 */
|
|
#define BITM_PORT_MUX_MUX8 (_ADI_MSK(0x00030000,uint32_t)) /* Mux for Port x Bit 8 */
|
|
#define BITM_PORT_MUX_MUX7 (_ADI_MSK(0x0000C000,uint32_t)) /* Mux for Port x Bit 7 */
|
|
#define BITM_PORT_MUX_MUX6 (_ADI_MSK(0x00003000,uint32_t)) /* Mux for Port x Bit 6 */
|
|
#define BITM_PORT_MUX_MUX5 (_ADI_MSK(0x00000C00,uint32_t)) /* Mux for Port x Bit 5 */
|
|
#define BITM_PORT_MUX_MUX4 (_ADI_MSK(0x00000300,uint32_t)) /* Mux for Port x Bit 4 */
|
|
#define BITM_PORT_MUX_MUX3 (_ADI_MSK(0x000000C0,uint32_t)) /* Mux for Port x Bit 3 */
|
|
#define BITM_PORT_MUX_MUX2 (_ADI_MSK(0x00000030,uint32_t)) /* Mux for Port x Bit 2 */
|
|
#define BITM_PORT_MUX_MUX1 (_ADI_MSK(0x0000000C,uint32_t)) /* Mux for Port x Bit 1 */
|
|
#define BITM_PORT_MUX_MUX0 (_ADI_MSK(0x00000003,uint32_t)) /* Mux for Port x Bit 0 */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PORT_DATA_TGL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PORT_DATA_TGL_PX15 15 /* Port x Bit 15 Toggle */
|
|
#define BITP_PORT_DATA_TGL_PX14 14 /* Port x Bit 14 Toggle */
|
|
#define BITP_PORT_DATA_TGL_PX13 13 /* Port x Bit 13 Toggle */
|
|
#define BITP_PORT_DATA_TGL_PX12 12 /* Port x Bit 12 Toggle */
|
|
#define BITP_PORT_DATA_TGL_PX11 11 /* Port x Bit 11 Toggle */
|
|
#define BITP_PORT_DATA_TGL_PX10 10 /* Port x Bit 10 Toggle */
|
|
#define BITP_PORT_DATA_TGL_PX9 9 /* Port x Bit 9 Toggle */
|
|
#define BITP_PORT_DATA_TGL_PX8 8 /* Port x Bit 8 Toggle */
|
|
#define BITP_PORT_DATA_TGL_PX7 7 /* Port x Bit 7 Toggle */
|
|
#define BITP_PORT_DATA_TGL_PX6 6 /* Port x Bit 6 Toggle */
|
|
#define BITP_PORT_DATA_TGL_PX5 5 /* Port x Bit 5 Toggle */
|
|
#define BITP_PORT_DATA_TGL_PX4 4 /* Port x Bit 4 Toggle */
|
|
#define BITP_PORT_DATA_TGL_PX3 3 /* Port x Bit 3 Toggle */
|
|
#define BITP_PORT_DATA_TGL_PX2 2 /* Port x Bit 2 Toggle */
|
|
#define BITP_PORT_DATA_TGL_PX1 1 /* Port x Bit 1 Toggle */
|
|
#define BITP_PORT_DATA_TGL_PX0 0 /* Port x Bit 0 Toggle */
|
|
#define BITM_PORT_DATA_TGL_PX15 (_ADI_MSK(0x00008000,uint32_t)) /* Port x Bit 15 Toggle */
|
|
#define BITM_PORT_DATA_TGL_PX14 (_ADI_MSK(0x00004000,uint32_t)) /* Port x Bit 14 Toggle */
|
|
#define BITM_PORT_DATA_TGL_PX13 (_ADI_MSK(0x00002000,uint32_t)) /* Port x Bit 13 Toggle */
|
|
#define BITM_PORT_DATA_TGL_PX12 (_ADI_MSK(0x00001000,uint32_t)) /* Port x Bit 12 Toggle */
|
|
#define BITM_PORT_DATA_TGL_PX11 (_ADI_MSK(0x00000800,uint32_t)) /* Port x Bit 11 Toggle */
|
|
#define BITM_PORT_DATA_TGL_PX10 (_ADI_MSK(0x00000400,uint32_t)) /* Port x Bit 10 Toggle */
|
|
#define BITM_PORT_DATA_TGL_PX9 (_ADI_MSK(0x00000200,uint32_t)) /* Port x Bit 9 Toggle */
|
|
#define BITM_PORT_DATA_TGL_PX8 (_ADI_MSK(0x00000100,uint32_t)) /* Port x Bit 8 Toggle */
|
|
#define BITM_PORT_DATA_TGL_PX7 (_ADI_MSK(0x00000080,uint32_t)) /* Port x Bit 7 Toggle */
|
|
#define BITM_PORT_DATA_TGL_PX6 (_ADI_MSK(0x00000040,uint32_t)) /* Port x Bit 6 Toggle */
|
|
#define BITM_PORT_DATA_TGL_PX5 (_ADI_MSK(0x00000020,uint32_t)) /* Port x Bit 5 Toggle */
|
|
#define BITM_PORT_DATA_TGL_PX4 (_ADI_MSK(0x00000010,uint32_t)) /* Port x Bit 4 Toggle */
|
|
#define BITM_PORT_DATA_TGL_PX3 (_ADI_MSK(0x00000008,uint32_t)) /* Port x Bit 3 Toggle */
|
|
#define BITM_PORT_DATA_TGL_PX2 (_ADI_MSK(0x00000004,uint32_t)) /* Port x Bit 2 Toggle */
|
|
#define BITM_PORT_DATA_TGL_PX1 (_ADI_MSK(0x00000002,uint32_t)) /* Port x Bit 1 Toggle */
|
|
#define BITM_PORT_DATA_TGL_PX0 (_ADI_MSK(0x00000001,uint32_t)) /* Port x Bit 0 Toggle */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PORT_POL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PORT_POL_PX15 15 /* Port x Bit 15 Polarity Invert */
|
|
#define BITP_PORT_POL_PX14 14 /* Port x Bit 14 Polarity Invert */
|
|
#define BITP_PORT_POL_PX13 13 /* Port x Bit 13 Polarity Invert */
|
|
#define BITP_PORT_POL_PX12 12 /* Port x Bit 12 Polarity Invert */
|
|
#define BITP_PORT_POL_PX11 11 /* Port x Bit 11 Polarity Invert */
|
|
#define BITP_PORT_POL_PX10 10 /* Port x Bit 10 Polarity Invert */
|
|
#define BITP_PORT_POL_PX9 9 /* Port x Bit 9 Polarity Invert */
|
|
#define BITP_PORT_POL_PX8 8 /* Port x Bit 8 Polarity Invert */
|
|
#define BITP_PORT_POL_PX7 7 /* Port x Bit 7 Polarity Invert */
|
|
#define BITP_PORT_POL_PX6 6 /* Port x Bit 6 Polarity Invert */
|
|
#define BITP_PORT_POL_PX5 5 /* Port x Bit 5 Polarity Invert */
|
|
#define BITP_PORT_POL_PX4 4 /* Port x Bit 4 Polarity Invert */
|
|
#define BITP_PORT_POL_PX3 3 /* Port x Bit 3 Polarity Invert */
|
|
#define BITP_PORT_POL_PX2 2 /* Port x Bit 2 Polarity Invert */
|
|
#define BITP_PORT_POL_PX1 1 /* Port x Bit 1 Polarity Invert */
|
|
#define BITP_PORT_POL_PX0 0 /* Port x Bit 0 Polarity Invert */
|
|
#define BITM_PORT_POL_PX15 (_ADI_MSK(0x00008000,uint32_t)) /* Port x Bit 15 Polarity Invert */
|
|
#define BITM_PORT_POL_PX14 (_ADI_MSK(0x00004000,uint32_t)) /* Port x Bit 14 Polarity Invert */
|
|
#define BITM_PORT_POL_PX13 (_ADI_MSK(0x00002000,uint32_t)) /* Port x Bit 13 Polarity Invert */
|
|
#define BITM_PORT_POL_PX12 (_ADI_MSK(0x00001000,uint32_t)) /* Port x Bit 12 Polarity Invert */
|
|
#define BITM_PORT_POL_PX11 (_ADI_MSK(0x00000800,uint32_t)) /* Port x Bit 11 Polarity Invert */
|
|
#define BITM_PORT_POL_PX10 (_ADI_MSK(0x00000400,uint32_t)) /* Port x Bit 10 Polarity Invert */
|
|
#define BITM_PORT_POL_PX9 (_ADI_MSK(0x00000200,uint32_t)) /* Port x Bit 9 Polarity Invert */
|
|
#define BITM_PORT_POL_PX8 (_ADI_MSK(0x00000100,uint32_t)) /* Port x Bit 8 Polarity Invert */
|
|
#define BITM_PORT_POL_PX7 (_ADI_MSK(0x00000080,uint32_t)) /* Port x Bit 7 Polarity Invert */
|
|
#define BITM_PORT_POL_PX6 (_ADI_MSK(0x00000040,uint32_t)) /* Port x Bit 6 Polarity Invert */
|
|
#define BITM_PORT_POL_PX5 (_ADI_MSK(0x00000020,uint32_t)) /* Port x Bit 5 Polarity Invert */
|
|
#define BITM_PORT_POL_PX4 (_ADI_MSK(0x00000010,uint32_t)) /* Port x Bit 4 Polarity Invert */
|
|
#define BITM_PORT_POL_PX3 (_ADI_MSK(0x00000008,uint32_t)) /* Port x Bit 3 Polarity Invert */
|
|
#define BITM_PORT_POL_PX2 (_ADI_MSK(0x00000004,uint32_t)) /* Port x Bit 2 Polarity Invert */
|
|
#define BITM_PORT_POL_PX1 (_ADI_MSK(0x00000002,uint32_t)) /* Port x Bit 1 Polarity Invert */
|
|
#define BITM_PORT_POL_PX0 (_ADI_MSK(0x00000001,uint32_t)) /* Port x Bit 0 Polarity Invert */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PORT_POL_SET Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PORT_POL_SET_PX15 15 /* Port x Bit 15 Polarity Invert Set */
|
|
#define BITP_PORT_POL_SET_PX14 14 /* Port x Bit 14 Polarity Invert Set */
|
|
#define BITP_PORT_POL_SET_PX13 13 /* Port x Bit 13 Polarity Invert Set */
|
|
#define BITP_PORT_POL_SET_PX12 12 /* Port x Bit 12 Polarity Invert Set */
|
|
#define BITP_PORT_POL_SET_PX11 11 /* Port x Bit 11 Polarity Invert Set */
|
|
#define BITP_PORT_POL_SET_PX10 10 /* Port x Bit 10 Polarity Invert Set */
|
|
#define BITP_PORT_POL_SET_PX9 9 /* Port x Bit 9 Polarity Invert Set */
|
|
#define BITP_PORT_POL_SET_PX8 8 /* Port x Bit 8 Polarity Invert Set */
|
|
#define BITP_PORT_POL_SET_PX7 7 /* Port x Bit 7 Polarity Invert Set */
|
|
#define BITP_PORT_POL_SET_PX6 6 /* Port x Bit 6 Polarity Invert Set */
|
|
#define BITP_PORT_POL_SET_PX5 5 /* Port x Bit 5 Polarity Invert Set */
|
|
#define BITP_PORT_POL_SET_PX4 4 /* Port x Bit 4 Polarity Invert Set */
|
|
#define BITP_PORT_POL_SET_PX3 3 /* Port x Bit 3 Polarity Invert Set */
|
|
#define BITP_PORT_POL_SET_PX2 2 /* Port x Bit 2 Polarity Invert Set */
|
|
#define BITP_PORT_POL_SET_PX1 1 /* Port x Bit 1 Polarity Invert Set */
|
|
#define BITP_PORT_POL_SET_PX0 0 /* Port x Bit 0 Polarity Invert Set */
|
|
#define BITM_PORT_POL_SET_PX15 (_ADI_MSK(0x00008000,uint32_t)) /* Port x Bit 15 Polarity Invert Set */
|
|
#define BITM_PORT_POL_SET_PX14 (_ADI_MSK(0x00004000,uint32_t)) /* Port x Bit 14 Polarity Invert Set */
|
|
#define BITM_PORT_POL_SET_PX13 (_ADI_MSK(0x00002000,uint32_t)) /* Port x Bit 13 Polarity Invert Set */
|
|
#define BITM_PORT_POL_SET_PX12 (_ADI_MSK(0x00001000,uint32_t)) /* Port x Bit 12 Polarity Invert Set */
|
|
#define BITM_PORT_POL_SET_PX11 (_ADI_MSK(0x00000800,uint32_t)) /* Port x Bit 11 Polarity Invert Set */
|
|
#define BITM_PORT_POL_SET_PX10 (_ADI_MSK(0x00000400,uint32_t)) /* Port x Bit 10 Polarity Invert Set */
|
|
#define BITM_PORT_POL_SET_PX9 (_ADI_MSK(0x00000200,uint32_t)) /* Port x Bit 9 Polarity Invert Set */
|
|
#define BITM_PORT_POL_SET_PX8 (_ADI_MSK(0x00000100,uint32_t)) /* Port x Bit 8 Polarity Invert Set */
|
|
#define BITM_PORT_POL_SET_PX7 (_ADI_MSK(0x00000080,uint32_t)) /* Port x Bit 7 Polarity Invert Set */
|
|
#define BITM_PORT_POL_SET_PX6 (_ADI_MSK(0x00000040,uint32_t)) /* Port x Bit 6 Polarity Invert Set */
|
|
#define BITM_PORT_POL_SET_PX5 (_ADI_MSK(0x00000020,uint32_t)) /* Port x Bit 5 Polarity Invert Set */
|
|
#define BITM_PORT_POL_SET_PX4 (_ADI_MSK(0x00000010,uint32_t)) /* Port x Bit 4 Polarity Invert Set */
|
|
#define BITM_PORT_POL_SET_PX3 (_ADI_MSK(0x00000008,uint32_t)) /* Port x Bit 3 Polarity Invert Set */
|
|
#define BITM_PORT_POL_SET_PX2 (_ADI_MSK(0x00000004,uint32_t)) /* Port x Bit 2 Polarity Invert Set */
|
|
#define BITM_PORT_POL_SET_PX1 (_ADI_MSK(0x00000002,uint32_t)) /* Port x Bit 1 Polarity Invert Set */
|
|
#define BITM_PORT_POL_SET_PX0 (_ADI_MSK(0x00000001,uint32_t)) /* Port x Bit 0 Polarity Invert Set */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PORT_POL_CLR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PORT_POL_CLR_PX15 15 /* Port x Bit 15 Polarity Invert Clear */
|
|
#define BITP_PORT_POL_CLR_PX14 14 /* Port x Bit 14 Polarity Invert Clear */
|
|
#define BITP_PORT_POL_CLR_PX13 13 /* Port x Bit 13 Polarity Invert Clear */
|
|
#define BITP_PORT_POL_CLR_PX12 12 /* Port x Bit 12 Polarity Invert Clear */
|
|
#define BITP_PORT_POL_CLR_PX11 11 /* Port x Bit 11 Polarity Invert Clear */
|
|
#define BITP_PORT_POL_CLR_PX10 10 /* Port x Bit 10 Polarity Invert Clear */
|
|
#define BITP_PORT_POL_CLR_PX9 9 /* Port x Bit 9 Polarity Invert Clear */
|
|
#define BITP_PORT_POL_CLR_PX8 8 /* Port x Bit 8 Polarity Invert Clear */
|
|
#define BITP_PORT_POL_CLR_PX7 7 /* Port x Bit 7 Polarity Invert Clear */
|
|
#define BITP_PORT_POL_CLR_PX6 6 /* Port x Bit 6 Polarity Invert Clear */
|
|
#define BITP_PORT_POL_CLR_PX5 5 /* Port x Bit 5 Polarity Invert Clear */
|
|
#define BITP_PORT_POL_CLR_PX4 4 /* Port x Bit 4 Polarity Invert Clear */
|
|
#define BITP_PORT_POL_CLR_PX3 3 /* Port x Bit 3 Polarity Invert Clear */
|
|
#define BITP_PORT_POL_CLR_PX2 2 /* Port x Bit 2 Polarity Invert Clear */
|
|
#define BITP_PORT_POL_CLR_PX1 1 /* Port x Bit 1 Polarity Invert Clear */
|
|
#define BITP_PORT_POL_CLR_PX0 0 /* Port x Bit 0 Polarity Invert Clear */
|
|
#define BITM_PORT_POL_CLR_PX15 (_ADI_MSK(0x00008000,uint32_t)) /* Port x Bit 15 Polarity Invert Clear */
|
|
#define BITM_PORT_POL_CLR_PX14 (_ADI_MSK(0x00004000,uint32_t)) /* Port x Bit 14 Polarity Invert Clear */
|
|
#define BITM_PORT_POL_CLR_PX13 (_ADI_MSK(0x00002000,uint32_t)) /* Port x Bit 13 Polarity Invert Clear */
|
|
#define BITM_PORT_POL_CLR_PX12 (_ADI_MSK(0x00001000,uint32_t)) /* Port x Bit 12 Polarity Invert Clear */
|
|
#define BITM_PORT_POL_CLR_PX11 (_ADI_MSK(0x00000800,uint32_t)) /* Port x Bit 11 Polarity Invert Clear */
|
|
#define BITM_PORT_POL_CLR_PX10 (_ADI_MSK(0x00000400,uint32_t)) /* Port x Bit 10 Polarity Invert Clear */
|
|
#define BITM_PORT_POL_CLR_PX9 (_ADI_MSK(0x00000200,uint32_t)) /* Port x Bit 9 Polarity Invert Clear */
|
|
#define BITM_PORT_POL_CLR_PX8 (_ADI_MSK(0x00000100,uint32_t)) /* Port x Bit 8 Polarity Invert Clear */
|
|
#define BITM_PORT_POL_CLR_PX7 (_ADI_MSK(0x00000080,uint32_t)) /* Port x Bit 7 Polarity Invert Clear */
|
|
#define BITM_PORT_POL_CLR_PX6 (_ADI_MSK(0x00000040,uint32_t)) /* Port x Bit 6 Polarity Invert Clear */
|
|
#define BITM_PORT_POL_CLR_PX5 (_ADI_MSK(0x00000020,uint32_t)) /* Port x Bit 5 Polarity Invert Clear */
|
|
#define BITM_PORT_POL_CLR_PX4 (_ADI_MSK(0x00000010,uint32_t)) /* Port x Bit 4 Polarity Invert Clear */
|
|
#define BITM_PORT_POL_CLR_PX3 (_ADI_MSK(0x00000008,uint32_t)) /* Port x Bit 3 Polarity Invert Clear */
|
|
#define BITM_PORT_POL_CLR_PX2 (_ADI_MSK(0x00000004,uint32_t)) /* Port x Bit 2 Polarity Invert Clear */
|
|
#define BITM_PORT_POL_CLR_PX1 (_ADI_MSK(0x00000002,uint32_t)) /* Port x Bit 1 Polarity Invert Clear */
|
|
#define BITM_PORT_POL_CLR_PX0 (_ADI_MSK(0x00000001,uint32_t)) /* Port x Bit 0 Polarity Invert Clear */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PORT_LOCK Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PORT_LOCK_LOCK 31 /* Lock */
|
|
#define BITP_PORT_LOCK_POLAR 5 /* Polarity Lock */
|
|
#define BITP_PORT_LOCK_INEN 4 /* Input Enable Lock */
|
|
#define BITP_PORT_LOCK_DIR 3 /* Direction Lock */
|
|
#define BITP_PORT_LOCK_DATA 2 /* Data Lock */
|
|
#define BITP_PORT_LOCK_MUX 1 /* Function Multiplexer Lock */
|
|
#define BITP_PORT_LOCK_FER 0 /* Function Enable Lock */
|
|
#define BITM_PORT_LOCK_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
|
|
#define BITM_PORT_LOCK_POLAR (_ADI_MSK(0x00000020,uint32_t)) /* Polarity Lock */
|
|
#define BITM_PORT_LOCK_INEN (_ADI_MSK(0x00000010,uint32_t)) /* Input Enable Lock */
|
|
#define BITM_PORT_LOCK_DIR (_ADI_MSK(0x00000008,uint32_t)) /* Direction Lock */
|
|
#define BITM_PORT_LOCK_DATA (_ADI_MSK(0x00000004,uint32_t)) /* Data Lock */
|
|
#define BITM_PORT_LOCK_MUX (_ADI_MSK(0x00000002,uint32_t)) /* Function Multiplexer Lock */
|
|
#define BITM_PORT_LOCK_FER (_ADI_MSK(0x00000001,uint32_t)) /* Function Enable Lock */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PORT_REVID Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PORT_REVID_MAJOR 4 /* Major ID */
|
|
#define BITP_PORT_REVID_REV 0 /* Revision ID */
|
|
#define BITM_PORT_REVID_MAJOR (_ADI_MSK(0x000000F0,uint32_t)) /* Major ID */
|
|
#define BITM_PORT_REVID_REV (_ADI_MSK(0x0000000F,uint32_t)) /* Revision ID */
|
|
|
|
/* ==================================================
|
|
Pads Controller Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
PADS0
|
|
========================= */
|
|
#define REG_PADS0_EMAC_PTP_CLKSEL 0xFFC03404 /* PADS0 Clock Selection for EMAC and PTP */
|
|
#define REG_PADS0_TWI_VSEL 0xFFC03408 /* PADS0 TWI Voltage Selection */
|
|
#define REG_PADS0_PORTS_HYST 0xFFC03440 /* PADS0 Hysteresis Enable Register */
|
|
|
|
/* =========================
|
|
PADS
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PADS_EMAC_PTP_CLKSEL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PADS_EMAC_PTP_CLKSEL_EMAC1 2 /* Select Clock Source for PTP Block in EMAC1 */
|
|
#define BITP_PADS_EMAC_PTP_CLKSEL_EMAC0 0 /* PTP Clock Source 0 */
|
|
#define BITM_PADS_EMAC_PTP_CLKSEL_EMAC1 (_ADI_MSK(0x0000000C,uint32_t)) /* Select Clock Source for PTP Block in EMAC1 */
|
|
#define BITM_PADS_EMAC_PTP_CLKSEL_EMAC0 (_ADI_MSK(0x00000003,uint32_t)) /* PTP Clock Source 0 */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PADS_TWI_VSEL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PADS_TWI_VSEL_TWI1 4 /* TWI Voltage Select 1 */
|
|
#define BITP_PADS_TWI_VSEL_TWI0 0 /* TWI Voltage Select 0 */
|
|
#define BITM_PADS_TWI_VSEL_TWI1 (_ADI_MSK(0x00000070,uint32_t)) /* TWI Voltage Select 1 */
|
|
#define BITM_PADS_TWI_VSEL_TWI0 (_ADI_MSK(0x00000007,uint32_t)) /* TWI Voltage Select 0 */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PADS_PORTS_HYST Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PADS_PORTS_HYST_G 6 /* Port G Hysteresis */
|
|
#define BITP_PADS_PORTS_HYST_F 5 /* Port F Hysteresis */
|
|
#define BITP_PADS_PORTS_HYST_E 4 /* Port E Hysteresis */
|
|
#define BITP_PADS_PORTS_HYST_D 3 /* Port D Hysteresis */
|
|
#define BITP_PADS_PORTS_HYST_C 2 /* Port C Hysteresis */
|
|
#define BITP_PADS_PORTS_HYST_B 1 /* Port B Hysteresis */
|
|
#define BITP_PADS_PORTS_HYST_A 0 /* Port A Hysteresis */
|
|
#define BITM_PADS_PORTS_HYST_G (_ADI_MSK(0x00000040,uint32_t)) /* Port G Hysteresis */
|
|
#define BITM_PADS_PORTS_HYST_F (_ADI_MSK(0x00000020,uint32_t)) /* Port F Hysteresis */
|
|
#define BITM_PADS_PORTS_HYST_E (_ADI_MSK(0x00000010,uint32_t)) /* Port E Hysteresis */
|
|
#define BITM_PADS_PORTS_HYST_D (_ADI_MSK(0x00000008,uint32_t)) /* Port D Hysteresis */
|
|
#define BITM_PADS_PORTS_HYST_C (_ADI_MSK(0x00000004,uint32_t)) /* Port C Hysteresis */
|
|
#define BITM_PADS_PORTS_HYST_B (_ADI_MSK(0x00000002,uint32_t)) /* Port B Hysteresis */
|
|
#define BITM_PADS_PORTS_HYST_A (_ADI_MSK(0x00000001,uint32_t)) /* Port A Hysteresis */
|
|
|
|
/* ==================================================
|
|
PINT Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
PINT0
|
|
========================= */
|
|
#define REG_PINT0_MSK_SET 0xFFC04000 /* PINT0 Pint Mask Set Register */
|
|
#define REG_PINT0_MSK_CLR 0xFFC04004 /* PINT0 Pint Mask Clear Register */
|
|
#define REG_PINT0_REQ 0xFFC04008 /* PINT0 Pint Request Register */
|
|
#define REG_PINT0_ASSIGN 0xFFC0400C /* PINT0 Pint Assign Register */
|
|
#define REG_PINT0_EDGE_SET 0xFFC04010 /* PINT0 Pint Edge Set Register */
|
|
#define REG_PINT0_EDGE_CLR 0xFFC04014 /* PINT0 Pint Edge Clear Register */
|
|
#define REG_PINT0_INV_SET 0xFFC04018 /* PINT0 Pint Invert Set Register */
|
|
#define REG_PINT0_INV_CLR 0xFFC0401C /* PINT0 Pint Invert Clear Register */
|
|
#define REG_PINT0_PINSTATE 0xFFC04020 /* PINT0 Pint Pinstate Register */
|
|
#define REG_PINT0_LATCH 0xFFC04024 /* PINT0 Pint Latch Register */
|
|
|
|
/* =========================
|
|
PINT1
|
|
========================= */
|
|
#define REG_PINT1_MSK_SET 0xFFC04100 /* PINT1 Pint Mask Set Register */
|
|
#define REG_PINT1_MSK_CLR 0xFFC04104 /* PINT1 Pint Mask Clear Register */
|
|
#define REG_PINT1_REQ 0xFFC04108 /* PINT1 Pint Request Register */
|
|
#define REG_PINT1_ASSIGN 0xFFC0410C /* PINT1 Pint Assign Register */
|
|
#define REG_PINT1_EDGE_SET 0xFFC04110 /* PINT1 Pint Edge Set Register */
|
|
#define REG_PINT1_EDGE_CLR 0xFFC04114 /* PINT1 Pint Edge Clear Register */
|
|
#define REG_PINT1_INV_SET 0xFFC04118 /* PINT1 Pint Invert Set Register */
|
|
#define REG_PINT1_INV_CLR 0xFFC0411C /* PINT1 Pint Invert Clear Register */
|
|
#define REG_PINT1_PINSTATE 0xFFC04120 /* PINT1 Pint Pinstate Register */
|
|
#define REG_PINT1_LATCH 0xFFC04124 /* PINT1 Pint Latch Register */
|
|
|
|
/* =========================
|
|
PINT2
|
|
========================= */
|
|
#define REG_PINT2_MSK_SET 0xFFC04200 /* PINT2 Pint Mask Set Register */
|
|
#define REG_PINT2_MSK_CLR 0xFFC04204 /* PINT2 Pint Mask Clear Register */
|
|
#define REG_PINT2_REQ 0xFFC04208 /* PINT2 Pint Request Register */
|
|
#define REG_PINT2_ASSIGN 0xFFC0420C /* PINT2 Pint Assign Register */
|
|
#define REG_PINT2_EDGE_SET 0xFFC04210 /* PINT2 Pint Edge Set Register */
|
|
#define REG_PINT2_EDGE_CLR 0xFFC04214 /* PINT2 Pint Edge Clear Register */
|
|
#define REG_PINT2_INV_SET 0xFFC04218 /* PINT2 Pint Invert Set Register */
|
|
#define REG_PINT2_INV_CLR 0xFFC0421C /* PINT2 Pint Invert Clear Register */
|
|
#define REG_PINT2_PINSTATE 0xFFC04220 /* PINT2 Pint Pinstate Register */
|
|
#define REG_PINT2_LATCH 0xFFC04224 /* PINT2 Pint Latch Register */
|
|
|
|
/* =========================
|
|
PINT3
|
|
========================= */
|
|
#define REG_PINT3_MSK_SET 0xFFC04300 /* PINT3 Pint Mask Set Register */
|
|
#define REG_PINT3_MSK_CLR 0xFFC04304 /* PINT3 Pint Mask Clear Register */
|
|
#define REG_PINT3_REQ 0xFFC04308 /* PINT3 Pint Request Register */
|
|
#define REG_PINT3_ASSIGN 0xFFC0430C /* PINT3 Pint Assign Register */
|
|
#define REG_PINT3_EDGE_SET 0xFFC04310 /* PINT3 Pint Edge Set Register */
|
|
#define REG_PINT3_EDGE_CLR 0xFFC04314 /* PINT3 Pint Edge Clear Register */
|
|
#define REG_PINT3_INV_SET 0xFFC04318 /* PINT3 Pint Invert Set Register */
|
|
#define REG_PINT3_INV_CLR 0xFFC0431C /* PINT3 Pint Invert Clear Register */
|
|
#define REG_PINT3_PINSTATE 0xFFC04320 /* PINT3 Pint Pinstate Register */
|
|
#define REG_PINT3_LATCH 0xFFC04324 /* PINT3 Pint Latch Register */
|
|
|
|
/* =========================
|
|
PINT4
|
|
========================= */
|
|
#define REG_PINT4_MSK_SET 0xFFC04400 /* PINT4 Pint Mask Set Register */
|
|
#define REG_PINT4_MSK_CLR 0xFFC04404 /* PINT4 Pint Mask Clear Register */
|
|
#define REG_PINT4_REQ 0xFFC04408 /* PINT4 Pint Request Register */
|
|
#define REG_PINT4_ASSIGN 0xFFC0440C /* PINT4 Pint Assign Register */
|
|
#define REG_PINT4_EDGE_SET 0xFFC04410 /* PINT4 Pint Edge Set Register */
|
|
#define REG_PINT4_EDGE_CLR 0xFFC04414 /* PINT4 Pint Edge Clear Register */
|
|
#define REG_PINT4_INV_SET 0xFFC04418 /* PINT4 Pint Invert Set Register */
|
|
#define REG_PINT4_INV_CLR 0xFFC0441C /* PINT4 Pint Invert Clear Register */
|
|
#define REG_PINT4_PINSTATE 0xFFC04420 /* PINT4 Pint Pinstate Register */
|
|
#define REG_PINT4_LATCH 0xFFC04424 /* PINT4 Pint Latch Register */
|
|
|
|
/* =========================
|
|
PINT5
|
|
========================= */
|
|
#define REG_PINT5_MSK_SET 0xFFC04500 /* PINT5 Pint Mask Set Register */
|
|
#define REG_PINT5_MSK_CLR 0xFFC04504 /* PINT5 Pint Mask Clear Register */
|
|
#define REG_PINT5_REQ 0xFFC04508 /* PINT5 Pint Request Register */
|
|
#define REG_PINT5_ASSIGN 0xFFC0450C /* PINT5 Pint Assign Register */
|
|
#define REG_PINT5_EDGE_SET 0xFFC04510 /* PINT5 Pint Edge Set Register */
|
|
#define REG_PINT5_EDGE_CLR 0xFFC04514 /* PINT5 Pint Edge Clear Register */
|
|
#define REG_PINT5_INV_SET 0xFFC04518 /* PINT5 Pint Invert Set Register */
|
|
#define REG_PINT5_INV_CLR 0xFFC0451C /* PINT5 Pint Invert Clear Register */
|
|
#define REG_PINT5_PINSTATE 0xFFC04520 /* PINT5 Pint Pinstate Register */
|
|
#define REG_PINT5_LATCH 0xFFC04524 /* PINT5 Pint Latch Register */
|
|
|
|
/* =========================
|
|
PINT
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PINT_MSK_SET Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PINT_MSK_SET_PIQ31 31 /* Pin Interrupt 31 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ30 30 /* Pin Interrupt 30 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ29 29 /* Pin Interrupt 29 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ28 28 /* Pin Interrupt 28 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ27 27 /* Pin Interrupt 27 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ26 26 /* Pin Interrupt 26 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ25 25 /* Pin Interrupt 25 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ24 24 /* Pin Interrupt 24 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ23 23 /* Pin Interrupt 23 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ22 22 /* Pin Interrupt 22 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ21 21 /* Pin Interrupt 21 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ20 20 /* Pin Interrupt 20 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ19 19 /* Pin Interrupt 19 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ18 18 /* Pin Interrupt 18 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ17 17 /* Pin Interrupt 17 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ16 16 /* Pin Interrupt 16 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ15 15 /* Pin Interrupt 15 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ14 14 /* Pin Interrupt 14 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ13 13 /* Pin Interrupt 13 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ12 12 /* Pin Interrupt 12 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ11 11 /* Pin Interrupt 11 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ10 10 /* Pin Interrupt 10 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ9 9 /* Pin Interrupt 9 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ8 8 /* Pin Interrupt 8 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ7 7 /* Pin Interrupt 7 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ6 6 /* Pin Interrupt 6 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ5 5 /* Pin Interrupt 5 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ4 4 /* Pin Interrupt 4 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ3 3 /* Pin Interrupt 3 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ2 2 /* Pin Interrupt 2 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ1 1 /* Pin Interrupt 1 Unmask */
|
|
#define BITP_PINT_MSK_SET_PIQ0 0 /* Pin Interrupt 0 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ31 (_ADI_MSK(0x80000000,uint32_t)) /* Pin Interrupt 31 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ30 (_ADI_MSK(0x40000000,uint32_t)) /* Pin Interrupt 30 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ29 (_ADI_MSK(0x20000000,uint32_t)) /* Pin Interrupt 29 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ28 (_ADI_MSK(0x10000000,uint32_t)) /* Pin Interrupt 28 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ27 (_ADI_MSK(0x08000000,uint32_t)) /* Pin Interrupt 27 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ26 (_ADI_MSK(0x04000000,uint32_t)) /* Pin Interrupt 26 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ25 (_ADI_MSK(0x02000000,uint32_t)) /* Pin Interrupt 25 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ24 (_ADI_MSK(0x01000000,uint32_t)) /* Pin Interrupt 24 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ23 (_ADI_MSK(0x00800000,uint32_t)) /* Pin Interrupt 23 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ22 (_ADI_MSK(0x00400000,uint32_t)) /* Pin Interrupt 22 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ21 (_ADI_MSK(0x00200000,uint32_t)) /* Pin Interrupt 21 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ20 (_ADI_MSK(0x00100000,uint32_t)) /* Pin Interrupt 20 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ19 (_ADI_MSK(0x00080000,uint32_t)) /* Pin Interrupt 19 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ18 (_ADI_MSK(0x00040000,uint32_t)) /* Pin Interrupt 18 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ17 (_ADI_MSK(0x00020000,uint32_t)) /* Pin Interrupt 17 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ16 (_ADI_MSK(0x00010000,uint32_t)) /* Pin Interrupt 16 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ15 (_ADI_MSK(0x00008000,uint32_t)) /* Pin Interrupt 15 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ14 (_ADI_MSK(0x00004000,uint32_t)) /* Pin Interrupt 14 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ13 (_ADI_MSK(0x00002000,uint32_t)) /* Pin Interrupt 13 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ12 (_ADI_MSK(0x00001000,uint32_t)) /* Pin Interrupt 12 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ11 (_ADI_MSK(0x00000800,uint32_t)) /* Pin Interrupt 11 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ10 (_ADI_MSK(0x00000400,uint32_t)) /* Pin Interrupt 10 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ9 (_ADI_MSK(0x00000200,uint32_t)) /* Pin Interrupt 9 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ8 (_ADI_MSK(0x00000100,uint32_t)) /* Pin Interrupt 8 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ7 (_ADI_MSK(0x00000080,uint32_t)) /* Pin Interrupt 7 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ6 (_ADI_MSK(0x00000040,uint32_t)) /* Pin Interrupt 6 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ5 (_ADI_MSK(0x00000020,uint32_t)) /* Pin Interrupt 5 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ4 (_ADI_MSK(0x00000010,uint32_t)) /* Pin Interrupt 4 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ3 (_ADI_MSK(0x00000008,uint32_t)) /* Pin Interrupt 3 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ2 (_ADI_MSK(0x00000004,uint32_t)) /* Pin Interrupt 2 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ1 (_ADI_MSK(0x00000002,uint32_t)) /* Pin Interrupt 1 Unmask */
|
|
#define BITM_PINT_MSK_SET_PIQ0 (_ADI_MSK(0x00000001,uint32_t)) /* Pin Interrupt 0 Unmask */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PINT_MSK_CLR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PINT_MSK_CLR_PIQ31 31 /* Pin Interrupt 31 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ30 30 /* Pin Interrupt 30 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ29 29 /* Pin Interrupt 29 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ28 28 /* Pin Interrupt 28 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ27 27 /* Pin Interrupt 27 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ26 26 /* Pin Interrupt 26 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ25 25 /* Pin Interrupt 25 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ24 24 /* Pin Interrupt 24 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ23 23 /* Pin Interrupt 23 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ22 22 /* Pin Interrupt 22 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ21 21 /* Pin Interrupt 21 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ20 20 /* Pin Interrupt 20 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ19 19 /* Pin Interrupt 19 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ18 18 /* Pin Interrupt 18 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ17 17 /* Pin Interrupt 17 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ16 16 /* Pin Interrupt 16 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ15 15 /* Pin Interrupt 15 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ14 14 /* Pin Interrupt 14 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ13 13 /* Pin Interrupt 13 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ12 12 /* Pin Interrupt 12 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ11 11 /* Pin Interrupt 11 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ10 10 /* Pin Interrupt 10 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ9 9 /* Pin Interrupt 9 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ8 8 /* Pin Interrupt 8 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ7 7 /* Pin Interrupt 7 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ6 6 /* Pin Interrupt 6 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ5 5 /* Pin Interrupt 5 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ4 4 /* Pin Interrupt 4 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ3 3 /* Pin Interrupt 3 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ2 2 /* Pin Interrupt 2 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ1 1 /* Pin Interrupt 1 Mask */
|
|
#define BITP_PINT_MSK_CLR_PIQ0 0 /* Pin Interrupt 0 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ31 (_ADI_MSK(0x80000000,uint32_t)) /* Pin Interrupt 31 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ30 (_ADI_MSK(0x40000000,uint32_t)) /* Pin Interrupt 30 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ29 (_ADI_MSK(0x20000000,uint32_t)) /* Pin Interrupt 29 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ28 (_ADI_MSK(0x10000000,uint32_t)) /* Pin Interrupt 28 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ27 (_ADI_MSK(0x08000000,uint32_t)) /* Pin Interrupt 27 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ26 (_ADI_MSK(0x04000000,uint32_t)) /* Pin Interrupt 26 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ25 (_ADI_MSK(0x02000000,uint32_t)) /* Pin Interrupt 25 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ24 (_ADI_MSK(0x01000000,uint32_t)) /* Pin Interrupt 24 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ23 (_ADI_MSK(0x00800000,uint32_t)) /* Pin Interrupt 23 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ22 (_ADI_MSK(0x00400000,uint32_t)) /* Pin Interrupt 22 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ21 (_ADI_MSK(0x00200000,uint32_t)) /* Pin Interrupt 21 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ20 (_ADI_MSK(0x00100000,uint32_t)) /* Pin Interrupt 20 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ19 (_ADI_MSK(0x00080000,uint32_t)) /* Pin Interrupt 19 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ18 (_ADI_MSK(0x00040000,uint32_t)) /* Pin Interrupt 18 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ17 (_ADI_MSK(0x00020000,uint32_t)) /* Pin Interrupt 17 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ16 (_ADI_MSK(0x00010000,uint32_t)) /* Pin Interrupt 16 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ15 (_ADI_MSK(0x00008000,uint32_t)) /* Pin Interrupt 15 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ14 (_ADI_MSK(0x00004000,uint32_t)) /* Pin Interrupt 14 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ13 (_ADI_MSK(0x00002000,uint32_t)) /* Pin Interrupt 13 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ12 (_ADI_MSK(0x00001000,uint32_t)) /* Pin Interrupt 12 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ11 (_ADI_MSK(0x00000800,uint32_t)) /* Pin Interrupt 11 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ10 (_ADI_MSK(0x00000400,uint32_t)) /* Pin Interrupt 10 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ9 (_ADI_MSK(0x00000200,uint32_t)) /* Pin Interrupt 9 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ8 (_ADI_MSK(0x00000100,uint32_t)) /* Pin Interrupt 8 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ7 (_ADI_MSK(0x00000080,uint32_t)) /* Pin Interrupt 7 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ6 (_ADI_MSK(0x00000040,uint32_t)) /* Pin Interrupt 6 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ5 (_ADI_MSK(0x00000020,uint32_t)) /* Pin Interrupt 5 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ4 (_ADI_MSK(0x00000010,uint32_t)) /* Pin Interrupt 4 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ3 (_ADI_MSK(0x00000008,uint32_t)) /* Pin Interrupt 3 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ2 (_ADI_MSK(0x00000004,uint32_t)) /* Pin Interrupt 2 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ1 (_ADI_MSK(0x00000002,uint32_t)) /* Pin Interrupt 1 Mask */
|
|
#define BITM_PINT_MSK_CLR_PIQ0 (_ADI_MSK(0x00000001,uint32_t)) /* Pin Interrupt 0 Mask */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PINT_REQ Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PINT_REQ_PIQ31 31 /* Pin Interrupt 31 Request */
|
|
#define BITP_PINT_REQ_PIQ30 30 /* Pin Interrupt 30 Request */
|
|
#define BITP_PINT_REQ_PIQ29 29 /* Pin Interrupt 29 Request */
|
|
#define BITP_PINT_REQ_PIQ28 28 /* Pin Interrupt 28 Request */
|
|
#define BITP_PINT_REQ_PIQ27 27 /* Pin Interrupt 27 Request */
|
|
#define BITP_PINT_REQ_PIQ26 26 /* Pin Interrupt 26 Request */
|
|
#define BITP_PINT_REQ_PIQ25 25 /* Pin Interrupt 25 Request */
|
|
#define BITP_PINT_REQ_PIQ24 24 /* Pin Interrupt 24 Request */
|
|
#define BITP_PINT_REQ_PIQ23 23 /* Pin Interrupt 23 Request */
|
|
#define BITP_PINT_REQ_PIQ22 22 /* Pin Interrupt 22 Request */
|
|
#define BITP_PINT_REQ_PIQ21 21 /* Pin Interrupt 21 Request */
|
|
#define BITP_PINT_REQ_PIQ20 20 /* Pin Interrupt 20 Request */
|
|
#define BITP_PINT_REQ_PIQ19 19 /* Pin Interrupt 19 Request */
|
|
#define BITP_PINT_REQ_PIQ18 18 /* Pin Interrupt 18 Request */
|
|
#define BITP_PINT_REQ_PIQ17 17 /* Pin Interrupt 17 Request */
|
|
#define BITP_PINT_REQ_PIQ16 16 /* Pin Interrupt 16 Request */
|
|
#define BITP_PINT_REQ_PIQ15 15 /* Pin Interrupt 15 Request */
|
|
#define BITP_PINT_REQ_PIQ14 14 /* Pin Interrupt 14 Request */
|
|
#define BITP_PINT_REQ_PIQ13 13 /* Pin Interrupt 13 Request */
|
|
#define BITP_PINT_REQ_PIQ12 12 /* Pin Interrupt 12 Request */
|
|
#define BITP_PINT_REQ_PIQ11 11 /* Pin Interrupt 11 Request */
|
|
#define BITP_PINT_REQ_PIQ10 10 /* Pin Interrupt 10 Request */
|
|
#define BITP_PINT_REQ_PIQ9 9 /* Pin Interrupt 9 Request */
|
|
#define BITP_PINT_REQ_PIQ8 8 /* Pin Interrupt 8 Request */
|
|
#define BITP_PINT_REQ_PIQ7 7 /* Pin Interrupt 7 Request */
|
|
#define BITP_PINT_REQ_PIQ6 6 /* Pin Interrupt 6 Request */
|
|
#define BITP_PINT_REQ_PIQ5 5 /* Pin Interrupt 5 Request */
|
|
#define BITP_PINT_REQ_PIQ4 4 /* Pin Interrupt 4 Request */
|
|
#define BITP_PINT_REQ_PIQ3 3 /* Pin Interrupt 3 Request */
|
|
#define BITP_PINT_REQ_PIQ2 2 /* Pin Interrupt 2 Request */
|
|
#define BITP_PINT_REQ_PIQ1 1 /* Pin Interrupt 1 Request */
|
|
#define BITP_PINT_REQ_PIQ0 0 /* Pin Interrupt 0 Request */
|
|
#define BITM_PINT_REQ_PIQ31 (_ADI_MSK(0x80000000,uint32_t)) /* Pin Interrupt 31 Request */
|
|
#define BITM_PINT_REQ_PIQ30 (_ADI_MSK(0x40000000,uint32_t)) /* Pin Interrupt 30 Request */
|
|
#define BITM_PINT_REQ_PIQ29 (_ADI_MSK(0x20000000,uint32_t)) /* Pin Interrupt 29 Request */
|
|
#define BITM_PINT_REQ_PIQ28 (_ADI_MSK(0x10000000,uint32_t)) /* Pin Interrupt 28 Request */
|
|
#define BITM_PINT_REQ_PIQ27 (_ADI_MSK(0x08000000,uint32_t)) /* Pin Interrupt 27 Request */
|
|
#define BITM_PINT_REQ_PIQ26 (_ADI_MSK(0x04000000,uint32_t)) /* Pin Interrupt 26 Request */
|
|
#define BITM_PINT_REQ_PIQ25 (_ADI_MSK(0x02000000,uint32_t)) /* Pin Interrupt 25 Request */
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#define BITM_PINT_REQ_PIQ24 (_ADI_MSK(0x01000000,uint32_t)) /* Pin Interrupt 24 Request */
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#define BITM_PINT_REQ_PIQ23 (_ADI_MSK(0x00800000,uint32_t)) /* Pin Interrupt 23 Request */
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#define BITM_PINT_REQ_PIQ22 (_ADI_MSK(0x00400000,uint32_t)) /* Pin Interrupt 22 Request */
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#define BITM_PINT_REQ_PIQ21 (_ADI_MSK(0x00200000,uint32_t)) /* Pin Interrupt 21 Request */
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#define BITM_PINT_REQ_PIQ20 (_ADI_MSK(0x00100000,uint32_t)) /* Pin Interrupt 20 Request */
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#define BITM_PINT_REQ_PIQ19 (_ADI_MSK(0x00080000,uint32_t)) /* Pin Interrupt 19 Request */
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#define BITM_PINT_REQ_PIQ18 (_ADI_MSK(0x00040000,uint32_t)) /* Pin Interrupt 18 Request */
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#define BITM_PINT_REQ_PIQ17 (_ADI_MSK(0x00020000,uint32_t)) /* Pin Interrupt 17 Request */
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#define BITM_PINT_REQ_PIQ16 (_ADI_MSK(0x00010000,uint32_t)) /* Pin Interrupt 16 Request */
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#define BITM_PINT_REQ_PIQ15 (_ADI_MSK(0x00008000,uint32_t)) /* Pin Interrupt 15 Request */
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#define BITM_PINT_REQ_PIQ14 (_ADI_MSK(0x00004000,uint32_t)) /* Pin Interrupt 14 Request */
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#define BITM_PINT_REQ_PIQ13 (_ADI_MSK(0x00002000,uint32_t)) /* Pin Interrupt 13 Request */
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#define BITM_PINT_REQ_PIQ12 (_ADI_MSK(0x00001000,uint32_t)) /* Pin Interrupt 12 Request */
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#define BITM_PINT_REQ_PIQ11 (_ADI_MSK(0x00000800,uint32_t)) /* Pin Interrupt 11 Request */
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#define BITM_PINT_REQ_PIQ10 (_ADI_MSK(0x00000400,uint32_t)) /* Pin Interrupt 10 Request */
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#define BITM_PINT_REQ_PIQ9 (_ADI_MSK(0x00000200,uint32_t)) /* Pin Interrupt 9 Request */
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#define BITM_PINT_REQ_PIQ8 (_ADI_MSK(0x00000100,uint32_t)) /* Pin Interrupt 8 Request */
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#define BITM_PINT_REQ_PIQ7 (_ADI_MSK(0x00000080,uint32_t)) /* Pin Interrupt 7 Request */
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#define BITM_PINT_REQ_PIQ6 (_ADI_MSK(0x00000040,uint32_t)) /* Pin Interrupt 6 Request */
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#define BITM_PINT_REQ_PIQ5 (_ADI_MSK(0x00000020,uint32_t)) /* Pin Interrupt 5 Request */
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#define BITM_PINT_REQ_PIQ4 (_ADI_MSK(0x00000010,uint32_t)) /* Pin Interrupt 4 Request */
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#define BITM_PINT_REQ_PIQ3 (_ADI_MSK(0x00000008,uint32_t)) /* Pin Interrupt 3 Request */
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#define BITM_PINT_REQ_PIQ2 (_ADI_MSK(0x00000004,uint32_t)) /* Pin Interrupt 2 Request */
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#define BITM_PINT_REQ_PIQ1 (_ADI_MSK(0x00000002,uint32_t)) /* Pin Interrupt 1 Request */
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#define BITM_PINT_REQ_PIQ0 (_ADI_MSK(0x00000001,uint32_t)) /* Pin Interrupt 0 Request */
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/* ------------------------------------------------------------------------------------------------------------------------
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PINT_ASSIGN Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_PINT_ASSIGN_B3MAP 24 /* Byte 3 Mapping */
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#define BITP_PINT_ASSIGN_B2MAP 16 /* Byte 2 Mapping */
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#define BITP_PINT_ASSIGN_B1MAP 8 /* Byte 1 Mapping */
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#define BITP_PINT_ASSIGN_B0MAP 0 /* Byte 0 Mapping */
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#define BITM_PINT_ASSIGN_B3MAP (_ADI_MSK(0xFF000000,uint32_t)) /* Byte 3 Mapping */
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#define BITM_PINT_ASSIGN_B2MAP (_ADI_MSK(0x00FF0000,uint32_t)) /* Byte 2 Mapping */
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#define BITM_PINT_ASSIGN_B1MAP (_ADI_MSK(0x0000FF00,uint32_t)) /* Byte 1 Mapping */
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#define BITM_PINT_ASSIGN_B0MAP (_ADI_MSK(0x000000FF,uint32_t)) /* Byte 0 Mapping */
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/* ------------------------------------------------------------------------------------------------------------------------
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PINT_EDGE_SET Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_PINT_EDGE_SET_PIQ31 31 /* Pin Interrupt 31 Edge */
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#define BITP_PINT_EDGE_SET_PIQ30 30 /* Pin Interrupt 30 Edge */
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#define BITP_PINT_EDGE_SET_PIQ29 29 /* Pin Interrupt 29 Edge */
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#define BITP_PINT_EDGE_SET_PIQ28 28 /* Pin Interrupt 28 Edge */
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#define BITP_PINT_EDGE_SET_PIQ27 27 /* Pin Interrupt 27 Edge */
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#define BITP_PINT_EDGE_SET_PIQ26 26 /* Pin Interrupt 26 Edge */
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#define BITP_PINT_EDGE_SET_PIQ25 25 /* Pin Interrupt 25 Edge */
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#define BITP_PINT_EDGE_SET_PIQ24 24 /* Pin Interrupt 24 Edge */
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#define BITP_PINT_EDGE_SET_PIQ23 23 /* Pin Interrupt 23 Edge */
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#define BITP_PINT_EDGE_SET_PIQ22 22 /* Pin Interrupt 22 Edge */
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#define BITP_PINT_EDGE_SET_PIQ21 21 /* Pin Interrupt 21 Edge */
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#define BITP_PINT_EDGE_SET_PIQ20 20 /* Pin Interrupt 20 Edge */
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#define BITP_PINT_EDGE_SET_PIQ19 19 /* Pin Interrupt 19 Edge */
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#define BITP_PINT_EDGE_SET_PIQ18 18 /* Pin Interrupt 18 Edge */
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#define BITP_PINT_EDGE_SET_PIQ17 17 /* Pin Interrupt 17 Edge */
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#define BITP_PINT_EDGE_SET_PIQ16 16 /* Pin Interrupt 16 Edge */
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#define BITP_PINT_EDGE_SET_PIQ15 15 /* Pin Interrupt 15 Edge */
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#define BITP_PINT_EDGE_SET_PIQ14 14 /* Pin Interrupt 14 Edge */
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#define BITP_PINT_EDGE_SET_PIQ13 13 /* Pin Interrupt 13 Edge */
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#define BITP_PINT_EDGE_SET_PIQ12 12 /* Pin Interrupt 12 Edge */
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#define BITP_PINT_EDGE_SET_PIQ11 11 /* Pin Interrupt 11 Edge */
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#define BITP_PINT_EDGE_SET_PIQ10 10 /* Pin Interrupt 10 Edge */
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#define BITP_PINT_EDGE_SET_PIQ9 9 /* Pin Interrupt 9 Edge */
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#define BITP_PINT_EDGE_SET_PIQ8 8 /* Pin Interrupt 8 Edge */
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#define BITP_PINT_EDGE_SET_PIQ7 7 /* Pin Interrupt 7 Edge */
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#define BITP_PINT_EDGE_SET_PIQ6 6 /* Pin Interrupt 6 Edge */
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#define BITP_PINT_EDGE_SET_PIQ5 5 /* Pin Interrupt 5 Edge */
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#define BITP_PINT_EDGE_SET_PIQ4 4 /* Pin Interrupt 4 Edge */
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#define BITP_PINT_EDGE_SET_PIQ3 3 /* Pin Interrupt 3 Edge */
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#define BITP_PINT_EDGE_SET_PIQ2 2 /* Pin Interrupt 2 Edge */
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#define BITP_PINT_EDGE_SET_PIQ1 1 /* Pin Interrupt 1 Edge */
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#define BITP_PINT_EDGE_SET_PIQ0 0 /* Pin Interrupt 0 Edge */
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#define BITM_PINT_EDGE_SET_PIQ31 (_ADI_MSK(0x80000000,uint32_t)) /* Pin Interrupt 31 Edge */
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#define BITM_PINT_EDGE_SET_PIQ30 (_ADI_MSK(0x40000000,uint32_t)) /* Pin Interrupt 30 Edge */
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#define BITM_PINT_EDGE_SET_PIQ29 (_ADI_MSK(0x20000000,uint32_t)) /* Pin Interrupt 29 Edge */
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#define BITM_PINT_EDGE_SET_PIQ28 (_ADI_MSK(0x10000000,uint32_t)) /* Pin Interrupt 28 Edge */
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#define BITM_PINT_EDGE_SET_PIQ27 (_ADI_MSK(0x08000000,uint32_t)) /* Pin Interrupt 27 Edge */
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#define BITM_PINT_EDGE_SET_PIQ26 (_ADI_MSK(0x04000000,uint32_t)) /* Pin Interrupt 26 Edge */
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#define BITM_PINT_EDGE_SET_PIQ25 (_ADI_MSK(0x02000000,uint32_t)) /* Pin Interrupt 25 Edge */
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#define BITM_PINT_EDGE_SET_PIQ24 (_ADI_MSK(0x01000000,uint32_t)) /* Pin Interrupt 24 Edge */
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#define BITM_PINT_EDGE_SET_PIQ23 (_ADI_MSK(0x00800000,uint32_t)) /* Pin Interrupt 23 Edge */
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#define BITM_PINT_EDGE_SET_PIQ22 (_ADI_MSK(0x00400000,uint32_t)) /* Pin Interrupt 22 Edge */
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#define BITM_PINT_EDGE_SET_PIQ21 (_ADI_MSK(0x00200000,uint32_t)) /* Pin Interrupt 21 Edge */
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#define BITM_PINT_EDGE_SET_PIQ20 (_ADI_MSK(0x00100000,uint32_t)) /* Pin Interrupt 20 Edge */
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#define BITM_PINT_EDGE_SET_PIQ19 (_ADI_MSK(0x00080000,uint32_t)) /* Pin Interrupt 19 Edge */
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#define BITM_PINT_EDGE_SET_PIQ18 (_ADI_MSK(0x00040000,uint32_t)) /* Pin Interrupt 18 Edge */
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#define BITM_PINT_EDGE_SET_PIQ17 (_ADI_MSK(0x00020000,uint32_t)) /* Pin Interrupt 17 Edge */
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#define BITM_PINT_EDGE_SET_PIQ16 (_ADI_MSK(0x00010000,uint32_t)) /* Pin Interrupt 16 Edge */
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#define BITM_PINT_EDGE_SET_PIQ15 (_ADI_MSK(0x00008000,uint32_t)) /* Pin Interrupt 15 Edge */
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#define BITM_PINT_EDGE_SET_PIQ14 (_ADI_MSK(0x00004000,uint32_t)) /* Pin Interrupt 14 Edge */
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#define BITM_PINT_EDGE_SET_PIQ13 (_ADI_MSK(0x00002000,uint32_t)) /* Pin Interrupt 13 Edge */
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#define BITM_PINT_EDGE_SET_PIQ12 (_ADI_MSK(0x00001000,uint32_t)) /* Pin Interrupt 12 Edge */
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#define BITM_PINT_EDGE_SET_PIQ11 (_ADI_MSK(0x00000800,uint32_t)) /* Pin Interrupt 11 Edge */
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#define BITM_PINT_EDGE_SET_PIQ10 (_ADI_MSK(0x00000400,uint32_t)) /* Pin Interrupt 10 Edge */
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#define BITM_PINT_EDGE_SET_PIQ9 (_ADI_MSK(0x00000200,uint32_t)) /* Pin Interrupt 9 Edge */
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#define BITM_PINT_EDGE_SET_PIQ8 (_ADI_MSK(0x00000100,uint32_t)) /* Pin Interrupt 8 Edge */
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#define BITM_PINT_EDGE_SET_PIQ7 (_ADI_MSK(0x00000080,uint32_t)) /* Pin Interrupt 7 Edge */
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#define BITM_PINT_EDGE_SET_PIQ6 (_ADI_MSK(0x00000040,uint32_t)) /* Pin Interrupt 6 Edge */
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#define BITM_PINT_EDGE_SET_PIQ5 (_ADI_MSK(0x00000020,uint32_t)) /* Pin Interrupt 5 Edge */
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#define BITM_PINT_EDGE_SET_PIQ4 (_ADI_MSK(0x00000010,uint32_t)) /* Pin Interrupt 4 Edge */
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#define BITM_PINT_EDGE_SET_PIQ3 (_ADI_MSK(0x00000008,uint32_t)) /* Pin Interrupt 3 Edge */
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#define BITM_PINT_EDGE_SET_PIQ2 (_ADI_MSK(0x00000004,uint32_t)) /* Pin Interrupt 2 Edge */
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#define BITM_PINT_EDGE_SET_PIQ1 (_ADI_MSK(0x00000002,uint32_t)) /* Pin Interrupt 1 Edge */
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#define BITM_PINT_EDGE_SET_PIQ0 (_ADI_MSK(0x00000001,uint32_t)) /* Pin Interrupt 0 Edge */
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/* ------------------------------------------------------------------------------------------------------------------------
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PINT_EDGE_CLR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_PINT_EDGE_CLR_PIQ31 31 /* Pin Interrupt 31 Level */
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#define BITP_PINT_EDGE_CLR_PIQ30 30 /* Pin Interrupt 30 Level */
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#define BITP_PINT_EDGE_CLR_PIQ29 29 /* Pin Interrupt 29 Level */
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#define BITP_PINT_EDGE_CLR_PIQ28 28 /* Pin Interrupt 28 Level */
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#define BITP_PINT_EDGE_CLR_PIQ27 27 /* Pin Interrupt 27 Level */
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#define BITP_PINT_EDGE_CLR_PIQ26 26 /* Pin Interrupt 26 Level */
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#define BITP_PINT_EDGE_CLR_PIQ25 25 /* Pin Interrupt 25 Level */
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#define BITP_PINT_EDGE_CLR_PIQ24 24 /* Pin Interrupt 24 Level */
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#define BITP_PINT_EDGE_CLR_PIQ23 23 /* Pin Interrupt 23 Level */
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#define BITP_PINT_EDGE_CLR_PIQ22 22 /* Pin Interrupt 22 Level */
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#define BITP_PINT_EDGE_CLR_PIQ21 21 /* Pin Interrupt 21 Level */
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#define BITP_PINT_EDGE_CLR_PIQ20 20 /* Pin Interrupt 20 Level */
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#define BITP_PINT_EDGE_CLR_PIQ19 19 /* Pin Interrupt 19 Level */
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#define BITP_PINT_EDGE_CLR_PIQ18 18 /* Pin Interrupt 18 Level */
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#define BITP_PINT_EDGE_CLR_PIQ17 17 /* Pin Interrupt 17 Level */
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#define BITP_PINT_EDGE_CLR_PIQ16 16 /* Pin Interrupt 16 Level */
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#define BITP_PINT_EDGE_CLR_PIQ15 15 /* Pin Interrupt 15 Level */
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#define BITP_PINT_EDGE_CLR_PIQ14 14 /* Pin Interrupt 14 Level */
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#define BITP_PINT_EDGE_CLR_PIQ13 13 /* Pin Interrupt 13 Level */
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#define BITP_PINT_EDGE_CLR_PIQ12 12 /* Pin Interrupt 12 Level */
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#define BITP_PINT_EDGE_CLR_PIQ11 11 /* Pin Interrupt 11 Level */
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#define BITP_PINT_EDGE_CLR_PIQ10 10 /* Pin Interrupt 10 Level */
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#define BITP_PINT_EDGE_CLR_PIQ9 9 /* Pin Interrupt 9 Level */
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#define BITP_PINT_EDGE_CLR_PIQ8 8 /* Pin Interrupt 8 Level */
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#define BITP_PINT_EDGE_CLR_PIQ7 7 /* Pin Interrupt 7 Level */
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#define BITP_PINT_EDGE_CLR_PIQ6 6 /* Pin Interrupt 6 Level */
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#define BITP_PINT_EDGE_CLR_PIQ5 5 /* Pin Interrupt 5 Level */
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#define BITP_PINT_EDGE_CLR_PIQ4 4 /* Pin Interrupt 4 Level */
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#define BITP_PINT_EDGE_CLR_PIQ3 3 /* Pin Interrupt 3 Level */
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#define BITP_PINT_EDGE_CLR_PIQ2 2 /* Pin Interrupt 2 Level */
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#define BITP_PINT_EDGE_CLR_PIQ1 1 /* Pin Interrupt 1 Level */
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#define BITP_PINT_EDGE_CLR_PIQ0 0 /* Pin Interrupt 0 Level */
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#define BITM_PINT_EDGE_CLR_PIQ31 (_ADI_MSK(0x80000000,uint32_t)) /* Pin Interrupt 31 Level */
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#define BITM_PINT_EDGE_CLR_PIQ30 (_ADI_MSK(0x40000000,uint32_t)) /* Pin Interrupt 30 Level */
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#define BITM_PINT_EDGE_CLR_PIQ29 (_ADI_MSK(0x20000000,uint32_t)) /* Pin Interrupt 29 Level */
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#define BITM_PINT_EDGE_CLR_PIQ28 (_ADI_MSK(0x10000000,uint32_t)) /* Pin Interrupt 28 Level */
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#define BITM_PINT_EDGE_CLR_PIQ27 (_ADI_MSK(0x08000000,uint32_t)) /* Pin Interrupt 27 Level */
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#define BITM_PINT_EDGE_CLR_PIQ26 (_ADI_MSK(0x04000000,uint32_t)) /* Pin Interrupt 26 Level */
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#define BITM_PINT_EDGE_CLR_PIQ25 (_ADI_MSK(0x02000000,uint32_t)) /* Pin Interrupt 25 Level */
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#define BITM_PINT_EDGE_CLR_PIQ24 (_ADI_MSK(0x01000000,uint32_t)) /* Pin Interrupt 24 Level */
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#define BITM_PINT_EDGE_CLR_PIQ23 (_ADI_MSK(0x00800000,uint32_t)) /* Pin Interrupt 23 Level */
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#define BITM_PINT_EDGE_CLR_PIQ22 (_ADI_MSK(0x00400000,uint32_t)) /* Pin Interrupt 22 Level */
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#define BITM_PINT_EDGE_CLR_PIQ21 (_ADI_MSK(0x00200000,uint32_t)) /* Pin Interrupt 21 Level */
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#define BITM_PINT_EDGE_CLR_PIQ20 (_ADI_MSK(0x00100000,uint32_t)) /* Pin Interrupt 20 Level */
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#define BITM_PINT_EDGE_CLR_PIQ19 (_ADI_MSK(0x00080000,uint32_t)) /* Pin Interrupt 19 Level */
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#define BITM_PINT_EDGE_CLR_PIQ18 (_ADI_MSK(0x00040000,uint32_t)) /* Pin Interrupt 18 Level */
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#define BITM_PINT_EDGE_CLR_PIQ17 (_ADI_MSK(0x00020000,uint32_t)) /* Pin Interrupt 17 Level */
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#define BITM_PINT_EDGE_CLR_PIQ16 (_ADI_MSK(0x00010000,uint32_t)) /* Pin Interrupt 16 Level */
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#define BITM_PINT_EDGE_CLR_PIQ15 (_ADI_MSK(0x00008000,uint32_t)) /* Pin Interrupt 15 Level */
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#define BITM_PINT_EDGE_CLR_PIQ14 (_ADI_MSK(0x00004000,uint32_t)) /* Pin Interrupt 14 Level */
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#define BITM_PINT_EDGE_CLR_PIQ13 (_ADI_MSK(0x00002000,uint32_t)) /* Pin Interrupt 13 Level */
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#define BITM_PINT_EDGE_CLR_PIQ12 (_ADI_MSK(0x00001000,uint32_t)) /* Pin Interrupt 12 Level */
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#define BITM_PINT_EDGE_CLR_PIQ11 (_ADI_MSK(0x00000800,uint32_t)) /* Pin Interrupt 11 Level */
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#define BITM_PINT_EDGE_CLR_PIQ10 (_ADI_MSK(0x00000400,uint32_t)) /* Pin Interrupt 10 Level */
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#define BITM_PINT_EDGE_CLR_PIQ9 (_ADI_MSK(0x00000200,uint32_t)) /* Pin Interrupt 9 Level */
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#define BITM_PINT_EDGE_CLR_PIQ8 (_ADI_MSK(0x00000100,uint32_t)) /* Pin Interrupt 8 Level */
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#define BITM_PINT_EDGE_CLR_PIQ7 (_ADI_MSK(0x00000080,uint32_t)) /* Pin Interrupt 7 Level */
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#define BITM_PINT_EDGE_CLR_PIQ6 (_ADI_MSK(0x00000040,uint32_t)) /* Pin Interrupt 6 Level */
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#define BITM_PINT_EDGE_CLR_PIQ5 (_ADI_MSK(0x00000020,uint32_t)) /* Pin Interrupt 5 Level */
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#define BITM_PINT_EDGE_CLR_PIQ4 (_ADI_MSK(0x00000010,uint32_t)) /* Pin Interrupt 4 Level */
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#define BITM_PINT_EDGE_CLR_PIQ3 (_ADI_MSK(0x00000008,uint32_t)) /* Pin Interrupt 3 Level */
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#define BITM_PINT_EDGE_CLR_PIQ2 (_ADI_MSK(0x00000004,uint32_t)) /* Pin Interrupt 2 Level */
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#define BITM_PINT_EDGE_CLR_PIQ1 (_ADI_MSK(0x00000002,uint32_t)) /* Pin Interrupt 1 Level */
|
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#define BITM_PINT_EDGE_CLR_PIQ0 (_ADI_MSK(0x00000001,uint32_t)) /* Pin Interrupt 0 Level */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PINT_INV_SET Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PINT_INV_SET_PIQ31 31 /* Pin Interrupt 31 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ30 30 /* Pin Interrupt 30 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ29 29 /* Pin Interrupt 29 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ28 28 /* Pin Interrupt 28 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ27 27 /* Pin Interrupt 27 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ26 26 /* Pin Interrupt 26 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ25 25 /* Pin Interrupt 25 Invert */
|
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#define BITP_PINT_INV_SET_PIQ24 24 /* Pin Interrupt 24 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ23 23 /* Pin Interrupt 23 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ22 22 /* Pin Interrupt 22 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ21 21 /* Pin Interrupt 21 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ20 20 /* Pin Interrupt 20 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ19 19 /* Pin Interrupt 19 Invert */
|
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#define BITP_PINT_INV_SET_PIQ18 18 /* Pin Interrupt 18 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ17 17 /* Pin Interrupt 17 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ16 16 /* Pin Interrupt 16 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ15 15 /* Pin Interrupt 15 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ14 14 /* Pin Interrupt 14 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ13 13 /* Pin Interrupt 13 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ12 12 /* Pin Interrupt 12 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ11 11 /* Pin Interrupt 11 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ10 10 /* Pin Interrupt 10 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ9 9 /* Pin Interrupt 9 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ8 8 /* Pin Interrupt 8 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ7 7 /* Pin Interrupt 7 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ6 6 /* Pin Interrupt 6 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ5 5 /* Pin Interrupt 5 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ4 4 /* Pin Interrupt 4 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ3 3 /* Pin Interrupt 3 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ2 2 /* Pin Interrupt 2 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ1 1 /* Pin Interrupt 1 Invert */
|
|
#define BITP_PINT_INV_SET_PIQ0 0 /* Pin Interrupt 0 Invert */
|
|
#define BITM_PINT_INV_SET_PIQ31 (_ADI_MSK(0x80000000,uint32_t)) /* Pin Interrupt 31 Invert */
|
|
#define BITM_PINT_INV_SET_PIQ30 (_ADI_MSK(0x40000000,uint32_t)) /* Pin Interrupt 30 Invert */
|
|
#define BITM_PINT_INV_SET_PIQ29 (_ADI_MSK(0x20000000,uint32_t)) /* Pin Interrupt 29 Invert */
|
|
#define BITM_PINT_INV_SET_PIQ28 (_ADI_MSK(0x10000000,uint32_t)) /* Pin Interrupt 28 Invert */
|
|
#define BITM_PINT_INV_SET_PIQ27 (_ADI_MSK(0x08000000,uint32_t)) /* Pin Interrupt 27 Invert */
|
|
#define BITM_PINT_INV_SET_PIQ26 (_ADI_MSK(0x04000000,uint32_t)) /* Pin Interrupt 26 Invert */
|
|
#define BITM_PINT_INV_SET_PIQ25 (_ADI_MSK(0x02000000,uint32_t)) /* Pin Interrupt 25 Invert */
|
|
#define BITM_PINT_INV_SET_PIQ24 (_ADI_MSK(0x01000000,uint32_t)) /* Pin Interrupt 24 Invert */
|
|
#define BITM_PINT_INV_SET_PIQ23 (_ADI_MSK(0x00800000,uint32_t)) /* Pin Interrupt 23 Invert */
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#define BITM_PINT_INV_SET_PIQ22 (_ADI_MSK(0x00400000,uint32_t)) /* Pin Interrupt 22 Invert */
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#define BITM_PINT_INV_SET_PIQ21 (_ADI_MSK(0x00200000,uint32_t)) /* Pin Interrupt 21 Invert */
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#define BITM_PINT_INV_SET_PIQ20 (_ADI_MSK(0x00100000,uint32_t)) /* Pin Interrupt 20 Invert */
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#define BITM_PINT_INV_SET_PIQ19 (_ADI_MSK(0x00080000,uint32_t)) /* Pin Interrupt 19 Invert */
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#define BITM_PINT_INV_SET_PIQ18 (_ADI_MSK(0x00040000,uint32_t)) /* Pin Interrupt 18 Invert */
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#define BITM_PINT_INV_SET_PIQ17 (_ADI_MSK(0x00020000,uint32_t)) /* Pin Interrupt 17 Invert */
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#define BITM_PINT_INV_SET_PIQ16 (_ADI_MSK(0x00010000,uint32_t)) /* Pin Interrupt 16 Invert */
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#define BITM_PINT_INV_SET_PIQ15 (_ADI_MSK(0x00008000,uint32_t)) /* Pin Interrupt 15 Invert */
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#define BITM_PINT_INV_SET_PIQ14 (_ADI_MSK(0x00004000,uint32_t)) /* Pin Interrupt 14 Invert */
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#define BITM_PINT_INV_SET_PIQ13 (_ADI_MSK(0x00002000,uint32_t)) /* Pin Interrupt 13 Invert */
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#define BITM_PINT_INV_SET_PIQ12 (_ADI_MSK(0x00001000,uint32_t)) /* Pin Interrupt 12 Invert */
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#define BITM_PINT_INV_SET_PIQ11 (_ADI_MSK(0x00000800,uint32_t)) /* Pin Interrupt 11 Invert */
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#define BITM_PINT_INV_SET_PIQ10 (_ADI_MSK(0x00000400,uint32_t)) /* Pin Interrupt 10 Invert */
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#define BITM_PINT_INV_SET_PIQ9 (_ADI_MSK(0x00000200,uint32_t)) /* Pin Interrupt 9 Invert */
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#define BITM_PINT_INV_SET_PIQ8 (_ADI_MSK(0x00000100,uint32_t)) /* Pin Interrupt 8 Invert */
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#define BITM_PINT_INV_SET_PIQ7 (_ADI_MSK(0x00000080,uint32_t)) /* Pin Interrupt 7 Invert */
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#define BITM_PINT_INV_SET_PIQ6 (_ADI_MSK(0x00000040,uint32_t)) /* Pin Interrupt 6 Invert */
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#define BITM_PINT_INV_SET_PIQ5 (_ADI_MSK(0x00000020,uint32_t)) /* Pin Interrupt 5 Invert */
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#define BITM_PINT_INV_SET_PIQ4 (_ADI_MSK(0x00000010,uint32_t)) /* Pin Interrupt 4 Invert */
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#define BITM_PINT_INV_SET_PIQ3 (_ADI_MSK(0x00000008,uint32_t)) /* Pin Interrupt 3 Invert */
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#define BITM_PINT_INV_SET_PIQ2 (_ADI_MSK(0x00000004,uint32_t)) /* Pin Interrupt 2 Invert */
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#define BITM_PINT_INV_SET_PIQ1 (_ADI_MSK(0x00000002,uint32_t)) /* Pin Interrupt 1 Invert */
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#define BITM_PINT_INV_SET_PIQ0 (_ADI_MSK(0x00000001,uint32_t)) /* Pin Interrupt 0 Invert */
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/* ------------------------------------------------------------------------------------------------------------------------
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PINT_INV_CLR Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_PINT_INV_CLR_PIQ31 31 /* Pin Interrupt 31 No Invert */
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#define BITP_PINT_INV_CLR_PIQ30 30 /* Pin Interrupt 30 No Invert */
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#define BITP_PINT_INV_CLR_PIQ29 29 /* Pin Interrupt 29 No Invert */
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#define BITP_PINT_INV_CLR_PIQ28 28 /* Pin Interrupt 28 No Invert */
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#define BITP_PINT_INV_CLR_PIQ27 27 /* Pin Interrupt 27 No Invert */
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#define BITP_PINT_INV_CLR_PIQ26 26 /* Pin Interrupt 26 No Invert */
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#define BITP_PINT_INV_CLR_PIQ25 25 /* Pin Interrupt 25 No Invert */
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#define BITP_PINT_INV_CLR_PIQ24 24 /* Pin Interrupt 24 No Invert */
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#define BITP_PINT_INV_CLR_PIQ23 23 /* Pin Interrupt 23 No Invert */
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#define BITP_PINT_INV_CLR_PIQ22 22 /* Pin Interrupt 22 No Invert */
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#define BITP_PINT_INV_CLR_PIQ21 21 /* Pin Interrupt 21 No Invert */
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#define BITP_PINT_INV_CLR_PIQ20 20 /* Pin Interrupt 20 No Invert */
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#define BITP_PINT_INV_CLR_PIQ19 19 /* Pin Interrupt 19 No Invert */
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#define BITP_PINT_INV_CLR_PIQ18 18 /* Pin Interrupt 18 No Invert */
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#define BITP_PINT_INV_CLR_PIQ17 17 /* Pin Interrupt 17 No Invert */
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#define BITP_PINT_INV_CLR_PIQ16 16 /* Pin Interrupt 16 No Invert */
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#define BITP_PINT_INV_CLR_PIQ15 15 /* Pin Interrupt 15 No Invert */
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#define BITP_PINT_INV_CLR_PIQ14 14 /* Pin Interrupt 14 No Invert */
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#define BITP_PINT_INV_CLR_PIQ13 13 /* Pin Interrupt 13 No Invert */
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#define BITP_PINT_INV_CLR_PIQ12 12 /* Pin Interrupt 12 No Invert */
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#define BITP_PINT_INV_CLR_PIQ11 11 /* Pin Interrupt 11 No Invert */
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#define BITP_PINT_INV_CLR_PIQ10 10 /* Pin Interrupt 10 No Invert */
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#define BITP_PINT_INV_CLR_PIQ9 9 /* Pin Interrupt 9 No Invert */
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#define BITP_PINT_INV_CLR_PIQ8 8 /* Pin Interrupt 8 No Invert */
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#define BITP_PINT_INV_CLR_PIQ7 7 /* Pin Interrupt 7 No Invert */
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#define BITP_PINT_INV_CLR_PIQ6 6 /* Pin Interrupt 6 No Invert */
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#define BITP_PINT_INV_CLR_PIQ5 5 /* Pin Interrupt 5 No Invert */
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#define BITP_PINT_INV_CLR_PIQ4 4 /* Pin Interrupt 4 No Invert */
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#define BITP_PINT_INV_CLR_PIQ3 3 /* Pin Interrupt 3 No Invert */
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#define BITP_PINT_INV_CLR_PIQ2 2 /* Pin Interrupt 2 No Invert */
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#define BITP_PINT_INV_CLR_PIQ1 1 /* Pin Interrupt 1 No Invert */
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#define BITP_PINT_INV_CLR_PIQ0 0 /* Pin Interrupt 0 No Invert */
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#define BITM_PINT_INV_CLR_PIQ31 (_ADI_MSK(0x80000000,uint32_t)) /* Pin Interrupt 31 No Invert */
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#define BITM_PINT_INV_CLR_PIQ30 (_ADI_MSK(0x40000000,uint32_t)) /* Pin Interrupt 30 No Invert */
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#define BITM_PINT_INV_CLR_PIQ29 (_ADI_MSK(0x20000000,uint32_t)) /* Pin Interrupt 29 No Invert */
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#define BITM_PINT_INV_CLR_PIQ28 (_ADI_MSK(0x10000000,uint32_t)) /* Pin Interrupt 28 No Invert */
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#define BITM_PINT_INV_CLR_PIQ27 (_ADI_MSK(0x08000000,uint32_t)) /* Pin Interrupt 27 No Invert */
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#define BITM_PINT_INV_CLR_PIQ26 (_ADI_MSK(0x04000000,uint32_t)) /* Pin Interrupt 26 No Invert */
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#define BITM_PINT_INV_CLR_PIQ25 (_ADI_MSK(0x02000000,uint32_t)) /* Pin Interrupt 25 No Invert */
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#define BITM_PINT_INV_CLR_PIQ24 (_ADI_MSK(0x01000000,uint32_t)) /* Pin Interrupt 24 No Invert */
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#define BITM_PINT_INV_CLR_PIQ23 (_ADI_MSK(0x00800000,uint32_t)) /* Pin Interrupt 23 No Invert */
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#define BITM_PINT_INV_CLR_PIQ22 (_ADI_MSK(0x00400000,uint32_t)) /* Pin Interrupt 22 No Invert */
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#define BITM_PINT_INV_CLR_PIQ21 (_ADI_MSK(0x00200000,uint32_t)) /* Pin Interrupt 21 No Invert */
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#define BITM_PINT_INV_CLR_PIQ20 (_ADI_MSK(0x00100000,uint32_t)) /* Pin Interrupt 20 No Invert */
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#define BITM_PINT_INV_CLR_PIQ19 (_ADI_MSK(0x00080000,uint32_t)) /* Pin Interrupt 19 No Invert */
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#define BITM_PINT_INV_CLR_PIQ18 (_ADI_MSK(0x00040000,uint32_t)) /* Pin Interrupt 18 No Invert */
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#define BITM_PINT_INV_CLR_PIQ17 (_ADI_MSK(0x00020000,uint32_t)) /* Pin Interrupt 17 No Invert */
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#define BITM_PINT_INV_CLR_PIQ16 (_ADI_MSK(0x00010000,uint32_t)) /* Pin Interrupt 16 No Invert */
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#define BITM_PINT_INV_CLR_PIQ15 (_ADI_MSK(0x00008000,uint32_t)) /* Pin Interrupt 15 No Invert */
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#define BITM_PINT_INV_CLR_PIQ14 (_ADI_MSK(0x00004000,uint32_t)) /* Pin Interrupt 14 No Invert */
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#define BITM_PINT_INV_CLR_PIQ13 (_ADI_MSK(0x00002000,uint32_t)) /* Pin Interrupt 13 No Invert */
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#define BITM_PINT_INV_CLR_PIQ12 (_ADI_MSK(0x00001000,uint32_t)) /* Pin Interrupt 12 No Invert */
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#define BITM_PINT_INV_CLR_PIQ11 (_ADI_MSK(0x00000800,uint32_t)) /* Pin Interrupt 11 No Invert */
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#define BITM_PINT_INV_CLR_PIQ10 (_ADI_MSK(0x00000400,uint32_t)) /* Pin Interrupt 10 No Invert */
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#define BITM_PINT_INV_CLR_PIQ9 (_ADI_MSK(0x00000200,uint32_t)) /* Pin Interrupt 9 No Invert */
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#define BITM_PINT_INV_CLR_PIQ8 (_ADI_MSK(0x00000100,uint32_t)) /* Pin Interrupt 8 No Invert */
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#define BITM_PINT_INV_CLR_PIQ7 (_ADI_MSK(0x00000080,uint32_t)) /* Pin Interrupt 7 No Invert */
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#define BITM_PINT_INV_CLR_PIQ6 (_ADI_MSK(0x00000040,uint32_t)) /* Pin Interrupt 6 No Invert */
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#define BITM_PINT_INV_CLR_PIQ5 (_ADI_MSK(0x00000020,uint32_t)) /* Pin Interrupt 5 No Invert */
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#define BITM_PINT_INV_CLR_PIQ4 (_ADI_MSK(0x00000010,uint32_t)) /* Pin Interrupt 4 No Invert */
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#define BITM_PINT_INV_CLR_PIQ3 (_ADI_MSK(0x00000008,uint32_t)) /* Pin Interrupt 3 No Invert */
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#define BITM_PINT_INV_CLR_PIQ2 (_ADI_MSK(0x00000004,uint32_t)) /* Pin Interrupt 2 No Invert */
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#define BITM_PINT_INV_CLR_PIQ1 (_ADI_MSK(0x00000002,uint32_t)) /* Pin Interrupt 1 No Invert */
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#define BITM_PINT_INV_CLR_PIQ0 (_ADI_MSK(0x00000001,uint32_t)) /* Pin Interrupt 0 No Invert */
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/* ------------------------------------------------------------------------------------------------------------------------
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PINT_PINSTATE Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_PINT_PINSTATE_PIQ31 31 /* Pin Interrupt 31 State */
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#define BITP_PINT_PINSTATE_PIQ30 30 /* Pin Interrupt 30 State */
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#define BITP_PINT_PINSTATE_PIQ29 29 /* Pin Interrupt 29 State */
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#define BITP_PINT_PINSTATE_PIQ28 28 /* Pin Interrupt 28 State */
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#define BITP_PINT_PINSTATE_PIQ27 27 /* Pin Interrupt 27 State */
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#define BITP_PINT_PINSTATE_PIQ26 26 /* Pin Interrupt 26 State */
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#define BITP_PINT_PINSTATE_PIQ25 25 /* Pin Interrupt 25 State */
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#define BITP_PINT_PINSTATE_PIQ24 24 /* Pin Interrupt 24 State */
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#define BITP_PINT_PINSTATE_PIQ23 23 /* Pin Interrupt 23 State */
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#define BITP_PINT_PINSTATE_PIQ22 22 /* Pin Interrupt 22 State */
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#define BITP_PINT_PINSTATE_PIQ21 21 /* Pin Interrupt 21 State */
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#define BITP_PINT_PINSTATE_PIQ20 20 /* Pin Interrupt 20 State */
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#define BITP_PINT_PINSTATE_PIQ19 19 /* Pin Interrupt 19 State */
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#define BITP_PINT_PINSTATE_PIQ18 18 /* Pin Interrupt 18 State */
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#define BITP_PINT_PINSTATE_PIQ17 17 /* Pin Interrupt 17 State */
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#define BITP_PINT_PINSTATE_PIQ16 16 /* Pin Interrupt 16 State */
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#define BITP_PINT_PINSTATE_PIQ15 15 /* Pin Interrupt 15 State */
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#define BITP_PINT_PINSTATE_PIQ14 14 /* Pin Interrupt 14 State */
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#define BITP_PINT_PINSTATE_PIQ13 13 /* Pin Interrupt 13 State */
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#define BITP_PINT_PINSTATE_PIQ12 12 /* Pin Interrupt 12 State */
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#define BITP_PINT_PINSTATE_PIQ11 11 /* Pin Interrupt 11 State */
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#define BITP_PINT_PINSTATE_PIQ10 10 /* Pin Interrupt 10 State */
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#define BITP_PINT_PINSTATE_PIQ9 9 /* Pin Interrupt 9 State */
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#define BITP_PINT_PINSTATE_PIQ8 8 /* Pin Interrupt 8 State */
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#define BITP_PINT_PINSTATE_PIQ7 7 /* Pin Interrupt 7 State */
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#define BITP_PINT_PINSTATE_PIQ6 6 /* Pin Interrupt 6 State */
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#define BITP_PINT_PINSTATE_PIQ5 5 /* Pin Interrupt 5 State */
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#define BITP_PINT_PINSTATE_PIQ4 4 /* Pin Interrupt 4 State */
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#define BITP_PINT_PINSTATE_PIQ3 3 /* Pin Interrupt 3 State */
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#define BITP_PINT_PINSTATE_PIQ2 2 /* Pin Interrupt 2 State */
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#define BITP_PINT_PINSTATE_PIQ1 1 /* Pin Interrupt 1 State */
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#define BITP_PINT_PINSTATE_PIQ0 0 /* Pin Interrupt 0 State */
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#define BITM_PINT_PINSTATE_PIQ31 (_ADI_MSK(0x80000000,uint32_t)) /* Pin Interrupt 31 State */
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#define BITM_PINT_PINSTATE_PIQ30 (_ADI_MSK(0x40000000,uint32_t)) /* Pin Interrupt 30 State */
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#define BITM_PINT_PINSTATE_PIQ29 (_ADI_MSK(0x20000000,uint32_t)) /* Pin Interrupt 29 State */
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#define BITM_PINT_PINSTATE_PIQ28 (_ADI_MSK(0x10000000,uint32_t)) /* Pin Interrupt 28 State */
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#define BITM_PINT_PINSTATE_PIQ27 (_ADI_MSK(0x08000000,uint32_t)) /* Pin Interrupt 27 State */
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#define BITM_PINT_PINSTATE_PIQ26 (_ADI_MSK(0x04000000,uint32_t)) /* Pin Interrupt 26 State */
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#define BITM_PINT_PINSTATE_PIQ25 (_ADI_MSK(0x02000000,uint32_t)) /* Pin Interrupt 25 State */
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#define BITM_PINT_PINSTATE_PIQ24 (_ADI_MSK(0x01000000,uint32_t)) /* Pin Interrupt 24 State */
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#define BITM_PINT_PINSTATE_PIQ23 (_ADI_MSK(0x00800000,uint32_t)) /* Pin Interrupt 23 State */
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#define BITM_PINT_PINSTATE_PIQ22 (_ADI_MSK(0x00400000,uint32_t)) /* Pin Interrupt 22 State */
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#define BITM_PINT_PINSTATE_PIQ21 (_ADI_MSK(0x00200000,uint32_t)) /* Pin Interrupt 21 State */
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#define BITM_PINT_PINSTATE_PIQ20 (_ADI_MSK(0x00100000,uint32_t)) /* Pin Interrupt 20 State */
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#define BITM_PINT_PINSTATE_PIQ19 (_ADI_MSK(0x00080000,uint32_t)) /* Pin Interrupt 19 State */
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#define BITM_PINT_PINSTATE_PIQ18 (_ADI_MSK(0x00040000,uint32_t)) /* Pin Interrupt 18 State */
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#define BITM_PINT_PINSTATE_PIQ17 (_ADI_MSK(0x00020000,uint32_t)) /* Pin Interrupt 17 State */
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#define BITM_PINT_PINSTATE_PIQ16 (_ADI_MSK(0x00010000,uint32_t)) /* Pin Interrupt 16 State */
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#define BITM_PINT_PINSTATE_PIQ15 (_ADI_MSK(0x00008000,uint32_t)) /* Pin Interrupt 15 State */
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#define BITM_PINT_PINSTATE_PIQ14 (_ADI_MSK(0x00004000,uint32_t)) /* Pin Interrupt 14 State */
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#define BITM_PINT_PINSTATE_PIQ13 (_ADI_MSK(0x00002000,uint32_t)) /* Pin Interrupt 13 State */
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#define BITM_PINT_PINSTATE_PIQ12 (_ADI_MSK(0x00001000,uint32_t)) /* Pin Interrupt 12 State */
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#define BITM_PINT_PINSTATE_PIQ11 (_ADI_MSK(0x00000800,uint32_t)) /* Pin Interrupt 11 State */
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#define BITM_PINT_PINSTATE_PIQ10 (_ADI_MSK(0x00000400,uint32_t)) /* Pin Interrupt 10 State */
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#define BITM_PINT_PINSTATE_PIQ9 (_ADI_MSK(0x00000200,uint32_t)) /* Pin Interrupt 9 State */
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#define BITM_PINT_PINSTATE_PIQ8 (_ADI_MSK(0x00000100,uint32_t)) /* Pin Interrupt 8 State */
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#define BITM_PINT_PINSTATE_PIQ7 (_ADI_MSK(0x00000080,uint32_t)) /* Pin Interrupt 7 State */
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#define BITM_PINT_PINSTATE_PIQ6 (_ADI_MSK(0x00000040,uint32_t)) /* Pin Interrupt 6 State */
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#define BITM_PINT_PINSTATE_PIQ5 (_ADI_MSK(0x00000020,uint32_t)) /* Pin Interrupt 5 State */
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#define BITM_PINT_PINSTATE_PIQ4 (_ADI_MSK(0x00000010,uint32_t)) /* Pin Interrupt 4 State */
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#define BITM_PINT_PINSTATE_PIQ3 (_ADI_MSK(0x00000008,uint32_t)) /* Pin Interrupt 3 State */
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#define BITM_PINT_PINSTATE_PIQ2 (_ADI_MSK(0x00000004,uint32_t)) /* Pin Interrupt 2 State */
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#define BITM_PINT_PINSTATE_PIQ1 (_ADI_MSK(0x00000002,uint32_t)) /* Pin Interrupt 1 State */
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#define BITM_PINT_PINSTATE_PIQ0 (_ADI_MSK(0x00000001,uint32_t)) /* Pin Interrupt 0 State */
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/* ------------------------------------------------------------------------------------------------------------------------
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PINT_LATCH Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_PINT_LATCH_PIQ31 31 /* Pin Interrupt 31 Latch */
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#define BITP_PINT_LATCH_PIQ30 30 /* Pin Interrupt 30 Latch */
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#define BITP_PINT_LATCH_PIQ29 29 /* Pin Interrupt 29 Latch */
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#define BITP_PINT_LATCH_PIQ28 28 /* Pin Interrupt 28 Latch */
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#define BITP_PINT_LATCH_PIQ27 27 /* Pin Interrupt 27 Latch */
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#define BITP_PINT_LATCH_PIQ26 26 /* Pin Interrupt 26 Latch */
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#define BITP_PINT_LATCH_PIQ25 25 /* Pin Interrupt 25 Latch */
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#define BITP_PINT_LATCH_PIQ24 24 /* Pin Interrupt 24 Latch */
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#define BITP_PINT_LATCH_PIQ23 23 /* Pin Interrupt 23 Latch */
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#define BITP_PINT_LATCH_PIQ22 22 /* Pin Interrupt 22 Latch */
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#define BITP_PINT_LATCH_PIQ21 21 /* Pin Interrupt 21 Latch */
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#define BITP_PINT_LATCH_PIQ20 20 /* Pin Interrupt 20 Latch */
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#define BITP_PINT_LATCH_PIQ19 19 /* Pin Interrupt 19 Latch */
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#define BITP_PINT_LATCH_PIQ18 18 /* Pin Interrupt 18 Latch */
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#define BITP_PINT_LATCH_PIQ17 17 /* Pin Interrupt 17 Latch */
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#define BITP_PINT_LATCH_PIQ16 16 /* Pin Interrupt 16 Latch */
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#define BITP_PINT_LATCH_PIQ15 15 /* Pin Interrupt 15 Latch */
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#define BITP_PINT_LATCH_PIQ14 14 /* Pin Interrupt 14 Latch */
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#define BITP_PINT_LATCH_PIQ13 13 /* Pin Interrupt 13 Latch */
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#define BITP_PINT_LATCH_PIQ12 12 /* Pin Interrupt 12 Latch */
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#define BITP_PINT_LATCH_PIQ11 11 /* Pin Interrupt 11 Latch */
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#define BITP_PINT_LATCH_PIQ10 10 /* Pin Interrupt 10 Latch */
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#define BITP_PINT_LATCH_PIQ9 9 /* Pin Interrupt 9 Latch */
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#define BITP_PINT_LATCH_PIQ8 8 /* Pin Interrupt 8 Latch */
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#define BITP_PINT_LATCH_PIQ7 7 /* Pin Interrupt 7 Latch */
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#define BITP_PINT_LATCH_PIQ6 6 /* Pin Interrupt 6 Latch */
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#define BITP_PINT_LATCH_PIQ5 5 /* Pin Interrupt 5 Latch */
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#define BITP_PINT_LATCH_PIQ4 4 /* Pin Interrupt 4 Latch */
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#define BITP_PINT_LATCH_PIQ3 3 /* Pin Interrupt 3 Latch */
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#define BITP_PINT_LATCH_PIQ2 2 /* Pin Interrupt 2 Latch */
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#define BITP_PINT_LATCH_PIQ1 1 /* Pin Interrupt 1 Latch */
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#define BITP_PINT_LATCH_PIQ0 0 /* Pin Interrupt 0 Latch */
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#define BITM_PINT_LATCH_PIQ31 (_ADI_MSK(0x80000000,uint32_t)) /* Pin Interrupt 31 Latch */
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#define BITM_PINT_LATCH_PIQ30 (_ADI_MSK(0x40000000,uint32_t)) /* Pin Interrupt 30 Latch */
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#define BITM_PINT_LATCH_PIQ29 (_ADI_MSK(0x20000000,uint32_t)) /* Pin Interrupt 29 Latch */
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#define BITM_PINT_LATCH_PIQ28 (_ADI_MSK(0x10000000,uint32_t)) /* Pin Interrupt 28 Latch */
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#define BITM_PINT_LATCH_PIQ27 (_ADI_MSK(0x08000000,uint32_t)) /* Pin Interrupt 27 Latch */
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#define BITM_PINT_LATCH_PIQ26 (_ADI_MSK(0x04000000,uint32_t)) /* Pin Interrupt 26 Latch */
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#define BITM_PINT_LATCH_PIQ25 (_ADI_MSK(0x02000000,uint32_t)) /* Pin Interrupt 25 Latch */
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#define BITM_PINT_LATCH_PIQ24 (_ADI_MSK(0x01000000,uint32_t)) /* Pin Interrupt 24 Latch */
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#define BITM_PINT_LATCH_PIQ23 (_ADI_MSK(0x00800000,uint32_t)) /* Pin Interrupt 23 Latch */
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#define BITM_PINT_LATCH_PIQ22 (_ADI_MSK(0x00400000,uint32_t)) /* Pin Interrupt 22 Latch */
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#define BITM_PINT_LATCH_PIQ21 (_ADI_MSK(0x00200000,uint32_t)) /* Pin Interrupt 21 Latch */
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#define BITM_PINT_LATCH_PIQ20 (_ADI_MSK(0x00100000,uint32_t)) /* Pin Interrupt 20 Latch */
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#define BITM_PINT_LATCH_PIQ19 (_ADI_MSK(0x00080000,uint32_t)) /* Pin Interrupt 19 Latch */
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#define BITM_PINT_LATCH_PIQ18 (_ADI_MSK(0x00040000,uint32_t)) /* Pin Interrupt 18 Latch */
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#define BITM_PINT_LATCH_PIQ17 (_ADI_MSK(0x00020000,uint32_t)) /* Pin Interrupt 17 Latch */
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#define BITM_PINT_LATCH_PIQ16 (_ADI_MSK(0x00010000,uint32_t)) /* Pin Interrupt 16 Latch */
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#define BITM_PINT_LATCH_PIQ15 (_ADI_MSK(0x00008000,uint32_t)) /* Pin Interrupt 15 Latch */
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#define BITM_PINT_LATCH_PIQ14 (_ADI_MSK(0x00004000,uint32_t)) /* Pin Interrupt 14 Latch */
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#define BITM_PINT_LATCH_PIQ13 (_ADI_MSK(0x00002000,uint32_t)) /* Pin Interrupt 13 Latch */
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#define BITM_PINT_LATCH_PIQ12 (_ADI_MSK(0x00001000,uint32_t)) /* Pin Interrupt 12 Latch */
|
|
#define BITM_PINT_LATCH_PIQ11 (_ADI_MSK(0x00000800,uint32_t)) /* Pin Interrupt 11 Latch */
|
|
#define BITM_PINT_LATCH_PIQ10 (_ADI_MSK(0x00000400,uint32_t)) /* Pin Interrupt 10 Latch */
|
|
#define BITM_PINT_LATCH_PIQ9 (_ADI_MSK(0x00000200,uint32_t)) /* Pin Interrupt 9 Latch */
|
|
#define BITM_PINT_LATCH_PIQ8 (_ADI_MSK(0x00000100,uint32_t)) /* Pin Interrupt 8 Latch */
|
|
#define BITM_PINT_LATCH_PIQ7 (_ADI_MSK(0x00000080,uint32_t)) /* Pin Interrupt 7 Latch */
|
|
#define BITM_PINT_LATCH_PIQ6 (_ADI_MSK(0x00000040,uint32_t)) /* Pin Interrupt 6 Latch */
|
|
#define BITM_PINT_LATCH_PIQ5 (_ADI_MSK(0x00000020,uint32_t)) /* Pin Interrupt 5 Latch */
|
|
#define BITM_PINT_LATCH_PIQ4 (_ADI_MSK(0x00000010,uint32_t)) /* Pin Interrupt 4 Latch */
|
|
#define BITM_PINT_LATCH_PIQ3 (_ADI_MSK(0x00000008,uint32_t)) /* Pin Interrupt 3 Latch */
|
|
#define BITM_PINT_LATCH_PIQ2 (_ADI_MSK(0x00000004,uint32_t)) /* Pin Interrupt 2 Latch */
|
|
#define BITM_PINT_LATCH_PIQ1 (_ADI_MSK(0x00000002,uint32_t)) /* Pin Interrupt 1 Latch */
|
|
#define BITM_PINT_LATCH_PIQ0 (_ADI_MSK(0x00000001,uint32_t)) /* Pin Interrupt 0 Latch */
|
|
|
|
/* ==================================================
|
|
Static Memory Controller Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
SMC0
|
|
========================= */
|
|
#define REG_SMC0_GCTL 0xFFC16004 /* SMC0 Grant Control Register */
|
|
#define REG_SMC0_GSTAT 0xFFC16008 /* SMC0 Grant Status Register */
|
|
#define REG_SMC0_B0CTL 0xFFC1600C /* SMC0 Bank 0 Control Register */
|
|
#define REG_SMC0_B0TIM 0xFFC16010 /* SMC0 Bank 0 Timing Register */
|
|
#define REG_SMC0_B0ETIM 0xFFC16014 /* SMC0 Bank 0 Extended Timing Register */
|
|
#define REG_SMC0_B1CTL 0xFFC1601C /* SMC0 Bank 1 Control Register */
|
|
#define REG_SMC0_B1TIM 0xFFC16020 /* SMC0 Bank 1 Timing Register */
|
|
#define REG_SMC0_B1ETIM 0xFFC16024 /* SMC0 Bank 1 Extended Timing Register */
|
|
#define REG_SMC0_B2CTL 0xFFC1602C /* SMC0 Bank 2 Control Register */
|
|
#define REG_SMC0_B2TIM 0xFFC16030 /* SMC0 Bank 2 Timing Register */
|
|
#define REG_SMC0_B2ETIM 0xFFC16034 /* SMC0 Bank 2 Extended Timing Register */
|
|
#define REG_SMC0_B3CTL 0xFFC1603C /* SMC0 Bank 3 Control Register */
|
|
#define REG_SMC0_B3TIM 0xFFC16040 /* SMC0 Bank 3 Timing Register */
|
|
#define REG_SMC0_B3ETIM 0xFFC16044 /* SMC0 Bank 3 Extended Timing Register */
|
|
|
|
/* =========================
|
|
SMC
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SMC_GCTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SMC_GCTL_BGDIS 4 /* Bus Grant Disable */
|
|
#define BITM_SMC_GCTL_BGDIS (_ADI_MSK(0x00000010,uint32_t)) /* Bus Grant Disable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SMC_GSTAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SMC_GSTAT_BGHSTAT 2 /* Bus Grant Hold Status */
|
|
#define BITP_SMC_GSTAT_BRQSTAT 1 /* Bus Request Status */
|
|
#define BITP_SMC_GSTAT_BGSTAT 0 /* Bus Grant Status */
|
|
#define BITM_SMC_GSTAT_BGHSTAT (_ADI_MSK(0x00000004,uint32_t)) /* Bus Grant Hold Status */
|
|
#define BITM_SMC_GSTAT_BRQSTAT (_ADI_MSK(0x00000002,uint32_t)) /* Bus Request Status */
|
|
#define BITM_SMC_GSTAT_BGSTAT (_ADI_MSK(0x00000001,uint32_t)) /* Bus Grant Status */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SMC_B0CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SMC_B0CTL_BTYPE 26 /* Burst Type for Flash */
|
|
#define BITP_SMC_B0CTL_BCLK 24 /* Burst Clock Frequency Divisor */
|
|
#define BITP_SMC_B0CTL_PGSZ 20 /* Flash Page Size */
|
|
#define BITP_SMC_B0CTL_RDYABTEN 14 /* ARDY Abort Enable */
|
|
#define BITP_SMC_B0CTL_RDYPOL 13 /* ARDY Polarity */
|
|
#define BITP_SMC_B0CTL_RDYEN 12 /* ARDY Enable */
|
|
#define BITP_SMC_B0CTL_SELCTRL 8 /* Select Control */
|
|
#define BITP_SMC_B0CTL_MODE 4 /* Memory Access Mode */
|
|
#define BITP_SMC_B0CTL_EN 0 /* Bank 0 Enable */
|
|
#define BITM_SMC_B0CTL_BTYPE (_ADI_MSK(0x04000000,uint32_t)) /* Burst Type for Flash */
|
|
#define BITM_SMC_B0CTL_BCLK (_ADI_MSK(0x03000000,uint32_t)) /* Burst Clock Frequency Divisor */
|
|
#define BITM_SMC_B0CTL_PGSZ (_ADI_MSK(0x00300000,uint32_t)) /* Flash Page Size */
|
|
#define BITM_SMC_B0CTL_RDYABTEN (_ADI_MSK(0x00004000,uint32_t)) /* ARDY Abort Enable */
|
|
#define BITM_SMC_B0CTL_RDYPOL (_ADI_MSK(0x00002000,uint32_t)) /* ARDY Polarity */
|
|
#define BITM_SMC_B0CTL_RDYEN (_ADI_MSK(0x00001000,uint32_t)) /* ARDY Enable */
|
|
#define BITM_SMC_B0CTL_SELCTRL (_ADI_MSK(0x00000300,uint32_t)) /* Select Control */
|
|
#define BITM_SMC_B0CTL_MODE (_ADI_MSK(0x00000030,uint32_t)) /* Memory Access Mode */
|
|
#define BITM_SMC_B0CTL_EN (_ADI_MSK(0x00000001,uint32_t)) /* Bank 0 Enable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SMC_B0TIM Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SMC_B0TIM_RAT 24 /* Read Access Time */
|
|
#define BITP_SMC_B0TIM_RHT 20 /* Read Hold Time */
|
|
#define BITP_SMC_B0TIM_RST 16 /* Read Setup Time */
|
|
#define BITP_SMC_B0TIM_WAT 8 /* Write Access Time */
|
|
#define BITP_SMC_B0TIM_WHT 4 /* Write Hold Time */
|
|
#define BITP_SMC_B0TIM_WST 0 /* Write Setup Time */
|
|
#define BITM_SMC_B0TIM_RAT (_ADI_MSK(0x3F000000,uint32_t)) /* Read Access Time */
|
|
#define BITM_SMC_B0TIM_RHT (_ADI_MSK(0x00700000,uint32_t)) /* Read Hold Time */
|
|
#define BITM_SMC_B0TIM_RST (_ADI_MSK(0x00070000,uint32_t)) /* Read Setup Time */
|
|
#define BITM_SMC_B0TIM_WAT (_ADI_MSK(0x00003F00,uint32_t)) /* Write Access Time */
|
|
#define BITM_SMC_B0TIM_WHT (_ADI_MSK(0x00000070,uint32_t)) /* Write Hold Time */
|
|
#define BITM_SMC_B0TIM_WST (_ADI_MSK(0x00000007,uint32_t)) /* Write Setup Time */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SMC_B0ETIM Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SMC_B0ETIM_PGWS 16 /* Page Wait States */
|
|
#define BITP_SMC_B0ETIM_IT 12 /* Idle Time */
|
|
#define BITP_SMC_B0ETIM_TT 8 /* Transition Time */
|
|
#define BITP_SMC_B0ETIM_PREAT 4 /* Pre Access Time */
|
|
#define BITP_SMC_B0ETIM_PREST 0 /* Pre Setup Time */
|
|
#define BITM_SMC_B0ETIM_PGWS (_ADI_MSK(0x000F0000,uint32_t)) /* Page Wait States */
|
|
#define BITM_SMC_B0ETIM_IT (_ADI_MSK(0x00007000,uint32_t)) /* Idle Time */
|
|
#define BITM_SMC_B0ETIM_TT (_ADI_MSK(0x00000700,uint32_t)) /* Transition Time */
|
|
#define BITM_SMC_B0ETIM_PREAT (_ADI_MSK(0x00000030,uint32_t)) /* Pre Access Time */
|
|
#define BITM_SMC_B0ETIM_PREST (_ADI_MSK(0x00000003,uint32_t)) /* Pre Setup Time */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SMC_B1CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SMC_B1CTL_BTYPE 26 /* Burst Type for Flash */
|
|
#define BITP_SMC_B1CTL_BCLK 24 /* Burst Clock Frequency Divisor */
|
|
#define BITP_SMC_B1CTL_PGSZ 20 /* Flash Page Size */
|
|
#define BITP_SMC_B1CTL_RDYABTEN 14 /* ARDY Abort Enable */
|
|
#define BITP_SMC_B1CTL_RDYPOL 13 /* ARDY Polarity */
|
|
#define BITP_SMC_B1CTL_RDYEN 12 /* ARDY Enable */
|
|
#define BITP_SMC_B1CTL_SELCTRL 8 /* Select Control */
|
|
#define BITP_SMC_B1CTL_MODE 4 /* Memory Access Mode */
|
|
#define BITP_SMC_B1CTL_EN 0 /* Bank 1 Enable */
|
|
#define BITM_SMC_B1CTL_BTYPE (_ADI_MSK(0x04000000,uint32_t)) /* Burst Type for Flash */
|
|
#define BITM_SMC_B1CTL_BCLK (_ADI_MSK(0x03000000,uint32_t)) /* Burst Clock Frequency Divisor */
|
|
#define BITM_SMC_B1CTL_PGSZ (_ADI_MSK(0x00300000,uint32_t)) /* Flash Page Size */
|
|
#define BITM_SMC_B1CTL_RDYABTEN (_ADI_MSK(0x00004000,uint32_t)) /* ARDY Abort Enable */
|
|
#define BITM_SMC_B1CTL_RDYPOL (_ADI_MSK(0x00002000,uint32_t)) /* ARDY Polarity */
|
|
#define BITM_SMC_B1CTL_RDYEN (_ADI_MSK(0x00001000,uint32_t)) /* ARDY Enable */
|
|
#define BITM_SMC_B1CTL_SELCTRL (_ADI_MSK(0x00000300,uint32_t)) /* Select Control */
|
|
#define BITM_SMC_B1CTL_MODE (_ADI_MSK(0x00000030,uint32_t)) /* Memory Access Mode */
|
|
#define BITM_SMC_B1CTL_EN (_ADI_MSK(0x00000001,uint32_t)) /* Bank 1 Enable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SMC_B1TIM Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SMC_B1TIM_RAT 24 /* Read Access Time */
|
|
#define BITP_SMC_B1TIM_RHT 20 /* Read Hold Time */
|
|
#define BITP_SMC_B1TIM_RST 16 /* Read Setup Time */
|
|
#define BITP_SMC_B1TIM_WAT 8 /* Write Access Time */
|
|
#define BITP_SMC_B1TIM_WHT 4 /* Write Hold Time */
|
|
#define BITP_SMC_B1TIM_WST 0 /* Write Setup Time */
|
|
#define BITM_SMC_B1TIM_RAT (_ADI_MSK(0x3F000000,uint32_t)) /* Read Access Time */
|
|
#define BITM_SMC_B1TIM_RHT (_ADI_MSK(0x00700000,uint32_t)) /* Read Hold Time */
|
|
#define BITM_SMC_B1TIM_RST (_ADI_MSK(0x00070000,uint32_t)) /* Read Setup Time */
|
|
#define BITM_SMC_B1TIM_WAT (_ADI_MSK(0x00003F00,uint32_t)) /* Write Access Time */
|
|
#define BITM_SMC_B1TIM_WHT (_ADI_MSK(0x00000070,uint32_t)) /* Write Hold Time */
|
|
#define BITM_SMC_B1TIM_WST (_ADI_MSK(0x00000007,uint32_t)) /* Write Setup Time */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SMC_B1ETIM Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SMC_B1ETIM_PGWS 16 /* Page Wait States */
|
|
#define BITP_SMC_B1ETIM_IT 12 /* Idle Time */
|
|
#define BITP_SMC_B1ETIM_TT 8 /* Transition Time */
|
|
#define BITP_SMC_B1ETIM_PREAT 4 /* Pre Access Time */
|
|
#define BITP_SMC_B1ETIM_PREST 0 /* Pre Setup Time */
|
|
#define BITM_SMC_B1ETIM_PGWS (_ADI_MSK(0x000F0000,uint32_t)) /* Page Wait States */
|
|
#define BITM_SMC_B1ETIM_IT (_ADI_MSK(0x00007000,uint32_t)) /* Idle Time */
|
|
#define BITM_SMC_B1ETIM_TT (_ADI_MSK(0x00000700,uint32_t)) /* Transition Time */
|
|
#define BITM_SMC_B1ETIM_PREAT (_ADI_MSK(0x00000030,uint32_t)) /* Pre Access Time */
|
|
#define BITM_SMC_B1ETIM_PREST (_ADI_MSK(0x00000003,uint32_t)) /* Pre Setup Time */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SMC_B2CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SMC_B2CTL_BTYPE 26 /* Burst Type for Flash */
|
|
#define BITP_SMC_B2CTL_BCLK 24 /* Burst Clock Frequency Divisor */
|
|
#define BITP_SMC_B2CTL_PGSZ 20 /* Flash Page Size */
|
|
#define BITP_SMC_B2CTL_RDYABTEN 14 /* ARDY Abort Enable */
|
|
#define BITP_SMC_B2CTL_RDYPOL 13 /* ARDY Polarity */
|
|
#define BITP_SMC_B2CTL_RDYEN 12 /* ARDY Enable */
|
|
#define BITP_SMC_B2CTL_SELCTRL 8 /* Select Control */
|
|
#define BITP_SMC_B2CTL_MODE 4 /* Memory Access Mode */
|
|
#define BITP_SMC_B2CTL_EN 0 /* Bank 2 Enable */
|
|
#define BITM_SMC_B2CTL_BTYPE (_ADI_MSK(0x04000000,uint32_t)) /* Burst Type for Flash */
|
|
#define BITM_SMC_B2CTL_BCLK (_ADI_MSK(0x03000000,uint32_t)) /* Burst Clock Frequency Divisor */
|
|
#define BITM_SMC_B2CTL_PGSZ (_ADI_MSK(0x00300000,uint32_t)) /* Flash Page Size */
|
|
#define BITM_SMC_B2CTL_RDYABTEN (_ADI_MSK(0x00004000,uint32_t)) /* ARDY Abort Enable */
|
|
#define BITM_SMC_B2CTL_RDYPOL (_ADI_MSK(0x00002000,uint32_t)) /* ARDY Polarity */
|
|
#define BITM_SMC_B2CTL_RDYEN (_ADI_MSK(0x00001000,uint32_t)) /* ARDY Enable */
|
|
#define BITM_SMC_B2CTL_SELCTRL (_ADI_MSK(0x00000300,uint32_t)) /* Select Control */
|
|
#define BITM_SMC_B2CTL_MODE (_ADI_MSK(0x00000030,uint32_t)) /* Memory Access Mode */
|
|
#define BITM_SMC_B2CTL_EN (_ADI_MSK(0x00000001,uint32_t)) /* Bank 2 Enable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SMC_B2TIM Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SMC_B2TIM_RAT 24 /* Read Access Time */
|
|
#define BITP_SMC_B2TIM_RHT 20 /* Read Hold Time */
|
|
#define BITP_SMC_B2TIM_RST 16 /* Read Setup Time */
|
|
#define BITP_SMC_B2TIM_WAT 8 /* Write Access Time */
|
|
#define BITP_SMC_B2TIM_WHT 4 /* Write Hold Time */
|
|
#define BITP_SMC_B2TIM_WST 0 /* Write Setup Time */
|
|
#define BITM_SMC_B2TIM_RAT (_ADI_MSK(0x3F000000,uint32_t)) /* Read Access Time */
|
|
#define BITM_SMC_B2TIM_RHT (_ADI_MSK(0x00700000,uint32_t)) /* Read Hold Time */
|
|
#define BITM_SMC_B2TIM_RST (_ADI_MSK(0x00070000,uint32_t)) /* Read Setup Time */
|
|
#define BITM_SMC_B2TIM_WAT (_ADI_MSK(0x00003F00,uint32_t)) /* Write Access Time */
|
|
#define BITM_SMC_B2TIM_WHT (_ADI_MSK(0x00000070,uint32_t)) /* Write Hold Time */
|
|
#define BITM_SMC_B2TIM_WST (_ADI_MSK(0x00000007,uint32_t)) /* Write Setup Time */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SMC_B2ETIM Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SMC_B2ETIM_PGWS 16 /* Page Wait States */
|
|
#define BITP_SMC_B2ETIM_IT 12 /* Idle Time */
|
|
#define BITP_SMC_B2ETIM_TT 8 /* Transition Time */
|
|
#define BITP_SMC_B2ETIM_PREAT 4 /* Pre Access Time */
|
|
#define BITP_SMC_B2ETIM_PREST 0 /* Pre Setup Time */
|
|
#define BITM_SMC_B2ETIM_PGWS (_ADI_MSK(0x000F0000,uint32_t)) /* Page Wait States */
|
|
#define BITM_SMC_B2ETIM_IT (_ADI_MSK(0x00007000,uint32_t)) /* Idle Time */
|
|
#define BITM_SMC_B2ETIM_TT (_ADI_MSK(0x00000700,uint32_t)) /* Transition Time */
|
|
#define BITM_SMC_B2ETIM_PREAT (_ADI_MSK(0x00000030,uint32_t)) /* Pre Access Time */
|
|
#define BITM_SMC_B2ETIM_PREST (_ADI_MSK(0x00000003,uint32_t)) /* Pre Setup Time */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SMC_B3CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SMC_B3CTL_BTYPE 26 /* Burst Type for Flash */
|
|
#define BITP_SMC_B3CTL_BCLK 24 /* Burst Clock Frequency Divisor */
|
|
#define BITP_SMC_B3CTL_PGSZ 20 /* Flash Page Size */
|
|
#define BITP_SMC_B3CTL_RDYABTEN 14 /* ARDY Abort Enable */
|
|
#define BITP_SMC_B3CTL_RDYPOL 13 /* ARDY Polarity */
|
|
#define BITP_SMC_B3CTL_RDYEN 12 /* ARDY Enable */
|
|
#define BITP_SMC_B3CTL_SELCTRL 8 /* Select Control */
|
|
#define BITP_SMC_B3CTL_MODE 4 /* Memory Access Mode */
|
|
#define BITP_SMC_B3CTL_EN 0 /* Bank 3 Enable */
|
|
#define BITM_SMC_B3CTL_BTYPE (_ADI_MSK(0x04000000,uint32_t)) /* Burst Type for Flash */
|
|
#define BITM_SMC_B3CTL_BCLK (_ADI_MSK(0x03000000,uint32_t)) /* Burst Clock Frequency Divisor */
|
|
#define BITM_SMC_B3CTL_PGSZ (_ADI_MSK(0x00300000,uint32_t)) /* Flash Page Size */
|
|
#define BITM_SMC_B3CTL_RDYABTEN (_ADI_MSK(0x00004000,uint32_t)) /* ARDY Abort Enable */
|
|
#define BITM_SMC_B3CTL_RDYPOL (_ADI_MSK(0x00002000,uint32_t)) /* ARDY Polarity */
|
|
#define BITM_SMC_B3CTL_RDYEN (_ADI_MSK(0x00001000,uint32_t)) /* ARDY Enable */
|
|
#define BITM_SMC_B3CTL_SELCTRL (_ADI_MSK(0x00000300,uint32_t)) /* Select Control */
|
|
#define BITM_SMC_B3CTL_MODE (_ADI_MSK(0x00000030,uint32_t)) /* Memory Access Mode */
|
|
#define BITM_SMC_B3CTL_EN (_ADI_MSK(0x00000001,uint32_t)) /* Bank 3 Enable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SMC_B3TIM Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SMC_B3TIM_RAT 24 /* Read Access Time */
|
|
#define BITP_SMC_B3TIM_RHT 20 /* Read Hold Time */
|
|
#define BITP_SMC_B3TIM_RST 16 /* Read Setup Time */
|
|
#define BITP_SMC_B3TIM_WAT 8 /* Write Access Time */
|
|
#define BITP_SMC_B3TIM_WHT 4 /* Write Hold Time */
|
|
#define BITP_SMC_B3TIM_WST 0 /* Write Setup Time */
|
|
#define BITM_SMC_B3TIM_RAT (_ADI_MSK(0x3F000000,uint32_t)) /* Read Access Time */
|
|
#define BITM_SMC_B3TIM_RHT (_ADI_MSK(0x00700000,uint32_t)) /* Read Hold Time */
|
|
#define BITM_SMC_B3TIM_RST (_ADI_MSK(0x00070000,uint32_t)) /* Read Setup Time */
|
|
#define BITM_SMC_B3TIM_WAT (_ADI_MSK(0x00003F00,uint32_t)) /* Write Access Time */
|
|
#define BITM_SMC_B3TIM_WHT (_ADI_MSK(0x00000070,uint32_t)) /* Write Hold Time */
|
|
#define BITM_SMC_B3TIM_WST (_ADI_MSK(0x00000007,uint32_t)) /* Write Setup Time */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SMC_B3ETIM Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SMC_B3ETIM_PGWS 16 /* Page Wait States */
|
|
#define BITP_SMC_B3ETIM_IT 12 /* Idle Time */
|
|
#define BITP_SMC_B3ETIM_TT 8 /* Transition Time */
|
|
#define BITP_SMC_B3ETIM_PREAT 4 /* Pre Access Time */
|
|
#define BITP_SMC_B3ETIM_PREST 0 /* Pre Setup Time */
|
|
#define BITM_SMC_B3ETIM_PGWS (_ADI_MSK(0x000F0000,uint32_t)) /* Page Wait States */
|
|
#define BITM_SMC_B3ETIM_IT (_ADI_MSK(0x00007000,uint32_t)) /* Idle Time */
|
|
#define BITM_SMC_B3ETIM_TT (_ADI_MSK(0x00000700,uint32_t)) /* Transition Time */
|
|
#define BITM_SMC_B3ETIM_PREAT (_ADI_MSK(0x00000030,uint32_t)) /* Pre Access Time */
|
|
#define BITM_SMC_B3ETIM_PREST (_ADI_MSK(0x00000003,uint32_t)) /* Pre Setup Time */
|
|
|
|
/* ==================================================
|
|
Watch Dog Timer Unit Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
WDOG0
|
|
========================= */
|
|
#define REG_WDOG0_CTL 0xFFC17000 /* WDOG0 Control Register */
|
|
#define REG_WDOG0_CNT 0xFFC17004 /* WDOG0 Count Register */
|
|
#define REG_WDOG0_STAT 0xFFC17008 /* WDOG0 Watchdog Timer Status Register */
|
|
|
|
/* =========================
|
|
WDOG1
|
|
========================= */
|
|
#define REG_WDOG1_CTL 0xFFC17800 /* WDOG1 Control Register */
|
|
#define REG_WDOG1_CNT 0xFFC17804 /* WDOG1 Count Register */
|
|
#define REG_WDOG1_STAT 0xFFC17808 /* WDOG1 Watchdog Timer Status Register */
|
|
|
|
/* =========================
|
|
WDOG
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
WDOG_CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_WDOG_CTL_WDRO 15 /* Watch Dog Rollover */
|
|
#define BITP_WDOG_CTL_WDEN 4 /* Watch Dog Enable */
|
|
|
|
#define BITM_WDOG_CTL_WDRO (_ADI_MSK(0x00008000,uint32_t)) /* Watch Dog Rollover */
|
|
#define ENUM_WDOG_CTL_WDTEXP (_ADI_MSK(0x00008000,uint32_t)) /* WDRO: WDT has expired */
|
|
#define BITM_WDOG_CTL_WDEN (_ADI_MSK(0x00000FF0,uint32_t)) /* Watch Dog Enable */
|
|
|
|
/* ==================================================
|
|
EPPI Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
EPPI0
|
|
========================= */
|
|
#define REG_EPPI0_STAT 0xFFC18000 /* EPPI0 Status Register */
|
|
#define REG_EPPI0_HCNT 0xFFC18004 /* EPPI0 Horizontal Transfer Count Register */
|
|
#define REG_EPPI0_HDLY 0xFFC18008 /* EPPI0 Horizontal Delay Count Register */
|
|
#define REG_EPPI0_VCNT 0xFFC1800C /* EPPI0 Vertical Transfer Count Register */
|
|
#define REG_EPPI0_VDLY 0xFFC18010 /* EPPI0 Vertical Delay Count Register */
|
|
#define REG_EPPI0_FRAME 0xFFC18014 /* EPPI0 Lines Per Frame Register */
|
|
#define REG_EPPI0_LINE 0xFFC18018 /* EPPI0 Samples Per Line Register */
|
|
#define REG_EPPI0_CLKDIV 0xFFC1801C /* EPPI0 Clock Divide Register */
|
|
#define REG_EPPI0_CTL 0xFFC18020 /* EPPI0 Control Register */
|
|
#define REG_EPPI0_FS1_WLHB 0xFFC18024 /* EPPI0 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
|
|
#define REG_EPPI0_FS1_PASPL 0xFFC18028 /* EPPI0 FS1 Period Register / EPPI Active Samples Per Line Register */
|
|
#define REG_EPPI0_FS2_WLVB 0xFFC1802C /* EPPI0 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
|
|
#define REG_EPPI0_FS2_PALPF 0xFFC18030 /* EPPI0 FS2 Period Register / EPPI Active Lines Per Field Register */
|
|
#define REG_EPPI0_IMSK 0xFFC18034 /* EPPI0 Interrupt Mask Register */
|
|
#define REG_EPPI0_ODDCLIP 0xFFC1803C /* EPPI0 Clipping Register for ODD (Chroma) Data */
|
|
#define REG_EPPI0_EVENCLIP 0xFFC18040 /* EPPI0 Clipping Register for EVEN (Luma) Data */
|
|
#define REG_EPPI0_FS1_DLY 0xFFC18044 /* EPPI0 Frame Sync 1 Delay Value */
|
|
#define REG_EPPI0_FS2_DLY 0xFFC18048 /* EPPI0 Frame Sync 2 Delay Value */
|
|
#define REG_EPPI0_CTL2 0xFFC1804C /* EPPI0 Control Register 2 */
|
|
|
|
/* =========================
|
|
EPPI1
|
|
========================= */
|
|
#define REG_EPPI1_STAT 0xFFC18400 /* EPPI1 Status Register */
|
|
#define REG_EPPI1_HCNT 0xFFC18404 /* EPPI1 Horizontal Transfer Count Register */
|
|
#define REG_EPPI1_HDLY 0xFFC18408 /* EPPI1 Horizontal Delay Count Register */
|
|
#define REG_EPPI1_VCNT 0xFFC1840C /* EPPI1 Vertical Transfer Count Register */
|
|
#define REG_EPPI1_VDLY 0xFFC18410 /* EPPI1 Vertical Delay Count Register */
|
|
#define REG_EPPI1_FRAME 0xFFC18414 /* EPPI1 Lines Per Frame Register */
|
|
#define REG_EPPI1_LINE 0xFFC18418 /* EPPI1 Samples Per Line Register */
|
|
#define REG_EPPI1_CLKDIV 0xFFC1841C /* EPPI1 Clock Divide Register */
|
|
#define REG_EPPI1_CTL 0xFFC18420 /* EPPI1 Control Register */
|
|
#define REG_EPPI1_FS1_WLHB 0xFFC18424 /* EPPI1 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
|
|
#define REG_EPPI1_FS1_PASPL 0xFFC18428 /* EPPI1 FS1 Period Register / EPPI Active Samples Per Line Register */
|
|
#define REG_EPPI1_FS2_WLVB 0xFFC1842C /* EPPI1 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
|
|
#define REG_EPPI1_FS2_PALPF 0xFFC18430 /* EPPI1 FS2 Period Register / EPPI Active Lines Per Field Register */
|
|
#define REG_EPPI1_IMSK 0xFFC18434 /* EPPI1 Interrupt Mask Register */
|
|
#define REG_EPPI1_ODDCLIP 0xFFC1843C /* EPPI1 Clipping Register for ODD (Chroma) Data */
|
|
#define REG_EPPI1_EVENCLIP 0xFFC18440 /* EPPI1 Clipping Register for EVEN (Luma) Data */
|
|
#define REG_EPPI1_FS1_DLY 0xFFC18444 /* EPPI1 Frame Sync 1 Delay Value */
|
|
#define REG_EPPI1_FS2_DLY 0xFFC18448 /* EPPI1 Frame Sync 2 Delay Value */
|
|
#define REG_EPPI1_CTL2 0xFFC1844C /* EPPI1 Control Register 2 */
|
|
|
|
/* =========================
|
|
EPPI2
|
|
========================= */
|
|
#define REG_EPPI2_STAT 0xFFC18800 /* EPPI2 Status Register */
|
|
#define REG_EPPI2_HCNT 0xFFC18804 /* EPPI2 Horizontal Transfer Count Register */
|
|
#define REG_EPPI2_HDLY 0xFFC18808 /* EPPI2 Horizontal Delay Count Register */
|
|
#define REG_EPPI2_VCNT 0xFFC1880C /* EPPI2 Vertical Transfer Count Register */
|
|
#define REG_EPPI2_VDLY 0xFFC18810 /* EPPI2 Vertical Delay Count Register */
|
|
#define REG_EPPI2_FRAME 0xFFC18814 /* EPPI2 Lines Per Frame Register */
|
|
#define REG_EPPI2_LINE 0xFFC18818 /* EPPI2 Samples Per Line Register */
|
|
#define REG_EPPI2_CLKDIV 0xFFC1881C /* EPPI2 Clock Divide Register */
|
|
#define REG_EPPI2_CTL 0xFFC18820 /* EPPI2 Control Register */
|
|
#define REG_EPPI2_FS1_WLHB 0xFFC18824 /* EPPI2 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
|
|
#define REG_EPPI2_FS1_PASPL 0xFFC18828 /* EPPI2 FS1 Period Register / EPPI Active Samples Per Line Register */
|
|
#define REG_EPPI2_FS2_WLVB 0xFFC1882C /* EPPI2 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
|
|
#define REG_EPPI2_FS2_PALPF 0xFFC18830 /* EPPI2 FS2 Period Register / EPPI Active Lines Per Field Register */
|
|
#define REG_EPPI2_IMSK 0xFFC18834 /* EPPI2 Interrupt Mask Register */
|
|
#define REG_EPPI2_ODDCLIP 0xFFC1883C /* EPPI2 Clipping Register for ODD (Chroma) Data */
|
|
#define REG_EPPI2_EVENCLIP 0xFFC18840 /* EPPI2 Clipping Register for EVEN (Luma) Data */
|
|
#define REG_EPPI2_FS1_DLY 0xFFC18844 /* EPPI2 Frame Sync 1 Delay Value */
|
|
#define REG_EPPI2_FS2_DLY 0xFFC18848 /* EPPI2 Frame Sync 2 Delay Value */
|
|
#define REG_EPPI2_CTL2 0xFFC1884C /* EPPI2 Control Register 2 */
|
|
|
|
/* =========================
|
|
EPPI
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EPPI_STAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EPPI_STAT_FLD 15 /* Current Field Received by EPPI */
|
|
#define BITP_EPPI_STAT_ERRDET 14 /* Preamble Error Detected */
|
|
#define BITP_EPPI_STAT_PXPERR 7 /* PxP Ready Error */
|
|
#define BITP_EPPI_STAT_ERRNCOR 6 /* Preamble Error Not Corrected */
|
|
#define BITP_EPPI_STAT_FTERRUNDR 5 /* Frame Track Underflow */
|
|
#define BITP_EPPI_STAT_FTERROVR 4 /* Frame Track Overflow */
|
|
#define BITP_EPPI_STAT_LTERRUNDR 3 /* Line Track Underflow */
|
|
#define BITP_EPPI_STAT_LTERROVR 2 /* Line Track Overflow */
|
|
#define BITP_EPPI_STAT_YFIFOERR 1 /* Luma FIFO Error */
|
|
#define BITP_EPPI_STAT_CFIFOERR 0 /* Chroma FIFO Error */
|
|
|
|
#define BITM_EPPI_STAT_FLD (_ADI_MSK(0x00008000,uint32_t)) /* Current Field Received by EPPI */
|
|
#define ENUM_EPPI_STAT_FIELD1 (_ADI_MSK(0x00000000,uint32_t)) /* FLD: Field 1 */
|
|
#define ENUM_EPPI_STAT_FIELD2 (_ADI_MSK(0x00008000,uint32_t)) /* FLD: Field 2 */
|
|
|
|
#define BITM_EPPI_STAT_ERRDET (_ADI_MSK(0x00004000,uint32_t)) /* Preamble Error Detected */
|
|
#define ENUM_EPPI_STAT_NO_PRERR (_ADI_MSK(0x00000000,uint32_t)) /* ERRDET: No preamble error detected */
|
|
#define ENUM_EPPI_STAT_PRERR (_ADI_MSK(0x00004000,uint32_t)) /* ERRDET: Preamble error detected */
|
|
#define BITM_EPPI_STAT_PXPERR (_ADI_MSK(0x00000080,uint32_t)) /* PxP Ready Error */
|
|
|
|
#define BITM_EPPI_STAT_ERRNCOR (_ADI_MSK(0x00000040,uint32_t)) /* Preamble Error Not Corrected */
|
|
#define ENUM_EPPI_STAT_NO_ERRNCOR (_ADI_MSK(0x00000000,uint32_t)) /* ERRNCOR: No uncorrected preamble error has occurred */
|
|
#define ENUM_EPPI_STAT_ERRNCOR (_ADI_MSK(0x00000040,uint32_t)) /* ERRNCOR: Preamble error detected but not corrected */
|
|
|
|
#define BITM_EPPI_STAT_FTERRUNDR (_ADI_MSK(0x00000020,uint32_t)) /* Frame Track Underflow */
|
|
#define ENUM_EPPI_STAT_NO_FTERRUNDR (_ADI_MSK(0x00000000,uint32_t)) /* FTERRUNDR: No Error Detected */
|
|
#define ENUM_EPPI_STAT_FTERRUNDR (_ADI_MSK(0x00000020,uint32_t)) /* FTERRUNDR: Error Occurred */
|
|
|
|
#define BITM_EPPI_STAT_FTERROVR (_ADI_MSK(0x00000010,uint32_t)) /* Frame Track Overflow */
|
|
#define ENUM_EPPI_STAT_NO_FTERROVR (_ADI_MSK(0x00000000,uint32_t)) /* FTERROVR: No Error Detected */
|
|
#define ENUM_EPPI_STAT_FTERROVR (_ADI_MSK(0x00000010,uint32_t)) /* FTERROVR: Error Occurred */
|
|
|
|
#define BITM_EPPI_STAT_LTERRUNDR (_ADI_MSK(0x00000008,uint32_t)) /* Line Track Underflow */
|
|
#define ENUM_EPPI_STAT_NO_LTERRUNDR (_ADI_MSK(0x00000000,uint32_t)) /* LTERRUNDR: No Error Detected */
|
|
#define ENUM_EPPI_STAT_LTERRUNDR (_ADI_MSK(0x00000008,uint32_t)) /* LTERRUNDR: Error Occurred */
|
|
|
|
#define BITM_EPPI_STAT_LTERROVR (_ADI_MSK(0x00000004,uint32_t)) /* Line Track Overflow */
|
|
#define ENUM_EPPI_STAT_NO_LTERROVR (_ADI_MSK(0x00000000,uint32_t)) /* LTERROVR: No Error Detected */
|
|
#define ENUM_EPPI_STAT_LTERROVR (_ADI_MSK(0x00000004,uint32_t)) /* LTERROVR: Error Occurred */
|
|
|
|
#define BITM_EPPI_STAT_YFIFOERR (_ADI_MSK(0x00000002,uint32_t)) /* Luma FIFO Error */
|
|
#define ENUM_EPPI_STAT_NO_YFIFOERR (_ADI_MSK(0x00000000,uint32_t)) /* YFIFOERR: No Error Detected */
|
|
#define ENUM_EPPI_STAT_YFIFOERR (_ADI_MSK(0x00000002,uint32_t)) /* YFIFOERR: Error Occurred */
|
|
|
|
#define BITM_EPPI_STAT_CFIFOERR (_ADI_MSK(0x00000001,uint32_t)) /* Chroma FIFO Error */
|
|
#define ENUM_EPPI_STAT_NO_CFIFOERR (_ADI_MSK(0x00000000,uint32_t)) /* CFIFOERR: No Error Detected */
|
|
#define ENUM_EPPI_STAT_CFIFOERR (_ADI_MSK(0x00000001,uint32_t)) /* CFIFOERR: Error Occurred */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EPPI_HCNT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EPPI_HCNT_VALUE 0 /* Horizontal Transfer Count */
|
|
#define BITM_EPPI_HCNT_VALUE (_ADI_MSK(0x0000FFFF,uint32_t)) /* Horizontal Transfer Count */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EPPI_HDLY Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EPPI_HDLY_VALUE 0 /* Horizontal Delay Count */
|
|
#define BITM_EPPI_HDLY_VALUE (_ADI_MSK(0x0000FFFF,uint32_t)) /* Horizontal Delay Count */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EPPI_VCNT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EPPI_VCNT_VALUE 0 /* Vertical Transfer Count */
|
|
#define BITM_EPPI_VCNT_VALUE (_ADI_MSK(0x0000FFFF,uint32_t)) /* Vertical Transfer Count */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EPPI_VDLY Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EPPI_VDLY_VALUE 0 /* Vertical Delay Count */
|
|
#define BITM_EPPI_VDLY_VALUE (_ADI_MSK(0x0000FFFF,uint32_t)) /* Vertical Delay Count */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EPPI_FRAME Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EPPI_FRAME_VALUE 0 /* Lines Per Frame */
|
|
#define BITM_EPPI_FRAME_VALUE (_ADI_MSK(0x0000FFFF,uint32_t)) /* Lines Per Frame */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EPPI_LINE Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EPPI_LINE_VALUE 0 /* Samples Per Line */
|
|
#define BITM_EPPI_LINE_VALUE (_ADI_MSK(0x0000FFFF,uint32_t)) /* Samples Per Line */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EPPI_CLKDIV Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EPPI_CLKDIV_VALUE 0 /* Internal Clock Divider */
|
|
#define BITM_EPPI_CLKDIV_VALUE (_ADI_MSK(0x0000FFFF,uint32_t)) /* Internal Clock Divider */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EPPI_CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EPPI_CTL_CLKGATEN 31 /* Clock Gating Enable */
|
|
#define BITP_EPPI_CTL_MUXSEL 30 /* MUX Select */
|
|
#define BITP_EPPI_CTL_DMAFINEN 29 /* DMA Finish Enable */
|
|
#define BITP_EPPI_CTL_DMACFG 28 /* One or Two DMA Channels Mode */
|
|
#define BITP_EPPI_CTL_RGBFMTEN 27 /* RGB Formatting Enable */
|
|
#define BITP_EPPI_CTL_SPLTWRD 26 /* Split Word */
|
|
#define BITP_EPPI_CTL_SUBSPLTODD 25 /* Sub-Split Odd Samples */
|
|
#define BITP_EPPI_CTL_SPLTEO 24 /* Split Even and Odd Data Samples */
|
|
#define BITP_EPPI_CTL_SWAPEN 23 /* Swap Enable */
|
|
#define BITP_EPPI_CTL_PACKEN 22 /* Pack/Unpack Enable */
|
|
#define BITP_EPPI_CTL_SKIPEO 21 /* Skip Even or Odd */
|
|
#define BITP_EPPI_CTL_SKIPEN 20 /* Skip Enable */
|
|
#define BITP_EPPI_CTL_DMIRR 19 /* Data Mirroring */
|
|
#define BITP_EPPI_CTL_DLEN 16 /* Data Length */
|
|
#define BITP_EPPI_CTL_POLS 14 /* Frame Sync Polarity */
|
|
#define BITP_EPPI_CTL_POLC 12 /* Clock Polarity */
|
|
#define BITP_EPPI_CTL_SIGNEXT 11 /* Sign Extension */
|
|
#define BITP_EPPI_CTL_IFSGEN 10 /* Internal Frame Sync Generation */
|
|
#define BITP_EPPI_CTL_ICLKGEN 9 /* Internal Clock Generation */
|
|
#define BITP_EPPI_CTL_BLANKGEN 8 /* king Generation (ITU Output Mode) */
|
|
#define BITP_EPPI_CTL_ITUTYPE 7 /* ITU Interlace or Progressive */
|
|
#define BITP_EPPI_CTL_FLDSEL 6 /* Field Select/Trigger */
|
|
#define BITP_EPPI_CTL_FSCFG 4 /* Frame Sync Configuration */
|
|
#define BITP_EPPI_CTL_XFRTYPE 2 /* Transfer Type ( Operating Mode) */
|
|
#define BITP_EPPI_CTL_DIR 1 /* PPI Direction */
|
|
#define BITP_EPPI_CTL_EN 0 /* PPI Enable */
|
|
|
|
#define BITM_EPPI_CTL_CLKGATEN (_ADI_MSK(0x80000000,uint32_t)) /* Clock Gating Enable */
|
|
#define ENUM_EPPI_CTL_CLKGATE_DIS (_ADI_MSK(0x00000000,uint32_t)) /* CLKGATEN: Disable */
|
|
#define ENUM_EPPI_CTL_CLKGATE_EN (_ADI_MSK(0x80000000,uint32_t)) /* CLKGATEN: Enable */
|
|
|
|
#define BITM_EPPI_CTL_MUXSEL (_ADI_MSK(0x40000000,uint32_t)) /* MUX Select */
|
|
#define ENUM_EPPI_CTL_MUXSEL0 (_ADI_MSK(0x00000000,uint32_t)) /* MUXSEL: Normal Operation */
|
|
#define ENUM_EPPI_CTL_MUXSEL1 (_ADI_MSK(0x40000000,uint32_t)) /* MUXSEL: Multiplexed Operation */
|
|
|
|
#define BITM_EPPI_CTL_DMAFINEN (_ADI_MSK(0x20000000,uint32_t)) /* DMA Finish Enable */
|
|
#define ENUM_EPPI_CTL_FINISH_DIS (_ADI_MSK(0x00000000,uint32_t)) /* DMAFINEN: No Finish Command */
|
|
#define ENUM_EPPI_CTL_FINISH_EN (_ADI_MSK(0x20000000,uint32_t)) /* DMAFINEN: Enable Send Finish Command */
|
|
|
|
#define BITM_EPPI_CTL_DMACFG (_ADI_MSK(0x10000000,uint32_t)) /* One or Two DMA Channels Mode */
|
|
#define ENUM_EPPI_CTL_DMA1CHAN (_ADI_MSK(0x00000000,uint32_t)) /* DMACFG: PPI uses one DMA Channel */
|
|
#define ENUM_EPPI_CTL_DMA2CHAN (_ADI_MSK(0x10000000,uint32_t)) /* DMACFG: PPI uses two DMA Channels */
|
|
|
|
#define BITM_EPPI_CTL_RGBFMTEN (_ADI_MSK(0x08000000,uint32_t)) /* RGB Formatting Enable */
|
|
#define ENUM_EPPI_CTL_RGBFMT_DIS (_ADI_MSK(0x00000000,uint32_t)) /* RGBFMTEN: Disable RGB Formatted Output */
|
|
#define ENUM_EPPI_CTL_RGBFMT_EN (_ADI_MSK(0x08000000,uint32_t)) /* RGBFMTEN: Enable RGB Formatted Output */
|
|
|
|
#define BITM_EPPI_CTL_SPLTWRD (_ADI_MSK(0x04000000,uint32_t)) /* Split Word */
|
|
#define ENUM_EPPI_CTL_NO_WORDSPLIT (_ADI_MSK(0x00000000,uint32_t)) /* SPLTWRD: PPI_DATA has (DLEN-1) bits of Y or Cr or Cb */
|
|
#define ENUM_EPPI_CTL_WORDSPLIT (_ADI_MSK(0x04000000,uint32_t)) /* SPLTWRD: PPI_DATA contains 2 elements per word */
|
|
|
|
#define BITM_EPPI_CTL_SUBSPLTODD (_ADI_MSK(0x02000000,uint32_t)) /* Sub-Split Odd Samples */
|
|
#define ENUM_EPPI_CTL_NO_SUBSPLIT (_ADI_MSK(0x00000000,uint32_t)) /* SUBSPLTODD: Disable */
|
|
#define ENUM_EPPI_CTL_SUBSPLIT_ODD (_ADI_MSK(0x02000000,uint32_t)) /* SUBSPLTODD: Enable */
|
|
|
|
#define BITM_EPPI_CTL_SPLTEO (_ADI_MSK(0x01000000,uint32_t)) /* Split Even and Odd Data Samples */
|
|
#define ENUM_EPPI_CTL_SPLTEO_DIS (_ADI_MSK(0x00000000,uint32_t)) /* SPLTEO: Do Not Split Samples */
|
|
#define ENUM_EPPI_CTL_SPLTEO_EN (_ADI_MSK(0x01000000,uint32_t)) /* SPLTEO: Split Even/Odd Samples */
|
|
|
|
#define BITM_EPPI_CTL_SWAPEN (_ADI_MSK(0x00800000,uint32_t)) /* Swap Enable */
|
|
#define ENUM_EPPI_CTL_SWAP_DIS (_ADI_MSK(0x00000000,uint32_t)) /* SWAPEN: Disable */
|
|
#define ENUM_EPPI_CTL_SWAP_EN (_ADI_MSK(0x00800000,uint32_t)) /* SWAPEN: Enable */
|
|
|
|
#define BITM_EPPI_CTL_PACKEN (_ADI_MSK(0x00400000,uint32_t)) /* Pack/Unpack Enable */
|
|
#define ENUM_EPPI_CTL_PACK_DIS (_ADI_MSK(0x00000000,uint32_t)) /* PACKEN: Disable */
|
|
#define ENUM_EPPI_CTL_PACK_EN (_ADI_MSK(0x00400000,uint32_t)) /* PACKEN: Enable */
|
|
|
|
#define BITM_EPPI_CTL_SKIPEO (_ADI_MSK(0x00200000,uint32_t)) /* Skip Even or Odd */
|
|
#define ENUM_EPPI_CTL_SKIPODD (_ADI_MSK(0x00000000,uint32_t)) /* SKIPEO: Skip Odd Samples */
|
|
#define ENUM_EPPI_CTL_SKIPEVEN (_ADI_MSK(0x00200000,uint32_t)) /* SKIPEO: Skip Even Samples */
|
|
|
|
#define BITM_EPPI_CTL_SKIPEN (_ADI_MSK(0x00100000,uint32_t)) /* Skip Enable */
|
|
#define ENUM_EPPI_CTL_NO_SKIP (_ADI_MSK(0x00000000,uint32_t)) /* SKIPEN: No Samples Skipping */
|
|
#define ENUM_EPPI_CTL_SKIP (_ADI_MSK(0x00100000,uint32_t)) /* SKIPEN: Skip Alternate Samples */
|
|
|
|
#define BITM_EPPI_CTL_DMIRR (_ADI_MSK(0x00080000,uint32_t)) /* Data Mirroring */
|
|
#define ENUM_EPPI_CTL_NO_MIRROR (_ADI_MSK(0x00000000,uint32_t)) /* DMIRR: No Data Mirroring */
|
|
#define ENUM_EPPI_CTL_MIRROR (_ADI_MSK(0x00080000,uint32_t)) /* DMIRR: Data Mirroring */
|
|
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#define BITM_EPPI_CTL_DLEN (_ADI_MSK(0x00070000,uint32_t)) /* Data Length */
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#define ENUM_EPPI_CTL_DLEN08 (_ADI_MSK(0x00000000,uint32_t)) /* DLEN: 8 bits */
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#define ENUM_EPPI_CTL_DLEN10 (_ADI_MSK(0x00010000,uint32_t)) /* DLEN: 10 bits */
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#define ENUM_EPPI_CTL_DLEN12 (_ADI_MSK(0x00020000,uint32_t)) /* DLEN: 12 bits */
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#define ENUM_EPPI_CTL_DLEN14 (_ADI_MSK(0x00030000,uint32_t)) /* DLEN: 14 bits */
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#define ENUM_EPPI_CTL_DLEN16 (_ADI_MSK(0x00040000,uint32_t)) /* DLEN: 16 bits */
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#define ENUM_EPPI_CTL_DLEN18 (_ADI_MSK(0x00050000,uint32_t)) /* DLEN: 18 bits */
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#define ENUM_EPPI_CTL_DLEN20 (_ADI_MSK(0x00060000,uint32_t)) /* DLEN: 20 bits */
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#define ENUM_EPPI_CTL_DLEN24 (_ADI_MSK(0x00070000,uint32_t)) /* DLEN: 24 bits */
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#define BITM_EPPI_CTL_POLS (_ADI_MSK(0x0000C000,uint32_t)) /* Frame Sync Polarity */
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#define ENUM_EPPI_CTL_FS1HI_FS2HI (_ADI_MSK(0x00000000,uint32_t)) /* POLS: FS1 and FS2 are active high */
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#define ENUM_EPPI_CTL_FS1LO_FS2HI (_ADI_MSK(0x00004000,uint32_t)) /* POLS: FS1 is active low. FS2 is active high */
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#define ENUM_EPPI_CTL_FS1HI_FS2LO (_ADI_MSK(0x00008000,uint32_t)) /* POLS: FS1 is active high. FS2 is active low */
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#define ENUM_EPPI_CTL_FS1LO_FS2LO (_ADI_MSK(0x0000C000,uint32_t)) /* POLS: FS1 and FS2 are active low */
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#define BITM_EPPI_CTL_POLC (_ADI_MSK(0x00003000,uint32_t)) /* Clock Polarity */
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#define ENUM_EPPI_CTL_POLC00 (_ADI_MSK(0x00000000,uint32_t)) /* POLC: Clock/Sync polarity mode 0 */
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#define ENUM_EPPI_CTL_POLC01 (_ADI_MSK(0x00001000,uint32_t)) /* POLC: Clock/Sync polarity mode 1 */
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#define ENUM_EPPI_CTL_POLC10 (_ADI_MSK(0x00002000,uint32_t)) /* POLC: Clock/Sync polarity mode 2 */
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#define ENUM_EPPI_CTL_POLC11 (_ADI_MSK(0x00003000,uint32_t)) /* POLC: Clock/Sync polarity mode 3 */
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#define BITM_EPPI_CTL_SIGNEXT (_ADI_MSK(0x00000800,uint32_t)) /* Sign Extension */
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#define ENUM_EPPI_CTL_ZEROFILL (_ADI_MSK(0x00000000,uint32_t)) /* SIGNEXT: Zero Filled */
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#define ENUM_EPPI_CTL_SIGNEXT (_ADI_MSK(0x00000800,uint32_t)) /* SIGNEXT: Sign Extended */
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#define BITM_EPPI_CTL_IFSGEN (_ADI_MSK(0x00000400,uint32_t)) /* Internal Frame Sync Generation */
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#define ENUM_EPPI_CTL_EXTFS (_ADI_MSK(0x00000000,uint32_t)) /* IFSGEN: External Frame Sync */
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#define ENUM_EPPI_CTL_INTFS (_ADI_MSK(0x00000400,uint32_t)) /* IFSGEN: Internal Frame Sync */
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#define BITM_EPPI_CTL_ICLKGEN (_ADI_MSK(0x00000200,uint32_t)) /* Internal Clock Generation */
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#define ENUM_EPPI_CTL_EXTCLK (_ADI_MSK(0x00000000,uint32_t)) /* ICLKGEN: External Clock */
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#define ENUM_EPPI_CTL_INTCLK (_ADI_MSK(0x00000200,uint32_t)) /* ICLKGEN: Internal Clock */
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#define BITM_EPPI_CTL_BLANKGEN (_ADI_MSK(0x00000100,uint32_t)) /* king Generation (ITU Output Mode) */
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#define ENUM_EPPI_CTL_NO_BLANKGEN (_ADI_MSK(0x00000000,uint32_t)) /* BLANKGEN: Disable */
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#define ENUM_EPPI_CTL_BLANKGEN (_ADI_MSK(0x00000100,uint32_t)) /* BLANKGEN: Enable */
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#define BITM_EPPI_CTL_ITUTYPE (_ADI_MSK(0x00000080,uint32_t)) /* ITU Interlace or Progressive */
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#define ENUM_EPPI_CTL_INTERLACED (_ADI_MSK(0x00000000,uint32_t)) /* ITUTYPE: Interlaced */
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#define ENUM_EPPI_CTL_PROGRESSIVE (_ADI_MSK(0x00000080,uint32_t)) /* ITUTYPE: Progressive */
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#define BITM_EPPI_CTL_FLDSEL (_ADI_MSK(0x00000040,uint32_t)) /* Field Select/Trigger */
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#define ENUM_EPPI_CTL_FLDSEL_LO (_ADI_MSK(0x00000000,uint32_t)) /* FLDSEL: Field Mode 0 */
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#define ENUM_EPPI_CTL_FLDSEL_HI (_ADI_MSK(0x00000040,uint32_t)) /* FLDSEL: Field Mode 1 */
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#define BITM_EPPI_CTL_FSCFG (_ADI_MSK(0x00000030,uint32_t)) /* Frame Sync Configuration */
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#define ENUM_EPPI_CTL_SYNC0 (_ADI_MSK(0x00000000,uint32_t)) /* FSCFG: Sync Mode 0 */
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#define ENUM_EPPI_CTL_SYNC1 (_ADI_MSK(0x00000010,uint32_t)) /* FSCFG: Sync Mode 1 */
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#define ENUM_EPPI_CTL_SYNC2 (_ADI_MSK(0x00000020,uint32_t)) /* FSCFG: Sync Mode 2 */
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#define ENUM_EPPI_CTL_SYNC3 (_ADI_MSK(0x00000030,uint32_t)) /* FSCFG: Sync Mode 3 */
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#define BITM_EPPI_CTL_XFRTYPE (_ADI_MSK(0x0000000C,uint32_t)) /* Transfer Type ( Operating Mode) */
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#define ENUM_EPPI_CTL_ACTIVE656 (_ADI_MSK(0x00000000,uint32_t)) /* XFRTYPE: ITU656 Active Video Only Mode */
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#define ENUM_EPPI_CTL_ENTIRE656 (_ADI_MSK(0x00000004,uint32_t)) /* XFRTYPE: ITU656 Entire Field Mode */
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#define ENUM_EPPI_CTL_VERT656 (_ADI_MSK(0x00000008,uint32_t)) /* XFRTYPE: ITU656 Vertical Blanking Only Mode */
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#define ENUM_EPPI_CTL_NON656 (_ADI_MSK(0x0000000C,uint32_t)) /* XFRTYPE: Non-ITU656 Mode (GP Mode) */
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#define BITM_EPPI_CTL_DIR (_ADI_MSK(0x00000002,uint32_t)) /* PPI Direction */
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#define ENUM_EPPI_CTL_RXMODE (_ADI_MSK(0x00000000,uint32_t)) /* DIR: Receive Mode */
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#define ENUM_EPPI_CTL_TXMODE (_ADI_MSK(0x00000002,uint32_t)) /* DIR: Transmit Mode */
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#define BITM_EPPI_CTL_EN (_ADI_MSK(0x00000001,uint32_t)) /* PPI Enable */
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#define ENUM_EPPI_CTL_DIS (_ADI_MSK(0x00000000,uint32_t)) /* EN: Disable */
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#define ENUM_EPPI_CTL_EN (_ADI_MSK(0x00000001,uint32_t)) /* EN: Enable */
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/* ------------------------------------------------------------------------------------------------------------------------
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EPPI_FS2_WLVB Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_EPPI_FS2_WLVB_F2VBAD 24 /* Field 2 Vertical Blanking After Data */
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#define BITP_EPPI_FS2_WLVB_F2VBBD 16 /* Field 2 Vertical Blanking Before Data */
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#define BITP_EPPI_FS2_WLVB_F1VBAD 8 /* Field 1 Vertical Blanking After Data */
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#define BITP_EPPI_FS2_WLVB_F1VBBD 0 /* Field 1 Vertical Blanking Before Data */
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#define BITM_EPPI_FS2_WLVB_F2VBAD (_ADI_MSK(0xFF000000,uint32_t)) /* Field 2 Vertical Blanking After Data */
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#define BITM_EPPI_FS2_WLVB_F2VBBD (_ADI_MSK(0x00FF0000,uint32_t)) /* Field 2 Vertical Blanking Before Data */
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#define BITM_EPPI_FS2_WLVB_F1VBAD (_ADI_MSK(0x0000FF00,uint32_t)) /* Field 1 Vertical Blanking After Data */
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#define BITM_EPPI_FS2_WLVB_F1VBBD (_ADI_MSK(0x000000FF,uint32_t)) /* Field 1 Vertical Blanking Before Data */
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/* ------------------------------------------------------------------------------------------------------------------------
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EPPI_FS2_PALPF Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_EPPI_FS2_PALPF_F2ACT 16 /* Field 2 Active */
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#define BITP_EPPI_FS2_PALPF_F1ACT 0 /* Field 1 Active */
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#define BITM_EPPI_FS2_PALPF_F2ACT (_ADI_MSK(0xFFFF0000,uint32_t)) /* Field 2 Active */
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#define BITM_EPPI_FS2_PALPF_F1ACT (_ADI_MSK(0x0000FFFF,uint32_t)) /* Field 1 Active */
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/* ------------------------------------------------------------------------------------------------------------------------
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EPPI_IMSK Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_EPPI_IMSK_PXPERR 7 /* PxP Ready Error Interrupt Mask */
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#define BITP_EPPI_IMSK_ERRNCOR 6 /* ITU Preamble Error Not Corrected Interrupt Mask */
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#define BITP_EPPI_IMSK_FTERRUNDR 5 /* Frame Track Underflow Error Interrupt Mask */
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#define BITP_EPPI_IMSK_FTERROVR 4 /* Frame Track Overflow Error Interrupt Mask */
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#define BITP_EPPI_IMSK_LTERRUNDR 3 /* Line Track Underflow Error Interrupt Mask */
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#define BITP_EPPI_IMSK_LTERROVR 2 /* Line Track Overflow Error Interrupt Mask */
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#define BITP_EPPI_IMSK_YFIFOERR 1 /* YFIFO Underflow or Overflow Error Interrupt Mask */
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#define BITP_EPPI_IMSK_CFIFOERR 0 /* CFIFO Underflow or Overflow Error Interrupt Mask */
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#define BITM_EPPI_IMSK_PXPERR (_ADI_MSK(0x00000080,uint32_t)) /* PxP Ready Error Interrupt Mask */
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#define ENUM_EPPI_IMSK_PXPERR_UMSK (_ADI_MSK(0x00000000,uint32_t)) /* PXPERR: Unmask Interrupt */
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#define ENUM_EPPI_IMSK_PXPERR_MSK (_ADI_MSK(0x00000080,uint32_t)) /* PXPERR: Mask Interrupt */
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#define BITM_EPPI_IMSK_ERRNCOR (_ADI_MSK(0x00000040,uint32_t)) /* ITU Preamble Error Not Corrected Interrupt Mask */
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#define ENUM_EPPI_IMSK_ERRNCOR_UMSK (_ADI_MSK(0x00000000,uint32_t)) /* ERRNCOR: Unmask Interrupt */
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#define ENUM_EPPI_IMSK_ERRNCOR_MSK (_ADI_MSK(0x00000040,uint32_t)) /* ERRNCOR: Mask Interrupt */
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#define BITM_EPPI_IMSK_FTERRUNDR (_ADI_MSK(0x00000020,uint32_t)) /* Frame Track Underflow Error Interrupt Mask */
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#define ENUM_EPPI_IMSK_FTERRUNDR_UMSK (_ADI_MSK(0x00000000,uint32_t)) /* FTERRUNDR: Unmask Interrupt */
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#define ENUM_EPPI_IMSK_FTERRUNDR_MSK (_ADI_MSK(0x00000020,uint32_t)) /* FTERRUNDR: Mask Interrupt */
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#define BITM_EPPI_IMSK_FTERROVR (_ADI_MSK(0x00000010,uint32_t)) /* Frame Track Overflow Error Interrupt Mask */
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#define ENUM_EPPI_IMSK_FTERROVR_UMSK (_ADI_MSK(0x00000000,uint32_t)) /* FTERROVR: Unmask Interrupt */
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#define ENUM_EPPI_IMSK_FTERROVR_MSK (_ADI_MSK(0x00000010,uint32_t)) /* FTERROVR: Mask Interrupt */
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#define BITM_EPPI_IMSK_LTERRUNDR (_ADI_MSK(0x00000008,uint32_t)) /* Line Track Underflow Error Interrupt Mask */
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#define ENUM_EPPI_IMSK_LTERRUNDR_UMSK (_ADI_MSK(0x00000000,uint32_t)) /* LTERRUNDR: Unmask Interrupt */
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#define ENUM_EPPI_IMSK_LTERRUNDR_MSK (_ADI_MSK(0x00000008,uint32_t)) /* LTERRUNDR: Mask Interrupt */
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#define BITM_EPPI_IMSK_LTERROVR (_ADI_MSK(0x00000004,uint32_t)) /* Line Track Overflow Error Interrupt Mask */
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#define ENUM_EPPI_IMSK_LTERROVR_UMSK (_ADI_MSK(0x00000000,uint32_t)) /* LTERROVR: Unmask Interrupt */
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#define ENUM_EPPI_IMSK_LTERROVR_MSK (_ADI_MSK(0x00000004,uint32_t)) /* LTERROVR: Mask Interrupt */
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#define BITM_EPPI_IMSK_YFIFOERR (_ADI_MSK(0x00000002,uint32_t)) /* YFIFO Underflow or Overflow Error Interrupt Mask */
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#define ENUM_EPPI_IMSK_YFIFOERR_UMSK (_ADI_MSK(0x00000000,uint32_t)) /* YFIFOERR: Unmask Interrupt */
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#define ENUM_EPPI_IMSK_YFIFOERR_MSK (_ADI_MSK(0x00000002,uint32_t)) /* YFIFOERR: Mask Interrupt */
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#define BITM_EPPI_IMSK_CFIFOERR (_ADI_MSK(0x00000001,uint32_t)) /* CFIFO Underflow or Overflow Error Interrupt Mask */
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#define ENUM_EPPI_IMSK_CFIFOERR_UMSK (_ADI_MSK(0x00000000,uint32_t)) /* CFIFOERR: Unmask Interrupt */
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#define ENUM_EPPI_IMSK_CFIFOERR_MSK (_ADI_MSK(0x00000001,uint32_t)) /* CFIFOERR: Mask Interrupt */
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/* ------------------------------------------------------------------------------------------------------------------------
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EPPI_ODDCLIP Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_EPPI_ODDCLIP_HIGHODD 16 /* High Odd Clipping Threshold (Chroma Data) */
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#define BITP_EPPI_ODDCLIP_LOWODD 0 /* Low Odd Clipping Threshold (Chroma Data) */
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#define BITM_EPPI_ODDCLIP_HIGHODD (_ADI_MSK(0xFFFF0000,uint32_t)) /* High Odd Clipping Threshold (Chroma Data) */
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#define BITM_EPPI_ODDCLIP_LOWODD (_ADI_MSK(0x0000FFFF,uint32_t)) /* Low Odd Clipping Threshold (Chroma Data) */
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/* ------------------------------------------------------------------------------------------------------------------------
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EPPI_EVENCLIP Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_EPPI_EVENCLIP_HIGHEVEN 16 /* High Even Clipping Threshold (Luma Data) */
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#define BITP_EPPI_EVENCLIP_LOWEVEN 0 /* Low Even Clipping Threshold (Luma Data) */
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#define BITM_EPPI_EVENCLIP_HIGHEVEN (_ADI_MSK(0xFFFF0000,uint32_t)) /* High Even Clipping Threshold (Luma Data) */
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#define BITM_EPPI_EVENCLIP_LOWEVEN (_ADI_MSK(0x0000FFFF,uint32_t)) /* Low Even Clipping Threshold (Luma Data) */
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/* ------------------------------------------------------------------------------------------------------------------------
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EPPI_CTL2 Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_EPPI_CTL2_FS1FINEN 1 /* HSYNC Finish Enable */
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#define BITM_EPPI_CTL2_FS1FINEN (_ADI_MSK(0x00000002,uint32_t)) /* HSYNC Finish Enable */
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#define ENUM_EPPI_CTL2_FS2FIN_EN (_ADI_MSK(0x00000000,uint32_t)) /* FS1FINEN: Finish sent after frame RX done */
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#define ENUM_EPPI_CTL2_FS1FIN_EN (_ADI_MSK(0x00000002,uint32_t)) /* FS1FINEN: Finish sent after frame/line RX done */
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/* ==================================================
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Pulse-Width Modulator Registers
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================================================== */
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/* =========================
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PWM0
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========================= */
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#define REG_PWM0_CTL 0xFFC1B000 /* PWM0 Control Register */
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#define REG_PWM0_CHANCFG 0xFFC1B004 /* PWM0 Channel Config Register */
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#define REG_PWM0_TRIPCFG 0xFFC1B008 /* PWM0 Trip Config Register */
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#define REG_PWM0_STAT 0xFFC1B00C /* PWM0 Status Register */
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#define REG_PWM0_IMSK 0xFFC1B010 /* PWM0 Interrupt Mask Register */
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#define REG_PWM0_ILAT 0xFFC1B014 /* PWM0 Interrupt Latch Register */
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#define REG_PWM0_CHOPCFG 0xFFC1B018 /* PWM0 Chop Configuration Register */
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#define REG_PWM0_DT 0xFFC1B01C /* PWM0 Dead Time Register */
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#define REG_PWM0_SYNC_WID 0xFFC1B020 /* PWM0 Sync Pulse Width Register */
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#define REG_PWM0_TM0 0xFFC1B024 /* PWM0 Timer 0 Period Register */
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#define REG_PWM0_TM1 0xFFC1B028 /* PWM0 Timer 1 Period Register */
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#define REG_PWM0_TM2 0xFFC1B02C /* PWM0 Timer 2 Period Register */
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#define REG_PWM0_TM3 0xFFC1B030 /* PWM0 Timer 3 Period Register */
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#define REG_PWM0_TM4 0xFFC1B034 /* PWM0 Timer 4 Period Register */
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#define REG_PWM0_DLYA 0xFFC1B038 /* PWM0 Channel A Delay Register */
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#define REG_PWM0_DLYB 0xFFC1B03C /* PWM0 Channel B Delay Register */
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#define REG_PWM0_DLYC 0xFFC1B040 /* PWM0 Channel C Delay Register */
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#define REG_PWM0_DLYD 0xFFC1B044 /* PWM0 Channel D Delay Register */
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#define REG_PWM0_ACTL 0xFFC1B048 /* PWM0 Channel A Control Register */
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#define REG_PWM0_AH0 0xFFC1B04C /* PWM0 Channel A-High Duty-0 Register */
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#define REG_PWM0_AH1 0xFFC1B050 /* PWM0 Channel A-High Duty-1 Register */
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#define REG_PWM0_AL0 0xFFC1B05C /* PWM0 Channel A-Low Duty-0 Register */
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#define REG_PWM0_AL1 0xFFC1B060 /* PWM0 Channel A-Low Duty-1 Register */
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#define REG_PWM0_BCTL 0xFFC1B064 /* PWM0 Channel B Control Register */
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#define REG_PWM0_BH0 0xFFC1B068 /* PWM0 Channel B-High Duty-0 Register */
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#define REG_PWM0_BH1 0xFFC1B06C /* PWM0 Channel B-High Duty-1 Register */
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#define REG_PWM0_BL0 0xFFC1B078 /* PWM0 Channel B-Low Duty-0 Register */
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#define REG_PWM0_BL1 0xFFC1B07C /* PWM0 Channel B-Low Duty-1 Register */
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#define REG_PWM0_CCTL 0xFFC1B080 /* PWM0 Channel C Control Register */
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#define REG_PWM0_CH0 0xFFC1B084 /* PWM0 Channel C-High Pulse Duty Register 0 */
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#define REG_PWM0_CH1 0xFFC1B088 /* PWM0 Channel C-High Pulse Duty Register 1 */
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#define REG_PWM0_CL0 0xFFC1B094 /* PWM0 Channel C-Low Pulse Duty Register 0 */
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#define REG_PWM0_CL1 0xFFC1B098 /* PWM0 Channel C-Low Duty-1 Register */
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#define REG_PWM0_DCTL 0xFFC1B09C /* PWM0 Channel D Control Register */
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#define REG_PWM0_DH0 0xFFC1B0A0 /* PWM0 Channel D-High Duty-0 Register */
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#define REG_PWM0_DH1 0xFFC1B0A4 /* PWM0 Channel D-High Pulse Duty Register 1 */
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#define REG_PWM0_DL0 0xFFC1B0B0 /* PWM0 Channel D-Low Pulse Duty Register 0 */
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#define REG_PWM0_DL1 0xFFC1B0B4 /* PWM0 Channel D-Low Pulse Duty Register 1 */
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/* =========================
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PWM1
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========================= */
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#define REG_PWM1_CTL 0xFFC1B400 /* PWM1 Control Register */
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#define REG_PWM1_CHANCFG 0xFFC1B404 /* PWM1 Channel Config Register */
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#define REG_PWM1_TRIPCFG 0xFFC1B408 /* PWM1 Trip Config Register */
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#define REG_PWM1_STAT 0xFFC1B40C /* PWM1 Status Register */
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#define REG_PWM1_IMSK 0xFFC1B410 /* PWM1 Interrupt Mask Register */
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#define REG_PWM1_ILAT 0xFFC1B414 /* PWM1 Interrupt Latch Register */
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#define REG_PWM1_CHOPCFG 0xFFC1B418 /* PWM1 Chop Configuration Register */
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#define REG_PWM1_DT 0xFFC1B41C /* PWM1 Dead Time Register */
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#define REG_PWM1_SYNC_WID 0xFFC1B420 /* PWM1 Sync Pulse Width Register */
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#define REG_PWM1_TM0 0xFFC1B424 /* PWM1 Timer 0 Period Register */
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#define REG_PWM1_TM1 0xFFC1B428 /* PWM1 Timer 1 Period Register */
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#define REG_PWM1_TM2 0xFFC1B42C /* PWM1 Timer 2 Period Register */
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#define REG_PWM1_TM3 0xFFC1B430 /* PWM1 Timer 3 Period Register */
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#define REG_PWM1_TM4 0xFFC1B434 /* PWM1 Timer 4 Period Register */
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#define REG_PWM1_DLYA 0xFFC1B438 /* PWM1 Channel A Delay Register */
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#define REG_PWM1_DLYB 0xFFC1B43C /* PWM1 Channel B Delay Register */
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#define REG_PWM1_DLYC 0xFFC1B440 /* PWM1 Channel C Delay Register */
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#define REG_PWM1_DLYD 0xFFC1B444 /* PWM1 Channel D Delay Register */
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#define REG_PWM1_ACTL 0xFFC1B448 /* PWM1 Channel A Control Register */
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#define REG_PWM1_AH0 0xFFC1B44C /* PWM1 Channel A-High Duty-0 Register */
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#define REG_PWM1_AH1 0xFFC1B450 /* PWM1 Channel A-High Duty-1 Register */
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#define REG_PWM1_AL0 0xFFC1B45C /* PWM1 Channel A-Low Duty-0 Register */
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#define REG_PWM1_AL1 0xFFC1B460 /* PWM1 Channel A-Low Duty-1 Register */
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#define REG_PWM1_BCTL 0xFFC1B464 /* PWM1 Channel B Control Register */
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#define REG_PWM1_BH0 0xFFC1B468 /* PWM1 Channel B-High Duty-0 Register */
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#define REG_PWM1_BH1 0xFFC1B46C /* PWM1 Channel B-High Duty-1 Register */
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#define REG_PWM1_BL0 0xFFC1B478 /* PWM1 Channel B-Low Duty-0 Register */
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#define REG_PWM1_BL1 0xFFC1B47C /* PWM1 Channel B-Low Duty-1 Register */
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#define REG_PWM1_CCTL 0xFFC1B480 /* PWM1 Channel C Control Register */
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#define REG_PWM1_CH0 0xFFC1B484 /* PWM1 Channel C-High Pulse Duty Register 0 */
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#define REG_PWM1_CH1 0xFFC1B488 /* PWM1 Channel C-High Pulse Duty Register 1 */
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#define REG_PWM1_CL0 0xFFC1B494 /* PWM1 Channel C-Low Pulse Duty Register 0 */
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#define REG_PWM1_CL1 0xFFC1B498 /* PWM1 Channel C-Low Duty-1 Register */
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#define REG_PWM1_DCTL 0xFFC1B49C /* PWM1 Channel D Control Register */
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#define REG_PWM1_DH0 0xFFC1B4A0 /* PWM1 Channel D-High Duty-0 Register */
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#define REG_PWM1_DH1 0xFFC1B4A4 /* PWM1 Channel D-High Pulse Duty Register 1 */
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#define REG_PWM1_DL0 0xFFC1B4B0 /* PWM1 Channel D-Low Pulse Duty Register 0 */
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#define REG_PWM1_DL1 0xFFC1B4B4 /* PWM1 Channel D-Low Pulse Duty Register 1 */
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/* =========================
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PWM
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========================= */
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/* ------------------------------------------------------------------------------------------------------------------------
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PWM_CTL Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_PWM_CTL_INTSYNCREF 18 /* Timer reference for Internal Sync */
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#define BITP_PWM_CTL_EXTSYNCSEL 17 /* External Sync Select */
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#define BITP_PWM_CTL_EXTSYNC 16 /* External Sync */
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#define BITP_PWM_CTL_DLYDEN 7 /* Enable Delay Counter for Channel D */
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#define BITP_PWM_CTL_DLYCEN 6 /* Enable Delay Counter for Channel C */
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#define BITP_PWM_CTL_DLYBEN 5 /* Enable Delay Counter for Channel B */
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#define BITP_PWM_CTL_DLYAEN 4 /* Enable Delay Counter for Channel A */
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#define BITP_PWM_CTL_SWTRIP 2 /* Software Trip */
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#define BITP_PWM_CTL_EMURUN 1 /* Output Behavior During Emulation Mode */
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#define BITP_PWM_CTL_GLOBEN 0 /* Module Enable */
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#define BITM_PWM_CTL_INTSYNCREF (_ADI_MSK(0x001C0000,uint32_t)) /* Timer reference for Internal Sync */
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#define ENUM_PWM_CTL_INTSYNC_0 (_ADI_MSK(0x00000000,uint32_t)) /* INTSYNCREF: PWMTMR0 provides sync reference */
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#define ENUM_PWM_CTL_INTSYNC_1 (_ADI_MSK(0x00040000,uint32_t)) /* INTSYNCREF: PWMTMR1 provides sync reference */
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#define ENUM_PWM_CTL_INTSYNC_2 (_ADI_MSK(0x00080000,uint32_t)) /* INTSYNCREF: PWMTMR2 provides sync reference */
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#define ENUM_PWM_CTL_INTSYNC_3 (_ADI_MSK(0x000C0000,uint32_t)) /* INTSYNCREF: PWMTMR3 provides sync reference */
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#define ENUM_PWM_CTL_INTSYNC_4 (_ADI_MSK(0x00100000,uint32_t)) /* INTSYNCREF: PWMTMR4 provides sync reference */
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#define BITM_PWM_CTL_EXTSYNCSEL (_ADI_MSK(0x00020000,uint32_t)) /* External Sync Select */
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#define ENUM_PWM_CTL_EXTSYNC_ASYNC (_ADI_MSK(0x00000000,uint32_t)) /* EXTSYNCSEL: Asynchronous External Sync */
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#define ENUM_PWM_CTL_EXTSYNC_SYNC (_ADI_MSK(0x00020000,uint32_t)) /* EXTSYNCSEL: Synchronous External Sync */
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#define BITM_PWM_CTL_EXTSYNC (_ADI_MSK(0x00010000,uint32_t)) /* External Sync */
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#define ENUM_PWM_CTL_INTSYNC (_ADI_MSK(0x00000000,uint32_t)) /* EXTSYNC: Internal sync used */
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#define ENUM_PWM_CTL_EXTSYNC (_ADI_MSK(0x00010000,uint32_t)) /* EXTSYNC: External sync used */
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#define BITM_PWM_CTL_DLYDEN (_ADI_MSK(0x00000080,uint32_t)) /* Enable Delay Counter for Channel D */
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#define ENUM_PWM_CTL_DLYD_DIS (_ADI_MSK(0x00000000,uint32_t)) /* DLYDEN: Disable */
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#define ENUM_PWM_CTL_DLYD_EN (_ADI_MSK(0x00000080,uint32_t)) /* DLYDEN: Enable */
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#define BITM_PWM_CTL_DLYCEN (_ADI_MSK(0x00000040,uint32_t)) /* Enable Delay Counter for Channel C */
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#define ENUM_PWM_CTL_DLYC_DIS (_ADI_MSK(0x00000000,uint32_t)) /* DLYCEN: Disable */
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#define ENUM_PWM_CTL_DLYC_EN (_ADI_MSK(0x00000040,uint32_t)) /* DLYCEN: Enable */
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#define BITM_PWM_CTL_DLYBEN (_ADI_MSK(0x00000020,uint32_t)) /* Enable Delay Counter for Channel B */
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#define ENUM_PWM_CTL_DLYB_DIS (_ADI_MSK(0x00000000,uint32_t)) /* DLYBEN: Disable */
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#define ENUM_PWM_CTL_DLYB_EN (_ADI_MSK(0x00000020,uint32_t)) /* DLYBEN: Enable */
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#define BITM_PWM_CTL_DLYAEN (_ADI_MSK(0x00000010,uint32_t)) /* Enable Delay Counter for Channel A */
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#define ENUM_PWM_CTL_DLYA_DIS (_ADI_MSK(0x00000000,uint32_t)) /* DLYAEN: Disable */
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#define ENUM_PWM_CTL_DLYA_EN (_ADI_MSK(0x00000010,uint32_t)) /* DLYAEN: Enable */
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#define BITM_PWM_CTL_SWTRIP (_ADI_MSK(0x00000004,uint32_t)) /* Software Trip */
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#define ENUM_PWM_CTL_FORCE_TRIP (_ADI_MSK(0x00000004,uint32_t)) /* SWTRIP: Force a Fault Trip Condition */
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#define BITM_PWM_CTL_EMURUN (_ADI_MSK(0x00000002,uint32_t)) /* Output Behavior During Emulation Mode */
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#define ENUM_PWM_CTL_EMURUN_DIS (_ADI_MSK(0x00000000,uint32_t)) /* EMURUN: Disable Outputs */
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#define ENUM_PWM_CTL_EMURUN_EN (_ADI_MSK(0x00000002,uint32_t)) /* EMURUN: Enable Outputs */
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#define BITM_PWM_CTL_GLOBEN (_ADI_MSK(0x00000001,uint32_t)) /* Module Enable */
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#define ENUM_PWM_CTL_PWM_DIS (_ADI_MSK(0x00000000,uint32_t)) /* GLOBEN: Disable */
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#define ENUM_PWM_CTL_PWM_EN (_ADI_MSK(0x00000001,uint32_t)) /* GLOBEN: Enable */
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/* ------------------------------------------------------------------------------------------------------------------------
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PWM_CHANCFG Pos/Masks Description
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|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_PWM_CHANCFG_ENCHOPDL 30 /* Channel D Gate Chopping Enable Low Side */
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#define BITP_PWM_CHANCFG_POLDL 29 /* Channel D low side Polarity */
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#define BITP_PWM_CHANCFG_ENCHOPDH 27 /* Channel D Gate Chopping Enable High Side */
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#define BITP_PWM_CHANCFG_POLDH 26 /* Channel D High side Polarity */
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#define BITP_PWM_CHANCFG_MODELSD 25 /* Channel D Mode of low Side Output */
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#define BITP_PWM_CHANCFG_REFTMRD 24 /* Channel D Timer Reference */
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#define BITP_PWM_CHANCFG_ENCHOPCL 22 /* Channel C Gate Chopping Enable Low Side */
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#define BITP_PWM_CHANCFG_POLCL 21 /* Channel C low side Polarity */
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#define BITP_PWM_CHANCFG_ENCHOPCH 19 /* Channel C Gate Chopping Enable High Side */
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#define BITP_PWM_CHANCFG_POLCH 18 /* Channel C High side Polarity */
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#define BITP_PWM_CHANCFG_MODELSC 17 /* Channel C Mode of low Side Output */
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#define BITP_PWM_CHANCFG_REFTMRC 16 /* Channel C Timer Reference */
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#define BITP_PWM_CHANCFG_ENCHOPBL 14 /* Channel B Gate Chopping Enable Low Side */
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#define BITP_PWM_CHANCFG_POLBL 13 /* Channel B low side Polarity */
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#define BITP_PWM_CHANCFG_ENCHOPBH 11 /* Channel B Gate Chopping Enable High Side */
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#define BITP_PWM_CHANCFG_POLBH 10 /* Channel B High side Polarity */
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#define BITP_PWM_CHANCFG_MODELSB 9 /* Channel B Mode of low Side Output */
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#define BITP_PWM_CHANCFG_REFTMRB 8 /* Channel B Timer Reference */
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#define BITP_PWM_CHANCFG_ENCHOPAL 6 /* Channel A Gate Chopping Enable Low Side */
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#define BITP_PWM_CHANCFG_POLAL 5 /* Channel A low side Polarity */
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#define BITP_PWM_CHANCFG_ENCHOPAH 3 /* Channel A Gate Chopping Enable High Side */
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#define BITP_PWM_CHANCFG_POLAH 2 /* Channel A High side Polarity */
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#define BITP_PWM_CHANCFG_MODELSA 1 /* Channel A Mode of low Side Output */
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#define BITP_PWM_CHANCFG_REFTMRA 0 /* Channel A Timer Reference */
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#define BITM_PWM_CHANCFG_ENCHOPDL (_ADI_MSK(0x40000000,uint32_t)) /* Channel D Gate Chopping Enable Low Side */
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#define ENUM_PWM_CHANCFG_CHOPDL_DIS (_ADI_MSK(0x00000000,uint32_t)) /* ENCHOPDL: Disable Chopping Channel D Low Side */
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#define ENUM_PWM_CHANCFG_CHOPDL_EN (_ADI_MSK(0x40000000,uint32_t)) /* ENCHOPDL: Enable Chopping Channel D Low Side */
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#define BITM_PWM_CHANCFG_POLDL (_ADI_MSK(0x20000000,uint32_t)) /* Channel D low side Polarity */
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#define ENUM_PWM_CHANCFG_DL_ACTLO (_ADI_MSK(0x00000000,uint32_t)) /* POLDL: Active Low */
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#define ENUM_PWM_CHANCFG_DL_ACTHI (_ADI_MSK(0x20000000,uint32_t)) /* POLDL: Active High */
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#define BITM_PWM_CHANCFG_ENCHOPDH (_ADI_MSK(0x08000000,uint32_t)) /* Channel D Gate Chopping Enable High Side */
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#define ENUM_PWM_CHANCFG_CHOPDH_DIS (_ADI_MSK(0x00000000,uint32_t)) /* ENCHOPDH: Disable Chopping Channel D High Side */
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#define ENUM_PWM_CHANCFG_CHOPDH_EN (_ADI_MSK(0x08000000,uint32_t)) /* ENCHOPDH: Enable Chopping Channel D High Side */
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#define BITM_PWM_CHANCFG_POLDH (_ADI_MSK(0x04000000,uint32_t)) /* Channel D High side Polarity */
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#define ENUM_PWM_CHANCFG_DH_ACTLO (_ADI_MSK(0x00000000,uint32_t)) /* POLDH: Active Low */
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#define ENUM_PWM_CHANCFG_DH_ACTHI (_ADI_MSK(0x04000000,uint32_t)) /* POLDH: Active High */
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#define BITM_PWM_CHANCFG_MODELSD (_ADI_MSK(0x02000000,uint32_t)) /* Channel D Mode of low Side Output */
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#define ENUM_PWM_CHANCFG_LOD_INVHI (_ADI_MSK(0x00000000,uint32_t)) /* MODELSD: Invert of high output */
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#define ENUM_PWM_CHANCFG_LOD_IND (_ADI_MSK(0x02000000,uint32_t)) /* MODELSD: Independent control */
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#define BITM_PWM_CHANCFG_REFTMRD (_ADI_MSK(0x01000000,uint32_t)) /* Channel D Timer Reference */
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#define ENUM_PWM_CHANCFG_REFTMRD_0 (_ADI_MSK(0x00000000,uint32_t)) /* REFTMRD: PWMTMR0 is Channel D reference */
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#define ENUM_PWM_CHANCFG_REFTMRD_1 (_ADI_MSK(0x01000000,uint32_t)) /* REFTMRD: PWMTMR1 is Channel D reference */
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#define BITM_PWM_CHANCFG_ENCHOPCL (_ADI_MSK(0x00400000,uint32_t)) /* Channel C Gate Chopping Enable Low Side */
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#define ENUM_PWM_CHANCFG_CHOPCL_DIS (_ADI_MSK(0x00000000,uint32_t)) /* ENCHOPCL: Disable Chopping Channel C Low Side */
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#define ENUM_PWM_CHANCFG_CHOPCL_EN (_ADI_MSK(0x00400000,uint32_t)) /* ENCHOPCL: Enable Chopping Channel C Low Side */
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#define BITM_PWM_CHANCFG_POLCL (_ADI_MSK(0x00200000,uint32_t)) /* Channel C low side Polarity */
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#define ENUM_PWM_CHANCFG_CL_ACTLO (_ADI_MSK(0x00000000,uint32_t)) /* POLCL: Active Low */
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#define ENUM_PWM_CHANCFG_CL_ACTHI (_ADI_MSK(0x00200000,uint32_t)) /* POLCL: Active High */
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#define BITM_PWM_CHANCFG_ENCHOPCH (_ADI_MSK(0x00080000,uint32_t)) /* Channel C Gate Chopping Enable High Side */
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#define ENUM_PWM_CHANCFG_CHOPCH_DIS (_ADI_MSK(0x00000000,uint32_t)) /* ENCHOPCH: Disable Chopping Channel C High Side */
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#define ENUM_PWM_CHANCFG_CHOPCH_EN (_ADI_MSK(0x00080000,uint32_t)) /* ENCHOPCH: Enable Chopping Channel C High Side */
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#define BITM_PWM_CHANCFG_POLCH (_ADI_MSK(0x00040000,uint32_t)) /* Channel C High side Polarity */
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#define ENUM_PWM_CHANCFG_CH_ACTLO (_ADI_MSK(0x00000000,uint32_t)) /* POLCH: Active Low */
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#define ENUM_PWM_CHANCFG_CH_ACTHI (_ADI_MSK(0x00040000,uint32_t)) /* POLCH: Active High */
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#define BITM_PWM_CHANCFG_MODELSC (_ADI_MSK(0x00020000,uint32_t)) /* Channel C Mode of low Side Output */
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#define ENUM_PWM_CHANCFG_LOC_INVHI (_ADI_MSK(0x00000000,uint32_t)) /* MODELSC: Invert of high output */
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#define ENUM_PWM_CHANCFG_LOC_IND (_ADI_MSK(0x00020000,uint32_t)) /* MODELSC: Independent control */
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#define BITM_PWM_CHANCFG_REFTMRC (_ADI_MSK(0x00010000,uint32_t)) /* Channel C Timer Reference */
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#define ENUM_PWM_CHANCFG_REFTMRC_0 (_ADI_MSK(0x00000000,uint32_t)) /* REFTMRC: PWMTMR0 is Channel C reference */
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#define ENUM_PWM_CHANCFG_REFTMRC_1 (_ADI_MSK(0x00010000,uint32_t)) /* REFTMRC: PWMTMR1 is Channel C reference */
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#define BITM_PWM_CHANCFG_ENCHOPBL (_ADI_MSK(0x00004000,uint32_t)) /* Channel B Gate Chopping Enable Low Side */
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#define ENUM_PWM_CHANCFG_CHOPBL_DIS (_ADI_MSK(0x00000000,uint32_t)) /* ENCHOPBL: Disable Chopping Channel B Low Side */
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#define ENUM_PWM_CHANCFG_CHOPBL_EN (_ADI_MSK(0x00004000,uint32_t)) /* ENCHOPBL: Enable Chopping Channel B Low Side */
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#define BITM_PWM_CHANCFG_POLBL (_ADI_MSK(0x00002000,uint32_t)) /* Channel B low side Polarity */
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#define ENUM_PWM_CHANCFG_BL_ACTLO (_ADI_MSK(0x00000000,uint32_t)) /* POLBL: Active Low */
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#define ENUM_PWM_CHANCFG_BL_ACTHI (_ADI_MSK(0x00002000,uint32_t)) /* POLBL: Active High */
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#define BITM_PWM_CHANCFG_ENCHOPBH (_ADI_MSK(0x00000800,uint32_t)) /* Channel B Gate Chopping Enable High Side */
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#define ENUM_PWM_CHANCFG_CHOPBH_DIS (_ADI_MSK(0x00000000,uint32_t)) /* ENCHOPBH: Disable Chopping Channel B High Side */
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#define ENUM_PWM_CHANCFG_CHOPBH_EN (_ADI_MSK(0x00000800,uint32_t)) /* ENCHOPBH: Enable Chopping Channel B High Side */
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#define BITM_PWM_CHANCFG_POLBH (_ADI_MSK(0x00000400,uint32_t)) /* Channel B High side Polarity */
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#define ENUM_PWM_CHANCFG_BH_ACTLO (_ADI_MSK(0x00000000,uint32_t)) /* POLBH: Active Low */
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#define ENUM_PWM_CHANCFG_BH_ACTHI (_ADI_MSK(0x00000400,uint32_t)) /* POLBH: Active High */
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#define BITM_PWM_CHANCFG_MODELSB (_ADI_MSK(0x00000200,uint32_t)) /* Channel B Mode of low Side Output */
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#define ENUM_PWM_CHANCFG_LOB_INV (_ADI_MSK(0x00000000,uint32_t)) /* MODELSB: Invert of high output */
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#define ENUM_PWM_CHANCFG_LOB_IND (_ADI_MSK(0x00000200,uint32_t)) /* MODELSB: Independent control */
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#define BITM_PWM_CHANCFG_REFTMRB (_ADI_MSK(0x00000100,uint32_t)) /* Channel B Timer Reference */
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#define ENUM_PWM_CHANCFG_REFTMRB_0 (_ADI_MSK(0x00000000,uint32_t)) /* REFTMRB: PWMTMR0 is Channel B reference */
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#define ENUM_PWM_CHANCFG_REFTMRB_1 (_ADI_MSK(0x00000100,uint32_t)) /* REFTMRB: PWMTMR1 is Channel B reference */
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#define BITM_PWM_CHANCFG_ENCHOPAL (_ADI_MSK(0x00000040,uint32_t)) /* Channel A Gate Chopping Enable Low Side */
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#define ENUM_PWM_CHANCFG_CHOPAL_DIS (_ADI_MSK(0x00000000,uint32_t)) /* ENCHOPAL: Disable Chopping Channel A Low Side */
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#define ENUM_PWM_CHANCFG_CHOPAL_EN (_ADI_MSK(0x00000040,uint32_t)) /* ENCHOPAL: Enable Chopping Channel A Low Side */
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#define BITM_PWM_CHANCFG_POLAL (_ADI_MSK(0x00000020,uint32_t)) /* Channel A low side Polarity */
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#define ENUM_PWM_CHANCFG_AL_ACTLO (_ADI_MSK(0x00000000,uint32_t)) /* POLAL: Active Low */
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#define ENUM_PWM_CHANCFG_AL_ACTHI (_ADI_MSK(0x00000020,uint32_t)) /* POLAL: Active High */
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#define BITM_PWM_CHANCFG_ENCHOPAH (_ADI_MSK(0x00000008,uint32_t)) /* Channel A Gate Chopping Enable High Side */
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#define ENUM_PWM_CHANCFG_CHOPAH_DIS (_ADI_MSK(0x00000000,uint32_t)) /* ENCHOPAH: Disable Chopping Channel A High Side */
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#define ENUM_PWM_CHANCFG_CHOPAH_EN (_ADI_MSK(0x00000008,uint32_t)) /* ENCHOPAH: Enable Chopping Channel A High Side */
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#define BITM_PWM_CHANCFG_POLAH (_ADI_MSK(0x00000004,uint32_t)) /* Channel A High side Polarity */
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#define ENUM_PWM_CHANCFG_AH_ACTLO (_ADI_MSK(0x00000000,uint32_t)) /* POLAH: Active Low */
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#define ENUM_PWM_CHANCFG_AH_ACTHI (_ADI_MSK(0x00000004,uint32_t)) /* POLAH: Active High */
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#define BITM_PWM_CHANCFG_MODELSA (_ADI_MSK(0x00000002,uint32_t)) /* Channel A Mode of low Side Output */
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#define ENUM_PWM_CHANCFG_LOA_INVHI (_ADI_MSK(0x00000000,uint32_t)) /* MODELSA: Invert of high output */
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#define ENUM_PWM_CHANCFG_LOA_IND (_ADI_MSK(0x00000002,uint32_t)) /* MODELSA: Independent control */
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#define BITM_PWM_CHANCFG_REFTMRA (_ADI_MSK(0x00000001,uint32_t)) /* Channel A Timer Reference */
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#define ENUM_PWM_CHANCFG_REFTMRA_0 (_ADI_MSK(0x00000000,uint32_t)) /* REFTMRA: PWMTMR0 is Channel A reference */
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#define ENUM_PWM_CHANCFG_REFTMRA_1 (_ADI_MSK(0x00000001,uint32_t)) /* REFTMRA: PWMTMR1 is Channel A reference */
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_TRIPCFG Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_TRIPCFG_MODE1D 27 /* Mode of TRIP1 for Channel D */
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#define BITP_PWM_TRIPCFG_EN1D 26 /* Enable TRIP1 as a trip source for Channel D */
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#define BITP_PWM_TRIPCFG_MODE0D 25 /* Mode of TRIP0 for Channel D */
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#define BITP_PWM_TRIPCFG_EN0D 24 /* Enable TRIP0 as a trip source for Channel D */
|
|
#define BITP_PWM_TRIPCFG_MODE1C 19 /* Mode of TRIP1 for Channel C */
|
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#define BITP_PWM_TRIPCFG_EN1C 18 /* Enable TRIP1 as a trip source for Channel C */
|
|
#define BITP_PWM_TRIPCFG_MODE0C 17 /* Mode of TRIP0 for Channel C */
|
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#define BITP_PWM_TRIPCFG_EN0C 16 /* Enable TRIP0 as a trip source for Channel C */
|
|
#define BITP_PWM_TRIPCFG_MODE1B 11 /* Mode of TRIP1 for Channel B */
|
|
#define BITP_PWM_TRIPCFG_EN1B 10 /* Enable TRIP1 as a trip source for Channel B */
|
|
#define BITP_PWM_TRIPCFG_MODE0B 9 /* Mode of TRIP0 for Channel B */
|
|
#define BITP_PWM_TRIPCFG_EN0B 8 /* Enable TRIP0 as a trip source for Channel B */
|
|
#define BITP_PWM_TRIPCFG_MODE1A 3 /* Mode of TRIP1 for Channel A */
|
|
#define BITP_PWM_TRIPCFG_EN1A 2 /* Enable TRIP1 as a trip source for Channel A */
|
|
#define BITP_PWM_TRIPCFG_MODE0A 1 /* Mode of TRIP0 for Channel A */
|
|
#define BITP_PWM_TRIPCFG_EN0A 0 /* Enable TRIP0 as a trip source for Channel A */
|
|
|
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#define BITM_PWM_TRIPCFG_MODE1D (_ADI_MSK(0x08000000,uint32_t)) /* Mode of TRIP1 for Channel D */
|
|
#define ENUM_PWM_TRIPCFG_TRIP1D_FLT (_ADI_MSK(0x00000000,uint32_t)) /* MODE1D: Fault Trip on TRIP1 Input */
|
|
#define ENUM_PWM_TRIPCFG_TRIP1D_RSTRT (_ADI_MSK(0x08000000,uint32_t)) /* MODE1D: Self Restart on TRIP1 Input */
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|
|
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#define BITM_PWM_TRIPCFG_EN1D (_ADI_MSK(0x04000000,uint32_t)) /* Enable TRIP1 as a trip source for Channel D */
|
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#define ENUM_PWM_TRIPCFG_TRIP1D_DIS (_ADI_MSK(0x00000000,uint32_t)) /* EN1D: Disable TRIP1 for Channel D */
|
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#define ENUM_PWM_TRIPCFG_TRIP1D_EN (_ADI_MSK(0x04000000,uint32_t)) /* EN1D: Enable TRIP1 for Channel D */
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#define BITM_PWM_TRIPCFG_MODE0D (_ADI_MSK(0x02000000,uint32_t)) /* Mode of TRIP0 for Channel D */
|
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#define ENUM_PWM_TRIPCFG_TRIP0D_FLT (_ADI_MSK(0x00000000,uint32_t)) /* MODE0D: Fault Trip on TRIP0 Input */
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#define ENUM_PWM_TRIPCFG_TRIP0D_RSTRT (_ADI_MSK(0x02000000,uint32_t)) /* MODE0D: Self Restart on TRIP0 Input */
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|
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#define BITM_PWM_TRIPCFG_EN0D (_ADI_MSK(0x01000000,uint32_t)) /* Enable TRIP0 as a trip source for Channel D */
|
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#define ENUM_PWM_TRIPCFG_TRIP0D_DIS (_ADI_MSK(0x00000000,uint32_t)) /* EN0D: Disable TRIP0 for Channel D */
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#define ENUM_PWM_TRIPCFG_TRIP0D_EN (_ADI_MSK(0x01000000,uint32_t)) /* EN0D: Enable TRIP0 for Channel D */
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#define BITM_PWM_TRIPCFG_MODE1C (_ADI_MSK(0x00080000,uint32_t)) /* Mode of TRIP1 for Channel C */
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#define ENUM_PWM_TRIPCFG_TRIP1C_FLT (_ADI_MSK(0x00000000,uint32_t)) /* MODE1C: Fault Trip on TRIP1 Input */
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#define ENUM_PWM_TRIPCFG_TRIP1C_RSTRT (_ADI_MSK(0x00080000,uint32_t)) /* MODE1C: Self Restart on TRIP1 Input */
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#define BITM_PWM_TRIPCFG_EN1C (_ADI_MSK(0x00040000,uint32_t)) /* Enable TRIP1 as a trip source for Channel C */
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#define ENUM_PWM_TRIPCFG_TRIP1C_DIS (_ADI_MSK(0x00000000,uint32_t)) /* EN1C: Disable TRIP1 for Channel C */
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#define ENUM_PWM_TRIPCFG_TRIP1C_EN (_ADI_MSK(0x00040000,uint32_t)) /* EN1C: Enable TRIP1 for Channel C */
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#define BITM_PWM_TRIPCFG_MODE0C (_ADI_MSK(0x00020000,uint32_t)) /* Mode of TRIP0 for Channel C */
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#define ENUM_PWM_TRIPCFG_TRIP0C_FLT (_ADI_MSK(0x00000000,uint32_t)) /* MODE0C: Fault Trip on TRIP0 Input */
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#define ENUM_PWM_TRIPCFG_TRIP0C_RSTRT (_ADI_MSK(0x00020000,uint32_t)) /* MODE0C: Self Restart on TRIP0 Input */
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#define BITM_PWM_TRIPCFG_EN0C (_ADI_MSK(0x00010000,uint32_t)) /* Enable TRIP0 as a trip source for Channel C */
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#define ENUM_PWM_TRIPCFG_TRIP0C_DIS (_ADI_MSK(0x00000000,uint32_t)) /* EN0C: Disable TRIP0 for Channel C */
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#define ENUM_PWM_TRIPCFG_TRIP0C_EN (_ADI_MSK(0x00010000,uint32_t)) /* EN0C: Enable TRIP0 for Channel C */
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#define BITM_PWM_TRIPCFG_MODE1B (_ADI_MSK(0x00000800,uint32_t)) /* Mode of TRIP1 for Channel B */
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#define ENUM_PWM_TRIPCFG_TRIP1B_FLT (_ADI_MSK(0x00000000,uint32_t)) /* MODE1B: Fault Trip on TRIP1 Input */
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#define ENUM_PWM_TRIPCFG_TRIP1B_RSTRT (_ADI_MSK(0x00000800,uint32_t)) /* MODE1B: Self Restart on TRIP1 Input */
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#define BITM_PWM_TRIPCFG_EN1B (_ADI_MSK(0x00000400,uint32_t)) /* Enable TRIP1 as a trip source for Channel B */
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#define ENUM_PWM_TRIPCFG_TRIP1B_DIS (_ADI_MSK(0x00000000,uint32_t)) /* EN1B: Disable TRIP1 for Channel B */
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#define ENUM_PWM_TRIPCFG_TRIP1B_EN (_ADI_MSK(0x00000400,uint32_t)) /* EN1B: Enable TRIP1 for Channel B */
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#define BITM_PWM_TRIPCFG_MODE0B (_ADI_MSK(0x00000200,uint32_t)) /* Mode of TRIP0 for Channel B */
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#define ENUM_PWM_TRIPCFG_TRIP0B_FLT (_ADI_MSK(0x00000000,uint32_t)) /* MODE0B: Fault Trip on TRIP0 Input */
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#define ENUM_PWM_TRIPCFG_TRIP0B_RSTRT (_ADI_MSK(0x00000200,uint32_t)) /* MODE0B: Self Restart on TRIP0 Input */
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#define BITM_PWM_TRIPCFG_EN0B (_ADI_MSK(0x00000100,uint32_t)) /* Enable TRIP0 as a trip source for Channel B */
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#define ENUM_PWM_TRIPCFG_TRIP0B_DIS (_ADI_MSK(0x00000000,uint32_t)) /* EN0B: Disable TRIP0 for Channel B */
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#define ENUM_PWM_TRIPCFG_TRIP0B_EN (_ADI_MSK(0x00000100,uint32_t)) /* EN0B: Enable TRIP0 for Channel B */
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#define BITM_PWM_TRIPCFG_MODE1A (_ADI_MSK(0x00000008,uint32_t)) /* Mode of TRIP1 for Channel A */
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#define ENUM_PWM_TRIPCFG_TRIP1A_FLT (_ADI_MSK(0x00000000,uint32_t)) /* MODE1A: Fault Trip on TRIP1 Input */
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#define ENUM_PWM_TRIPCFG_TRIP1A_RSTRT (_ADI_MSK(0x00000008,uint32_t)) /* MODE1A: Self Restart on TRIP1 Input */
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#define BITM_PWM_TRIPCFG_EN1A (_ADI_MSK(0x00000004,uint32_t)) /* Enable TRIP1 as a trip source for Channel A */
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#define ENUM_PWM_TRIPCFG_TRIP1A_DIS (_ADI_MSK(0x00000000,uint32_t)) /* EN1A: Disable TRIP1 for Channel A */
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#define ENUM_PWM_TRIPCFG_TRIP1A_EN (_ADI_MSK(0x00000004,uint32_t)) /* EN1A: Enable TRIP1 for Channel A */
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#define BITM_PWM_TRIPCFG_MODE0A (_ADI_MSK(0x00000002,uint32_t)) /* Mode of TRIP0 for Channel A */
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#define ENUM_PWM_TRIPCFG_TRIP0A_FLT (_ADI_MSK(0x00000000,uint32_t)) /* MODE0A: Fault Trip on TRIP0 Input */
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#define ENUM_PWM_TRIPCFG_TRIP0A_RSTRT (_ADI_MSK(0x00000002,uint32_t)) /* MODE0A: Self Restart on TRIP0 Input */
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#define BITM_PWM_TRIPCFG_EN0A (_ADI_MSK(0x00000001,uint32_t)) /* Enable TRIP0 as a trip source for Channel A */
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#define ENUM_PWM_TRIPCFG_TRIP0A_DIS (_ADI_MSK(0x00000000,uint32_t)) /* EN0A: Disable TRIP0 for Channel A */
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#define ENUM_PWM_TRIPCFG_TRIP0A_EN (_ADI_MSK(0x00000001,uint32_t)) /* EN0A: Enable TRIP0 for Channel A */
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/* ------------------------------------------------------------------------------------------------------------------------
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PWM_STAT Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_PWM_STAT_TMR4PHASE 28 /* PWMTMR4 Phase Status */
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#define BITP_PWM_STAT_TMR3PHASE 27 /* PWMTMR3 Phase Status */
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#define BITP_PWM_STAT_TMR2PHASE 26 /* PWMTMR2 Phase Status */
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#define BITP_PWM_STAT_TMR1PHASE 25 /* PWMTMR1 Phase Status */
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#define BITP_PWM_STAT_TMR0PHASE 24 /* PWMTMR0 Phase Status */
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#define BITP_PWM_STAT_TMR4PER 20 /* PWMTMR4 Period Boundary Status */
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#define BITP_PWM_STAT_TMR3PER 19 /* PWMTMR3 Period Boundary Status */
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#define BITP_PWM_STAT_TMR2PER 18 /* PWMTMR2 Period Boundary Status */
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#define BITP_PWM_STAT_TMR1PER 17 /* PWMTMR1 Period Boundary Status */
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#define BITP_PWM_STAT_TMR0PER 16 /* PWMTMR0 Period Boundary Status */
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#define BITP_PWM_STAT_SRTRIPD 11 /* Self-Restart Trip Status for Channel D */
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#define BITP_PWM_STAT_FLTTRIPD 10 /* Fault Trip Status for Channel D */
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#define BITP_PWM_STAT_SRTRIPC 9 /* Self-Restart Trip Status for Channel C */
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#define BITP_PWM_STAT_FLTTRIPC 8 /* Fault Trip Status for Channel C */
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#define BITP_PWM_STAT_SRTRIPB 7 /* Self-Restart Trip Status for Channel B */
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#define BITP_PWM_STAT_FLTTRIPB 6 /* Fault Trip Status for Channel B */
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#define BITP_PWM_STAT_SRTRIPA 5 /* Self-Restart Trip Status for Channel A */
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#define BITP_PWM_STAT_FLTTRIPA 4 /* Fault Trip Status for Channel A */
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#define BITP_PWM_STAT_RAWTRIP1 3 /* Raw Trip 1 Status */
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#define BITP_PWM_STAT_RAWTRIP0 2 /* Raw Trip 0 Status */
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#define BITP_PWM_STAT_TRIP1 1 /* Status bit set when TRIP1 is active low */
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#define BITP_PWM_STAT_TRIP0 0 /* Status bit set when TRIP0 is active low */
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#define BITM_PWM_STAT_TMR4PHASE (_ADI_MSK(0x10000000,uint32_t)) /* PWMTMR4 Phase Status */
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#define ENUM_PWM_STAT_TMR4PH1 (_ADI_MSK(0x00000000,uint32_t)) /* TMR4PHASE: 1st Half Phase */
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#define ENUM_PWM_STAT_TMR4PH2 (_ADI_MSK(0x10000000,uint32_t)) /* TMR4PHASE: 2nd Half Phase */
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#define BITM_PWM_STAT_TMR3PHASE (_ADI_MSK(0x08000000,uint32_t)) /* PWMTMR3 Phase Status */
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#define ENUM_PWM_STAT_TMR3PH1 (_ADI_MSK(0x00000000,uint32_t)) /* TMR3PHASE: 1st Half Phase */
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#define ENUM_PWM_STAT_TMR3PH2 (_ADI_MSK(0x08000000,uint32_t)) /* TMR3PHASE: 2nd Half Phase */
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#define BITM_PWM_STAT_TMR2PHASE (_ADI_MSK(0x04000000,uint32_t)) /* PWMTMR2 Phase Status */
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#define ENUM_PWM_STAT_TMR2PH1 (_ADI_MSK(0x00000000,uint32_t)) /* TMR2PHASE: 1st Half Phase */
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#define ENUM_PWM_STAT_TMR2PH2 (_ADI_MSK(0x04000000,uint32_t)) /* TMR2PHASE: 2nd Half Phase */
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#define BITM_PWM_STAT_TMR1PHASE (_ADI_MSK(0x02000000,uint32_t)) /* PWMTMR1 Phase Status */
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#define ENUM_PWM_STAT_TMR1PH1 (_ADI_MSK(0x00000000,uint32_t)) /* TMR1PHASE: 1st Half Phase */
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#define ENUM_PWM_STAT_TMR1PH2 (_ADI_MSK(0x02000000,uint32_t)) /* TMR1PHASE: 2nd Half Phase */
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#define BITM_PWM_STAT_TMR0PHASE (_ADI_MSK(0x01000000,uint32_t)) /* PWMTMR0 Phase Status */
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#define ENUM_PWM_STAT_TMR0PH1 (_ADI_MSK(0x00000000,uint32_t)) /* TMR0PHASE: 1st Half Phase */
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#define ENUM_PWM_STAT_TMR0PH2 (_ADI_MSK(0x01000000,uint32_t)) /* TMR0PHASE: 2nd Half Phase */
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#define BITM_PWM_STAT_TMR4PER (_ADI_MSK(0x00100000,uint32_t)) /* PWMTMR4 Period Boundary Status */
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#define ENUM_PWM_STAT_NOT_PER4 (_ADI_MSK(0x00000000,uint32_t)) /* TMR4PER: PWMTMR4 period boundary not reached */
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#define ENUM_PWM_STAT_PER4 (_ADI_MSK(0x00100000,uint32_t)) /* TMR4PER: PWMTMR4 period boundary reached */
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#define BITM_PWM_STAT_TMR3PER (_ADI_MSK(0x00080000,uint32_t)) /* PWMTMR3 Period Boundary Status */
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#define ENUM_PWM_STAT_NOT_PER3 (_ADI_MSK(0x00000000,uint32_t)) /* TMR3PER: PWMTMR3 period boundary not reached */
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#define ENUM_PWM_STAT_PER3 (_ADI_MSK(0x00080000,uint32_t)) /* TMR3PER: PWMTMR3 period boundary reached */
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#define BITM_PWM_STAT_TMR2PER (_ADI_MSK(0x00040000,uint32_t)) /* PWMTMR2 Period Boundary Status */
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#define ENUM_PWM_STAT_NOT_PER2 (_ADI_MSK(0x00000000,uint32_t)) /* TMR2PER: PWMTMR2 period boundary not reached */
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#define ENUM_PWM_STAT_PER2 (_ADI_MSK(0x00040000,uint32_t)) /* TMR2PER: PWMTMR2 period boundary reached */
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#define BITM_PWM_STAT_TMR1PER (_ADI_MSK(0x00020000,uint32_t)) /* PWMTMR1 Period Boundary Status */
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#define ENUM_PWM_STAT_NOT_PER1 (_ADI_MSK(0x00000000,uint32_t)) /* TMR1PER: PWMTMR1 period boundary not reached */
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#define ENUM_PWM_STAT_PER1 (_ADI_MSK(0x00020000,uint32_t)) /* TMR1PER: PWMTMR1 period boundary reached */
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#define BITM_PWM_STAT_TMR0PER (_ADI_MSK(0x00010000,uint32_t)) /* PWMTMR0 Period Boundary Status */
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#define ENUM_PWM_STAT_NOT_PER0 (_ADI_MSK(0x00000000,uint32_t)) /* TMR0PER: PWMTMR0 period boundary not reached */
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#define ENUM_PWM_STAT_PER0 (_ADI_MSK(0x00010000,uint32_t)) /* TMR0PER: PWMTMR0 period boundary reached */
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#define BITM_PWM_STAT_SRTRIPD (_ADI_MSK(0x00000800,uint32_t)) /* Self-Restart Trip Status for Channel D */
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#define ENUM_PWM_STAT_SRD_NOTRIP (_ADI_MSK(0x00000000,uint32_t)) /* SRTRIPD: Channel D Self-Restart Trip Status is "not tripped" */
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#define ENUM_PWM_STAT_SRD_TRIP (_ADI_MSK(0x00000800,uint32_t)) /* SRTRIPD: Channel D Self-Restart Trip Status is "tripped" */
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#define BITM_PWM_STAT_FLTTRIPD (_ADI_MSK(0x00000400,uint32_t)) /* Fault Trip Status for Channel D */
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#define ENUM_PWM_STAT_FLTD_NOTRIP (_ADI_MSK(0x00000000,uint32_t)) /* FLTTRIPD: Channel D Fault Trip Status is "not tripped" */
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#define ENUM_PWM_STAT_FLTD_TRIP (_ADI_MSK(0x00000400,uint32_t)) /* FLTTRIPD: Channel D Fault Trip Status is "tripped" */
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#define BITM_PWM_STAT_SRTRIPC (_ADI_MSK(0x00000200,uint32_t)) /* Self-Restart Trip Status for Channel C */
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#define ENUM_PWM_STAT_SRC_NOTRIP (_ADI_MSK(0x00000000,uint32_t)) /* SRTRIPC: Channel C Self-Restart Trip Status is "not tripped" */
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#define ENUM_PWM_STAT_SRC_TRIP (_ADI_MSK(0x00000200,uint32_t)) /* SRTRIPC: Channel C Self-Restart Trip Status is "tripped" */
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#define BITM_PWM_STAT_FLTTRIPC (_ADI_MSK(0x00000100,uint32_t)) /* Fault Trip Status for Channel C */
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#define ENUM_PWM_STAT_FLTC_NOTRIP (_ADI_MSK(0x00000000,uint32_t)) /* FLTTRIPC: Channel C Fault Trip Status is "not tripped" */
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#define ENUM_PWM_STAT_FLTC_TRIP (_ADI_MSK(0x00000100,uint32_t)) /* FLTTRIPC: Channel C Fault Trip Status is "tripped" */
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#define BITM_PWM_STAT_SRTRIPB (_ADI_MSK(0x00000080,uint32_t)) /* Self-Restart Trip Status for Channel B */
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#define ENUM_PWM_STAT_SRB_NOTRIP (_ADI_MSK(0x00000000,uint32_t)) /* SRTRIPB: Channel B Self-Restart Trip Status is "not tripped" */
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#define ENUM_PWM_STAT_SRB_TRIP (_ADI_MSK(0x00000080,uint32_t)) /* SRTRIPB: Channel B Self-Restart Trip Status is "tripped" */
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#define BITM_PWM_STAT_FLTTRIPB (_ADI_MSK(0x00000040,uint32_t)) /* Fault Trip Status for Channel B */
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#define ENUM_PWM_STAT_FLTB_NOTRIP (_ADI_MSK(0x00000000,uint32_t)) /* FLTTRIPB: Channel B Fault Trip Status is "not tripped" */
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#define ENUM_PWM_STAT_FLTB_TRIP (_ADI_MSK(0x00000040,uint32_t)) /* FLTTRIPB: Channel A Fault Trip Status is "tripped" */
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#define BITM_PWM_STAT_SRTRIPA (_ADI_MSK(0x00000020,uint32_t)) /* Self-Restart Trip Status for Channel A */
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#define ENUM_PWM_STAT_SRA_NOTRIP (_ADI_MSK(0x00000000,uint32_t)) /* SRTRIPA: Channel A Self-Restart Trip Status is "not tripped" */
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#define ENUM_PWM_STAT_SRA_TRIP (_ADI_MSK(0x00000020,uint32_t)) /* SRTRIPA: Channel A Self-Restart Trip Status is "tripped" */
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#define BITM_PWM_STAT_FLTTRIPA (_ADI_MSK(0x00000010,uint32_t)) /* Fault Trip Status for Channel A */
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#define ENUM_PWM_STAT_FLTA_NOTRIP (_ADI_MSK(0x00000000,uint32_t)) /* FLTTRIPA: Channel A Fault Trip Status is "not tripped" */
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#define ENUM_PWM_STAT_FLTA_TRIP (_ADI_MSK(0x00000010,uint32_t)) /* FLTTRIPA: Channel A Fault Trip Status is "tripped" */
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#define BITM_PWM_STAT_RAWTRIP1 (_ADI_MSK(0x00000008,uint32_t)) /* Raw Trip 1 Status */
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#define ENUM_PWM_STAT_TRIP1LVL_LO (_ADI_MSK(0x00000000,uint32_t)) /* RAWTRIP1: TRIP1 Level is Low */
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#define ENUM_PWM_STAT_TRIP1LVL_HI (_ADI_MSK(0x00000008,uint32_t)) /* RAWTRIP1: TRIP1 Level is High */
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#define BITM_PWM_STAT_RAWTRIP0 (_ADI_MSK(0x00000004,uint32_t)) /* Raw Trip 0 Status */
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#define ENUM_PWM_STAT_TRIP0LVL_LO (_ADI_MSK(0x00000000,uint32_t)) /* RAWTRIP0: TRIP0 Level is Low */
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#define ENUM_PWM_STAT_TRIP0LVL_HI (_ADI_MSK(0x00000004,uint32_t)) /* RAWTRIP0: TRIP0 Level is High */
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#define BITM_PWM_STAT_TRIP1 (_ADI_MSK(0x00000002,uint32_t)) /* Status bit set when TRIP1 is active low */
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#define ENUM_PWM_STAT_NO_TRIP1 (_ADI_MSK(0x00000000,uint32_t)) /* TRIP1: TRIP1 status is "not tripped" */
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#define ENUM_PWM_STAT_TRIP1 (_ADI_MSK(0x00000002,uint32_t)) /* TRIP1: TRIP1 status is "tripped" (active low) */
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#define BITM_PWM_STAT_TRIP0 (_ADI_MSK(0x00000001,uint32_t)) /* Status bit set when TRIP0 is active low */
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#define ENUM_PWM_STAT_NO_TRIP0 (_ADI_MSK(0x00000000,uint32_t)) /* TRIP0: TRIP0 status is "not tripped" */
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#define ENUM_PWM_STAT_TRIP0 (_ADI_MSK(0x00000001,uint32_t)) /* TRIP0: TRIP0 status is "tripped" (active low) */
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/* ------------------------------------------------------------------------------------------------------------------------
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PWM_IMSK Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_PWM_IMSK_TMR4PER 20 /* PWMTMR4 Period Boundary Interrupt Enable */
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#define BITP_PWM_IMSK_TMR3PER 19 /* PWMTMR3 Period Boundary Interrupt Enable */
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#define BITP_PWM_IMSK_TMR2PER 18 /* PWMTMR2 Period Boundary Interrupt Enable */
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#define BITP_PWM_IMSK_TMR1PER 17 /* PWMTMR1 Period Boundary Interrupt Enable */
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#define BITP_PWM_IMSK_TMR0PER 16 /* PWMTMR0 Period Boundary Interrupt Enable */
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#define BITP_PWM_IMSK_TRIP1 1 /* TRIP1 Interrupt Enable */
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#define BITP_PWM_IMSK_TRIP0 0 /* TRIP0 Interrupt Enable */
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#define BITM_PWM_IMSK_TMR4PER (_ADI_MSK(0x00100000,uint32_t)) /* PWMTMR4 Period Boundary Interrupt Enable */
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#define ENUM_PWM_IMSK_PER4_MSK (_ADI_MSK(0x00000000,uint32_t)) /* TMR4PER: Mask PWMTMR4 Period Interrupt */
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#define ENUM_PWM_IMSK_PER4_UMSK (_ADI_MSK(0x00100000,uint32_t)) /* TMR4PER: Unmask PWMTMR4 Period Interrupt */
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#define BITM_PWM_IMSK_TMR3PER (_ADI_MSK(0x00080000,uint32_t)) /* PWMTMR3 Period Boundary Interrupt Enable */
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#define ENUM_PWM_IMSK_PER3_MSK (_ADI_MSK(0x00000000,uint32_t)) /* TMR3PER: Mask PWMTMR3 Period Interrupt */
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#define ENUM_PWM_IMSK_PER3_UMSK (_ADI_MSK(0x00080000,uint32_t)) /* TMR3PER: Unmask PWMTMR3 Period Interrupt */
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#define BITM_PWM_IMSK_TMR2PER (_ADI_MSK(0x00040000,uint32_t)) /* PWMTMR2 Period Boundary Interrupt Enable */
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#define ENUM_PWM_IMSK_PER2_MSK (_ADI_MSK(0x00000000,uint32_t)) /* TMR2PER: Mask PWMTMR2 Period Interrupt */
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#define ENUM_PWM_IMSK_PER2_UMSK (_ADI_MSK(0x00040000,uint32_t)) /* TMR2PER: Unmask PWMTMR2 Period Interrupt */
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#define BITM_PWM_IMSK_TMR1PER (_ADI_MSK(0x00020000,uint32_t)) /* PWMTMR1 Period Boundary Interrupt Enable */
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#define ENUM_PWM_IMSK_PER1_MSK (_ADI_MSK(0x00000000,uint32_t)) /* TMR1PER: Mask PWMTMR1 Period Interrupt */
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#define ENUM_PWM_IMSK_PER1_UMSK (_ADI_MSK(0x00020000,uint32_t)) /* TMR1PER: Unmask PWMTMR1 Period Interrupt */
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#define BITM_PWM_IMSK_TMR0PER (_ADI_MSK(0x00010000,uint32_t)) /* PWMTMR0 Period Boundary Interrupt Enable */
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#define ENUM_PWM_IMSK_PER0_MSK (_ADI_MSK(0x00000000,uint32_t)) /* TMR0PER: Mask PWMTMR0 Period Interrupt */
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#define ENUM_PWM_IMSK_PER0_UMSK (_ADI_MSK(0x00010000,uint32_t)) /* TMR0PER: Unmask PWMTMR0 Period Interrupt */
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#define BITM_PWM_IMSK_TRIP1 (_ADI_MSK(0x00000002,uint32_t)) /* TRIP1 Interrupt Enable */
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#define ENUM_PWM_IMSK_TRIP1_MSK (_ADI_MSK(0x00000000,uint32_t)) /* TRIP1: Mask TRIP1 Interrupt */
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#define ENUM_PWM_IMSK_TRIP1_UMSK (_ADI_MSK(0x00000002,uint32_t)) /* TRIP1: Unmask TRIP1 Interrupt */
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#define BITM_PWM_IMSK_TRIP0 (_ADI_MSK(0x00000001,uint32_t)) /* TRIP0 Interrupt Enable */
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#define ENUM_PWM_IMSK_TRIP0_MSK (_ADI_MSK(0x00000000,uint32_t)) /* TRIP0: Mask TRIP0 Interrupt */
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#define ENUM_PWM_IMSK_TRIP0_UMSK (_ADI_MSK(0x00000001,uint32_t)) /* TRIP0: Unmask TRIP0 Interrupt */
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/* ------------------------------------------------------------------------------------------------------------------------
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PWM_ILAT Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_PWM_ILAT_TMR4PER 20 /* PWMTMR4 Period Latched Interrupt Status */
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#define BITP_PWM_ILAT_TMR3PER 19 /* PWMTMR3 Period Latched Interrupt Status */
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#define BITP_PWM_ILAT_TMR2PER 18 /* PWMTMR2 Period Latched Interrupt Status */
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#define BITP_PWM_ILAT_TMR1PER 17 /* PWMTMR1 Period Latched Interrupt Status */
|
|
#define BITP_PWM_ILAT_TMR0PER 16 /* PWMTMR0 Period Boundary Interrupt Latched Status */
|
|
#define BITP_PWM_ILAT_TRIP1 1 /* TRIP1 Interrupt Latched Status */
|
|
#define BITP_PWM_ILAT_TRIP0 0 /* TRIP0 Interrupt Latched Status */
|
|
|
|
#define BITM_PWM_ILAT_TMR4PER (_ADI_MSK(0x00100000,uint32_t)) /* PWMTMR4 Period Latched Interrupt Status */
|
|
#define ENUM_PWM_ILAT_PER4_INTLO (_ADI_MSK(0x00000000,uint32_t)) /* TMR4PER: No Interrupt Latched */
|
|
#define ENUM_PWM_ILAT_PER4_INTHI (_ADI_MSK(0x00100000,uint32_t)) /* TMR4PER: Interrupt Latched */
|
|
|
|
#define BITM_PWM_ILAT_TMR3PER (_ADI_MSK(0x00080000,uint32_t)) /* PWMTMR3 Period Latched Interrupt Status */
|
|
#define ENUM_PWM_ILAT_PER3_INTLO (_ADI_MSK(0x00000000,uint32_t)) /* TMR3PER: No Interrupt Latched */
|
|
#define ENUM_PWM_ILAT_PER3_INTHI (_ADI_MSK(0x00080000,uint32_t)) /* TMR3PER: Interrupt Latched */
|
|
|
|
#define BITM_PWM_ILAT_TMR2PER (_ADI_MSK(0x00040000,uint32_t)) /* PWMTMR2 Period Latched Interrupt Status */
|
|
#define ENUM_PWM_ILAT_PER2_INTLO (_ADI_MSK(0x00000000,uint32_t)) /* TMR2PER: No Interrupt Latched */
|
|
#define ENUM_PWM_ILAT_PER2_INTHI (_ADI_MSK(0x00040000,uint32_t)) /* TMR2PER: Interrupt Latched */
|
|
|
|
#define BITM_PWM_ILAT_TMR1PER (_ADI_MSK(0x00020000,uint32_t)) /* PWMTMR1 Period Latched Interrupt Status */
|
|
#define ENUM_PWM_ILAT_PER1_INTLO (_ADI_MSK(0x00000000,uint32_t)) /* TMR1PER: No Interrupt Latched */
|
|
#define ENUM_PWM_ILAT_PER1_INTHI (_ADI_MSK(0x00020000,uint32_t)) /* TMR1PER: Interrupt Latched */
|
|
|
|
#define BITM_PWM_ILAT_TMR0PER (_ADI_MSK(0x00010000,uint32_t)) /* PWMTMR0 Period Boundary Interrupt Latched Status */
|
|
#define ENUM_PWM_ILAT_PER0_INTLO (_ADI_MSK(0x00000000,uint32_t)) /* TMR0PER: No Interrupt Latched */
|
|
#define ENUM_PWM_ILAT_PER0_INTHI (_ADI_MSK(0x00010000,uint32_t)) /* TMR0PER: Interrupt Latched */
|
|
|
|
#define BITM_PWM_ILAT_TRIP1 (_ADI_MSK(0x00000002,uint32_t)) /* TRIP1 Interrupt Latched Status */
|
|
#define ENUM_PWM_ILAT_TRIP1_INTLO (_ADI_MSK(0x00000000,uint32_t)) /* TRIP1: No Interrupt Latched */
|
|
#define ENUM_PWM_ILAT_TRIP1_INTHI (_ADI_MSK(0x00000002,uint32_t)) /* TRIP1: Interrupt Latched */
|
|
|
|
#define BITM_PWM_ILAT_TRIP0 (_ADI_MSK(0x00000001,uint32_t)) /* TRIP0 Interrupt Latched Status */
|
|
#define ENUM_PWM_ILAT_TRIP0_INTLO (_ADI_MSK(0x00000000,uint32_t)) /* TRIP0: No Interrupt Latched */
|
|
#define ENUM_PWM_ILAT_TRIP0_INTHI (_ADI_MSK(0x00000001,uint32_t)) /* TRIP0: Interrupt Latched */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_CHOPCFG Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_CHOPCFG_VALUE 0 /* Gate Chopping Divisor */
|
|
#define BITM_PWM_CHOPCFG_VALUE (_ADI_MSK(0x000000FF,uint32_t)) /* Gate Chopping Divisor */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_DT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_DT_VALUE 0 /* Dead Time */
|
|
#define BITM_PWM_DT_VALUE (_ADI_MSK(0x000003FF,uint32_t)) /* Dead Time */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_SYNC_WID Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_SYNC_WID_VALUE 0 /* Sync Pulse Width */
|
|
#define BITM_PWM_SYNC_WID_VALUE (_ADI_MSK(0x000003FF,uint32_t)) /* Sync Pulse Width */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_TM0 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_TM0_VALUE 0 /* Timer PWMTMR0 Period Value */
|
|
#define BITM_PWM_TM0_VALUE (_ADI_MSK(0x0000FFFF,uint32_t)) /* Timer PWMTMR0 Period Value */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_TM1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_TM1_VALUE 0 /* Timer PWMTMR1 Period Value */
|
|
#define BITM_PWM_TM1_VALUE (_ADI_MSK(0x0000FFFF,uint32_t)) /* Timer PWMTMR1 Period Value */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_TM2 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_TM2_VALUE 0 /* Timer PWMTMR2 Period Value */
|
|
#define BITM_PWM_TM2_VALUE (_ADI_MSK(0x0000FFFF,uint32_t)) /* Timer PWMTMR2 Period Value */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_TM3 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_TM3_VALUE 0 /* Timer PWMTMR3 Period Value */
|
|
#define BITM_PWM_TM3_VALUE (_ADI_MSK(0x0000FFFF,uint32_t)) /* Timer PWMTMR3 Period Value */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_TM4 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_TM4_VALUE 0 /* Timer PWMTMR4 Period Value */
|
|
#define BITM_PWM_TM4_VALUE (_ADI_MSK(0x0000FFFF,uint32_t)) /* Timer PWMTMR4 Period Value */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_DLYA Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_DLYA_VALUE 0 /* Channel A Delay Value */
|
|
#define BITM_PWM_DLYA_VALUE (_ADI_MSK(0x0000FFFF,uint32_t)) /* Channel A Delay Value */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_DLYB Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_DLYB_VALUE 0 /* Channel B Delay Value */
|
|
#define BITM_PWM_DLYB_VALUE (_ADI_MSK(0x0000FFFF,uint32_t)) /* Channel B Delay Value */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_DLYC Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_DLYC_VALUE 0 /* Channel C Delay Value */
|
|
#define BITM_PWM_DLYC_VALUE (_ADI_MSK(0x0000FFFF,uint32_t)) /* Channel C Delay Value */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_DLYD Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_DLYD_VALUE 0 /* Channel D Delay Value */
|
|
#define BITM_PWM_DLYD_VALUE (_ADI_MSK(0x0000FFFF,uint32_t)) /* Channel D Delay Value */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_ACTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_ACTL_PULSEMODELO 10 /* Low Side Output Pulse Position */
|
|
#define BITP_PWM_ACTL_PULSEMODEHI 8 /* High Side Output Pulse Position */
|
|
#define BITP_PWM_ACTL_XOVR 2 /* high-low Crossover Enable */
|
|
#define BITP_PWM_ACTL_DISLO 1 /* Channel Low Side Output Disable */
|
|
#define BITP_PWM_ACTL_DISHI 0 /* Channel High Side Output Disable */
|
|
|
|
#define BITM_PWM_ACTL_PULSEMODELO (_ADI_MSK(0x00000C00,uint32_t)) /* Low Side Output Pulse Position */
|
|
#define ENUM_PWM_SYM_LO (_ADI_MSK(0x00000000,uint32_t)) /* PULSEMODELO: Symmetrical */
|
|
#define ENUM_PWM_ASYM_LO (_ADI_MSK(0x00000400,uint32_t)) /* PULSEMODELO: Asymmetrical */
|
|
#define ENUM_PWM_LEFT_LO (_ADI_MSK(0x00000800,uint32_t)) /* PULSEMODELO: Left Half */
|
|
#define ENUM_PWM_RIGHT_LO (_ADI_MSK(0x00000C00,uint32_t)) /* PULSEMODELO: Right Half */
|
|
|
|
#define BITM_PWM_ACTL_PULSEMODEHI (_ADI_MSK(0x00000300,uint32_t)) /* High Side Output Pulse Position */
|
|
#define ENUM_PWM_SYM_HI (_ADI_MSK(0x00000000,uint32_t)) /* PULSEMODEHI: Symmetrical */
|
|
#define ENUM_PWM_ASYM_HI (_ADI_MSK(0x00000100,uint32_t)) /* PULSEMODEHI: Asymmetrical */
|
|
#define ENUM_PWM_LEFT_HI (_ADI_MSK(0x00000200,uint32_t)) /* PULSEMODEHI: Left Half */
|
|
#define ENUM_PWM_RIGHT_HI (_ADI_MSK(0x00000300,uint32_t)) /* PULSEMODEHI: Right Half */
|
|
|
|
#define BITM_PWM_ACTL_XOVR (_ADI_MSK(0x00000004,uint32_t)) /* high-low Crossover Enable */
|
|
#define ENUM_PWM_XOVR_DIS (_ADI_MSK(0x00000000,uint32_t)) /* XOVR: Disable Crossover */
|
|
#define ENUM_PWM_XOVR_EN (_ADI_MSK(0x00000004,uint32_t)) /* XOVR: Enable Crossover */
|
|
|
|
#define BITM_PWM_ACTL_DISLO (_ADI_MSK(0x00000002,uint32_t)) /* Channel Low Side Output Disable */
|
|
#define ENUM_PWM_LO_DIS (_ADI_MSK(0x00000000,uint32_t)) /* DISLO: Disable Low Side Output */
|
|
#define ENUM_PWM_LO_EN (_ADI_MSK(0x00000002,uint32_t)) /* DISLO: Enable Low Side Output */
|
|
|
|
#define BITM_PWM_ACTL_DISHI (_ADI_MSK(0x00000001,uint32_t)) /* Channel High Side Output Disable */
|
|
#define ENUM_PWM_HI_DIS (_ADI_MSK(0x00000000,uint32_t)) /* DISHI: Disable High Side Output */
|
|
#define ENUM_PWM_HI_EN (_ADI_MSK(0x00000001,uint32_t)) /* DISHI: Enable High Side Output */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_AH0 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_AH0_DUTY 0 /* Duty Cycle Asserted Count */
|
|
#define BITM_PWM_AH0_DUTY (_ADI_MSK(0x0000FFFF,uint32_t)) /* Duty Cycle Asserted Count */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_AH1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_AH1_DUTY 0 /* Duty Cycle De-Asserted Count */
|
|
#define BITM_PWM_AH1_DUTY (_ADI_MSK(0x0000FFFF,uint32_t)) /* Duty Cycle De-Asserted Count */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_AL0 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_AL0_DUTY 0 /* Duty Cycle Asserted Count */
|
|
#define BITM_PWM_AL0_DUTY (_ADI_MSK(0x0000FFFF,uint32_t)) /* Duty Cycle Asserted Count */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_AL1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_AL1_DUTY 0 /* Duty Cycle De-Asserted Count */
|
|
#define BITM_PWM_AL1_DUTY (_ADI_MSK(0x0000FFFF,uint32_t)) /* Duty Cycle De-Asserted Count */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_BCTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_BCTL_PULSEMODELO 10 /* Low Side Output Pulse Position */
|
|
#define BITP_PWM_BCTL_PULSEMODEHI 8 /* High Side Output Pulse Position */
|
|
#define BITP_PWM_BCTL_XOVR 2 /* high-low Crossover Enable */
|
|
#define BITP_PWM_BCTL_DISLO 1 /* Channel Low Side Output Disable */
|
|
#define BITP_PWM_BCTL_DISHI 0 /* Channel High Side Output Disable */
|
|
|
|
/* The fields and enumerations for PWM_BCTL are also in PWM - see the common set of ENUM_PWM_* #defines located with register PWM_ACTL */
|
|
|
|
#define BITM_PWM_BCTL_PULSEMODELO (_ADI_MSK(0x00000C00,uint32_t)) /* Low Side Output Pulse Position */
|
|
#define BITM_PWM_BCTL_PULSEMODEHI (_ADI_MSK(0x00000300,uint32_t)) /* High Side Output Pulse Position */
|
|
#define BITM_PWM_BCTL_XOVR (_ADI_MSK(0x00000004,uint32_t)) /* high-low Crossover Enable */
|
|
#define BITM_PWM_BCTL_DISLO (_ADI_MSK(0x00000002,uint32_t)) /* Channel Low Side Output Disable */
|
|
#define BITM_PWM_BCTL_DISHI (_ADI_MSK(0x00000001,uint32_t)) /* Channel High Side Output Disable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_BH0 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_BH0_DUTY 0 /* Duty Cycle Asserted Count */
|
|
#define BITM_PWM_BH0_DUTY (_ADI_MSK(0x0000FFFF,uint32_t)) /* Duty Cycle Asserted Count */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_BH1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_BH1_DUTY 0 /* Duty Cycle De-Asserted Count */
|
|
#define BITM_PWM_BH1_DUTY (_ADI_MSK(0x0000FFFF,uint32_t)) /* Duty Cycle De-Asserted Count */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_BL0 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_BL0_DUTY 0 /* Duty Cycle Asserted Count */
|
|
#define BITM_PWM_BL0_DUTY (_ADI_MSK(0x0000FFFF,uint32_t)) /* Duty Cycle Asserted Count */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_BL1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_BL1_DUTY 0 /* Duty Cycle De-Asserted Count */
|
|
#define BITM_PWM_BL1_DUTY (_ADI_MSK(0x0000FFFF,uint32_t)) /* Duty Cycle De-Asserted Count */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_CCTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_CCTL_PULSEMODELO 10 /* Low Side Output Pulse Position */
|
|
#define BITP_PWM_CCTL_PULSEMODEHI 8 /* High Side Output Pulse Position */
|
|
#define BITP_PWM_CCTL_XOVR 2 /* high-low Crossover Enable */
|
|
#define BITP_PWM_CCTL_DISLO 1 /* Channel Low Side Output Disable */
|
|
#define BITP_PWM_CCTL_DISHI 0 /* Channel High Side Output Disable */
|
|
|
|
/* The fields and enumerations for PWM_CCTL are also in PWM - see the common set of ENUM_PWM_* #defines located with register PWM_ACTL */
|
|
|
|
#define BITM_PWM_CCTL_PULSEMODELO (_ADI_MSK(0x00000C00,uint32_t)) /* Low Side Output Pulse Position */
|
|
#define BITM_PWM_CCTL_PULSEMODEHI (_ADI_MSK(0x00000300,uint32_t)) /* High Side Output Pulse Position */
|
|
#define BITM_PWM_CCTL_XOVR (_ADI_MSK(0x00000004,uint32_t)) /* high-low Crossover Enable */
|
|
#define BITM_PWM_CCTL_DISLO (_ADI_MSK(0x00000002,uint32_t)) /* Channel Low Side Output Disable */
|
|
#define BITM_PWM_CCTL_DISHI (_ADI_MSK(0x00000001,uint32_t)) /* Channel High Side Output Disable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_CH0 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_CH0_DUTY 0 /* Duty Cycle Asserted Count */
|
|
#define BITM_PWM_CH0_DUTY (_ADI_MSK(0x0000FFFF,uint32_t)) /* Duty Cycle Asserted Count */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_CH1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_CH1_DUTY 0 /* Duty Cycle De-Asserted Count */
|
|
#define BITM_PWM_CH1_DUTY (_ADI_MSK(0x0000FFFF,uint32_t)) /* Duty Cycle De-Asserted Count */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_CL0 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_CL0_DUTY 0 /* Duty Cycle Asserted Count */
|
|
#define BITM_PWM_CL0_DUTY (_ADI_MSK(0x0000FFFF,uint32_t)) /* Duty Cycle Asserted Count */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_CL1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_CL1_DUTY 0 /* Duty Cycle De-Asserted Count */
|
|
#define BITM_PWM_CL1_DUTY (_ADI_MSK(0x0000FFFF,uint32_t)) /* Duty Cycle De-Asserted Count */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_DCTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_DCTL_PULSEMODELO 10 /* Low Side Output Pulse Position */
|
|
#define BITP_PWM_DCTL_PULSEMODEHI 8 /* High Side Output Pulse Position */
|
|
#define BITP_PWM_DCTL_XOVR 2 /* high-low Crossover Enable */
|
|
#define BITP_PWM_DCTL_DISLO 1 /* Channel Low Side Output Disable */
|
|
#define BITP_PWM_DCTL_DISHI 0 /* Channel High Side Output Disable */
|
|
|
|
/* The fields and enumerations for PWM_DCTL are also in PWM - see the common set of ENUM_PWM_* #defines located with register PWM_ACTL */
|
|
|
|
#define BITM_PWM_DCTL_PULSEMODELO (_ADI_MSK(0x00000C00,uint32_t)) /* Low Side Output Pulse Position */
|
|
#define BITM_PWM_DCTL_PULSEMODEHI (_ADI_MSK(0x00000300,uint32_t)) /* High Side Output Pulse Position */
|
|
#define BITM_PWM_DCTL_XOVR (_ADI_MSK(0x00000004,uint32_t)) /* high-low Crossover Enable */
|
|
#define BITM_PWM_DCTL_DISLO (_ADI_MSK(0x00000002,uint32_t)) /* Channel Low Side Output Disable */
|
|
#define BITM_PWM_DCTL_DISHI (_ADI_MSK(0x00000001,uint32_t)) /* Channel High Side Output Disable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_DH0 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_DH0_DUTY 0 /* Duty Cycle Asserted Count */
|
|
#define BITM_PWM_DH0_DUTY (_ADI_MSK(0x0000FFFF,uint32_t)) /* Duty Cycle Asserted Count */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_DH1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_DH1_DUTY 0 /* Duty Cycle De-Asserted Count */
|
|
#define BITM_PWM_DH1_DUTY (_ADI_MSK(0x0000FFFF,uint32_t)) /* Duty Cycle De-Asserted Count */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_DL0 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_DL0_DUTY 0 /* Duty Cycle Asserted Count */
|
|
#define BITM_PWM_DL0_DUTY (_ADI_MSK(0x0000FFFF,uint32_t)) /* Duty Cycle Asserted Count */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PWM_DL1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PWM_DL1_DUTY 0 /* Duty Cycle De-Asserted Count */
|
|
#define BITM_PWM_DL1_DUTY (_ADI_MSK(0x0000FFFF,uint32_t)) /* Duty Cycle De-Asserted Count */
|
|
|
|
/* ==================================================
|
|
Video Subsystem Registers Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
VID0
|
|
========================= */
|
|
#define REG_VID0_CONN 0xFFC1D000 /* VID0 Video Subsystem Connect Register */
|
|
|
|
/* =========================
|
|
VID
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
VID_CONN Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_VID_CONN_PPI2BCAST 23 /* PPI_2 Broadcast Mode */
|
|
#define BITP_VID_CONN_PPI1BCAST 22 /* PPI_1 Broadcast Mode */
|
|
#define BITP_VID_CONN_PPI0BCAST 21 /* PPI_0 Broadcast Mode */
|
|
#define BITP_VID_CONN_PPI2TX 16 /* PPI_2_TX Connectivity */
|
|
#define BITP_VID_CONN_PPI1TX 12 /* PPI_1_TX Connectivity */
|
|
#define BITP_VID_CONN_PPI0TX 8 /* PPI_0_TX Connectivity */
|
|
#define BITM_VID_CONN_PPI2BCAST (_ADI_MSK(0x00800000,uint32_t)) /* PPI_2 Broadcast Mode */
|
|
#define BITM_VID_CONN_PPI1BCAST (_ADI_MSK(0x00400000,uint32_t)) /* PPI_1 Broadcast Mode */
|
|
#define BITM_VID_CONN_PPI0BCAST (_ADI_MSK(0x00200000,uint32_t)) /* PPI_0 Broadcast Mode */
|
|
#define BITM_VID_CONN_PPI2TX (_ADI_MSK(0x000F0000,uint32_t)) /* PPI_2_TX Connectivity */
|
|
#define BITM_VID_CONN_PPI1TX (_ADI_MSK(0x0000F000,uint32_t)) /* PPI_1_TX Connectivity */
|
|
#define BITM_VID_CONN_PPI0TX (_ADI_MSK(0x00000F00,uint32_t)) /* PPI_0_TX Connectivity */
|
|
|
|
/* ==================================================
|
|
System Watchpoint Unit Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
SWU0
|
|
========================= */
|
|
#define REG_SWU0_GCTL 0xFFC1E000 /* SWU0 Global Control Register */
|
|
#define REG_SWU0_GSTAT 0xFFC1E004 /* SWU0 Global Status Register */
|
|
#define REG_SWU0_CTL0 0xFFC1E010 /* SWU0 Control Register n */
|
|
#define REG_SWU0_CTL1 0xFFC1E030 /* SWU0 Control Register n */
|
|
#define REG_SWU0_CTL2 0xFFC1E050 /* SWU0 Control Register n */
|
|
#define REG_SWU0_CTL3 0xFFC1E070 /* SWU0 Control Register n */
|
|
#define REG_SWU0_LA0 0xFFC1E014 /* SWU0 Lower Address Register n */
|
|
#define REG_SWU0_LA1 0xFFC1E034 /* SWU0 Lower Address Register n */
|
|
#define REG_SWU0_LA2 0xFFC1E054 /* SWU0 Lower Address Register n */
|
|
#define REG_SWU0_LA3 0xFFC1E074 /* SWU0 Lower Address Register n */
|
|
#define REG_SWU0_UA0 0xFFC1E018 /* SWU0 Upper Address Register n */
|
|
#define REG_SWU0_UA1 0xFFC1E038 /* SWU0 Upper Address Register n */
|
|
#define REG_SWU0_UA2 0xFFC1E058 /* SWU0 Upper Address Register n */
|
|
#define REG_SWU0_UA3 0xFFC1E078 /* SWU0 Upper Address Register n */
|
|
#define REG_SWU0_ID0 0xFFC1E01C /* SWU0 ID Register n */
|
|
#define REG_SWU0_ID1 0xFFC1E03C /* SWU0 ID Register n */
|
|
#define REG_SWU0_ID2 0xFFC1E05C /* SWU0 ID Register n */
|
|
#define REG_SWU0_ID3 0xFFC1E07C /* SWU0 ID Register n */
|
|
#define REG_SWU0_CNT0 0xFFC1E020 /* SWU0 Count Register n */
|
|
#define REG_SWU0_CNT1 0xFFC1E040 /* SWU0 Count Register n */
|
|
#define REG_SWU0_CNT2 0xFFC1E060 /* SWU0 Count Register n */
|
|
#define REG_SWU0_CNT3 0xFFC1E080 /* SWU0 Count Register n */
|
|
#define REG_SWU0_TARG0 0xFFC1E024 /* SWU0 Target Register n */
|
|
#define REG_SWU0_TARG1 0xFFC1E044 /* SWU0 Target Register n */
|
|
#define REG_SWU0_TARG2 0xFFC1E064 /* SWU0 Target Register n */
|
|
#define REG_SWU0_TARG3 0xFFC1E084 /* SWU0 Target Register n */
|
|
#define REG_SWU0_HIST0 0xFFC1E028 /* SWU0 Bandwidth History Register n */
|
|
#define REG_SWU0_HIST1 0xFFC1E048 /* SWU0 Bandwidth History Register n */
|
|
#define REG_SWU0_HIST2 0xFFC1E068 /* SWU0 Bandwidth History Register n */
|
|
#define REG_SWU0_HIST3 0xFFC1E088 /* SWU0 Bandwidth History Register n */
|
|
#define REG_SWU0_CUR0 0xFFC1E02C /* SWU0 Current Register n */
|
|
#define REG_SWU0_CUR1 0xFFC1E04C /* SWU0 Current Register n */
|
|
#define REG_SWU0_CUR2 0xFFC1E06C /* SWU0 Current Register n */
|
|
#define REG_SWU0_CUR3 0xFFC1E08C /* SWU0 Current Register n */
|
|
|
|
/* =========================
|
|
SWU1
|
|
========================= */
|
|
#define REG_SWU1_GCTL 0xFFCAB000 /* SWU1 Global Control Register */
|
|
#define REG_SWU1_GSTAT 0xFFCAB004 /* SWU1 Global Status Register */
|
|
#define REG_SWU1_CTL0 0xFFCAB010 /* SWU1 Control Register n */
|
|
#define REG_SWU1_CTL1 0xFFCAB030 /* SWU1 Control Register n */
|
|
#define REG_SWU1_CTL2 0xFFCAB050 /* SWU1 Control Register n */
|
|
#define REG_SWU1_CTL3 0xFFCAB070 /* SWU1 Control Register n */
|
|
#define REG_SWU1_LA0 0xFFCAB014 /* SWU1 Lower Address Register n */
|
|
#define REG_SWU1_LA1 0xFFCAB034 /* SWU1 Lower Address Register n */
|
|
#define REG_SWU1_LA2 0xFFCAB054 /* SWU1 Lower Address Register n */
|
|
#define REG_SWU1_LA3 0xFFCAB074 /* SWU1 Lower Address Register n */
|
|
#define REG_SWU1_UA0 0xFFCAB018 /* SWU1 Upper Address Register n */
|
|
#define REG_SWU1_UA1 0xFFCAB038 /* SWU1 Upper Address Register n */
|
|
#define REG_SWU1_UA2 0xFFCAB058 /* SWU1 Upper Address Register n */
|
|
#define REG_SWU1_UA3 0xFFCAB078 /* SWU1 Upper Address Register n */
|
|
#define REG_SWU1_ID0 0xFFCAB01C /* SWU1 ID Register n */
|
|
#define REG_SWU1_ID1 0xFFCAB03C /* SWU1 ID Register n */
|
|
#define REG_SWU1_ID2 0xFFCAB05C /* SWU1 ID Register n */
|
|
#define REG_SWU1_ID3 0xFFCAB07C /* SWU1 ID Register n */
|
|
#define REG_SWU1_CNT0 0xFFCAB020 /* SWU1 Count Register n */
|
|
#define REG_SWU1_CNT1 0xFFCAB040 /* SWU1 Count Register n */
|
|
#define REG_SWU1_CNT2 0xFFCAB060 /* SWU1 Count Register n */
|
|
#define REG_SWU1_CNT3 0xFFCAB080 /* SWU1 Count Register n */
|
|
#define REG_SWU1_TARG0 0xFFCAB024 /* SWU1 Target Register n */
|
|
#define REG_SWU1_TARG1 0xFFCAB044 /* SWU1 Target Register n */
|
|
#define REG_SWU1_TARG2 0xFFCAB064 /* SWU1 Target Register n */
|
|
#define REG_SWU1_TARG3 0xFFCAB084 /* SWU1 Target Register n */
|
|
#define REG_SWU1_HIST0 0xFFCAB028 /* SWU1 Bandwidth History Register n */
|
|
#define REG_SWU1_HIST1 0xFFCAB048 /* SWU1 Bandwidth History Register n */
|
|
#define REG_SWU1_HIST2 0xFFCAB068 /* SWU1 Bandwidth History Register n */
|
|
#define REG_SWU1_HIST3 0xFFCAB088 /* SWU1 Bandwidth History Register n */
|
|
#define REG_SWU1_CUR0 0xFFCAB02C /* SWU1 Current Register n */
|
|
#define REG_SWU1_CUR1 0xFFCAB04C /* SWU1 Current Register n */
|
|
#define REG_SWU1_CUR2 0xFFCAB06C /* SWU1 Current Register n */
|
|
#define REG_SWU1_CUR3 0xFFCAB08C /* SWU1 Current Register n */
|
|
|
|
/* =========================
|
|
SWU2
|
|
========================= */
|
|
#define REG_SWU2_GCTL 0xFFCAC000 /* SWU2 Global Control Register */
|
|
#define REG_SWU2_GSTAT 0xFFCAC004 /* SWU2 Global Status Register */
|
|
#define REG_SWU2_CTL0 0xFFCAC010 /* SWU2 Control Register n */
|
|
#define REG_SWU2_CTL1 0xFFCAC030 /* SWU2 Control Register n */
|
|
#define REG_SWU2_CTL2 0xFFCAC050 /* SWU2 Control Register n */
|
|
#define REG_SWU2_CTL3 0xFFCAC070 /* SWU2 Control Register n */
|
|
#define REG_SWU2_LA0 0xFFCAC014 /* SWU2 Lower Address Register n */
|
|
#define REG_SWU2_LA1 0xFFCAC034 /* SWU2 Lower Address Register n */
|
|
#define REG_SWU2_LA2 0xFFCAC054 /* SWU2 Lower Address Register n */
|
|
#define REG_SWU2_LA3 0xFFCAC074 /* SWU2 Lower Address Register n */
|
|
#define REG_SWU2_UA0 0xFFCAC018 /* SWU2 Upper Address Register n */
|
|
#define REG_SWU2_UA1 0xFFCAC038 /* SWU2 Upper Address Register n */
|
|
#define REG_SWU2_UA2 0xFFCAC058 /* SWU2 Upper Address Register n */
|
|
#define REG_SWU2_UA3 0xFFCAC078 /* SWU2 Upper Address Register n */
|
|
#define REG_SWU2_ID0 0xFFCAC01C /* SWU2 ID Register n */
|
|
#define REG_SWU2_ID1 0xFFCAC03C /* SWU2 ID Register n */
|
|
#define REG_SWU2_ID2 0xFFCAC05C /* SWU2 ID Register n */
|
|
#define REG_SWU2_ID3 0xFFCAC07C /* SWU2 ID Register n */
|
|
#define REG_SWU2_CNT0 0xFFCAC020 /* SWU2 Count Register n */
|
|
#define REG_SWU2_CNT1 0xFFCAC040 /* SWU2 Count Register n */
|
|
#define REG_SWU2_CNT2 0xFFCAC060 /* SWU2 Count Register n */
|
|
#define REG_SWU2_CNT3 0xFFCAC080 /* SWU2 Count Register n */
|
|
#define REG_SWU2_TARG0 0xFFCAC024 /* SWU2 Target Register n */
|
|
#define REG_SWU2_TARG1 0xFFCAC044 /* SWU2 Target Register n */
|
|
#define REG_SWU2_TARG2 0xFFCAC064 /* SWU2 Target Register n */
|
|
#define REG_SWU2_TARG3 0xFFCAC084 /* SWU2 Target Register n */
|
|
#define REG_SWU2_HIST0 0xFFCAC028 /* SWU2 Bandwidth History Register n */
|
|
#define REG_SWU2_HIST1 0xFFCAC048 /* SWU2 Bandwidth History Register n */
|
|
#define REG_SWU2_HIST2 0xFFCAC068 /* SWU2 Bandwidth History Register n */
|
|
#define REG_SWU2_HIST3 0xFFCAC088 /* SWU2 Bandwidth History Register n */
|
|
#define REG_SWU2_CUR0 0xFFCAC02C /* SWU2 Current Register n */
|
|
#define REG_SWU2_CUR1 0xFFCAC04C /* SWU2 Current Register n */
|
|
#define REG_SWU2_CUR2 0xFFCAC06C /* SWU2 Current Register n */
|
|
#define REG_SWU2_CUR3 0xFFCAC08C /* SWU2 Current Register n */
|
|
|
|
/* =========================
|
|
SWU3
|
|
========================= */
|
|
#define REG_SWU3_GCTL 0xFFCAD000 /* SWU3 Global Control Register */
|
|
#define REG_SWU3_GSTAT 0xFFCAD004 /* SWU3 Global Status Register */
|
|
#define REG_SWU3_CTL0 0xFFCAD010 /* SWU3 Control Register n */
|
|
#define REG_SWU3_CTL1 0xFFCAD030 /* SWU3 Control Register n */
|
|
#define REG_SWU3_CTL2 0xFFCAD050 /* SWU3 Control Register n */
|
|
#define REG_SWU3_CTL3 0xFFCAD070 /* SWU3 Control Register n */
|
|
#define REG_SWU3_LA0 0xFFCAD014 /* SWU3 Lower Address Register n */
|
|
#define REG_SWU3_LA1 0xFFCAD034 /* SWU3 Lower Address Register n */
|
|
#define REG_SWU3_LA2 0xFFCAD054 /* SWU3 Lower Address Register n */
|
|
#define REG_SWU3_LA3 0xFFCAD074 /* SWU3 Lower Address Register n */
|
|
#define REG_SWU3_UA0 0xFFCAD018 /* SWU3 Upper Address Register n */
|
|
#define REG_SWU3_UA1 0xFFCAD038 /* SWU3 Upper Address Register n */
|
|
#define REG_SWU3_UA2 0xFFCAD058 /* SWU3 Upper Address Register n */
|
|
#define REG_SWU3_UA3 0xFFCAD078 /* SWU3 Upper Address Register n */
|
|
#define REG_SWU3_ID0 0xFFCAD01C /* SWU3 ID Register n */
|
|
#define REG_SWU3_ID1 0xFFCAD03C /* SWU3 ID Register n */
|
|
#define REG_SWU3_ID2 0xFFCAD05C /* SWU3 ID Register n */
|
|
#define REG_SWU3_ID3 0xFFCAD07C /* SWU3 ID Register n */
|
|
#define REG_SWU3_CNT0 0xFFCAD020 /* SWU3 Count Register n */
|
|
#define REG_SWU3_CNT1 0xFFCAD040 /* SWU3 Count Register n */
|
|
#define REG_SWU3_CNT2 0xFFCAD060 /* SWU3 Count Register n */
|
|
#define REG_SWU3_CNT3 0xFFCAD080 /* SWU3 Count Register n */
|
|
#define REG_SWU3_TARG0 0xFFCAD024 /* SWU3 Target Register n */
|
|
#define REG_SWU3_TARG1 0xFFCAD044 /* SWU3 Target Register n */
|
|
#define REG_SWU3_TARG2 0xFFCAD064 /* SWU3 Target Register n */
|
|
#define REG_SWU3_TARG3 0xFFCAD084 /* SWU3 Target Register n */
|
|
#define REG_SWU3_HIST0 0xFFCAD028 /* SWU3 Bandwidth History Register n */
|
|
#define REG_SWU3_HIST1 0xFFCAD048 /* SWU3 Bandwidth History Register n */
|
|
#define REG_SWU3_HIST2 0xFFCAD068 /* SWU3 Bandwidth History Register n */
|
|
#define REG_SWU3_HIST3 0xFFCAD088 /* SWU3 Bandwidth History Register n */
|
|
#define REG_SWU3_CUR0 0xFFCAD02C /* SWU3 Current Register n */
|
|
#define REG_SWU3_CUR1 0xFFCAD04C /* SWU3 Current Register n */
|
|
#define REG_SWU3_CUR2 0xFFCAD06C /* SWU3 Current Register n */
|
|
#define REG_SWU3_CUR3 0xFFCAD08C /* SWU3 Current Register n */
|
|
|
|
/* =========================
|
|
SWU4
|
|
========================= */
|
|
#define REG_SWU4_GCTL 0xFFCAE000 /* SWU4 Global Control Register */
|
|
#define REG_SWU4_GSTAT 0xFFCAE004 /* SWU4 Global Status Register */
|
|
#define REG_SWU4_CTL0 0xFFCAE010 /* SWU4 Control Register n */
|
|
#define REG_SWU4_CTL1 0xFFCAE030 /* SWU4 Control Register n */
|
|
#define REG_SWU4_CTL2 0xFFCAE050 /* SWU4 Control Register n */
|
|
#define REG_SWU4_CTL3 0xFFCAE070 /* SWU4 Control Register n */
|
|
#define REG_SWU4_LA0 0xFFCAE014 /* SWU4 Lower Address Register n */
|
|
#define REG_SWU4_LA1 0xFFCAE034 /* SWU4 Lower Address Register n */
|
|
#define REG_SWU4_LA2 0xFFCAE054 /* SWU4 Lower Address Register n */
|
|
#define REG_SWU4_LA3 0xFFCAE074 /* SWU4 Lower Address Register n */
|
|
#define REG_SWU4_UA0 0xFFCAE018 /* SWU4 Upper Address Register n */
|
|
#define REG_SWU4_UA1 0xFFCAE038 /* SWU4 Upper Address Register n */
|
|
#define REG_SWU4_UA2 0xFFCAE058 /* SWU4 Upper Address Register n */
|
|
#define REG_SWU4_UA3 0xFFCAE078 /* SWU4 Upper Address Register n */
|
|
#define REG_SWU4_ID0 0xFFCAE01C /* SWU4 ID Register n */
|
|
#define REG_SWU4_ID1 0xFFCAE03C /* SWU4 ID Register n */
|
|
#define REG_SWU4_ID2 0xFFCAE05C /* SWU4 ID Register n */
|
|
#define REG_SWU4_ID3 0xFFCAE07C /* SWU4 ID Register n */
|
|
#define REG_SWU4_CNT0 0xFFCAE020 /* SWU4 Count Register n */
|
|
#define REG_SWU4_CNT1 0xFFCAE040 /* SWU4 Count Register n */
|
|
#define REG_SWU4_CNT2 0xFFCAE060 /* SWU4 Count Register n */
|
|
#define REG_SWU4_CNT3 0xFFCAE080 /* SWU4 Count Register n */
|
|
#define REG_SWU4_TARG0 0xFFCAE024 /* SWU4 Target Register n */
|
|
#define REG_SWU4_TARG1 0xFFCAE044 /* SWU4 Target Register n */
|
|
#define REG_SWU4_TARG2 0xFFCAE064 /* SWU4 Target Register n */
|
|
#define REG_SWU4_TARG3 0xFFCAE084 /* SWU4 Target Register n */
|
|
#define REG_SWU4_HIST0 0xFFCAE028 /* SWU4 Bandwidth History Register n */
|
|
#define REG_SWU4_HIST1 0xFFCAE048 /* SWU4 Bandwidth History Register n */
|
|
#define REG_SWU4_HIST2 0xFFCAE068 /* SWU4 Bandwidth History Register n */
|
|
#define REG_SWU4_HIST3 0xFFCAE088 /* SWU4 Bandwidth History Register n */
|
|
#define REG_SWU4_CUR0 0xFFCAE02C /* SWU4 Current Register n */
|
|
#define REG_SWU4_CUR1 0xFFCAE04C /* SWU4 Current Register n */
|
|
#define REG_SWU4_CUR2 0xFFCAE06C /* SWU4 Current Register n */
|
|
#define REG_SWU4_CUR3 0xFFCAE08C /* SWU4 Current Register n */
|
|
|
|
/* =========================
|
|
SWU5
|
|
========================= */
|
|
#define REG_SWU5_GCTL 0xFFCAF000 /* SWU5 Global Control Register */
|
|
#define REG_SWU5_GSTAT 0xFFCAF004 /* SWU5 Global Status Register */
|
|
#define REG_SWU5_CTL0 0xFFCAF010 /* SWU5 Control Register n */
|
|
#define REG_SWU5_CTL1 0xFFCAF030 /* SWU5 Control Register n */
|
|
#define REG_SWU5_CTL2 0xFFCAF050 /* SWU5 Control Register n */
|
|
#define REG_SWU5_CTL3 0xFFCAF070 /* SWU5 Control Register n */
|
|
#define REG_SWU5_LA0 0xFFCAF014 /* SWU5 Lower Address Register n */
|
|
#define REG_SWU5_LA1 0xFFCAF034 /* SWU5 Lower Address Register n */
|
|
#define REG_SWU5_LA2 0xFFCAF054 /* SWU5 Lower Address Register n */
|
|
#define REG_SWU5_LA3 0xFFCAF074 /* SWU5 Lower Address Register n */
|
|
#define REG_SWU5_UA0 0xFFCAF018 /* SWU5 Upper Address Register n */
|
|
#define REG_SWU5_UA1 0xFFCAF038 /* SWU5 Upper Address Register n */
|
|
#define REG_SWU5_UA2 0xFFCAF058 /* SWU5 Upper Address Register n */
|
|
#define REG_SWU5_UA3 0xFFCAF078 /* SWU5 Upper Address Register n */
|
|
#define REG_SWU5_ID0 0xFFCAF01C /* SWU5 ID Register n */
|
|
#define REG_SWU5_ID1 0xFFCAF03C /* SWU5 ID Register n */
|
|
#define REG_SWU5_ID2 0xFFCAF05C /* SWU5 ID Register n */
|
|
#define REG_SWU5_ID3 0xFFCAF07C /* SWU5 ID Register n */
|
|
#define REG_SWU5_CNT0 0xFFCAF020 /* SWU5 Count Register n */
|
|
#define REG_SWU5_CNT1 0xFFCAF040 /* SWU5 Count Register n */
|
|
#define REG_SWU5_CNT2 0xFFCAF060 /* SWU5 Count Register n */
|
|
#define REG_SWU5_CNT3 0xFFCAF080 /* SWU5 Count Register n */
|
|
#define REG_SWU5_TARG0 0xFFCAF024 /* SWU5 Target Register n */
|
|
#define REG_SWU5_TARG1 0xFFCAF044 /* SWU5 Target Register n */
|
|
#define REG_SWU5_TARG2 0xFFCAF064 /* SWU5 Target Register n */
|
|
#define REG_SWU5_TARG3 0xFFCAF084 /* SWU5 Target Register n */
|
|
#define REG_SWU5_HIST0 0xFFCAF028 /* SWU5 Bandwidth History Register n */
|
|
#define REG_SWU5_HIST1 0xFFCAF048 /* SWU5 Bandwidth History Register n */
|
|
#define REG_SWU5_HIST2 0xFFCAF068 /* SWU5 Bandwidth History Register n */
|
|
#define REG_SWU5_HIST3 0xFFCAF088 /* SWU5 Bandwidth History Register n */
|
|
#define REG_SWU5_CUR0 0xFFCAF02C /* SWU5 Current Register n */
|
|
#define REG_SWU5_CUR1 0xFFCAF04C /* SWU5 Current Register n */
|
|
#define REG_SWU5_CUR2 0xFFCAF06C /* SWU5 Current Register n */
|
|
#define REG_SWU5_CUR3 0xFFCAF08C /* SWU5 Current Register n */
|
|
|
|
/* =========================
|
|
SWU6
|
|
========================= */
|
|
#define REG_SWU6_GCTL 0xFFC82000 /* SWU6 Global Control Register */
|
|
#define REG_SWU6_GSTAT 0xFFC82004 /* SWU6 Global Status Register */
|
|
#define REG_SWU6_CTL0 0xFFC82010 /* SWU6 Control Register n */
|
|
#define REG_SWU6_CTL1 0xFFC82030 /* SWU6 Control Register n */
|
|
#define REG_SWU6_CTL2 0xFFC82050 /* SWU6 Control Register n */
|
|
#define REG_SWU6_CTL3 0xFFC82070 /* SWU6 Control Register n */
|
|
#define REG_SWU6_LA0 0xFFC82014 /* SWU6 Lower Address Register n */
|
|
#define REG_SWU6_LA1 0xFFC82034 /* SWU6 Lower Address Register n */
|
|
#define REG_SWU6_LA2 0xFFC82054 /* SWU6 Lower Address Register n */
|
|
#define REG_SWU6_LA3 0xFFC82074 /* SWU6 Lower Address Register n */
|
|
#define REG_SWU6_UA0 0xFFC82018 /* SWU6 Upper Address Register n */
|
|
#define REG_SWU6_UA1 0xFFC82038 /* SWU6 Upper Address Register n */
|
|
#define REG_SWU6_UA2 0xFFC82058 /* SWU6 Upper Address Register n */
|
|
#define REG_SWU6_UA3 0xFFC82078 /* SWU6 Upper Address Register n */
|
|
#define REG_SWU6_ID0 0xFFC8201C /* SWU6 ID Register n */
|
|
#define REG_SWU6_ID1 0xFFC8203C /* SWU6 ID Register n */
|
|
#define REG_SWU6_ID2 0xFFC8205C /* SWU6 ID Register n */
|
|
#define REG_SWU6_ID3 0xFFC8207C /* SWU6 ID Register n */
|
|
#define REG_SWU6_CNT0 0xFFC82020 /* SWU6 Count Register n */
|
|
#define REG_SWU6_CNT1 0xFFC82040 /* SWU6 Count Register n */
|
|
#define REG_SWU6_CNT2 0xFFC82060 /* SWU6 Count Register n */
|
|
#define REG_SWU6_CNT3 0xFFC82080 /* SWU6 Count Register n */
|
|
#define REG_SWU6_TARG0 0xFFC82024 /* SWU6 Target Register n */
|
|
#define REG_SWU6_TARG1 0xFFC82044 /* SWU6 Target Register n */
|
|
#define REG_SWU6_TARG2 0xFFC82064 /* SWU6 Target Register n */
|
|
#define REG_SWU6_TARG3 0xFFC82084 /* SWU6 Target Register n */
|
|
#define REG_SWU6_HIST0 0xFFC82028 /* SWU6 Bandwidth History Register n */
|
|
#define REG_SWU6_HIST1 0xFFC82048 /* SWU6 Bandwidth History Register n */
|
|
#define REG_SWU6_HIST2 0xFFC82068 /* SWU6 Bandwidth History Register n */
|
|
#define REG_SWU6_HIST3 0xFFC82088 /* SWU6 Bandwidth History Register n */
|
|
#define REG_SWU6_CUR0 0xFFC8202C /* SWU6 Current Register n */
|
|
#define REG_SWU6_CUR1 0xFFC8204C /* SWU6 Current Register n */
|
|
#define REG_SWU6_CUR2 0xFFC8206C /* SWU6 Current Register n */
|
|
#define REG_SWU6_CUR3 0xFFC8208C /* SWU6 Current Register n */
|
|
|
|
/* =========================
|
|
SWU
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SWU_GCTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SWU_GCTL_RST 1 /* Global Reset */
|
|
#define BITP_SWU_GCTL_EN 0 /* Global Enable */
|
|
#define BITM_SWU_GCTL_RST (_ADI_MSK(0x00000002,uint32_t)) /* Global Reset */
|
|
#define BITM_SWU_GCTL_EN (_ADI_MSK(0x00000001,uint32_t)) /* Global Enable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SWU_GSTAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SWU_GSTAT_ADDRERR 30 /* Address Error Status */
|
|
#define BITP_SWU_GSTAT_OVRBW3 15 /* Group 3 Bandwidth Above Maximum Target */
|
|
#define BITP_SWU_GSTAT_UNDRBW3 14 /* Group 3 Bandwidth Below Minimum Target */
|
|
#define BITP_SWU_GSTAT_OVRBW2 13 /* Group 2 Bandwidth Above Maximum Target */
|
|
#define BITP_SWU_GSTAT_UNDRBW2 12 /* Group 2 Bandwidth Below Minimum Target */
|
|
#define BITP_SWU_GSTAT_OVRBW1 11 /* Group 1 Bandwidth Above Maximum Target */
|
|
#define BITP_SWU_GSTAT_UNDRBW1 10 /* Group 1 Bandwidth Below Minimum Target */
|
|
#define BITP_SWU_GSTAT_OVRBW0 9 /* Group 0 Bandwidth Above Maximum Target */
|
|
#define BITP_SWU_GSTAT_UNDRBW0 8 /* Group 0 Bandwidth Below Minimum Target */
|
|
#define BITP_SWU_GSTAT_INT3 7 /* Group 3 Interrupt Status */
|
|
#define BITP_SWU_GSTAT_INT2 6 /* Group 2 Interrupt Status */
|
|
#define BITP_SWU_GSTAT_INT1 5 /* Group 1 Interrupt Status */
|
|
#define BITP_SWU_GSTAT_INT0 4 /* Group 0 Interrupt Status */
|
|
#define BITP_SWU_GSTAT_MTCH3 3 /* Group 3 Match */
|
|
#define BITP_SWU_GSTAT_MTCH2 2 /* Group 2 Match */
|
|
#define BITP_SWU_GSTAT_MTCH1 1 /* Group 1 Match */
|
|
#define BITP_SWU_GSTAT_MTCH0 0 /* Group 0 Match */
|
|
#define BITM_SWU_GSTAT_ADDRERR (_ADI_MSK(0x40000000,uint32_t)) /* Address Error Status */
|
|
#define BITM_SWU_GSTAT_OVRBW3 (_ADI_MSK(0x00008000,uint32_t)) /* Group 3 Bandwidth Above Maximum Target */
|
|
#define BITM_SWU_GSTAT_UNDRBW3 (_ADI_MSK(0x00004000,uint32_t)) /* Group 3 Bandwidth Below Minimum Target */
|
|
#define BITM_SWU_GSTAT_OVRBW2 (_ADI_MSK(0x00002000,uint32_t)) /* Group 2 Bandwidth Above Maximum Target */
|
|
#define BITM_SWU_GSTAT_UNDRBW2 (_ADI_MSK(0x00001000,uint32_t)) /* Group 2 Bandwidth Below Minimum Target */
|
|
#define BITM_SWU_GSTAT_OVRBW1 (_ADI_MSK(0x00000800,uint32_t)) /* Group 1 Bandwidth Above Maximum Target */
|
|
#define BITM_SWU_GSTAT_UNDRBW1 (_ADI_MSK(0x00000400,uint32_t)) /* Group 1 Bandwidth Below Minimum Target */
|
|
#define BITM_SWU_GSTAT_OVRBW0 (_ADI_MSK(0x00000200,uint32_t)) /* Group 0 Bandwidth Above Maximum Target */
|
|
#define BITM_SWU_GSTAT_UNDRBW0 (_ADI_MSK(0x00000100,uint32_t)) /* Group 0 Bandwidth Below Minimum Target */
|
|
#define BITM_SWU_GSTAT_INT3 (_ADI_MSK(0x00000080,uint32_t)) /* Group 3 Interrupt Status */
|
|
#define BITM_SWU_GSTAT_INT2 (_ADI_MSK(0x00000040,uint32_t)) /* Group 2 Interrupt Status */
|
|
#define BITM_SWU_GSTAT_INT1 (_ADI_MSK(0x00000020,uint32_t)) /* Group 1 Interrupt Status */
|
|
#define BITM_SWU_GSTAT_INT0 (_ADI_MSK(0x00000010,uint32_t)) /* Group 0 Interrupt Status */
|
|
#define BITM_SWU_GSTAT_MTCH3 (_ADI_MSK(0x00000008,uint32_t)) /* Group 3 Match */
|
|
#define BITM_SWU_GSTAT_MTCH2 (_ADI_MSK(0x00000004,uint32_t)) /* Group 2 Match */
|
|
#define BITM_SWU_GSTAT_MTCH1 (_ADI_MSK(0x00000002,uint32_t)) /* Group 1 Match */
|
|
#define BITM_SWU_GSTAT_MTCH0 (_ADI_MSK(0x00000001,uint32_t)) /* Group 0 Match */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SWU_CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SWU_CTL_MAXACT 19 /* Action for Bandwidth Above Maximum */
|
|
#define BITP_SWU_CTL_MINACT 18 /* Action for Bandwidth Below Minimum */
|
|
#define BITP_SWU_CTL_BLENINC 17 /* Increment Bandwidth Count by Burst Length */
|
|
#define BITP_SWU_CTL_BWEN 16 /* Bandwidth Mode Enable */
|
|
#define BITP_SWU_CTL_TMEN 15 /* Trace Message Enable */
|
|
#define BITP_SWU_CTL_TRGEN 14 /* Trigger Enable */
|
|
#define BITP_SWU_CTL_INTEN 13 /* Interrupt Enable */
|
|
#define BITP_SWU_CTL_DBGEN 12 /* Debug Event Enable */
|
|
#define BITP_SWU_CTL_CNTRPTEN 9 /* Count Repeat Enable */
|
|
#define BITP_SWU_CTL_CNTEN 8 /* Count Enable */
|
|
#define BITP_SWU_CTL_LCMPEN 6 /* Locked Comparison Enable */
|
|
#define BITP_SWU_CTL_SCMPEN 5 /* Secure Comparison Enable */
|
|
#define BITP_SWU_CTL_IDCMPEN 4 /* ID Comparison Enable */
|
|
#define BITP_SWU_CTL_ACMPM 2 /* Address Comparison Mode */
|
|
#define BITP_SWU_CTL_DIR 1 /* Transaction Direction for Match */
|
|
#define BITP_SWU_CTL_EN 0 /* Enable Watchpoint */
|
|
#define BITM_SWU_CTL_MAXACT (_ADI_MSK(0x00080000,uint32_t)) /* Action for Bandwidth Above Maximum */
|
|
#define BITM_SWU_CTL_MINACT (_ADI_MSK(0x00040000,uint32_t)) /* Action for Bandwidth Below Minimum */
|
|
#define BITM_SWU_CTL_BLENINC (_ADI_MSK(0x00020000,uint32_t)) /* Increment Bandwidth Count by Burst Length */
|
|
#define BITM_SWU_CTL_BWEN (_ADI_MSK(0x00010000,uint32_t)) /* Bandwidth Mode Enable */
|
|
#define BITM_SWU_CTL_TMEN (_ADI_MSK(0x00008000,uint32_t)) /* Trace Message Enable */
|
|
#define BITM_SWU_CTL_TRGEN (_ADI_MSK(0x00004000,uint32_t)) /* Trigger Enable */
|
|
#define BITM_SWU_CTL_INTEN (_ADI_MSK(0x00002000,uint32_t)) /* Interrupt Enable */
|
|
#define BITM_SWU_CTL_DBGEN (_ADI_MSK(0x00001000,uint32_t)) /* Debug Event Enable */
|
|
#define BITM_SWU_CTL_CNTRPTEN (_ADI_MSK(0x00000200,uint32_t)) /* Count Repeat Enable */
|
|
#define BITM_SWU_CTL_CNTEN (_ADI_MSK(0x00000100,uint32_t)) /* Count Enable */
|
|
#define BITM_SWU_CTL_LCMPEN (_ADI_MSK(0x00000040,uint32_t)) /* Locked Comparison Enable */
|
|
#define BITM_SWU_CTL_SCMPEN (_ADI_MSK(0x00000020,uint32_t)) /* Secure Comparison Enable */
|
|
#define BITM_SWU_CTL_IDCMPEN (_ADI_MSK(0x00000010,uint32_t)) /* ID Comparison Enable */
|
|
#define BITM_SWU_CTL_ACMPM (_ADI_MSK(0x0000000C,uint32_t)) /* Address Comparison Mode */
|
|
#define BITM_SWU_CTL_DIR (_ADI_MSK(0x00000002,uint32_t)) /* Transaction Direction for Match */
|
|
#define BITM_SWU_CTL_EN (_ADI_MSK(0x00000001,uint32_t)) /* Enable Watchpoint */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SWU_ID Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SWU_ID_IDMASK 16 /* Identity Mask (for Or with ID) */
|
|
#define BITP_SWU_ID_ID 0 /* Identity */
|
|
#define BITM_SWU_ID_IDMASK (_ADI_MSK(0xFFFF0000,uint32_t)) /* Identity Mask (for Or with ID) */
|
|
#define BITM_SWU_ID_ID (_ADI_MSK(0x0000FFFF,uint32_t)) /* Identity */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SWU_CNT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SWU_CNT_COUNT 0 /* Count */
|
|
#define BITM_SWU_CNT_COUNT (_ADI_MSK(0x0000FFFF,uint32_t)) /* Count */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SWU_TARG Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SWU_TARG_BWMAX 16 /* Maximum Bandwidth Target */
|
|
#define BITP_SWU_TARG_BWMIN 0 /* Minimum Bandwidth Target */
|
|
#define BITM_SWU_TARG_BWMAX (_ADI_MSK(0xFFFF0000,uint32_t)) /* Maximum Bandwidth Target */
|
|
#define BITM_SWU_TARG_BWMIN (_ADI_MSK(0x0000FFFF,uint32_t)) /* Minimum Bandwidth Target */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SWU_HIST Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SWU_HIST_BWHIST1 16 /* Bandwidth from Window Before Last */
|
|
#define BITP_SWU_HIST_BWHIST0 0 /* Bandwidth from Last Window */
|
|
#define BITM_SWU_HIST_BWHIST1 (_ADI_MSK(0xFFFF0000,uint32_t)) /* Bandwidth from Window Before Last */
|
|
#define BITM_SWU_HIST_BWHIST0 (_ADI_MSK(0x0000FFFF,uint32_t)) /* Bandwidth from Last Window */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SWU_CUR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SWU_CUR_CURBW 16 /* Current Bandwidth */
|
|
#define BITP_SWU_CUR_CURCNT 0 /* Current Count */
|
|
#define BITM_SWU_CUR_CURBW (_ADI_MSK(0xFFFF0000,uint32_t)) /* Current Bandwidth */
|
|
#define BITM_SWU_CUR_CURCNT (_ADI_MSK(0x0000FFFF,uint32_t)) /* Current Count */
|
|
|
|
/* ==================================================
|
|
System Debug Unit Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
SDU0
|
|
========================= */
|
|
#define REG_SDU0_IDCODE 0xFFC1F020 /* SDU0 ID Code Register */
|
|
#define REG_SDU0_CTL 0xFFC1F050 /* SDU0 Control Register */
|
|
#define REG_SDU0_STAT 0xFFC1F054 /* SDU0 Status Register */
|
|
#define REG_SDU0_MACCTL 0xFFC1F058 /* SDU0 Memory Access Control Register */
|
|
#define REG_SDU0_MACADDR 0xFFC1F05C /* SDU0 Memory Access Address Register */
|
|
#define REG_SDU0_MACDATA 0xFFC1F060 /* SDU0 Memory Access Data Register */
|
|
#define REG_SDU0_DMARD 0xFFC1F064 /* SDU0 DMA Read Data Register */
|
|
#define REG_SDU0_DMAWD 0xFFC1F068 /* SDU0 DMA Write Data Register */
|
|
#define REG_SDU0_MSG 0xFFC1F080 /* SDU0 Message Register */
|
|
#define REG_SDU0_MSG_SET 0xFFC1F084 /* SDU0 Message Set Register */
|
|
#define REG_SDU0_MSG_CLR 0xFFC1F088 /* SDU0 Message Clear Register */
|
|
#define REG_SDU0_GHLT 0xFFC1F08C /* SDU0 Group Halt Register */
|
|
|
|
/* =========================
|
|
SDU
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SDU_IDCODE Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SDU_IDCODE_REVID 28 /* Revision ID */
|
|
#define BITP_SDU_IDCODE_PRID 12 /* Product ID */
|
|
#define BITP_SDU_IDCODE_MFID 1 /* Manufacturer ID */
|
|
#define BITM_SDU_IDCODE_REVID (_ADI_MSK(0xF0000000,uint32_t)) /* Revision ID */
|
|
#define BITM_SDU_IDCODE_PRID (_ADI_MSK(0x0FFFF000,uint32_t)) /* Product ID */
|
|
#define BITM_SDU_IDCODE_MFID (_ADI_MSK(0x00000FFE,uint32_t)) /* Manufacturer ID */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SDU_CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SDU_CTL_EHLT 8 /* Emulator Halt Select */
|
|
#define BITP_SDU_CTL_EMEEN 4 /* Emulation Event Enable */
|
|
#define BITP_SDU_CTL_DMAEN 2 /* DMA Enable */
|
|
#define BITP_SDU_CTL_CSPEN 1 /* Core Scan Path Enable */
|
|
#define BITP_SDU_CTL_SYSRST 0 /* System Reset */
|
|
#define BITM_SDU_CTL_EHLT (_ADI_MSK(0x0000FF00,uint32_t)) /* Emulator Halt Select */
|
|
#define BITM_SDU_CTL_EMEEN (_ADI_MSK(0x00000010,uint32_t)) /* Emulation Event Enable */
|
|
#define BITM_SDU_CTL_DMAEN (_ADI_MSK(0x00000004,uint32_t)) /* DMA Enable */
|
|
#define BITM_SDU_CTL_CSPEN (_ADI_MSK(0x00000002,uint32_t)) /* Core Scan Path Enable */
|
|
#define BITM_SDU_CTL_SYSRST (_ADI_MSK(0x00000001,uint32_t)) /* System Reset */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SDU_STAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SDU_STAT_CRST 22 /* Core Reset */
|
|
#define BITP_SDU_STAT_CHLT 21 /* Core Halt */
|
|
#define BITP_SDU_STAT_EME 20 /* Emulation Event */
|
|
#define BITP_SDU_STAT_GHLTC 17 /* Group Halt Cause */
|
|
#define BITP_SDU_STAT_GHLT 16 /* Group Halt */
|
|
#define BITP_SDU_STAT_DMAFIFO 12 /* DMA FIFO */
|
|
#define BITP_SDU_STAT_ADDRERR 11 /* Address Error */
|
|
#define BITP_SDU_STAT_DMAWDRDY 10 /* DMAWD Ready */
|
|
#define BITP_SDU_STAT_DMARDRDY 9 /* DMARD Ready */
|
|
#define BITP_SDU_STAT_MACRDY 8 /* MAC Ready */
|
|
#define BITP_SDU_STAT_ERRC 4 /* Error Cause */
|
|
#define BITP_SDU_STAT_SECURE 3 /* Secure Mode */
|
|
#define BITP_SDU_STAT_DEEPSLEEP 2 /* Deep Sleep Mode */
|
|
#define BITP_SDU_STAT_ERR 1 /* Error */
|
|
#define BITP_SDU_STAT_SYSRST 0 /* System Reset */
|
|
#define BITM_SDU_STAT_CRST (_ADI_MSK(0x00400000,uint32_t)) /* Core Reset */
|
|
#define BITM_SDU_STAT_CHLT (_ADI_MSK(0x00200000,uint32_t)) /* Core Halt */
|
|
#define BITM_SDU_STAT_EME (_ADI_MSK(0x00100000,uint32_t)) /* Emulation Event */
|
|
#define BITM_SDU_STAT_GHLTC (_ADI_MSK(0x000E0000,uint32_t)) /* Group Halt Cause */
|
|
#define BITM_SDU_STAT_GHLT (_ADI_MSK(0x00010000,uint32_t)) /* Group Halt */
|
|
#define BITM_SDU_STAT_DMAFIFO (_ADI_MSK(0x00007000,uint32_t)) /* DMA FIFO */
|
|
#define BITM_SDU_STAT_ADDRERR (_ADI_MSK(0x00000800,uint32_t)) /* Address Error */
|
|
#define BITM_SDU_STAT_DMAWDRDY (_ADI_MSK(0x00000400,uint32_t)) /* DMAWD Ready */
|
|
#define BITM_SDU_STAT_DMARDRDY (_ADI_MSK(0x00000200,uint32_t)) /* DMARD Ready */
|
|
#define BITM_SDU_STAT_MACRDY (_ADI_MSK(0x00000100,uint32_t)) /* MAC Ready */
|
|
#define BITM_SDU_STAT_ERRC (_ADI_MSK(0x000000F0,uint32_t)) /* Error Cause */
|
|
#define BITM_SDU_STAT_SECURE (_ADI_MSK(0x00000008,uint32_t)) /* Secure Mode */
|
|
#define BITM_SDU_STAT_DEEPSLEEP (_ADI_MSK(0x00000004,uint32_t)) /* Deep Sleep Mode */
|
|
#define BITM_SDU_STAT_ERR (_ADI_MSK(0x00000002,uint32_t)) /* Error */
|
|
#define BITM_SDU_STAT_SYSRST (_ADI_MSK(0x00000001,uint32_t)) /* System Reset */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SDU_MACCTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SDU_MACCTL_AUTOINC 4 /* Auto (Post) Increment MACADDR (by SIZE) */
|
|
#define BITP_SDU_MACCTL_RNW 3 /* Read Not Write */
|
|
#define BITP_SDU_MACCTL_SIZE 0 /* Transfer Data Size */
|
|
#define BITM_SDU_MACCTL_AUTOINC (_ADI_MSK(0x00000010,uint32_t)) /* Auto (Post) Increment MACADDR (by SIZE) */
|
|
#define BITM_SDU_MACCTL_RNW (_ADI_MSK(0x00000008,uint32_t)) /* Read Not Write */
|
|
#define BITM_SDU_MACCTL_SIZE (_ADI_MSK(0x00000007,uint32_t)) /* Transfer Data Size */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SDU_MSG Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SDU_MSG_CALLERR 31 /* Flag Set by the Boot Code Prior to an Error Call */
|
|
#define BITP_SDU_MSG_CALLBACK 30 /* Flag Set by the Boot Code Prior to a Callback Call */
|
|
#define BITP_SDU_MSG_CALLINIT 29 /* Flag Set by the Boot Code Prior to an Initcode Call */
|
|
#define BITP_SDU_MSG_CALLAPP 28 /* Flag Set by the Boot Code Prior to an Application Call */
|
|
#define BITP_SDU_MSG_HALTONERR 27 /* Generate an Emulation Exception Prior to an Error Call */
|
|
#define BITP_SDU_MSG_HALTONCALL 26 /* Generate an Emulation Exception Prior to a Callback Call */
|
|
#define BITP_SDU_MSG_HALTONINIT 25 /* Generate an Emulation Exception Prior to an Initcode Call */
|
|
#define BITP_SDU_MSG_HALTONAPP 24 /* Generate an Emulation Exception Prior to an Application Call */
|
|
#define BITP_SDU_MSG_L3INIT 23 /* Indicates that the L3 Resource is Initialized */
|
|
#define BITP_SDU_MSG_L2INIT 22 /* Indicates that the L2 Resource is Initialized */
|
|
#define BITP_SDU_MSG_C1L1INIT 17 /* Indicates that the Core 1 L1 Resource is Initialized */
|
|
#define BITP_SDU_MSG_C0L1INIT 16 /* Indicates that the Core 0 L1 Resource is Initialized */
|
|
#define BITM_SDU_MSG_CALLERR (_ADI_MSK(0x80000000,uint32_t)) /* Flag Set by the Boot Code Prior to an Error Call */
|
|
#define BITM_SDU_MSG_CALLBACK (_ADI_MSK(0x40000000,uint32_t)) /* Flag Set by the Boot Code Prior to a Callback Call */
|
|
#define BITM_SDU_MSG_CALLINIT (_ADI_MSK(0x20000000,uint32_t)) /* Flag Set by the Boot Code Prior to an Initcode Call */
|
|
#define BITM_SDU_MSG_CALLAPP (_ADI_MSK(0x10000000,uint32_t)) /* Flag Set by the Boot Code Prior to an Application Call */
|
|
#define BITM_SDU_MSG_HALTONERR (_ADI_MSK(0x08000000,uint32_t)) /* Generate an Emulation Exception Prior to an Error Call */
|
|
#define BITM_SDU_MSG_HALTONCALL (_ADI_MSK(0x04000000,uint32_t)) /* Generate an Emulation Exception Prior to a Callback Call */
|
|
#define BITM_SDU_MSG_HALTONINIT (_ADI_MSK(0x02000000,uint32_t)) /* Generate an Emulation Exception Prior to an Initcode Call */
|
|
#define BITM_SDU_MSG_HALTONAPP (_ADI_MSK(0x01000000,uint32_t)) /* Generate an Emulation Exception Prior to an Application Call */
|
|
#define BITM_SDU_MSG_L3INIT (_ADI_MSK(0x00800000,uint32_t)) /* Indicates that the L3 Resource is Initialized */
|
|
#define BITM_SDU_MSG_L2INIT (_ADI_MSK(0x00400000,uint32_t)) /* Indicates that the L2 Resource is Initialized */
|
|
#define BITM_SDU_MSG_C1L1INIT (_ADI_MSK(0x00020000,uint32_t)) /* Indicates that the Core 1 L1 Resource is Initialized */
|
|
#define BITM_SDU_MSG_C0L1INIT (_ADI_MSK(0x00010000,uint32_t)) /* Indicates that the Core 0 L1 Resource is Initialized */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SDU_GHLT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SDU_GHLT_SS2 18 /* Slave Select 2 */
|
|
#define BITP_SDU_GHLT_SS1 17 /* Slave Select 1 */
|
|
#define BITP_SDU_GHLT_SS0 16 /* Slave Select 0 */
|
|
#define BITP_SDU_GHLT_MS2 2 /* Master Select 2 */
|
|
#define BITP_SDU_GHLT_MS1 1 /* Master Select 1 */
|
|
#define BITP_SDU_GHLT_MS0 0 /* Master Select 0 */
|
|
#define BITM_SDU_GHLT_SS2 (_ADI_MSK(0x00040000,uint32_t)) /* Slave Select 2 */
|
|
#define BITM_SDU_GHLT_SS1 (_ADI_MSK(0x00020000,uint32_t)) /* Slave Select 1 */
|
|
#define BITM_SDU_GHLT_SS0 (_ADI_MSK(0x00010000,uint32_t)) /* Slave Select 0 */
|
|
#define BITM_SDU_GHLT_MS2 (_ADI_MSK(0x00000004,uint32_t)) /* Master Select 2 */
|
|
#define BITM_SDU_GHLT_MS1 (_ADI_MSK(0x00000002,uint32_t)) /* Master Select 1 */
|
|
#define BITM_SDU_GHLT_MS0 (_ADI_MSK(0x00000001,uint32_t)) /* Master Select 0 */
|
|
|
|
/* ==================================================
|
|
Ethernet MAC Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
EMAC0
|
|
========================= */
|
|
#define REG_EMAC0_MACCFG 0xFFC20000 /* EMAC0 MAC Configuration Register */
|
|
#define REG_EMAC0_MACFRMFILT 0xFFC20004 /* EMAC0 MAC Rx Frame Filter Register */
|
|
#define REG_EMAC0_HASHTBL_HI 0xFFC20008 /* EMAC0 Hash Table High Register */
|
|
#define REG_EMAC0_HASHTBL_LO 0xFFC2000C /* EMAC0 Hash Table Low Register */
|
|
#define REG_EMAC0_SMI_ADDR 0xFFC20010 /* EMAC0 SMI Address Register */
|
|
#define REG_EMAC0_SMI_DATA 0xFFC20014 /* EMAC0 SMI Data Register */
|
|
#define REG_EMAC0_FLOWCTL 0xFFC20018 /* EMAC0 FLow Control Register */
|
|
#define REG_EMAC0_VLANTAG 0xFFC2001C /* EMAC0 VLAN Tag Register */
|
|
#define REG_EMAC0_DBG 0xFFC20024 /* EMAC0 Debug Register */
|
|
#define REG_EMAC0_ISTAT 0xFFC20038 /* EMAC0 Interrupt Status Register */
|
|
#define REG_EMAC0_IMSK 0xFFC2003C /* EMAC0 Interrupt Mask Register */
|
|
#define REG_EMAC0_ADDR0_HI 0xFFC20040 /* EMAC0 MAC Address 0 High Register */
|
|
#define REG_EMAC0_ADDR0_LO 0xFFC20044 /* EMAC0 MAC Address 0 Low Register */
|
|
#define REG_EMAC0_MMC_CTL 0xFFC20100 /* EMAC0 MMC Control Register */
|
|
#define REG_EMAC0_MMC_RXINT 0xFFC20104 /* EMAC0 MMC Rx Interrupt Register */
|
|
#define REG_EMAC0_MMC_TXINT 0xFFC20108 /* EMAC0 MMC Tx Interrupt Register */
|
|
#define REG_EMAC0_MMC_RXIMSK 0xFFC2010C /* EMAC0 MMC Rx Interrupt Mask Register */
|
|
#define REG_EMAC0_MMC_TXIMSK 0xFFC20110 /* EMAC0 MMC TX Interrupt Mask Register */
|
|
#define REG_EMAC0_TXOCTCNT_GB 0xFFC20114 /* EMAC0 Tx OCT Count (Good/Bad) Register */
|
|
#define REG_EMAC0_TXFRMCNT_GB 0xFFC20118 /* EMAC0 Tx Frame Count (Good/Bad) Register */
|
|
#define REG_EMAC0_TXBCASTFRM_G 0xFFC2011C /* EMAC0 Tx Broadcast Frames (Good) Register */
|
|
#define REG_EMAC0_TXMCASTFRM_G 0xFFC20120 /* EMAC0 Tx Multicast Frames (Good) Register */
|
|
#define REG_EMAC0_TX64_GB 0xFFC20124 /* EMAC0 Tx 64-Byte Frames (Good/Bad) Register */
|
|
#define REG_EMAC0_TX65TO127_GB 0xFFC20128 /* EMAC0 Tx 65- to 127-Byte Frames (Good/Bad) Register */
|
|
#define REG_EMAC0_TX128TO255_GB 0xFFC2012C /* EMAC0 Tx 128- to 255-Byte Frames (Good/Bad) Register */
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#define REG_EMAC0_TX256TO511_GB 0xFFC20130 /* EMAC0 Tx 256- to 511-Byte Frames (Good/Bad) Register */
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#define REG_EMAC0_TX512TO1023_GB 0xFFC20134 /* EMAC0 Tx 512- to 1023-Byte Frames (Good/Bad) Register */
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#define REG_EMAC0_TX1024TOMAX_GB 0xFFC20138 /* EMAC0 Tx 1024- to Max-Byte Frames (Good/Bad) Register */
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#define REG_EMAC0_TXUCASTFRM_GB 0xFFC2013C /* EMAC0 Tx Unicast Frames (Good/Bad) Register */
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#define REG_EMAC0_TXMCASTFRM_GB 0xFFC20140 /* EMAC0 Tx Multicast Frames (Good/Bad) Register */
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#define REG_EMAC0_TXBCASTFRM_GB 0xFFC20144 /* EMAC0 Tx Broadcast Frames (Good/Bad) Register */
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#define REG_EMAC0_TXUNDR_ERR 0xFFC20148 /* EMAC0 Tx Underflow Error Register */
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#define REG_EMAC0_TXSNGCOL_G 0xFFC2014C /* EMAC0 Tx Single Collision (Good) Register */
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#define REG_EMAC0_TXMULTCOL_G 0xFFC20150 /* EMAC0 Tx Multiple Collision (Good) Register */
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#define REG_EMAC0_TXDEFERRED 0xFFC20154 /* EMAC0 Tx Deferred Register */
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#define REG_EMAC0_TXLATECOL 0xFFC20158 /* EMAC0 Tx Late Collision Register */
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#define REG_EMAC0_TXEXCESSCOL 0xFFC2015C /* EMAC0 Tx Excess Collision Register */
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#define REG_EMAC0_TXCARR_ERR 0xFFC20160 /* EMAC0 Tx Carrier Error Register */
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#define REG_EMAC0_TXOCTCNT_G 0xFFC20164 /* EMAC0 Tx Octet Count (Good) Register */
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#define REG_EMAC0_TXFRMCNT_G 0xFFC20168 /* EMAC0 Tx Frame Count (Good) Register */
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#define REG_EMAC0_TXEXCESSDEF 0xFFC2016C /* EMAC0 Tx Excess Deferral Register */
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#define REG_EMAC0_TXPAUSEFRM 0xFFC20170 /* EMAC0 Tx Pause Frame Register */
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#define REG_EMAC0_TXVLANFRM_G 0xFFC20174 /* EMAC0 Tx VLAN Frames (Good) Register */
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#define REG_EMAC0_RXFRMCNT_GB 0xFFC20180 /* EMAC0 Rx Frame Count (Good/Bad) Register */
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#define REG_EMAC0_RXOCTCNT_GB 0xFFC20184 /* EMAC0 Rx Octet Count (Good/Bad) Register */
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#define REG_EMAC0_RXOCTCNT_G 0xFFC20188 /* EMAC0 Rx Octet Count (Good) Register */
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#define REG_EMAC0_RXBCASTFRM_G 0xFFC2018C /* EMAC0 Rx Broadcast Frames (Good) Register */
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#define REG_EMAC0_RXMCASTFRM_G 0xFFC20190 /* EMAC0 Rx Multicast Frames (Good) Register */
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#define REG_EMAC0_RXCRC_ERR 0xFFC20194 /* EMAC0 Rx CRC Error Register */
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#define REG_EMAC0_RXALIGN_ERR 0xFFC20198 /* EMAC0 Rx alignment Error Register */
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#define REG_EMAC0_RXRUNT_ERR 0xFFC2019C /* EMAC0 Rx Runt Error Register */
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#define REG_EMAC0_RXJAB_ERR 0xFFC201A0 /* EMAC0 Rx Jab Error Register */
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#define REG_EMAC0_RXUSIZE_G 0xFFC201A4 /* EMAC0 Rx Undersize (Good) Register */
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#define REG_EMAC0_RXOSIZE_G 0xFFC201A8 /* EMAC0 Rx Oversize (Good) Register */
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#define REG_EMAC0_RX64_GB 0xFFC201AC /* EMAC0 Rx 64-Byte Frames (Good/Bad) Register */
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#define REG_EMAC0_RX65TO127_GB 0xFFC201B0 /* EMAC0 Rx 65- to 127-Byte Frames (Good/Bad) Register */
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#define REG_EMAC0_RX128TO255_GB 0xFFC201B4 /* EMAC0 Rx 128- to 255-Byte Frames (Good/Bad) Register */
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#define REG_EMAC0_RX256TO511_GB 0xFFC201B8 /* EMAC0 Rx 256- to 511-Byte Frames (Good/Bad) Register */
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#define REG_EMAC0_RX512TO1023_GB 0xFFC201BC /* EMAC0 Rx 512- to 1023-Byte Frames (Good/Bad) Register */
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#define REG_EMAC0_RX1024TOMAX_GB 0xFFC201C0 /* EMAC0 Rx 1024- to Max-Byte Frames (Good/Bad) Register */
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#define REG_EMAC0_RXUCASTFRM_G 0xFFC201C4 /* EMAC0 Rx Unicast Frames (Good) Register */
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#define REG_EMAC0_RXLEN_ERR 0xFFC201C8 /* EMAC0 Rx Length Error Register */
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#define REG_EMAC0_RXOORTYPE 0xFFC201CC /* EMAC0 Rx Out Of Range Type Register */
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#define REG_EMAC0_RXPAUSEFRM 0xFFC201D0 /* EMAC0 Rx Pause Frames Register */
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#define REG_EMAC0_RXFIFO_OVF 0xFFC201D4 /* EMAC0 Rx FIFO Overflow Register */
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#define REG_EMAC0_RXVLANFRM_GB 0xFFC201D8 /* EMAC0 Rx VLAN Frames (Good/Bad) Register */
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#define REG_EMAC0_RXWDOG_ERR 0xFFC201DC /* EMAC0 Rx Watch Dog Error Register */
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#define REG_EMAC0_IPC_RXIMSK 0xFFC20200 /* EMAC0 MMC IPC Rx Interrupt Mask Register */
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#define REG_EMAC0_IPC_RXINT 0xFFC20208 /* EMAC0 MMC IPC Rx Interrupt Register */
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#define REG_EMAC0_RXIPV4_GD_FRM 0xFFC20210 /* EMAC0 Rx IPv4 Datagrams (Good) Register */
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#define REG_EMAC0_RXIPV4_HDR_ERR_FRM 0xFFC20214 /* EMAC0 Rx IPv4 Datagrams Header Errors Register */
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#define REG_EMAC0_RXIPV4_NOPAY_FRM 0xFFC20218 /* EMAC0 Rx IPv4 Datagrams No Payload Frame Register */
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#define REG_EMAC0_RXIPV4_FRAG_FRM 0xFFC2021C /* EMAC0 Rx IPv4 Datagrams Fragmented Frames Register */
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#define REG_EMAC0_RXIPV4_UDSBL_FRM 0xFFC20220 /* EMAC0 Rx IPv4 UDP Disabled Frames Register */
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#define REG_EMAC0_RXIPV6_GD_FRM 0xFFC20224 /* EMAC0 Rx IPv6 Datagrams Good Frames Register */
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#define REG_EMAC0_RXIPV6_HDR_ERR_FRM 0xFFC20228 /* EMAC0 Rx IPv6 Datagrams Header Error Frames Register */
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#define REG_EMAC0_RXIPV6_NOPAY_FRM 0xFFC2022C /* EMAC0 Rx IPv6 Datagrams No Payload Frames Register */
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#define REG_EMAC0_RXUDP_GD_FRM 0xFFC20230 /* EMAC0 Rx UDP Good Frames Register */
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#define REG_EMAC0_RXUDP_ERR_FRM 0xFFC20234 /* EMAC0 Rx UDP Error Frames Register */
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#define REG_EMAC0_RXTCP_GD_FRM 0xFFC20238 /* EMAC0 Rx TCP Good Frames Register */
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#define REG_EMAC0_RXTCP_ERR_FRM 0xFFC2023C /* EMAC0 Rx TCP Error Frames Register */
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#define REG_EMAC0_RXICMP_GD_FRM 0xFFC20240 /* EMAC0 Rx ICMP Good Frames Register */
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#define REG_EMAC0_RXICMP_ERR_FRM 0xFFC20244 /* EMAC0 Rx ICMP Error Frames Register */
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#define REG_EMAC0_RXIPV4_GD_OCT 0xFFC20250 /* EMAC0 Rx IPv4 Datagrams Good Octets Register */
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#define REG_EMAC0_RXIPV4_HDR_ERR_OCT 0xFFC20254 /* EMAC0 Rx IPv4 Datagrams Header Errors Register */
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#define REG_EMAC0_RXIPV4_NOPAY_OCT 0xFFC20258 /* EMAC0 Rx IPv4 Datagrams No Payload Octets Register */
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#define REG_EMAC0_RXIPV4_FRAG_OCT 0xFFC2025C /* EMAC0 Rx IPv4 Datagrams Fragmented Octets Register */
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#define REG_EMAC0_RXIPV4_UDSBL_OCT 0xFFC20260 /* EMAC0 Rx IPv4 UDP Disabled Octets Register */
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#define REG_EMAC0_RXIPV6_GD_OCT 0xFFC20264 /* EMAC0 Rx IPv6 Good Octets Register */
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#define REG_EMAC0_RXIPV6_HDR_ERR_OCT 0xFFC20268 /* EMAC0 Rx IPv6 Header Errors Register */
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#define REG_EMAC0_RXIPV6_NOPAY_OCT 0xFFC2026C /* EMAC0 Rx IPv6 No Payload Octets Register */
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#define REG_EMAC0_RXUDP_GD_OCT 0xFFC20270 /* EMAC0 Rx UDP Good Octets Register */
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#define REG_EMAC0_RXUDP_ERR_OCT 0xFFC20274 /* EMAC0 Rx UDP Error Octets Register */
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#define REG_EMAC0_RXTCP_GD_OCT 0xFFC20278 /* EMAC0 Rx TCP Good Octets Register */
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#define REG_EMAC0_RXTCP_ERR_OCT 0xFFC2027C /* EMAC0 Rx TCP Error Octets Register */
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#define REG_EMAC0_RXICMP_GD_OCT 0xFFC20280 /* EMAC0 Rx ICMP Good Octets Register */
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#define REG_EMAC0_RXICMP_ERR_OCT 0xFFC20284 /* EMAC0 Rx ICMP Error Octets Register */
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#define REG_EMAC0_TM_CTL 0xFFC20700 /* EMAC0 Time Stamp Control Register */
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#define REG_EMAC0_TM_SUBSEC 0xFFC20704 /* EMAC0 Time Stamp Sub Second Increment Register */
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#define REG_EMAC0_TM_SEC 0xFFC20708 /* EMAC0 Time Stamp Low Seconds Register */
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#define REG_EMAC0_TM_NSEC 0xFFC2070C /* EMAC0 Time Stamp Nano Seconds Register */
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#define REG_EMAC0_TM_SECUPDT 0xFFC20710 /* EMAC0 Time Stamp Seconds Update Register */
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#define REG_EMAC0_TM_NSECUPDT 0xFFC20714 /* EMAC0 Time Stamp Nano Seconds Update Register */
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#define REG_EMAC0_TM_ADDEND 0xFFC20718 /* EMAC0 Time Stamp Addend Register */
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#define REG_EMAC0_TM_TGTM 0xFFC2071C /* EMAC0 Time Stamp Target Time Seconds Register */
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#define REG_EMAC0_TM_NTGTM 0xFFC20720 /* EMAC0 Time Stamp Target Time Nano Seconds Register */
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#define REG_EMAC0_TM_HISEC 0xFFC20724 /* EMAC0 Time Stamp High Second Register */
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#define REG_EMAC0_TM_STMPSTAT 0xFFC20728 /* EMAC0 Time Stamp Status Register */
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#define REG_EMAC0_TM_PPSCTL 0xFFC2072C /* EMAC0 PPS Control Register */
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#define REG_EMAC0_TM_AUXSTMP_NSEC 0xFFC20730 /* EMAC0 Time Stamp Auxilary TS Nano Seconds Register */
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#define REG_EMAC0_TM_AUXSTMP_SEC 0xFFC20734 /* EMAC0 Time Stamp Auxilary TM Seconds Register */
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#define REG_EMAC0_TM_PPSINTVL 0xFFC20760 /* EMAC0 Time Stamp PPS Interval Register */
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#define REG_EMAC0_TM_PPSWIDTH 0xFFC20764 /* EMAC0 PPS Width Register */
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#define REG_EMAC0_DMA_BUSMODE 0xFFC21000 /* EMAC0 DMA Bus Mode Register */
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#define REG_EMAC0_DMA_TXPOLL 0xFFC21004 /* EMAC0 DMA Tx Poll Demand Register */
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#define REG_EMAC0_DMA_RXPOLL 0xFFC21008 /* EMAC0 DMA Rx Poll Demand register */
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#define REG_EMAC0_DMA_RXDSC_ADDR 0xFFC2100C /* EMAC0 DMA Rx Descriptor List Address Register */
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#define REG_EMAC0_DMA_TXDSC_ADDR 0xFFC21010 /* EMAC0 DMA Tx Descriptor List Address Register */
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#define REG_EMAC0_DMA_STAT 0xFFC21014 /* EMAC0 DMA Status Register */
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#define REG_EMAC0_DMA_OPMODE 0xFFC21018 /* EMAC0 DMA Operation Mode Register */
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#define REG_EMAC0_DMA_IEN 0xFFC2101C /* EMAC0 DMA Interrupt Enable Register */
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#define REG_EMAC0_DMA_MISS_FRM 0xFFC21020 /* EMAC0 DMA Missed Frame Register */
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#define REG_EMAC0_DMA_RXIWDOG 0xFFC21024 /* EMAC0 DMA Rx Interrupt Watch Dog Register */
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#define REG_EMAC0_DMA_BMMODE 0xFFC21028 /* EMAC0 DMA SCB Bus Mode Register */
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#define REG_EMAC0_DMA_BMSTAT 0xFFC2102C /* EMAC0 DMA SCB Status Register */
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#define REG_EMAC0_DMA_TXDSC_CUR 0xFFC21048 /* EMAC0 DMA Tx Descriptor Current Register */
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#define REG_EMAC0_DMA_RXDSC_CUR 0xFFC2104C /* EMAC0 DMA Rx Descriptor Current Register */
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#define REG_EMAC0_DMA_TXBUF_CUR 0xFFC21050 /* EMAC0 DMA Tx Buffer Current Register */
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#define REG_EMAC0_DMA_RXBUF_CUR 0xFFC21054 /* EMAC0 DMA Rx Buffer Current Register */
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/* =========================
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EMAC1
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========================= */
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#define REG_EMAC1_MACCFG 0xFFC22000 /* EMAC1 MAC Configuration Register */
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#define REG_EMAC1_MACFRMFILT 0xFFC22004 /* EMAC1 MAC Rx Frame Filter Register */
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#define REG_EMAC1_HASHTBL_HI 0xFFC22008 /* EMAC1 Hash Table High Register */
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#define REG_EMAC1_HASHTBL_LO 0xFFC2200C /* EMAC1 Hash Table Low Register */
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#define REG_EMAC1_SMI_ADDR 0xFFC22010 /* EMAC1 SMI Address Register */
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#define REG_EMAC1_SMI_DATA 0xFFC22014 /* EMAC1 SMI Data Register */
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#define REG_EMAC1_FLOWCTL 0xFFC22018 /* EMAC1 FLow Control Register */
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#define REG_EMAC1_VLANTAG 0xFFC2201C /* EMAC1 VLAN Tag Register */
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#define REG_EMAC1_DBG 0xFFC22024 /* EMAC1 Debug Register */
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#define REG_EMAC1_ISTAT 0xFFC22038 /* EMAC1 Interrupt Status Register */
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#define REG_EMAC1_IMSK 0xFFC2203C /* EMAC1 Interrupt Mask Register */
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#define REG_EMAC1_ADDR0_HI 0xFFC22040 /* EMAC1 MAC Address 0 High Register */
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#define REG_EMAC1_ADDR0_LO 0xFFC22044 /* EMAC1 MAC Address 0 Low Register */
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#define REG_EMAC1_MMC_CTL 0xFFC22100 /* EMAC1 MMC Control Register */
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#define REG_EMAC1_MMC_RXINT 0xFFC22104 /* EMAC1 MMC Rx Interrupt Register */
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#define REG_EMAC1_MMC_TXINT 0xFFC22108 /* EMAC1 MMC Tx Interrupt Register */
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#define REG_EMAC1_MMC_RXIMSK 0xFFC2210C /* EMAC1 MMC Rx Interrupt Mask Register */
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#define REG_EMAC1_MMC_TXIMSK 0xFFC22110 /* EMAC1 MMC TX Interrupt Mask Register */
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#define REG_EMAC1_TXOCTCNT_GB 0xFFC22114 /* EMAC1 Tx OCT Count (Good/Bad) Register */
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#define REG_EMAC1_TXFRMCNT_GB 0xFFC22118 /* EMAC1 Tx Frame Count (Good/Bad) Register */
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#define REG_EMAC1_TXBCASTFRM_G 0xFFC2211C /* EMAC1 Tx Broadcast Frames (Good) Register */
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#define REG_EMAC1_TXMCASTFRM_G 0xFFC22120 /* EMAC1 Tx Multicast Frames (Good) Register */
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#define REG_EMAC1_TX64_GB 0xFFC22124 /* EMAC1 Tx 64-Byte Frames (Good/Bad) Register */
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#define REG_EMAC1_TX65TO127_GB 0xFFC22128 /* EMAC1 Tx 65- to 127-Byte Frames (Good/Bad) Register */
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#define REG_EMAC1_TX128TO255_GB 0xFFC2212C /* EMAC1 Tx 128- to 255-Byte Frames (Good/Bad) Register */
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#define REG_EMAC1_TX256TO511_GB 0xFFC22130 /* EMAC1 Tx 256- to 511-Byte Frames (Good/Bad) Register */
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#define REG_EMAC1_TX512TO1023_GB 0xFFC22134 /* EMAC1 Tx 512- to 1023-Byte Frames (Good/Bad) Register */
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#define REG_EMAC1_TX1024TOMAX_GB 0xFFC22138 /* EMAC1 Tx 1024- to Max-Byte Frames (Good/Bad) Register */
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#define REG_EMAC1_TXUCASTFRM_GB 0xFFC2213C /* EMAC1 Tx Unicast Frames (Good/Bad) Register */
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#define REG_EMAC1_TXMCASTFRM_GB 0xFFC22140 /* EMAC1 Tx Multicast Frames (Good/Bad) Register */
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#define REG_EMAC1_TXBCASTFRM_GB 0xFFC22144 /* EMAC1 Tx Broadcast Frames (Good/Bad) Register */
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#define REG_EMAC1_TXUNDR_ERR 0xFFC22148 /* EMAC1 Tx Underflow Error Register */
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#define REG_EMAC1_TXSNGCOL_G 0xFFC2214C /* EMAC1 Tx Single Collision (Good) Register */
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#define REG_EMAC1_TXMULTCOL_G 0xFFC22150 /* EMAC1 Tx Multiple Collision (Good) Register */
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#define REG_EMAC1_TXDEFERRED 0xFFC22154 /* EMAC1 Tx Deferred Register */
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#define REG_EMAC1_TXLATECOL 0xFFC22158 /* EMAC1 Tx Late Collision Register */
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#define REG_EMAC1_TXEXCESSCOL 0xFFC2215C /* EMAC1 Tx Excess Collision Register */
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#define REG_EMAC1_TXCARR_ERR 0xFFC22160 /* EMAC1 Tx Carrier Error Register */
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#define REG_EMAC1_TXOCTCNT_G 0xFFC22164 /* EMAC1 Tx Octet Count (Good) Register */
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#define REG_EMAC1_TXFRMCNT_G 0xFFC22168 /* EMAC1 Tx Frame Count (Good) Register */
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#define REG_EMAC1_TXEXCESSDEF 0xFFC2216C /* EMAC1 Tx Excess Deferral Register */
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#define REG_EMAC1_TXPAUSEFRM 0xFFC22170 /* EMAC1 Tx Pause Frame Register */
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#define REG_EMAC1_TXVLANFRM_G 0xFFC22174 /* EMAC1 Tx VLAN Frames (Good) Register */
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#define REG_EMAC1_RXFRMCNT_GB 0xFFC22180 /* EMAC1 Rx Frame Count (Good/Bad) Register */
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#define REG_EMAC1_RXOCTCNT_GB 0xFFC22184 /* EMAC1 Rx Octet Count (Good/Bad) Register */
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#define REG_EMAC1_RXOCTCNT_G 0xFFC22188 /* EMAC1 Rx Octet Count (Good) Register */
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#define REG_EMAC1_RXBCASTFRM_G 0xFFC2218C /* EMAC1 Rx Broadcast Frames (Good) Register */
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#define REG_EMAC1_RXMCASTFRM_G 0xFFC22190 /* EMAC1 Rx Multicast Frames (Good) Register */
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#define REG_EMAC1_RXCRC_ERR 0xFFC22194 /* EMAC1 Rx CRC Error Register */
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#define REG_EMAC1_RXALIGN_ERR 0xFFC22198 /* EMAC1 Rx alignment Error Register */
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#define REG_EMAC1_RXRUNT_ERR 0xFFC2219C /* EMAC1 Rx Runt Error Register */
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#define REG_EMAC1_RXJAB_ERR 0xFFC221A0 /* EMAC1 Rx Jab Error Register */
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#define REG_EMAC1_RXUSIZE_G 0xFFC221A4 /* EMAC1 Rx Undersize (Good) Register */
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#define REG_EMAC1_RXOSIZE_G 0xFFC221A8 /* EMAC1 Rx Oversize (Good) Register */
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#define REG_EMAC1_RX64_GB 0xFFC221AC /* EMAC1 Rx 64-Byte Frames (Good/Bad) Register */
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#define REG_EMAC1_RX65TO127_GB 0xFFC221B0 /* EMAC1 Rx 65- to 127-Byte Frames (Good/Bad) Register */
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#define REG_EMAC1_RX128TO255_GB 0xFFC221B4 /* EMAC1 Rx 128- to 255-Byte Frames (Good/Bad) Register */
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#define REG_EMAC1_RX256TO511_GB 0xFFC221B8 /* EMAC1 Rx 256- to 511-Byte Frames (Good/Bad) Register */
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#define REG_EMAC1_RX512TO1023_GB 0xFFC221BC /* EMAC1 Rx 512- to 1023-Byte Frames (Good/Bad) Register */
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#define REG_EMAC1_RX1024TOMAX_GB 0xFFC221C0 /* EMAC1 Rx 1024- to Max-Byte Frames (Good/Bad) Register */
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#define REG_EMAC1_RXUCASTFRM_G 0xFFC221C4 /* EMAC1 Rx Unicast Frames (Good) Register */
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#define REG_EMAC1_RXLEN_ERR 0xFFC221C8 /* EMAC1 Rx Length Error Register */
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#define REG_EMAC1_RXOORTYPE 0xFFC221CC /* EMAC1 Rx Out Of Range Type Register */
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#define REG_EMAC1_RXPAUSEFRM 0xFFC221D0 /* EMAC1 Rx Pause Frames Register */
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#define REG_EMAC1_RXFIFO_OVF 0xFFC221D4 /* EMAC1 Rx FIFO Overflow Register */
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#define REG_EMAC1_RXVLANFRM_GB 0xFFC221D8 /* EMAC1 Rx VLAN Frames (Good/Bad) Register */
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#define REG_EMAC1_RXWDOG_ERR 0xFFC221DC /* EMAC1 Rx Watch Dog Error Register */
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#define REG_EMAC1_IPC_RXIMSK 0xFFC22200 /* EMAC1 MMC IPC Rx Interrupt Mask Register */
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#define REG_EMAC1_IPC_RXINT 0xFFC22208 /* EMAC1 MMC IPC Rx Interrupt Register */
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#define REG_EMAC1_RXIPV4_GD_FRM 0xFFC22210 /* EMAC1 Rx IPv4 Datagrams (Good) Register */
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#define REG_EMAC1_RXIPV4_HDR_ERR_FRM 0xFFC22214 /* EMAC1 Rx IPv4 Datagrams Header Errors Register */
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#define REG_EMAC1_RXIPV4_NOPAY_FRM 0xFFC22218 /* EMAC1 Rx IPv4 Datagrams No Payload Frame Register */
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#define REG_EMAC1_RXIPV4_FRAG_FRM 0xFFC2221C /* EMAC1 Rx IPv4 Datagrams Fragmented Frames Register */
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#define REG_EMAC1_RXIPV4_UDSBL_FRM 0xFFC22220 /* EMAC1 Rx IPv4 UDP Disabled Frames Register */
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#define REG_EMAC1_RXIPV6_GD_FRM 0xFFC22224 /* EMAC1 Rx IPv6 Datagrams Good Frames Register */
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#define REG_EMAC1_RXIPV6_HDR_ERR_FRM 0xFFC22228 /* EMAC1 Rx IPv6 Datagrams Header Error Frames Register */
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#define REG_EMAC1_RXIPV6_NOPAY_FRM 0xFFC2222C /* EMAC1 Rx IPv6 Datagrams No Payload Frames Register */
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#define REG_EMAC1_RXUDP_GD_FRM 0xFFC22230 /* EMAC1 Rx UDP Good Frames Register */
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#define REG_EMAC1_RXUDP_ERR_FRM 0xFFC22234 /* EMAC1 Rx UDP Error Frames Register */
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#define REG_EMAC1_RXTCP_GD_FRM 0xFFC22238 /* EMAC1 Rx TCP Good Frames Register */
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#define REG_EMAC1_RXTCP_ERR_FRM 0xFFC2223C /* EMAC1 Rx TCP Error Frames Register */
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#define REG_EMAC1_RXICMP_GD_FRM 0xFFC22240 /* EMAC1 Rx ICMP Good Frames Register */
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#define REG_EMAC1_RXICMP_ERR_FRM 0xFFC22244 /* EMAC1 Rx ICMP Error Frames Register */
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#define REG_EMAC1_RXIPV4_GD_OCT 0xFFC22250 /* EMAC1 Rx IPv4 Datagrams Good Octets Register */
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#define REG_EMAC1_RXIPV4_HDR_ERR_OCT 0xFFC22254 /* EMAC1 Rx IPv4 Datagrams Header Errors Register */
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#define REG_EMAC1_RXIPV4_NOPAY_OCT 0xFFC22258 /* EMAC1 Rx IPv4 Datagrams No Payload Octets Register */
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#define REG_EMAC1_RXIPV4_FRAG_OCT 0xFFC2225C /* EMAC1 Rx IPv4 Datagrams Fragmented Octets Register */
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#define REG_EMAC1_RXIPV4_UDSBL_OCT 0xFFC22260 /* EMAC1 Rx IPv4 UDP Disabled Octets Register */
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#define REG_EMAC1_RXIPV6_GD_OCT 0xFFC22264 /* EMAC1 Rx IPv6 Good Octets Register */
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#define REG_EMAC1_RXIPV6_HDR_ERR_OCT 0xFFC22268 /* EMAC1 Rx IPv6 Header Errors Register */
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#define REG_EMAC1_RXIPV6_NOPAY_OCT 0xFFC2226C /* EMAC1 Rx IPv6 No Payload Octets Register */
|
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#define REG_EMAC1_RXUDP_GD_OCT 0xFFC22270 /* EMAC1 Rx UDP Good Octets Register */
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#define REG_EMAC1_RXUDP_ERR_OCT 0xFFC22274 /* EMAC1 Rx UDP Error Octets Register */
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#define REG_EMAC1_RXTCP_GD_OCT 0xFFC22278 /* EMAC1 Rx TCP Good Octets Register */
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#define REG_EMAC1_RXTCP_ERR_OCT 0xFFC2227C /* EMAC1 Rx TCP Error Octets Register */
|
|
#define REG_EMAC1_RXICMP_GD_OCT 0xFFC22280 /* EMAC1 Rx ICMP Good Octets Register */
|
|
#define REG_EMAC1_RXICMP_ERR_OCT 0xFFC22284 /* EMAC1 Rx ICMP Error Octets Register */
|
|
#define REG_EMAC1_TM_CTL 0xFFC22700 /* EMAC1 Time Stamp Control Register */
|
|
#define REG_EMAC1_TM_SUBSEC 0xFFC22704 /* EMAC1 Time Stamp Sub Second Increment Register */
|
|
#define REG_EMAC1_TM_SEC 0xFFC22708 /* EMAC1 Time Stamp Low Seconds Register */
|
|
#define REG_EMAC1_TM_NSEC 0xFFC2270C /* EMAC1 Time Stamp Nano Seconds Register */
|
|
#define REG_EMAC1_TM_SECUPDT 0xFFC22710 /* EMAC1 Time Stamp Seconds Update Register */
|
|
#define REG_EMAC1_TM_NSECUPDT 0xFFC22714 /* EMAC1 Time Stamp Nano Seconds Update Register */
|
|
#define REG_EMAC1_TM_ADDEND 0xFFC22718 /* EMAC1 Time Stamp Addend Register */
|
|
#define REG_EMAC1_TM_TGTM 0xFFC2271C /* EMAC1 Time Stamp Target Time Seconds Register */
|
|
#define REG_EMAC1_TM_NTGTM 0xFFC22720 /* EMAC1 Time Stamp Target Time Nano Seconds Register */
|
|
#define REG_EMAC1_TM_HISEC 0xFFC22724 /* EMAC1 Time Stamp High Second Register */
|
|
#define REG_EMAC1_TM_STMPSTAT 0xFFC22728 /* EMAC1 Time Stamp Status Register */
|
|
#define REG_EMAC1_TM_PPSCTL 0xFFC2272C /* EMAC1 PPS Control Register */
|
|
#define REG_EMAC1_TM_AUXSTMP_NSEC 0xFFC22730 /* EMAC1 Time Stamp Auxilary TS Nano Seconds Register */
|
|
#define REG_EMAC1_TM_AUXSTMP_SEC 0xFFC22734 /* EMAC1 Time Stamp Auxilary TM Seconds Register */
|
|
#define REG_EMAC1_TM_PPSINTVL 0xFFC22760 /* EMAC1 Time Stamp PPS Interval Register */
|
|
#define REG_EMAC1_TM_PPSWIDTH 0xFFC22764 /* EMAC1 PPS Width Register */
|
|
#define REG_EMAC1_DMA_BUSMODE 0xFFC23000 /* EMAC1 DMA Bus Mode Register */
|
|
#define REG_EMAC1_DMA_TXPOLL 0xFFC23004 /* EMAC1 DMA Tx Poll Demand Register */
|
|
#define REG_EMAC1_DMA_RXPOLL 0xFFC23008 /* EMAC1 DMA Rx Poll Demand register */
|
|
#define REG_EMAC1_DMA_RXDSC_ADDR 0xFFC2300C /* EMAC1 DMA Rx Descriptor List Address Register */
|
|
#define REG_EMAC1_DMA_TXDSC_ADDR 0xFFC23010 /* EMAC1 DMA Tx Descriptor List Address Register */
|
|
#define REG_EMAC1_DMA_STAT 0xFFC23014 /* EMAC1 DMA Status Register */
|
|
#define REG_EMAC1_DMA_OPMODE 0xFFC23018 /* EMAC1 DMA Operation Mode Register */
|
|
#define REG_EMAC1_DMA_IEN 0xFFC2301C /* EMAC1 DMA Interrupt Enable Register */
|
|
#define REG_EMAC1_DMA_MISS_FRM 0xFFC23020 /* EMAC1 DMA Missed Frame Register */
|
|
#define REG_EMAC1_DMA_RXIWDOG 0xFFC23024 /* EMAC1 DMA Rx Interrupt Watch Dog Register */
|
|
#define REG_EMAC1_DMA_BMMODE 0xFFC23028 /* EMAC1 DMA SCB Bus Mode Register */
|
|
#define REG_EMAC1_DMA_BMSTAT 0xFFC2302C /* EMAC1 DMA SCB Status Register */
|
|
#define REG_EMAC1_DMA_TXDSC_CUR 0xFFC23048 /* EMAC1 DMA Tx Descriptor Current Register */
|
|
#define REG_EMAC1_DMA_RXDSC_CUR 0xFFC2304C /* EMAC1 DMA Rx Descriptor Current Register */
|
|
#define REG_EMAC1_DMA_TXBUF_CUR 0xFFC23050 /* EMAC1 DMA Tx Buffer Current Register */
|
|
#define REG_EMAC1_DMA_RXBUF_CUR 0xFFC23054 /* EMAC1 DMA Rx Buffer Current Register */
|
|
|
|
/* =========================
|
|
EMAC
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EMAC_MACCFG Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EMAC_MACCFG_CST 25 /* CRC Stripping */
|
|
#define BITP_EMAC_MACCFG_WD 23 /* Watch Dog Disable */
|
|
#define BITP_EMAC_MACCFG_JB 22 /* Jabber Disable */
|
|
#define BITP_EMAC_MACCFG_JE 20 /* Jumbo Frame Enable */
|
|
#define BITP_EMAC_MACCFG_IFG 17 /* Inter Frame Gap */
|
|
#define BITP_EMAC_MACCFG_DCRS 16 /* Disable Carrier Sense */
|
|
#define BITP_EMAC_MACCFG_FES 14 /* Speed of Operation */
|
|
#define BITP_EMAC_MACCFG_DO 13 /* Disable Receive Own */
|
|
#define BITP_EMAC_MACCFG_LM 12 /* Loopback Mode */
|
|
#define BITP_EMAC_MACCFG_DM 11 /* Duplex Mode */
|
|
#define BITP_EMAC_MACCFG_IPC 10 /* IP Checksum */
|
|
#define BITP_EMAC_MACCFG_DR 9 /* Disable Retry */
|
|
#define BITP_EMAC_MACCFG_ACS 7 /* Automatic Pad/CRC Stripping */
|
|
#define BITP_EMAC_MACCFG_BL 5 /* Back Off Limit */
|
|
#define BITP_EMAC_MACCFG_DC 4 /* Deferral Check */
|
|
#define BITP_EMAC_MACCFG_TE 3 /* Transmitter Enable */
|
|
#define BITP_EMAC_MACCFG_RE 2 /* Receiver Enable */
|
|
#define BITM_EMAC_MACCFG_CST (_ADI_MSK(0x02000000,uint32_t)) /* CRC Stripping */
|
|
#define BITM_EMAC_MACCFG_WD (_ADI_MSK(0x00800000,uint32_t)) /* Watch Dog Disable */
|
|
#define BITM_EMAC_MACCFG_JB (_ADI_MSK(0x00400000,uint32_t)) /* Jabber Disable */
|
|
#define BITM_EMAC_MACCFG_JE (_ADI_MSK(0x00100000,uint32_t)) /* Jumbo Frame Enable */
|
|
|
|
#define BITM_EMAC_MACCFG_IFG (_ADI_MSK(0x000E0000,uint32_t)) /* Inter Frame Gap */
|
|
#define ENUM_EMAC_MACCFG_BIT_TIMES_96 (_ADI_MSK(0x00000000,uint32_t)) /* IFG: 96 bit times */
|
|
#define ENUM_EMAC_MACCFG_BIT_TIMES_88 (_ADI_MSK(0x00020000,uint32_t)) /* IFG: 88 bit times */
|
|
#define ENUM_EMAC_MACCFG_BIT_TIMES_80 (_ADI_MSK(0x00040000,uint32_t)) /* IFG: 80 bit times */
|
|
#define ENUM_EMAC_MACCFG_BIT_TIMES_72 (_ADI_MSK(0x00060000,uint32_t)) /* IFG: 72 bit times */
|
|
#define ENUM_EMAC_MACCFG_BIT_TIMES_64 (_ADI_MSK(0x00080000,uint32_t)) /* IFG: 64 bit times */
|
|
#define ENUM_EMAC_MACCFG_BIT_TIMES_56 (_ADI_MSK(0x000A0000,uint32_t)) /* IFG: 56 bit times */
|
|
#define ENUM_EMAC_MACCFG_BIT_TIMES_48 (_ADI_MSK(0x000C0000,uint32_t)) /* IFG: 48 bit times */
|
|
#define ENUM_EMAC_MACCFG_BIT_TIMES_40 (_ADI_MSK(0x000E0000,uint32_t)) /* IFG: 40 bit times */
|
|
#define BITM_EMAC_MACCFG_DCRS (_ADI_MSK(0x00010000,uint32_t)) /* Disable Carrier Sense */
|
|
#define BITM_EMAC_MACCFG_FES (_ADI_MSK(0x00004000,uint32_t)) /* Speed of Operation */
|
|
#define BITM_EMAC_MACCFG_DO (_ADI_MSK(0x00002000,uint32_t)) /* Disable Receive Own */
|
|
#define BITM_EMAC_MACCFG_LM (_ADI_MSK(0x00001000,uint32_t)) /* Loopback Mode */
|
|
#define BITM_EMAC_MACCFG_DM (_ADI_MSK(0x00000800,uint32_t)) /* Duplex Mode */
|
|
#define BITM_EMAC_MACCFG_IPC (_ADI_MSK(0x00000400,uint32_t)) /* IP Checksum */
|
|
|
|
#define BITM_EMAC_MACCFG_DR (_ADI_MSK(0x00000200,uint32_t)) /* Disable Retry */
|
|
#define ENUM_EMAC_MACCFG_RETRY_ENABLED (_ADI_MSK(0x00000000,uint32_t)) /* DR: Retry enabled */
|
|
#define ENUM_EMAC_MACCFG_RETRY_DISABLED (_ADI_MSK(0x00000200,uint32_t)) /* DR: Retry disabled */
|
|
#define BITM_EMAC_MACCFG_ACS (_ADI_MSK(0x00000080,uint32_t)) /* Automatic Pad/CRC Stripping */
|
|
|
|
#define BITM_EMAC_MACCFG_BL (_ADI_MSK(0x00000060,uint32_t)) /* Back Off Limit */
|
|
#define ENUM_EMAC_MACCFG_BL_10 (_ADI_MSK(0x00000000,uint32_t)) /* BL: k = min (n, 10) */
|
|
#define ENUM_EMAC_MACCFG_BL_8 (_ADI_MSK(0x00000020,uint32_t)) /* BL: k = min (n, 8) */
|
|
#define ENUM_EMAC_MACCFG_BL_4 (_ADI_MSK(0x00000040,uint32_t)) /* BL: k = min (n, 4) */
|
|
#define ENUM_EMAC_MACCFG_BL_1 (_ADI_MSK(0x00000060,uint32_t)) /* BL: k = min (n, 1) */
|
|
#define BITM_EMAC_MACCFG_DC (_ADI_MSK(0x00000010,uint32_t)) /* Deferral Check */
|
|
#define BITM_EMAC_MACCFG_TE (_ADI_MSK(0x00000008,uint32_t)) /* Transmitter Enable */
|
|
#define BITM_EMAC_MACCFG_RE (_ADI_MSK(0x00000004,uint32_t)) /* Receiver Enable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EMAC_MACFRMFILT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EMAC_MACFRMFILT_RA 31 /* Receive All Frames */
|
|
#define BITP_EMAC_MACFRMFILT_HPF 10 /* Hash or Perfect Filter */
|
|
#define BITP_EMAC_MACFRMFILT_PCF 6 /* Pass Control Frames */
|
|
#define BITP_EMAC_MACFRMFILT_DBF 5 /* Disable Broadcast Frames */
|
|
#define BITP_EMAC_MACFRMFILT_PM 4 /* Pass All Multicast Frames */
|
|
#define BITP_EMAC_MACFRMFILT_DAIF 3 /* Destination Address Inverse Filtering */
|
|
#define BITP_EMAC_MACFRMFILT_HMC 2 /* Hash Multicast */
|
|
#define BITP_EMAC_MACFRMFILT_HUC 1 /* Hash Unicast */
|
|
#define BITP_EMAC_MACFRMFILT_PR 0 /* Promiscuous Mode */
|
|
#define BITM_EMAC_MACFRMFILT_RA (_ADI_MSK(0x80000000,uint32_t)) /* Receive All Frames */
|
|
#define BITM_EMAC_MACFRMFILT_HPF (_ADI_MSK(0x00000400,uint32_t)) /* Hash or Perfect Filter */
|
|
|
|
#define BITM_EMAC_MACFRMFILT_PCF (_ADI_MSK(0x000000C0,uint32_t)) /* Pass Control Frames */
|
|
#define ENUM_EMAC_MACFRMFILT_FILT_ALL (_ADI_MSK(0x00000000,uint32_t)) /* PCF: Pass no control frames */
|
|
#define ENUM_EMAC_MACFRMFILT_NO_PAUSE (_ADI_MSK(0x00000040,uint32_t)) /* PCF: Pass no PAUSE frames */
|
|
#define ENUM_EMAC_MACFRMFILT_FWD_ALL (_ADI_MSK(0x00000080,uint32_t)) /* PCF: Pass all control frames */
|
|
#define ENUM_EMAC_MACFRMFILT_PADR_FILT (_ADI_MSK(0x000000C0,uint32_t)) /* PCF: Pass address filtered control frames */
|
|
|
|
#define BITM_EMAC_MACFRMFILT_DBF (_ADI_MSK(0x00000020,uint32_t)) /* Disable Broadcast Frames */
|
|
#define ENUM_EMAC_MACFRMFILT_DIS_BCAST (_ADI_MSK(0x00000000,uint32_t)) /* DBF: AFM module passes all received broadcast frames */
|
|
#define ENUM_EMAC_MACFRMFILT_EN_BCAST (_ADI_MSK(0x00000020,uint32_t)) /* DBF: AFM module filters all incoming broadcast frames */
|
|
#define BITM_EMAC_MACFRMFILT_PM (_ADI_MSK(0x00000010,uint32_t)) /* Pass All Multicast Frames */
|
|
#define BITM_EMAC_MACFRMFILT_DAIF (_ADI_MSK(0x00000008,uint32_t)) /* Destination Address Inverse Filtering */
|
|
#define BITM_EMAC_MACFRMFILT_HMC (_ADI_MSK(0x00000004,uint32_t)) /* Hash Multicast */
|
|
#define BITM_EMAC_MACFRMFILT_HUC (_ADI_MSK(0x00000002,uint32_t)) /* Hash Unicast */
|
|
#define BITM_EMAC_MACFRMFILT_PR (_ADI_MSK(0x00000001,uint32_t)) /* Promiscuous Mode */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EMAC_SMI_ADDR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EMAC_SMI_ADDR_PA 11 /* Physical Layer Address */
|
|
#define BITP_EMAC_SMI_ADDR_SMIR 6 /* SMI Register Address */
|
|
#define BITP_EMAC_SMI_ADDR_CR 2 /* Clock Range */
|
|
#define BITP_EMAC_SMI_ADDR_SMIW 1 /* SMI Write */
|
|
#define BITP_EMAC_SMI_ADDR_SMIB 0 /* SMI Busy */
|
|
#define BITM_EMAC_SMI_ADDR_PA (_ADI_MSK(0x0000F800,uint32_t)) /* Physical Layer Address */
|
|
#define BITM_EMAC_SMI_ADDR_SMIR (_ADI_MSK(0x000007C0,uint32_t)) /* SMI Register Address */
|
|
#define BITM_EMAC_SMI_ADDR_CR (_ADI_MSK(0x0000003C,uint32_t)) /* Clock Range */
|
|
#define BITM_EMAC_SMI_ADDR_SMIW (_ADI_MSK(0x00000002,uint32_t)) /* SMI Write */
|
|
#define BITM_EMAC_SMI_ADDR_SMIB (_ADI_MSK(0x00000001,uint32_t)) /* SMI Busy */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EMAC_SMI_DATA Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EMAC_SMI_DATA_SMID 0 /* SMI Data */
|
|
#define BITM_EMAC_SMI_DATA_SMID (_ADI_MSK(0x0000FFFF,uint32_t)) /* SMI Data */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EMAC_FLOWCTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EMAC_FLOWCTL_PT 16 /* Pause Time */
|
|
#define BITP_EMAC_FLOWCTL_UP 3 /* Unicast Pause Frame Detect */
|
|
#define BITP_EMAC_FLOWCTL_RFE 2 /* Receive Flow Control Enable */
|
|
#define BITP_EMAC_FLOWCTL_TFE 1 /* Transmit Flow Control Enable */
|
|
#define BITP_EMAC_FLOWCTL_FCBBPA 0 /* Initiate Pause Control Frame */
|
|
#define BITM_EMAC_FLOWCTL_PT (_ADI_MSK(0xFFFF0000,uint32_t)) /* Pause Time */
|
|
#define BITM_EMAC_FLOWCTL_UP (_ADI_MSK(0x00000008,uint32_t)) /* Unicast Pause Frame Detect */
|
|
#define BITM_EMAC_FLOWCTL_RFE (_ADI_MSK(0x00000004,uint32_t)) /* Receive Flow Control Enable */
|
|
#define BITM_EMAC_FLOWCTL_TFE (_ADI_MSK(0x00000002,uint32_t)) /* Transmit Flow Control Enable */
|
|
#define BITM_EMAC_FLOWCTL_FCBBPA (_ADI_MSK(0x00000001,uint32_t)) /* Initiate Pause Control Frame */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EMAC_VLANTAG Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EMAC_VLANTAG_ETV 16 /* Enable Tag VLAN Comparison */
|
|
#define BITP_EMAC_VLANTAG_VL 0 /* VLAN Tag Id Receive Frames */
|
|
#define BITM_EMAC_VLANTAG_ETV (_ADI_MSK(0x00010000,uint32_t)) /* Enable Tag VLAN Comparison */
|
|
#define BITM_EMAC_VLANTAG_VL (_ADI_MSK(0x0000FFFF,uint32_t)) /* VLAN Tag Id Receive Frames */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EMAC_DBG Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EMAC_DBG_TXFIFOFULL 25 /* Tx FIFO Full */
|
|
#define BITP_EMAC_DBG_TXFIFONE 24 /* Tx FIFO Not Empty */
|
|
#define BITP_EMAC_DBG_TXFIFOACT 22 /* Tx FIFO Active */
|
|
#define BITP_EMAC_DBG_TXFIFOCTLST 20 /* Tx FIFO Controller State */
|
|
#define BITP_EMAC_DBG_TXPAUSE 19 /* Tx Paused */
|
|
#define BITP_EMAC_DBG_TXFRCTL 17 /* Tx Frame Controller State */
|
|
#define BITP_EMAC_DBG_MMTEA 16 /* MM Tx Engine Active */
|
|
#define BITP_EMAC_DBG_RXFIFOST 8 /* Rx FIFO State */
|
|
#define BITP_EMAC_DBG_RXFIFOCTLST 5 /* Rx FIFO Controller State */
|
|
#define BITP_EMAC_DBG_RXFIFOACT 4 /* Rx FIFO Active */
|
|
#define BITP_EMAC_DBG_SFIFOST 1 /* Small FIFO State */
|
|
#define BITP_EMAC_DBG_MMREA 0 /* MM Rx Engine Active */
|
|
#define BITM_EMAC_DBG_TXFIFOFULL (_ADI_MSK(0x02000000,uint32_t)) /* Tx FIFO Full */
|
|
#define BITM_EMAC_DBG_TXFIFONE (_ADI_MSK(0x01000000,uint32_t)) /* Tx FIFO Not Empty */
|
|
#define BITM_EMAC_DBG_TXFIFOACT (_ADI_MSK(0x00400000,uint32_t)) /* Tx FIFO Active */
|
|
#define BITM_EMAC_DBG_TXFIFOCTLST (_ADI_MSK(0x00300000,uint32_t)) /* Tx FIFO Controller State */
|
|
#define BITM_EMAC_DBG_TXPAUSE (_ADI_MSK(0x00080000,uint32_t)) /* Tx Paused */
|
|
|
|
#define BITM_EMAC_DBG_TXFRCTL (_ADI_MSK(0x00060000,uint32_t)) /* Tx Frame Controller State */
|
|
#define ENUM_EMAC_DBG_TXFRCTL_IDLE (_ADI_MSK(0x00000000,uint32_t)) /* TXFRCTL: Idle */
|
|
#define ENUM_EMAC_DBG_TXFRCTL_WT_STATUS (_ADI_MSK(0x00020000,uint32_t)) /* TXFRCTL: Wait */
|
|
#define ENUM_EMAC_DBG_TXFRCTL_PAUSE (_ADI_MSK(0x00040000,uint32_t)) /* TXFRCTL: Pause */
|
|
#define ENUM_EMAC_DBG_TXFRCTL_TXFRAME (_ADI_MSK(0x00060000,uint32_t)) /* TXFRCTL: Transmit */
|
|
#define BITM_EMAC_DBG_MMTEA (_ADI_MSK(0x00010000,uint32_t)) /* MM Tx Engine Active */
|
|
|
|
#define BITM_EMAC_DBG_RXFIFOST (_ADI_MSK(0x00000300,uint32_t)) /* Rx FIFO State */
|
|
#define ENUM_EMAC_DBG_FIFO_EMPTY (_ADI_MSK(0x00000000,uint32_t)) /* RXFIFOST: Rx FIFO Empty */
|
|
#define ENUM_EMAC_DBG_FIFO_BEL_THERSHLD (_ADI_MSK(0x00000100,uint32_t)) /* RXFIFOST: Rx FIFO Below De-activate FCT */
|
|
#define ENUM_EMAC_DBG_FIFO_ABV_THERSHLD (_ADI_MSK(0x00000200,uint32_t)) /* RXFIFOST: Rx FIFO Above De-activate FCT */
|
|
#define ENUM_EMAC_DBG_FIFO_FULL (_ADI_MSK(0x00000300,uint32_t)) /* RXFIFOST: Rx FIFO Full */
|
|
|
|
#define BITM_EMAC_DBG_RXFIFOCTLST (_ADI_MSK(0x00000060,uint32_t)) /* Rx FIFO Controller State */
|
|
#define ENUM_EMAC_DBG_IDLE_FIFO (_ADI_MSK(0x00000000,uint32_t)) /* RXFIFOCTLST: Idle */
|
|
#define ENUM_EMAC_DBG_RD_DATA_FIFO (_ADI_MSK(0x00000020,uint32_t)) /* RXFIFOCTLST: Read Data */
|
|
#define ENUM_EMAC_DBG_RD_STS_FIFO (_ADI_MSK(0x00000040,uint32_t)) /* RXFIFOCTLST: Read Status */
|
|
#define ENUM_EMAC_DBG_FLUSH_FIFO (_ADI_MSK(0x00000060,uint32_t)) /* RXFIFOCTLST: Flush */
|
|
#define BITM_EMAC_DBG_RXFIFOACT (_ADI_MSK(0x00000010,uint32_t)) /* Rx FIFO Active */
|
|
#define BITM_EMAC_DBG_SFIFOST (_ADI_MSK(0x00000006,uint32_t)) /* Small FIFO State */
|
|
#define BITM_EMAC_DBG_MMREA (_ADI_MSK(0x00000001,uint32_t)) /* MM Rx Engine Active */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EMAC_ISTAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EMAC_ISTAT_TS 9 /* Time Stamp Interrupt Status */
|
|
#define BITP_EMAC_ISTAT_MMCRC 7 /* MMC Receive Checksum Offload Interrupt Status */
|
|
#define BITP_EMAC_ISTAT_MMCTX 6 /* MMC Transmit Interrupt Status */
|
|
#define BITP_EMAC_ISTAT_MMCRX 5 /* MMC Receive Interrupt Status */
|
|
#define BITP_EMAC_ISTAT_MMC 4 /* MMC Interrupt Status */
|
|
#define BITM_EMAC_ISTAT_TS (_ADI_MSK(0x00000200,uint32_t)) /* Time Stamp Interrupt Status */
|
|
#define BITM_EMAC_ISTAT_MMCRC (_ADI_MSK(0x00000080,uint32_t)) /* MMC Receive Checksum Offload Interrupt Status */
|
|
#define BITM_EMAC_ISTAT_MMCTX (_ADI_MSK(0x00000040,uint32_t)) /* MMC Transmit Interrupt Status */
|
|
#define BITM_EMAC_ISTAT_MMCRX (_ADI_MSK(0x00000020,uint32_t)) /* MMC Receive Interrupt Status */
|
|
#define BITM_EMAC_ISTAT_MMC (_ADI_MSK(0x00000010,uint32_t)) /* MMC Interrupt Status */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EMAC_IMSK Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EMAC_IMSK_TS 9 /* Time Stamp Interrupt Mask */
|
|
#define BITM_EMAC_IMSK_TS (_ADI_MSK(0x00000200,uint32_t)) /* Time Stamp Interrupt Mask */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EMAC_ADDR0_HI Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EMAC_ADDR0_HI_ADDR 0 /* Address */
|
|
#define BITM_EMAC_ADDR0_HI_ADDR (_ADI_MSK(0x0000FFFF,uint32_t)) /* Address */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EMAC_MMC_CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EMAC_MMC_CTL_FULLPSET 5 /* Full Preset */
|
|
#define BITP_EMAC_MMC_CTL_CNTRPSET 4 /* Counter Reset/Preset */
|
|
#define BITP_EMAC_MMC_CTL_CNTRFRZ 3 /* Counter Freeze */
|
|
#define BITP_EMAC_MMC_CTL_RDRST 2 /* Read Reset */
|
|
#define BITP_EMAC_MMC_CTL_NOROLL 1 /* No Rollover */
|
|
#define BITP_EMAC_MMC_CTL_RST 0 /* Reset */
|
|
#define BITM_EMAC_MMC_CTL_FULLPSET (_ADI_MSK(0x00000020,uint32_t)) /* Full Preset */
|
|
#define BITM_EMAC_MMC_CTL_CNTRPSET (_ADI_MSK(0x00000010,uint32_t)) /* Counter Reset/Preset */
|
|
#define BITM_EMAC_MMC_CTL_CNTRFRZ (_ADI_MSK(0x00000008,uint32_t)) /* Counter Freeze */
|
|
#define BITM_EMAC_MMC_CTL_RDRST (_ADI_MSK(0x00000004,uint32_t)) /* Read Reset */
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#define BITM_EMAC_MMC_CTL_NOROLL (_ADI_MSK(0x00000002,uint32_t)) /* No Rollover */
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#define BITM_EMAC_MMC_CTL_RST (_ADI_MSK(0x00000001,uint32_t)) /* Reset */
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/* ------------------------------------------------------------------------------------------------------------------------
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EMAC_MMC_RXINT Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_EMAC_MMC_RXINT_WDOGERR 23 /* Rx Watch Dog Error Count Half/Full */
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#define BITP_EMAC_MMC_RXINT_VLANFRGB 22 /* Rx VLAN Frames (Good/Bad) Count Half/Full */
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#define BITP_EMAC_MMC_RXINT_FIFOOVF 21 /* Rx FIFO Overflow Count Half/Full */
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#define BITP_EMAC_MMC_RXINT_PAUSEFR 20 /* Rx Pause Frames Count Half/Full */
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#define BITP_EMAC_MMC_RXINT_OUTRANGE 19 /* Rx Out Of Range Type Count Half/Full */
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#define BITP_EMAC_MMC_RXINT_LENERR 18 /* Rx Length Error Count Half/Full */
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#define BITP_EMAC_MMC_RXINT_UCASTG 17 /* Rx Unicast Frames (Good) Count Half/Full */
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#define BITP_EMAC_MMC_RXINT_R1024TOMAX 16 /* Rx 1024-to-max Octets (Good/Bad) Count Half/Full */
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#define BITP_EMAC_MMC_RXINT_R512TO1023 15 /* Rx 512-to-1023 Octets (Good/Bad) Count Half/Full */
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#define BITP_EMAC_MMC_RXINT_R256TO511 14 /* Rx 255-to-511 Octets (Good/Bad) Count Half/Full */
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#define BITP_EMAC_MMC_RXINT_R128TO255 13 /* Rx 128-to-255 Octets (Good/Bad) Count Half/Full */
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#define BITP_EMAC_MMC_RXINT_R65TO127 12 /* Rx 65-to-127 Octets (Good/Bad) Count Half/Full */
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#define BITP_EMAC_MMC_RXINT_R64 11 /* Rx 64 Octets (Good/Bad) Count Half/Full */
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#define BITP_EMAC_MMC_RXINT_OSIZEG 10 /* Rx Oversize (Good) Count Half/Full */
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#define BITP_EMAC_MMC_RXINT_USIZEG 9 /* Rx Undersize (Good) Count Half/Full */
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#define BITP_EMAC_MMC_RXINT_JABERR 8 /* Rx Jabber Error Count Half/Full */
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#define BITP_EMAC_MMC_RXINT_RUNTERR 7 /* Rx Runt Error Count Half/Full */
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#define BITP_EMAC_MMC_RXINT_ALIGNERR 6 /* Rx Alignment Error Count Half/Full */
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#define BITP_EMAC_MMC_RXINT_CRCERR 5 /* Rx CRC Error Counter Half/Full */
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#define BITP_EMAC_MMC_RXINT_MCASTG 4 /* Rx Multicast Count (Good) Half/Full */
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#define BITP_EMAC_MMC_RXINT_BCASTG 3 /* Rx Broadcast Count (Good) Half/Full */
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#define BITP_EMAC_MMC_RXINT_OCTCNTG 2 /* Octet Count (Good) Half/Full */
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#define BITP_EMAC_MMC_RXINT_OCTCNTGB 1 /* Octet Count (Good/Bad) Half/Full */
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#define BITP_EMAC_MMC_RXINT_FRCNTGB 0 /* Frame Count (Good/Bad) Half/Full */
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#define BITM_EMAC_MMC_RXINT_WDOGERR (_ADI_MSK(0x00800000,uint32_t)) /* Rx Watch Dog Error Count Half/Full */
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#define BITM_EMAC_MMC_RXINT_VLANFRGB (_ADI_MSK(0x00400000,uint32_t)) /* Rx VLAN Frames (Good/Bad) Count Half/Full */
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#define BITM_EMAC_MMC_RXINT_FIFOOVF (_ADI_MSK(0x00200000,uint32_t)) /* Rx FIFO Overflow Count Half/Full */
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#define BITM_EMAC_MMC_RXINT_PAUSEFR (_ADI_MSK(0x00100000,uint32_t)) /* Rx Pause Frames Count Half/Full */
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#define BITM_EMAC_MMC_RXINT_OUTRANGE (_ADI_MSK(0x00080000,uint32_t)) /* Rx Out Of Range Type Count Half/Full */
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#define BITM_EMAC_MMC_RXINT_LENERR (_ADI_MSK(0x00040000,uint32_t)) /* Rx Length Error Count Half/Full */
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#define BITM_EMAC_MMC_RXINT_UCASTG (_ADI_MSK(0x00020000,uint32_t)) /* Rx Unicast Frames (Good) Count Half/Full */
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#define BITM_EMAC_MMC_RXINT_R1024TOMAX (_ADI_MSK(0x00010000,uint32_t)) /* Rx 1024-to-max Octets (Good/Bad) Count Half/Full */
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#define BITM_EMAC_MMC_RXINT_R512TO1023 (_ADI_MSK(0x00008000,uint32_t)) /* Rx 512-to-1023 Octets (Good/Bad) Count Half/Full */
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#define BITM_EMAC_MMC_RXINT_R256TO511 (_ADI_MSK(0x00004000,uint32_t)) /* Rx 255-to-511 Octets (Good/Bad) Count Half/Full */
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#define BITM_EMAC_MMC_RXINT_R128TO255 (_ADI_MSK(0x00002000,uint32_t)) /* Rx 128-to-255 Octets (Good/Bad) Count Half/Full */
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#define BITM_EMAC_MMC_RXINT_R65TO127 (_ADI_MSK(0x00001000,uint32_t)) /* Rx 65-to-127 Octets (Good/Bad) Count Half/Full */
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#define BITM_EMAC_MMC_RXINT_R64 (_ADI_MSK(0x00000800,uint32_t)) /* Rx 64 Octets (Good/Bad) Count Half/Full */
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#define BITM_EMAC_MMC_RXINT_OSIZEG (_ADI_MSK(0x00000400,uint32_t)) /* Rx Oversize (Good) Count Half/Full */
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#define BITM_EMAC_MMC_RXINT_USIZEG (_ADI_MSK(0x00000200,uint32_t)) /* Rx Undersize (Good) Count Half/Full */
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#define BITM_EMAC_MMC_RXINT_JABERR (_ADI_MSK(0x00000100,uint32_t)) /* Rx Jabber Error Count Half/Full */
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#define BITM_EMAC_MMC_RXINT_RUNTERR (_ADI_MSK(0x00000080,uint32_t)) /* Rx Runt Error Count Half/Full */
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#define BITM_EMAC_MMC_RXINT_ALIGNERR (_ADI_MSK(0x00000040,uint32_t)) /* Rx Alignment Error Count Half/Full */
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#define BITM_EMAC_MMC_RXINT_CRCERR (_ADI_MSK(0x00000020,uint32_t)) /* Rx CRC Error Counter Half/Full */
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#define BITM_EMAC_MMC_RXINT_MCASTG (_ADI_MSK(0x00000010,uint32_t)) /* Rx Multicast Count (Good) Half/Full */
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#define BITM_EMAC_MMC_RXINT_BCASTG (_ADI_MSK(0x00000008,uint32_t)) /* Rx Broadcast Count (Good) Half/Full */
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#define BITM_EMAC_MMC_RXINT_OCTCNTG (_ADI_MSK(0x00000004,uint32_t)) /* Octet Count (Good) Half/Full */
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#define BITM_EMAC_MMC_RXINT_OCTCNTGB (_ADI_MSK(0x00000002,uint32_t)) /* Octet Count (Good/Bad) Half/Full */
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#define BITM_EMAC_MMC_RXINT_FRCNTGB (_ADI_MSK(0x00000001,uint32_t)) /* Frame Count (Good/Bad) Half/Full */
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/* ------------------------------------------------------------------------------------------------------------------------
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EMAC_MMC_TXINT Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_EMAC_MMC_TXINT_VLANFRGB 24 /* Tx VLAN Frames (Good) Count Half/Full */
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#define BITP_EMAC_MMC_TXINT_PAUSEFRM 23 /* Tx Pause Frames Count Half/Full */
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#define BITP_EMAC_MMC_TXINT_EXCESSDEF 22 /* Tx Excess Deferred Count Half/Full */
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#define BITP_EMAC_MMC_TXINT_FRCNTG 21 /* Tx Frame Count (Good) Count Half/Full */
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#define BITP_EMAC_MMC_TXINT_OCTCNTG 20 /* Tx Octet Count (Good) Count Half/Full */
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#define BITP_EMAC_MMC_TXINT_CARRERR 19 /* Tx Carrier Error Count Half/Full */
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#define BITP_EMAC_MMC_TXINT_EXCESSCOL 18 /* Tx Exess Collision Count Half/Full */
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#define BITP_EMAC_MMC_TXINT_LATECOL 17 /* Tx Late Collision Count Half/Full */
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#define BITP_EMAC_MMC_TXINT_DEFERRED 16 /* Tx Deffered Count Half/Full */
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#define BITP_EMAC_MMC_TXINT_MULTCOLG 15 /* Tx Multiple collision (Good) Count Half/Full */
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#define BITP_EMAC_MMC_TXINT_SNGCOLG 14 /* Tx Single Collision (Good) Count Half/Full */
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#define BITP_EMAC_MMC_TXINT_UNDERR 13 /* Tx Underflow Error Count Half/Full */
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#define BITP_EMAC_MMC_TXINT_BCASTGB 12 /* Tx Broadcast Frames (Good/Bad) Count Half/Full */
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#define BITP_EMAC_MMC_TXINT_MCASTGB 11 /* Tx Multicast Frames (Good/Bad) Count Half/Full */
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#define BITP_EMAC_MMC_TXINT_UCASTGB 10 /* Tx Unicast Frames (Good/Bad) Count Half/Full */
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#define BITP_EMAC_MMC_TXINT_T1024TOMAX 9 /* Tx 1024-to-max Octets (Good/Bad) Count Half/Full */
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#define BITP_EMAC_MMC_TXINT_T512TO1023 8 /* Tx 512-to-1023 Octets (Good/Bad) Count Half/Full */
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#define BITP_EMAC_MMC_TXINT_T256TO511 7 /* Tx 256-to-511 Octets (Good/Bad) Count Half/Full */
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#define BITP_EMAC_MMC_TXINT_T128TO255 6 /* Tx 128-to-255 Octets (Good/Bad) Count Half/Full */
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#define BITP_EMAC_MMC_TXINT_T65TO127 5 /* Tx 65-to-127 Octets (Good/Bad) Count Half/Full */
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#define BITP_EMAC_MMC_TXINT_T64 4 /* Tx 64 Octets (Good/Bad) Count Half/Full */
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#define BITP_EMAC_MMC_TXINT_MCASTG 3 /* Tx Multicast Frames (Good) Count Half/Full */
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#define BITP_EMAC_MMC_TXINT_BCASTG 2 /* Tx Broadcast Frames (Good) Count Half/Full */
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#define BITP_EMAC_MMC_TXINT_FRCNTGB 1 /* Tx Frame Count (Good/Bad) Count Half/Full */
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#define BITP_EMAC_MMC_TXINT_OCTCNTGB 0 /* Tx Octet Count (Good/Bad) Count Half/Full */
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#define BITM_EMAC_MMC_TXINT_VLANFRGB (_ADI_MSK(0x01000000,uint32_t)) /* Tx VLAN Frames (Good) Count Half/Full */
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#define BITM_EMAC_MMC_TXINT_PAUSEFRM (_ADI_MSK(0x00800000,uint32_t)) /* Tx Pause Frames Count Half/Full */
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#define BITM_EMAC_MMC_TXINT_EXCESSDEF (_ADI_MSK(0x00400000,uint32_t)) /* Tx Excess Deferred Count Half/Full */
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#define BITM_EMAC_MMC_TXINT_FRCNTG (_ADI_MSK(0x00200000,uint32_t)) /* Tx Frame Count (Good) Count Half/Full */
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#define BITM_EMAC_MMC_TXINT_OCTCNTG (_ADI_MSK(0x00100000,uint32_t)) /* Tx Octet Count (Good) Count Half/Full */
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#define BITM_EMAC_MMC_TXINT_CARRERR (_ADI_MSK(0x00080000,uint32_t)) /* Tx Carrier Error Count Half/Full */
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#define BITM_EMAC_MMC_TXINT_EXCESSCOL (_ADI_MSK(0x00040000,uint32_t)) /* Tx Exess Collision Count Half/Full */
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#define BITM_EMAC_MMC_TXINT_LATECOL (_ADI_MSK(0x00020000,uint32_t)) /* Tx Late Collision Count Half/Full */
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#define BITM_EMAC_MMC_TXINT_DEFERRED (_ADI_MSK(0x00010000,uint32_t)) /* Tx Deffered Count Half/Full */
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#define BITM_EMAC_MMC_TXINT_MULTCOLG (_ADI_MSK(0x00008000,uint32_t)) /* Tx Multiple collision (Good) Count Half/Full */
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#define BITM_EMAC_MMC_TXINT_SNGCOLG (_ADI_MSK(0x00004000,uint32_t)) /* Tx Single Collision (Good) Count Half/Full */
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#define BITM_EMAC_MMC_TXINT_UNDERR (_ADI_MSK(0x00002000,uint32_t)) /* Tx Underflow Error Count Half/Full */
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#define BITM_EMAC_MMC_TXINT_BCASTGB (_ADI_MSK(0x00001000,uint32_t)) /* Tx Broadcast Frames (Good/Bad) Count Half/Full */
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#define BITM_EMAC_MMC_TXINT_MCASTGB (_ADI_MSK(0x00000800,uint32_t)) /* Tx Multicast Frames (Good/Bad) Count Half/Full */
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#define BITM_EMAC_MMC_TXINT_UCASTGB (_ADI_MSK(0x00000400,uint32_t)) /* Tx Unicast Frames (Good/Bad) Count Half/Full */
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#define BITM_EMAC_MMC_TXINT_T1024TOMAX (_ADI_MSK(0x00000200,uint32_t)) /* Tx 1024-to-max Octets (Good/Bad) Count Half/Full */
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#define BITM_EMAC_MMC_TXINT_T512TO1023 (_ADI_MSK(0x00000100,uint32_t)) /* Tx 512-to-1023 Octets (Good/Bad) Count Half/Full */
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#define BITM_EMAC_MMC_TXINT_T256TO511 (_ADI_MSK(0x00000080,uint32_t)) /* Tx 256-to-511 Octets (Good/Bad) Count Half/Full */
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#define BITM_EMAC_MMC_TXINT_T128TO255 (_ADI_MSK(0x00000040,uint32_t)) /* Tx 128-to-255 Octets (Good/Bad) Count Half/Full */
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#define BITM_EMAC_MMC_TXINT_T65TO127 (_ADI_MSK(0x00000020,uint32_t)) /* Tx 65-to-127 Octets (Good/Bad) Count Half/Full */
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#define BITM_EMAC_MMC_TXINT_T64 (_ADI_MSK(0x00000010,uint32_t)) /* Tx 64 Octets (Good/Bad) Count Half/Full */
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#define BITM_EMAC_MMC_TXINT_MCASTG (_ADI_MSK(0x00000008,uint32_t)) /* Tx Multicast Frames (Good) Count Half/Full */
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#define BITM_EMAC_MMC_TXINT_BCASTG (_ADI_MSK(0x00000004,uint32_t)) /* Tx Broadcast Frames (Good) Count Half/Full */
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#define BITM_EMAC_MMC_TXINT_FRCNTGB (_ADI_MSK(0x00000002,uint32_t)) /* Tx Frame Count (Good/Bad) Count Half/Full */
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#define BITM_EMAC_MMC_TXINT_OCTCNTGB (_ADI_MSK(0x00000001,uint32_t)) /* Tx Octet Count (Good/Bad) Count Half/Full */
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/* ------------------------------------------------------------------------------------------------------------------------
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EMAC_MMC_RXIMSK Pos/Masks Description
|
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_EMAC_MMC_RXIMSK_WATCHERR 23 /* Rx Watch Dog Error Count Half/Full Mask */
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#define BITP_EMAC_MMC_RXIMSK_VLANFRGB 22 /* Rx VLAN Frames (Good/Bad) Count Half/Full Mask */
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#define BITP_EMAC_MMC_RXIMSK_FIFOOV 21 /* Rx FIFO Overflow Count Half/Full Mask */
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#define BITP_EMAC_MMC_RXIMSK_PAUSEFRM 20 /* Rx Pause Frames Count Half/Full Mask */
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#define BITP_EMAC_MMC_RXIMSK_OUTRANGE 19 /* Rx Out Of Range Type Count Half/Full Mask */
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#define BITP_EMAC_MMC_RXIMSK_LENERR 18 /* Rx Length Error Count Half/Full Mask */
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#define BITP_EMAC_MMC_RXIMSK_UCASTG 17 /* Rx Unicast Frames (Good) Count Half/Full Mask */
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#define BITP_EMAC_MMC_RXIMSK_R1024TOMAX 16 /* Rx 1024-to-max Octets (Good/Bad) Count Half/Full Mask */
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#define BITP_EMAC_MMC_RXIMSK_R512TO1023 15 /* Rx 512-to-1023 Octets (Good/Bad) Count Half/Full Mask */
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#define BITP_EMAC_MMC_RXIMSK_R256TO511 14 /* Rx 255-to-511 Octets (Good/Bad) Count Half/Full Mask */
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#define BITP_EMAC_MMC_RXIMSK_R128TO255 13 /* Rx 128-to-255 Octets (Good/Bad) Count Half/Full Mask */
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#define BITP_EMAC_MMC_RXIMSK_R65TO127 12 /* Rx 65-to-127 Octets (Good/Bad) Count Half/Full Mask */
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#define BITP_EMAC_MMC_RXIMSK_R64 11 /* Rx 64 Octets (Good/Bad) Count Half/Full Mask */
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#define BITP_EMAC_MMC_RXIMSK_OSIZEG 10 /* Rx Oversize (Good) Count Half/Full Mask */
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#define BITP_EMAC_MMC_RXIMSK_USIZEG 9 /* Rx Undersize (Good) Count Half/Full Mask */
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#define BITP_EMAC_MMC_RXIMSK_JABERR 8 /* Rx Jabber Error Count Half/Full Mask */
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#define BITP_EMAC_MMC_RXIMSK_RUNTERR 7 /* Rx Runt Error Count Half/Full Mask */
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#define BITP_EMAC_MMC_RXIMSK_ALIGNERR 6 /* Rx Alignment Error Count Half/Full Mask */
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#define BITP_EMAC_MMC_RXIMSK_CRCERR 5 /* Rx CRC Error Count Half/Full Mask */
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#define BITP_EMAC_MMC_RXIMSK_MCASTG 4 /* Rx Multicast Frames (Good) Count Half/Full Mask */
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#define BITP_EMAC_MMC_RXIMSK_BCASTG 3 /* Rx Broadcast Frames (Good) Count Half/Full Mask */
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#define BITP_EMAC_MMC_RXIMSK_OCTCNTG 2 /* Rx Octet Count (Good) Count Half/Full Mask */
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#define BITP_EMAC_MMC_RXIMSK_OCTCNTGB 1 /* Rx Octet Count (Good/Bad) Count Half/Full Mask */
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#define BITP_EMAC_MMC_RXIMSK_FRCNTGB 0 /* Rx Frame Count (Good/Bad) Count Half/Full Mask */
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#define BITM_EMAC_MMC_RXIMSK_WATCHERR (_ADI_MSK(0x00800000,uint32_t)) /* Rx Watch Dog Error Count Half/Full Mask */
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#define BITM_EMAC_MMC_RXIMSK_VLANFRGB (_ADI_MSK(0x00400000,uint32_t)) /* Rx VLAN Frames (Good/Bad) Count Half/Full Mask */
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#define BITM_EMAC_MMC_RXIMSK_FIFOOV (_ADI_MSK(0x00200000,uint32_t)) /* Rx FIFO Overflow Count Half/Full Mask */
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#define BITM_EMAC_MMC_RXIMSK_PAUSEFRM (_ADI_MSK(0x00100000,uint32_t)) /* Rx Pause Frames Count Half/Full Mask */
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#define BITM_EMAC_MMC_RXIMSK_OUTRANGE (_ADI_MSK(0x00080000,uint32_t)) /* Rx Out Of Range Type Count Half/Full Mask */
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#define BITM_EMAC_MMC_RXIMSK_LENERR (_ADI_MSK(0x00040000,uint32_t)) /* Rx Length Error Count Half/Full Mask */
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#define BITM_EMAC_MMC_RXIMSK_UCASTG (_ADI_MSK(0x00020000,uint32_t)) /* Rx Unicast Frames (Good) Count Half/Full Mask */
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#define BITM_EMAC_MMC_RXIMSK_R1024TOMAX (_ADI_MSK(0x00010000,uint32_t)) /* Rx 1024-to-max Octets (Good/Bad) Count Half/Full Mask */
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#define BITM_EMAC_MMC_RXIMSK_R512TO1023 (_ADI_MSK(0x00008000,uint32_t)) /* Rx 512-to-1023 Octets (Good/Bad) Count Half/Full Mask */
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#define BITM_EMAC_MMC_RXIMSK_R256TO511 (_ADI_MSK(0x00004000,uint32_t)) /* Rx 255-to-511 Octets (Good/Bad) Count Half/Full Mask */
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#define BITM_EMAC_MMC_RXIMSK_R128TO255 (_ADI_MSK(0x00002000,uint32_t)) /* Rx 128-to-255 Octets (Good/Bad) Count Half/Full Mask */
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#define BITM_EMAC_MMC_RXIMSK_R65TO127 (_ADI_MSK(0x00001000,uint32_t)) /* Rx 65-to-127 Octets (Good/Bad) Count Half/Full Mask */
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#define BITM_EMAC_MMC_RXIMSK_R64 (_ADI_MSK(0x00000800,uint32_t)) /* Rx 64 Octets (Good/Bad) Count Half/Full Mask */
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#define BITM_EMAC_MMC_RXIMSK_OSIZEG (_ADI_MSK(0x00000400,uint32_t)) /* Rx Oversize (Good) Count Half/Full Mask */
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#define BITM_EMAC_MMC_RXIMSK_USIZEG (_ADI_MSK(0x00000200,uint32_t)) /* Rx Undersize (Good) Count Half/Full Mask */
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#define BITM_EMAC_MMC_RXIMSK_JABERR (_ADI_MSK(0x00000100,uint32_t)) /* Rx Jabber Error Count Half/Full Mask */
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#define BITM_EMAC_MMC_RXIMSK_RUNTERR (_ADI_MSK(0x00000080,uint32_t)) /* Rx Runt Error Count Half/Full Mask */
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#define BITM_EMAC_MMC_RXIMSK_ALIGNERR (_ADI_MSK(0x00000040,uint32_t)) /* Rx Alignment Error Count Half/Full Mask */
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#define BITM_EMAC_MMC_RXIMSK_CRCERR (_ADI_MSK(0x00000020,uint32_t)) /* Rx CRC Error Count Half/Full Mask */
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#define BITM_EMAC_MMC_RXIMSK_MCASTG (_ADI_MSK(0x00000010,uint32_t)) /* Rx Multicast Frames (Good) Count Half/Full Mask */
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#define BITM_EMAC_MMC_RXIMSK_BCASTG (_ADI_MSK(0x00000008,uint32_t)) /* Rx Broadcast Frames (Good) Count Half/Full Mask */
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#define BITM_EMAC_MMC_RXIMSK_OCTCNTG (_ADI_MSK(0x00000004,uint32_t)) /* Rx Octet Count (Good) Count Half/Full Mask */
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#define BITM_EMAC_MMC_RXIMSK_OCTCNTGB (_ADI_MSK(0x00000002,uint32_t)) /* Rx Octet Count (Good/Bad) Count Half/Full Mask */
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#define BITM_EMAC_MMC_RXIMSK_FRCNTGB (_ADI_MSK(0x00000001,uint32_t)) /* Rx Frame Count (Good/Bad) Count Half/Full Mask */
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|
|
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
EMAC_MMC_TXIMSK Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
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#define BITP_EMAC_MMC_TXIMSK_VLANFRG 24 /* Tx VLAN Frames (Good) Count Half/Full Mask */
|
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#define BITP_EMAC_MMC_TXIMSK_PAUSEFRM 23 /* Tx Pause Frames Count Half/Full Mask */
|
|
#define BITP_EMAC_MMC_TXIMSK_EXCESSDEF 22 /* Tx Excess Deferred Count Half/Full Mask */
|
|
#define BITP_EMAC_MMC_TXIMSK_FRCNTG 21 /* Tx Frame Count (Good) Count Half/Full Mask */
|
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#define BITP_EMAC_MMC_TXIMSK_OCTCNTG 20 /* Tx Octet Count (Good) Count Half/Full Mask */
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#define BITP_EMAC_MMC_TXIMSK_CARRERR 19 /* Tx Carrier Error Count Half/Full Mask */
|
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#define BITP_EMAC_MMC_TXIMSK_EXCESSCOL 18 /* Tx Exess collision Count Half/Full Mask */
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#define BITP_EMAC_MMC_TXIMSK_LATECOL 17 /* Tx Late Collision Count Half/Full Mask */
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#define BITP_EMAC_MMC_TXIMSK_DEFERRED 16 /* Tx Deferred Count Half/Full Mask */
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#define BITP_EMAC_MMC_TXIMSK_MULTCOLG 15 /* Tx Multiple Collisions (Good) Count Mask */
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#define BITP_EMAC_MMC_TXIMSK_SNGCOLG 14 /* Tx Single Collision (Good) Count Half/Full Mask */
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#define BITP_EMAC_MMC_TXIMSK_UNDERR 13 /* Tx Underflow Error Count Half/Full Mask */
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#define BITP_EMAC_MMC_TXIMSK_BCASTGB 12 /* Tx Broadcast Frames (Good/Bad) Count Half/Full Mask */
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#define BITP_EMAC_MMC_TXIMSK_MCASTGB 11 /* Tx Multicast Frames (Good/Bad) Count Half/Full Mask */
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#define BITP_EMAC_MMC_TXIMSK_UCASTGB 10 /* Tx Unicast Frames (Good/Bad) Count Half/Full Mask */
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#define BITP_EMAC_MMC_TXIMSK_T1024TOMAX 9 /* Tx 1024-to-max Octets (Good/Bad) Count Half/Full Mask */
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#define BITP_EMAC_MMC_TXIMSK_T512TO1023 8 /* Tx 512-to-1023 Octets (Good/Bad) Count Half/Full Mask */
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#define BITP_EMAC_MMC_TXIMSK_T256TO511 7 /* Tx 256-to-511 Octets (Good/Bad) Count Half/Full Mask */
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#define BITP_EMAC_MMC_TXIMSK_T128TO255 6 /* Tx 128-to-255 Octets (Good/Bad) Count Half/Full Mask */
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#define BITP_EMAC_MMC_TXIMSK_T65TO127 5 /* Tx 65-to-127 Octets (Good/Bad) Count Half/Full Mask */
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#define BITP_EMAC_MMC_TXIMSK_T64 4 /* Tx 64 Octets (Good/Bad) Count Half/Full Mask */
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#define BITP_EMAC_MMC_TXIMSK_MCASTG 3 /* Tx Multicast Frames (Good) Count Half/Full Mask */
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#define BITP_EMAC_MMC_TXIMSK_BCASTG 2 /* Tx Broadcast Frames (Good) Count Half/Full Mask */
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#define BITP_EMAC_MMC_TXIMSK_FRCNTGB 1 /* Tx Frame Count (Good/Bad) Count Half/Full Mask */
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#define BITP_EMAC_MMC_TXIMSK_OCTCNTGB 0 /* Tx Octet Count (Good/Bad) Count Half/Full Mask */
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#define BITM_EMAC_MMC_TXIMSK_VLANFRG (_ADI_MSK(0x01000000,uint32_t)) /* Tx VLAN Frames (Good) Count Half/Full Mask */
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#define BITM_EMAC_MMC_TXIMSK_PAUSEFRM (_ADI_MSK(0x00800000,uint32_t)) /* Tx Pause Frames Count Half/Full Mask */
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#define BITM_EMAC_MMC_TXIMSK_EXCESSDEF (_ADI_MSK(0x00400000,uint32_t)) /* Tx Excess Deferred Count Half/Full Mask */
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#define BITM_EMAC_MMC_TXIMSK_FRCNTG (_ADI_MSK(0x00200000,uint32_t)) /* Tx Frame Count (Good) Count Half/Full Mask */
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#define BITM_EMAC_MMC_TXIMSK_OCTCNTG (_ADI_MSK(0x00100000,uint32_t)) /* Tx Octet Count (Good) Count Half/Full Mask */
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#define BITM_EMAC_MMC_TXIMSK_CARRERR (_ADI_MSK(0x00080000,uint32_t)) /* Tx Carrier Error Count Half/Full Mask */
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#define BITM_EMAC_MMC_TXIMSK_EXCESSCOL (_ADI_MSK(0x00040000,uint32_t)) /* Tx Exess collision Count Half/Full Mask */
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#define BITM_EMAC_MMC_TXIMSK_LATECOL (_ADI_MSK(0x00020000,uint32_t)) /* Tx Late Collision Count Half/Full Mask */
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#define BITM_EMAC_MMC_TXIMSK_DEFERRED (_ADI_MSK(0x00010000,uint32_t)) /* Tx Deferred Count Half/Full Mask */
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#define BITM_EMAC_MMC_TXIMSK_MULTCOLG (_ADI_MSK(0x00008000,uint32_t)) /* Tx Multiple Collisions (Good) Count Mask */
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#define BITM_EMAC_MMC_TXIMSK_SNGCOLG (_ADI_MSK(0x00004000,uint32_t)) /* Tx Single Collision (Good) Count Half/Full Mask */
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#define BITM_EMAC_MMC_TXIMSK_UNDERR (_ADI_MSK(0x00002000,uint32_t)) /* Tx Underflow Error Count Half/Full Mask */
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#define BITM_EMAC_MMC_TXIMSK_BCASTGB (_ADI_MSK(0x00001000,uint32_t)) /* Tx Broadcast Frames (Good/Bad) Count Half/Full Mask */
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#define BITM_EMAC_MMC_TXIMSK_MCASTGB (_ADI_MSK(0x00000800,uint32_t)) /* Tx Multicast Frames (Good/Bad) Count Half/Full Mask */
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#define BITM_EMAC_MMC_TXIMSK_UCASTGB (_ADI_MSK(0x00000400,uint32_t)) /* Tx Unicast Frames (Good/Bad) Count Half/Full Mask */
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#define BITM_EMAC_MMC_TXIMSK_T1024TOMAX (_ADI_MSK(0x00000200,uint32_t)) /* Tx 1024-to-max Octets (Good/Bad) Count Half/Full Mask */
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#define BITM_EMAC_MMC_TXIMSK_T512TO1023 (_ADI_MSK(0x00000100,uint32_t)) /* Tx 512-to-1023 Octets (Good/Bad) Count Half/Full Mask */
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#define BITM_EMAC_MMC_TXIMSK_T256TO511 (_ADI_MSK(0x00000080,uint32_t)) /* Tx 256-to-511 Octets (Good/Bad) Count Half/Full Mask */
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#define BITM_EMAC_MMC_TXIMSK_T128TO255 (_ADI_MSK(0x00000040,uint32_t)) /* Tx 128-to-255 Octets (Good/Bad) Count Half/Full Mask */
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#define BITM_EMAC_MMC_TXIMSK_T65TO127 (_ADI_MSK(0x00000020,uint32_t)) /* Tx 65-to-127 Octets (Good/Bad) Count Half/Full Mask */
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#define BITM_EMAC_MMC_TXIMSK_T64 (_ADI_MSK(0x00000010,uint32_t)) /* Tx 64 Octets (Good/Bad) Count Half/Full Mask */
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#define BITM_EMAC_MMC_TXIMSK_MCASTG (_ADI_MSK(0x00000008,uint32_t)) /* Tx Multicast Frames (Good) Count Half/Full Mask */
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#define BITM_EMAC_MMC_TXIMSK_BCASTG (_ADI_MSK(0x00000004,uint32_t)) /* Tx Broadcast Frames (Good) Count Half/Full Mask */
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#define BITM_EMAC_MMC_TXIMSK_FRCNTGB (_ADI_MSK(0x00000002,uint32_t)) /* Tx Frame Count (Good/Bad) Count Half/Full Mask */
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#define BITM_EMAC_MMC_TXIMSK_OCTCNTGB (_ADI_MSK(0x00000001,uint32_t)) /* Tx Octet Count (Good/Bad) Count Half/Full Mask */
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/* ------------------------------------------------------------------------------------------------------------------------
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EMAC_IPC_RXIMSK Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_EMAC_IPC_RXIMSK_ICMPERROCT 29 /* Rx ICMP Error Octets Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_ICMPGOCT 28 /* Rx ICMP (Good) Octets Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_TCPERROCT 27 /* Rx TCP Error Octets Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_TCPGOCT 26 /* Rx TCP (Good) Octets Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_UDPERROCT 25 /* Rx UDP Error Octets Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_UDPGOCT 24 /* Rx UDP (Good) Octets Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_V6NOPAYOCT 23 /* Rx IPv6 No Payload Octets Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_V6HDERROCT 22 /* Rx IPv6 Header Error Octets Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_V6GOCT 21 /* Rx IPv6 (Good) Octets Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_V4UDSBLOCT 20 /* Rx IPv4 UDS Disable Octets Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_V4FRAGOCT 19 /* Rx IPv4 Fragmented Octets Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_V4NOPAYOCT 18 /* Rx IPv4 No Payload Octets Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_V4HDERROCT 17 /* Rx IPv4 Header Error Octets Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_V4GOCT 16 /* Rx IPv4 (Good) Octets Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_ICMPERRFRM 13 /* Rx ICMP Error Frames Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_ICMPGFRM 12 /* Rx ICMP (Good) Frames Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_TCPERRFRM 11 /* Rx TCP Error Frames Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_TCPGFRM 10 /* Rx TCP (Good) Frames Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_UDPERRFRM 9 /* Rx UDP Error Frames Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_UDPGFRM 8 /* Rx UDP (Good) Frames Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_V6NOPAYFRM 7 /* Rx IPv6 No Payload Frames Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_V6HDERRFRM 6 /* Rx IPv6 Header Error Frames Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_V6GFRM 5 /* Rx IPv6 (Good) Frames Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_V4UDSBLFRM 4 /* Rx IPv4 UDS Disable Frames Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_V4FRAGFRM 3 /* Rx IPv4 Fragmented Frames Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_V4NOPAYFRM 2 /* Rx IPv4 No Payload Frame Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_V4HDERRFRM 1 /* Rx IPv4 Header Error Frame Count Half/Full Mask */
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#define BITP_EMAC_IPC_RXIMSK_V4GFRM 0 /* Rx IPv4 (Good) Frames Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_ICMPERROCT (_ADI_MSK(0x20000000,uint32_t)) /* Rx ICMP Error Octets Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_ICMPGOCT (_ADI_MSK(0x10000000,uint32_t)) /* Rx ICMP (Good) Octets Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_TCPERROCT (_ADI_MSK(0x08000000,uint32_t)) /* Rx TCP Error Octets Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_TCPGOCT (_ADI_MSK(0x04000000,uint32_t)) /* Rx TCP (Good) Octets Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_UDPERROCT (_ADI_MSK(0x02000000,uint32_t)) /* Rx UDP Error Octets Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_UDPGOCT (_ADI_MSK(0x01000000,uint32_t)) /* Rx UDP (Good) Octets Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_V6NOPAYOCT (_ADI_MSK(0x00800000,uint32_t)) /* Rx IPv6 No Payload Octets Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_V6HDERROCT (_ADI_MSK(0x00400000,uint32_t)) /* Rx IPv6 Header Error Octets Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_V6GOCT (_ADI_MSK(0x00200000,uint32_t)) /* Rx IPv6 (Good) Octets Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_V4UDSBLOCT (_ADI_MSK(0x00100000,uint32_t)) /* Rx IPv4 UDS Disable Octets Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_V4FRAGOCT (_ADI_MSK(0x00080000,uint32_t)) /* Rx IPv4 Fragmented Octets Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_V4NOPAYOCT (_ADI_MSK(0x00040000,uint32_t)) /* Rx IPv4 No Payload Octets Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_V4HDERROCT (_ADI_MSK(0x00020000,uint32_t)) /* Rx IPv4 Header Error Octets Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_V4GOCT (_ADI_MSK(0x00010000,uint32_t)) /* Rx IPv4 (Good) Octets Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_ICMPERRFRM (_ADI_MSK(0x00002000,uint32_t)) /* Rx ICMP Error Frames Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_ICMPGFRM (_ADI_MSK(0x00001000,uint32_t)) /* Rx ICMP (Good) Frames Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_TCPERRFRM (_ADI_MSK(0x00000800,uint32_t)) /* Rx TCP Error Frames Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_TCPGFRM (_ADI_MSK(0x00000400,uint32_t)) /* Rx TCP (Good) Frames Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_UDPERRFRM (_ADI_MSK(0x00000200,uint32_t)) /* Rx UDP Error Frames Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_UDPGFRM (_ADI_MSK(0x00000100,uint32_t)) /* Rx UDP (Good) Frames Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_V6NOPAYFRM (_ADI_MSK(0x00000080,uint32_t)) /* Rx IPv6 No Payload Frames Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_V6HDERRFRM (_ADI_MSK(0x00000040,uint32_t)) /* Rx IPv6 Header Error Frames Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_V6GFRM (_ADI_MSK(0x00000020,uint32_t)) /* Rx IPv6 (Good) Frames Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_V4UDSBLFRM (_ADI_MSK(0x00000010,uint32_t)) /* Rx IPv4 UDS Disable Frames Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_V4FRAGFRM (_ADI_MSK(0x00000008,uint32_t)) /* Rx IPv4 Fragmented Frames Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_V4NOPAYFRM (_ADI_MSK(0x00000004,uint32_t)) /* Rx IPv4 No Payload Frame Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_V4HDERRFRM (_ADI_MSK(0x00000002,uint32_t)) /* Rx IPv4 Header Error Frame Count Half/Full Mask */
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#define BITM_EMAC_IPC_RXIMSK_V4GFRM (_ADI_MSK(0x00000001,uint32_t)) /* Rx IPv4 (Good) Frames Count Half/Full Mask */
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/* ------------------------------------------------------------------------------------------------------------------------
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EMAC_IPC_RXINT Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_EMAC_IPC_RXINT_ICMPERROCT 29 /* Rx ICMP Error Octets Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_ICMPGOCT 28 /* Rx ICMP (Good) Octets Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_TCPERROCT 27 /* Rx TCP Error Octets Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_TCPGOCT 26 /* Rx TCP (Good) Octets Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_UDPERROCT 25 /* Rx UDP Error Octets Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_UDPGOCT 24 /* Rx UDP (Good) Octets Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_V6NOPAYOCT 23 /* Rx IPv6 No Payload Octets Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_V6HDERROCT 22 /* Rx IPv6 Header Error Octets Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_V6GOCT 21 /* Rx IPv6 (Good) Octets Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_V4UDSBLOCT 20 /* Rx IPv4 UDS Disable Octets Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_V4FRAGOCT 19 /* Rx IPv4 Fragmented Octets Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_V4NOPAYOCT 18 /* Rx IPv4 No Payload Octets Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_V4HDERROCT 17 /* Rx IPv4 Header Error Octets Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_V4GOCT 16 /* Rx IPv4 (Good) Octets Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_ICMPERRFRM 13 /* Rx ICMP Error Frames Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_ICMPGFRM 12 /* Rx ICMP (Good) Frames Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_TCPERRFRM 11 /* Rx TCP Error Frames Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_TCPGFRM 10 /* Rx TCP (Good) Frames Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_UDPERRFRM 9 /* Rx IDP Error Frames Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_UDPGFRM 8 /* Rx UDP (Good) Frames Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_V6NOPAYFRM 7 /* Rx IPv6 No Payload Frames Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_V6HDERRFRM 6 /* Rx IPv6 Header Error Frames Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_V6GFRM 5 /* Rx IPv6 (Good) Frames Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_V4UDSBLFRM 4 /* Rx IPv4 UDS Disable Frames Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_V4FRAGFRM 3 /* Rx IPv4 Fragmented Frames Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_V4NOPAYFRM 2 /* Rx IPv4 No Payload Frames Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_V4HDERRFRM 1 /* Rx IPv4 Header Error Frames Count Half/Full Interrupt */
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#define BITP_EMAC_IPC_RXINT_V4GFRM 0 /* Rx IPv4 (Good) Frames Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_ICMPERROCT (_ADI_MSK(0x20000000,uint32_t)) /* Rx ICMP Error Octets Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_ICMPGOCT (_ADI_MSK(0x10000000,uint32_t)) /* Rx ICMP (Good) Octets Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_TCPERROCT (_ADI_MSK(0x08000000,uint32_t)) /* Rx TCP Error Octets Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_TCPGOCT (_ADI_MSK(0x04000000,uint32_t)) /* Rx TCP (Good) Octets Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_UDPERROCT (_ADI_MSK(0x02000000,uint32_t)) /* Rx UDP Error Octets Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_UDPGOCT (_ADI_MSK(0x01000000,uint32_t)) /* Rx UDP (Good) Octets Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_V6NOPAYOCT (_ADI_MSK(0x00800000,uint32_t)) /* Rx IPv6 No Payload Octets Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_V6HDERROCT (_ADI_MSK(0x00400000,uint32_t)) /* Rx IPv6 Header Error Octets Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_V6GOCT (_ADI_MSK(0x00200000,uint32_t)) /* Rx IPv6 (Good) Octets Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_V4UDSBLOCT (_ADI_MSK(0x00100000,uint32_t)) /* Rx IPv4 UDS Disable Octets Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_V4FRAGOCT (_ADI_MSK(0x00080000,uint32_t)) /* Rx IPv4 Fragmented Octets Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_V4NOPAYOCT (_ADI_MSK(0x00040000,uint32_t)) /* Rx IPv4 No Payload Octets Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_V4HDERROCT (_ADI_MSK(0x00020000,uint32_t)) /* Rx IPv4 Header Error Octets Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_V4GOCT (_ADI_MSK(0x00010000,uint32_t)) /* Rx IPv4 (Good) Octets Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_ICMPERRFRM (_ADI_MSK(0x00002000,uint32_t)) /* Rx ICMP Error Frames Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_ICMPGFRM (_ADI_MSK(0x00001000,uint32_t)) /* Rx ICMP (Good) Frames Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_TCPERRFRM (_ADI_MSK(0x00000800,uint32_t)) /* Rx TCP Error Frames Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_TCPGFRM (_ADI_MSK(0x00000400,uint32_t)) /* Rx TCP (Good) Frames Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_UDPERRFRM (_ADI_MSK(0x00000200,uint32_t)) /* Rx IDP Error Frames Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_UDPGFRM (_ADI_MSK(0x00000100,uint32_t)) /* Rx UDP (Good) Frames Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_V6NOPAYFRM (_ADI_MSK(0x00000080,uint32_t)) /* Rx IPv6 No Payload Frames Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_V6HDERRFRM (_ADI_MSK(0x00000040,uint32_t)) /* Rx IPv6 Header Error Frames Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_V6GFRM (_ADI_MSK(0x00000020,uint32_t)) /* Rx IPv6 (Good) Frames Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_V4UDSBLFRM (_ADI_MSK(0x00000010,uint32_t)) /* Rx IPv4 UDS Disable Frames Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_V4FRAGFRM (_ADI_MSK(0x00000008,uint32_t)) /* Rx IPv4 Fragmented Frames Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_V4NOPAYFRM (_ADI_MSK(0x00000004,uint32_t)) /* Rx IPv4 No Payload Frames Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_V4HDERRFRM (_ADI_MSK(0x00000002,uint32_t)) /* Rx IPv4 Header Error Frames Count Half/Full Interrupt */
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#define BITM_EMAC_IPC_RXINT_V4GFRM (_ADI_MSK(0x00000001,uint32_t)) /* Rx IPv4 (Good) Frames Count Half/Full Interrupt */
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/* ------------------------------------------------------------------------------------------------------------------------
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EMAC_TM_CTL Pos/Masks Description
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|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_EMAC_TM_CTL_ATSFC 24 /* Auxilary Time Stamp FIFO Clear */
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#define BITP_EMAC_TM_CTL_TSENMACADDR 18 /* Time Stamp Enable MAC Address */
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#define BITP_EMAC_TM_CTL_SNAPTYPSEL 16 /* Snapshot Type Select */
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#define BITP_EMAC_TM_CTL_TSMSTRENA 15 /* Time Stamp Master (Frames) Enable */
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#define BITP_EMAC_TM_CTL_TSEVNTENA 14 /* Time Stamp Event (PTP Frames) Enable */
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#define BITP_EMAC_TM_CTL_TSIPV4ENA 13 /* Time Stamp IPV4 (PTP Frames) Enable */
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#define BITP_EMAC_TM_CTL_TSIPV6ENA 12 /* Time Stamp IPV6 (PTP Frames) Enable */
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#define BITP_EMAC_TM_CTL_TSIPENA 11 /* Time Stamp IP Enable */
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#define BITP_EMAC_TM_CTL_TSVER2ENA 10 /* Time Stamp VER2 (Snooping) Enable */
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#define BITP_EMAC_TM_CTL_TSCTRLSSR 9 /* Time Stamp Control Nanosecond Rollover */
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#define BITP_EMAC_TM_CTL_TSENALL 8 /* Time Stamp Enable All (Frames) */
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#define BITP_EMAC_TM_CTL_TSADDREG 5 /* Time Stamp Addend Register Update */
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#define BITP_EMAC_TM_CTL_TSTRIG 4 /* Time Stamp (Target Time) Trigger Enable */
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#define BITP_EMAC_TM_CTL_TSUPDT 3 /* Time Stamp (System Time) Update */
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#define BITP_EMAC_TM_CTL_TSINIT 2 /* Time Stamp (System Time) Initialize */
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#define BITP_EMAC_TM_CTL_TSCFUPDT 1 /* Time Stamp (System Time) Fine/Coarse Update */
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#define BITP_EMAC_TM_CTL_TSENA 0 /* Time Stamp (PTP) Enable */
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#define BITM_EMAC_TM_CTL_ATSFC (_ADI_MSK(0x01000000,uint32_t)) /* Auxilary Time Stamp FIFO Clear */
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#define BITM_EMAC_TM_CTL_TSENMACADDR (_ADI_MSK(0x00040000,uint32_t)) /* Time Stamp Enable MAC Address */
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#define ENUM_EMAC_TM_CTL_D_PTP_ADDRFILT (_ADI_MSK(0x00000000,uint32_t)) /* TSENMACADDR: Disable PTP MAC address filter */
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#define ENUM_EMAC_TM_CTL_E_PTP_ADDRFILT (_ADI_MSK(0x00040000,uint32_t)) /* TSENMACADDR: Enable PTP MAC address filter */
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#define BITM_EMAC_TM_CTL_SNAPTYPSEL (_ADI_MSK(0x00030000,uint32_t)) /* Snapshot Type Select */
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#define BITM_EMAC_TM_CTL_TSMSTRENA (_ADI_MSK(0x00008000,uint32_t)) /* Time Stamp Master (Frames) Enable */
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#define ENUM_EMAC_TM_CTL_E_SLVSNPT_MSGS (_ADI_MSK(0x00000000,uint32_t)) /* TSMSTRENA: Enable Snapshot for Slave Messages */
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#define ENUM_EMAC_TM_CTL_E_MSSNPST_MSGS (_ADI_MSK(0x00008000,uint32_t)) /* TSMSTRENA: Enable Snapshot for Master Messages */
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#define BITM_EMAC_TM_CTL_TSEVNTENA (_ADI_MSK(0x00004000,uint32_t)) /* Time Stamp Event (PTP Frames) Enable */
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#define ENUM_EMAC_TM_CTL_E_ATSTMP_MSGS (_ADI_MSK(0x00000000,uint32_t)) /* TSEVNTENA: Enable Time Stamp for All Messages */
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#define ENUM_EMAC_TM_CTL_E_ETSTMP_MSGS (_ADI_MSK(0x00004000,uint32_t)) /* TSEVNTENA: Enable Time Stamp for Event Messages Only */
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#define BITM_EMAC_TM_CTL_TSIPV4ENA (_ADI_MSK(0x00002000,uint32_t)) /* Time Stamp IPV4 (PTP Frames) Enable */
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#define ENUM_EMAC_TM_CTL_D_TSTMP_IPV4 (_ADI_MSK(0x00000000,uint32_t)) /* TSIPV4ENA: Disable Time Stamp for PTP Over IPv4 Frames */
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#define ENUM_EMAC_TM_CTL_E_TSTMP_IPV4 (_ADI_MSK(0x00002000,uint32_t)) /* TSIPV4ENA: Enable Time Stamp for PTP Over IPv4 Frames */
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#define BITM_EMAC_TM_CTL_TSIPV6ENA (_ADI_MSK(0x00001000,uint32_t)) /* Time Stamp IPV6 (PTP Frames) Enable */
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#define ENUM_EMAC_TM_CTL_D_TSTMP_IPV6 (_ADI_MSK(0x00000000,uint32_t)) /* TSIPV6ENA: Disable Time Stamp for PTP Over IPv6 frames */
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#define ENUM_EMAC_TM_CTL_E_TSTMP_IPV6 (_ADI_MSK(0x00001000,uint32_t)) /* TSIPV6ENA: Enable Time Stamp for PTP Over IPv6 Frames */
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#define BITM_EMAC_TM_CTL_TSIPENA (_ADI_MSK(0x00000800,uint32_t)) /* Time Stamp IP Enable */
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#define ENUM_EMAC_TM_CTL_D_PTP_OV_ETHER (_ADI_MSK(0x00000000,uint32_t)) /* TSIPENA: Disable PTP Over Ethernet Frames */
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#define ENUM_EMAC_TM_CTL_E_PTP_OV_ETHER (_ADI_MSK(0x00000800,uint32_t)) /* TSIPENA: Enable PTP Over Ethernet Frames */
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#define BITM_EMAC_TM_CTL_TSVER2ENA (_ADI_MSK(0x00000400,uint32_t)) /* Time Stamp VER2 (Snooping) Enable */
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#define ENUM_EMAC_TM_CTL_D_PKT_SNOOP_V2 (_ADI_MSK(0x00000000,uint32_t)) /* TSVER2ENA: Disable packet snooping for V2 frames */
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#define ENUM_EMAC_TM_CTL_E_PKT_SNOOP_V2 (_ADI_MSK(0x00000400,uint32_t)) /* TSVER2ENA: Enable packet snooping for V2 frames */
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#define BITM_EMAC_TM_CTL_TSCTRLSSR (_ADI_MSK(0x00000200,uint32_t)) /* Time Stamp Control Nanosecond Rollover */
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#define ENUM_EMAC_TM_CTL_RO_SUBSEC_RES (_ADI_MSK(0x00000000,uint32_t)) /* TSCTRLSSR: Roll Over Nanosecond After 0x7FFFFFFF */
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#define ENUM_EMAC_TM_CTL_RO_NANO_RES (_ADI_MSK(0x00000200,uint32_t)) /* TSCTRLSSR: Roll Over Nanosecond After 0x3B9AC9FF */
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#define BITM_EMAC_TM_CTL_TSENALL (_ADI_MSK(0x00000100,uint32_t)) /* Time Stamp Enable All (Frames) */
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#define ENUM_EMAC_TM_CTL_D_TSALL_FRAMES (_ADI_MSK(0x00000000,uint32_t)) /* TSENALL: Disable timestamp for all frames */
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#define ENUM_EMAC_TM_CTL_E_TSALL_FRAMES (_ADI_MSK(0x00000100,uint32_t)) /* TSENALL: Enable timestamp for all frames */
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#define BITM_EMAC_TM_CTL_TSADDREG (_ADI_MSK(0x00000020,uint32_t)) /* Time Stamp Addend Register Update */
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#define BITM_EMAC_TM_CTL_TSTRIG (_ADI_MSK(0x00000010,uint32_t)) /* Time Stamp (Target Time) Trigger Enable */
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#define ENUM_EMAC_TM_CTL_EN_TRIGGER (_ADI_MSK(0x00000010,uint32_t)) /* TSTRIG: Interrupt (TS) if system time is greater than target time register */
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#define BITM_EMAC_TM_CTL_TSUPDT (_ADI_MSK(0x00000008,uint32_t)) /* Time Stamp (System Time) Update */
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#define ENUM_EMAC_TM_CTL_EN_UPDATE (_ADI_MSK(0x00000008,uint32_t)) /* TSUPDT: System time updated with Time stamp register values */
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#define BITM_EMAC_TM_CTL_TSINIT (_ADI_MSK(0x00000004,uint32_t)) /* Time Stamp (System Time) Initialize */
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#define ENUM_EMAC_TM_CTL_EN_TS_INIT (_ADI_MSK(0x00000004,uint32_t)) /* TSINIT: System time initialized with Time stamp register values */
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#define BITM_EMAC_TM_CTL_TSCFUPDT (_ADI_MSK(0x00000002,uint32_t)) /* Time Stamp (System Time) Fine/Coarse Update */
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#define ENUM_EMAC_TM_CTL_EN_COARSE_UPDT (_ADI_MSK(0x00000000,uint32_t)) /* TSCFUPDT: Use Coarse Correction Method for System Time Update */
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#define ENUM_EMAC_TM_CTL_EN_FINE_UPDT (_ADI_MSK(0x00000002,uint32_t)) /* TSCFUPDT: Use Fine Correction Method for System Time Update */
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#define BITM_EMAC_TM_CTL_TSENA (_ADI_MSK(0x00000001,uint32_t)) /* Time Stamp (PTP) Enable */
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#define ENUM_EMAC_TM_CTL_DTS (_ADI_MSK(0x00000000,uint32_t)) /* TSENA: Disable PTP Module */
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#define ENUM_EMAC_TM_CTL_TS (_ADI_MSK(0x00000001,uint32_t)) /* TSENA: Enable PTP Module */
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/* ------------------------------------------------------------------------------------------------------------------------
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EMAC_TM_SUBSEC Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_EMAC_TM_SUBSEC_SSINC 0 /* Sub-Second Increment Value */
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#define BITM_EMAC_TM_SUBSEC_SSINC (_ADI_MSK(0x000000FF,uint32_t)) /* Sub-Second Increment Value */
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/* ------------------------------------------------------------------------------------------------------------------------
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EMAC_TM_NSEC Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_EMAC_TM_NSEC_TSSS 0 /* Time Stamp Nanoseconds */
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#define BITM_EMAC_TM_NSEC_TSSS (_ADI_MSK(0x7FFFFFFF,uint32_t)) /* Time Stamp Nanoseconds */
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/* ------------------------------------------------------------------------------------------------------------------------
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EMAC_TM_NSECUPDT Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_EMAC_TM_NSECUPDT_ADDSUB 31 /* Add or Subtract the Time */
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#define BITP_EMAC_TM_NSECUPDT_TSSS 0 /* Time Stamp Sub Second Initialize/Increment */
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#define BITM_EMAC_TM_NSECUPDT_ADDSUB (_ADI_MSK(0x80000000,uint32_t)) /* Add or Subtract the Time */
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#define BITM_EMAC_TM_NSECUPDT_TSSS (_ADI_MSK(0x7FFFFFFF,uint32_t)) /* Time Stamp Sub Second Initialize/Increment */
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/* ------------------------------------------------------------------------------------------------------------------------
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EMAC_TM_NTGTM Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_EMAC_TM_NTGTM_TSTRBUSY 31 /* Target Time Register Busy */
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#define BITP_EMAC_TM_NTGTM_TSTR 0 /* Target Time Nano Seconds */
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#define BITM_EMAC_TM_NTGTM_TSTRBUSY (_ADI_MSK(0x80000000,uint32_t)) /* Target Time Register Busy */
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#define BITM_EMAC_TM_NTGTM_TSTR (_ADI_MSK(0x7FFFFFFF,uint32_t)) /* Target Time Nano Seconds */
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/* ------------------------------------------------------------------------------------------------------------------------
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EMAC_TM_HISEC Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_EMAC_TM_HISEC_TSHWR 0 /* Time Stamp Higher Word Seconds Register */
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#define BITM_EMAC_TM_HISEC_TSHWR (_ADI_MSK(0x0000FFFF,uint32_t)) /* Time Stamp Higher Word Seconds Register */
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/* ------------------------------------------------------------------------------------------------------------------------
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EMAC_TM_STMPSTAT Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_EMAC_TM_STMPSTAT_ATSNS 25 /* Auxilary Time Stamp Number of Snapshots */
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#define BITP_EMAC_TM_STMPSTAT_ATSSTM 24 /* Auxilary Time Stamp Snapshot Trigger Missed */
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#define BITP_EMAC_TM_STMPSTAT_TSTRGTERR 3 /* Time Stamp Target Time Programming Error */
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#define BITP_EMAC_TM_STMPSTAT_ATSTS 2 /* Auxilary Time Stamp Trigger Snapshot */
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#define BITP_EMAC_TM_STMPSTAT_TSTARGT 1 /* Time Stamp Target Time Reached */
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#define BITP_EMAC_TM_STMPSTAT_TSSOVF 0 /* Time Stamp Seconds Overflow */
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#define BITM_EMAC_TM_STMPSTAT_ATSNS (_ADI_MSK(0x0E000000,uint32_t)) /* Auxilary Time Stamp Number of Snapshots */
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#define BITM_EMAC_TM_STMPSTAT_ATSSTM (_ADI_MSK(0x01000000,uint32_t)) /* Auxilary Time Stamp Snapshot Trigger Missed */
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#define BITM_EMAC_TM_STMPSTAT_TSTRGTERR (_ADI_MSK(0x00000008,uint32_t)) /* Time Stamp Target Time Programming Error */
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#define BITM_EMAC_TM_STMPSTAT_ATSTS (_ADI_MSK(0x00000004,uint32_t)) /* Auxilary Time Stamp Trigger Snapshot */
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#define BITM_EMAC_TM_STMPSTAT_TSTARGT (_ADI_MSK(0x00000002,uint32_t)) /* Time Stamp Target Time Reached */
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#define BITM_EMAC_TM_STMPSTAT_TSSOVF (_ADI_MSK(0x00000001,uint32_t)) /* Time Stamp Seconds Overflow */
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/* ------------------------------------------------------------------------------------------------------------------------
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EMAC_TM_PPSCTL Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_EMAC_TM_PPSCTL_TRGTMODSEL 5 /* Target Time Register Mode */
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#define BITP_EMAC_TM_PPSCTL_PPSEN 4 /* Enable the flexible PPS output mode */
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#define BITP_EMAC_TM_PPSCTL_PPSCTL 0 /* PPS Frequency Control */
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#define BITM_EMAC_TM_PPSCTL_TRGTMODSEL (_ADI_MSK(0x00000060,uint32_t)) /* Target Time Register Mode */
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#define BITM_EMAC_TM_PPSCTL_PPSEN (_ADI_MSK(0x00000010,uint32_t)) /* Enable the flexible PPS output mode */
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#define BITM_EMAC_TM_PPSCTL_PPSCTL (_ADI_MSK(0x0000000F,uint32_t)) /* PPS Frequency Control */
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/* ------------------------------------------------------------------------------------------------------------------------
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EMAC_DMA_BUSMODE Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_EMAC_DMA_BUSMODE_AAL 25 /* Address Aligned Bursts */
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#define BITP_EMAC_DMA_BUSMODE_PBL8 24 /* PBL * 8 */
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#define BITP_EMAC_DMA_BUSMODE_USP 23 /* Use Separate PBL */
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#define BITP_EMAC_DMA_BUSMODE_RPBL 17 /* Receive Programmable Burst Length */
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#define BITP_EMAC_DMA_BUSMODE_FB 16 /* Fixed Burst */
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#define BITP_EMAC_DMA_BUSMODE_PBL 8 /* Programmable Burst Length */
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#define BITP_EMAC_DMA_BUSMODE_ATDS 7 /* Alternate Descriptor Size */
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#define BITP_EMAC_DMA_BUSMODE_DSL 2 /* Descriptor Skip Length */
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#define BITP_EMAC_DMA_BUSMODE_SWR 0 /* Software Reset */
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#define BITM_EMAC_DMA_BUSMODE_AAL (_ADI_MSK(0x02000000,uint32_t)) /* Address Aligned Bursts */
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#define BITM_EMAC_DMA_BUSMODE_PBL8 (_ADI_MSK(0x01000000,uint32_t)) /* PBL * 8 */
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#define BITM_EMAC_DMA_BUSMODE_USP (_ADI_MSK(0x00800000,uint32_t)) /* Use Separate PBL */
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#define BITM_EMAC_DMA_BUSMODE_RPBL (_ADI_MSK(0x007E0000,uint32_t)) /* Receive Programmable Burst Length */
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#define BITM_EMAC_DMA_BUSMODE_FB (_ADI_MSK(0x00010000,uint32_t)) /* Fixed Burst */
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#define BITM_EMAC_DMA_BUSMODE_PBL (_ADI_MSK(0x00003F00,uint32_t)) /* Programmable Burst Length */
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#define BITM_EMAC_DMA_BUSMODE_ATDS (_ADI_MSK(0x00000080,uint32_t)) /* Alternate Descriptor Size */
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#define BITM_EMAC_DMA_BUSMODE_DSL (_ADI_MSK(0x0000007C,uint32_t)) /* Descriptor Skip Length */
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#define BITM_EMAC_DMA_BUSMODE_SWR (_ADI_MSK(0x00000001,uint32_t)) /* Software Reset */
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/* ------------------------------------------------------------------------------------------------------------------------
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EMAC_DMA_STAT Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_EMAC_DMA_STAT_TTI 29 /* Time Stamp Trigger Interrupt */
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#define BITP_EMAC_DMA_STAT_MCI 27 /* MAC MMC Interrupt */
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#define BITP_EMAC_DMA_STAT_EB 23 /* Error Bits */
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#define BITP_EMAC_DMA_STAT_TS 20 /* Transmit Process State */
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#define BITP_EMAC_DMA_STAT_RS 17 /* Receive Process State */
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#define BITP_EMAC_DMA_STAT_NIS 16 /* Normal Interrupt Summary */
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#define BITP_EMAC_DMA_STAT_AIS 15 /* Abnormal Interrupt Summary */
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#define BITP_EMAC_DMA_STAT_ERI 14 /* Early Receive Interrupt */
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#define BITP_EMAC_DMA_STAT_FBI 13 /* Fatal Bus Error Interrupt */
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#define BITP_EMAC_DMA_STAT_ETI 10 /* Early Transmit Interrupt */
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#define BITP_EMAC_DMA_STAT_RWT 9 /* Receive WatchDog Timeout */
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#define BITP_EMAC_DMA_STAT_RPS 8 /* Receive Process Stopped */
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#define BITP_EMAC_DMA_STAT_RU 7 /* Receive Buffer Unavailable */
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#define BITP_EMAC_DMA_STAT_RI 6 /* Receive Interrupt */
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#define BITP_EMAC_DMA_STAT_UNF 5 /* Transmit Buffer Underflow */
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#define BITP_EMAC_DMA_STAT_OVF 4 /* Receive Buffer Overflow */
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#define BITP_EMAC_DMA_STAT_TJT 3 /* Transmit Jabber Timeout */
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#define BITP_EMAC_DMA_STAT_TU 2 /* Transmit Buffer Unavailable */
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#define BITP_EMAC_DMA_STAT_TPS 1 /* Transmit Process Stopped */
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#define BITP_EMAC_DMA_STAT_TI 0 /* Transmit Interrupt */
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#define BITM_EMAC_DMA_STAT_TTI (_ADI_MSK(0x20000000,uint32_t)) /* Time Stamp Trigger Interrupt */
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#define BITM_EMAC_DMA_STAT_MCI (_ADI_MSK(0x08000000,uint32_t)) /* MAC MMC Interrupt */
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#define BITM_EMAC_DMA_STAT_EB (_ADI_MSK(0x03800000,uint32_t)) /* Error Bits */
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#define BITM_EMAC_DMA_STAT_TS (_ADI_MSK(0x00700000,uint32_t)) /* Transmit Process State */
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#define ENUM_EMAC_DMA_STAT_TS_STOPPED (_ADI_MSK(0x00000000,uint32_t)) /* TS: Stopped; Reset or Stop Transmit Command issued */
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#define ENUM_EMAC_DMA_STAT_TS_R_FTD (_ADI_MSK(0x00100000,uint32_t)) /* TS: Running; Fetching Transmit Transfer Descriptor */
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#define ENUM_EMAC_DMA_STAT_TS_R_WSTAT (_ADI_MSK(0x00200000,uint32_t)) /* TS: Running; Waiting for status */
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#define ENUM_EMAC_DMA_STAT_TS_R_TXHMBUF (_ADI_MSK(0x00300000,uint32_t)) /* TS: Reading Data from host memory buffer and queuing it to TX buffer */
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#define ENUM_EMAC_DMA_STAT_TS_WR_TSTMP (_ADI_MSK(0x00400000,uint32_t)) /* TS: TIME_STAMP write state */
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#define ENUM_EMAC_DMA_STAT_TS_SUSPENDED (_ADI_MSK(0x00600000,uint32_t)) /* TS: Suspended; Transmit Descriptor Unavailable or TX Buffer Underflow */
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#define ENUM_EMAC_DMA_STAT_TS_R_CLSTD (_ADI_MSK(0x00700000,uint32_t)) /* TS: Closing Transmit Descriptor */
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#define BITM_EMAC_DMA_STAT_RS (_ADI_MSK(0x000E0000,uint32_t)) /* Receive Process State */
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#define ENUM_EMAC_DMA_STAT_RS_STOPPED (_ADI_MSK(0x00000000,uint32_t)) /* RS: Stopped: Reset or Stop Receive Command issued. */
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#define ENUM_EMAC_DMA_STAT_RS_R_FRD (_ADI_MSK(0x00020000,uint32_t)) /* RS: Running: Fetching Receive Transfer Descriptor. */
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#define ENUM_EMAC_DMA_STAT_RS_R_WTRX (_ADI_MSK(0x00060000,uint32_t)) /* RS: Running: Waiting for receive packet */
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#define ENUM_EMAC_DMA_STAT_RS_SUSPENDED (_ADI_MSK(0x00080000,uint32_t)) /* RS: Suspended: Receive Descriptor Unavailable */
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#define ENUM_EMAC_DMA_STAT_RS_R_CLSRD (_ADI_MSK(0x000A0000,uint32_t)) /* RS: Running: Closing Receive Descriptor */
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#define ENUM_EMAC_DMA_STAT_RS_WR_TSTMP (_ADI_MSK(0x000C0000,uint32_t)) /* RS: TIME_STAMP write state */
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#define ENUM_EMAC_DMA_STAT_RS_R_RXWRHM (_ADI_MSK(0x000E0000,uint32_t)) /* RS: Running: Transferring RX packet data from RX buffer to host memory */
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#define BITM_EMAC_DMA_STAT_NIS (_ADI_MSK(0x00010000,uint32_t)) /* Normal Interrupt Summary */
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#define BITM_EMAC_DMA_STAT_AIS (_ADI_MSK(0x00008000,uint32_t)) /* Abnormal Interrupt Summary */
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#define BITM_EMAC_DMA_STAT_ERI (_ADI_MSK(0x00004000,uint32_t)) /* Early Receive Interrupt */
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#define BITM_EMAC_DMA_STAT_FBI (_ADI_MSK(0x00002000,uint32_t)) /* Fatal Bus Error Interrupt */
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#define BITM_EMAC_DMA_STAT_ETI (_ADI_MSK(0x00000400,uint32_t)) /* Early Transmit Interrupt */
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#define BITM_EMAC_DMA_STAT_RWT (_ADI_MSK(0x00000200,uint32_t)) /* Receive WatchDog Timeout */
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#define BITM_EMAC_DMA_STAT_RPS (_ADI_MSK(0x00000100,uint32_t)) /* Receive Process Stopped */
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#define BITM_EMAC_DMA_STAT_RU (_ADI_MSK(0x00000080,uint32_t)) /* Receive Buffer Unavailable */
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#define BITM_EMAC_DMA_STAT_RI (_ADI_MSK(0x00000040,uint32_t)) /* Receive Interrupt */
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#define BITM_EMAC_DMA_STAT_UNF (_ADI_MSK(0x00000020,uint32_t)) /* Transmit Buffer Underflow */
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#define BITM_EMAC_DMA_STAT_OVF (_ADI_MSK(0x00000010,uint32_t)) /* Receive Buffer Overflow */
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#define BITM_EMAC_DMA_STAT_TJT (_ADI_MSK(0x00000008,uint32_t)) /* Transmit Jabber Timeout */
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#define BITM_EMAC_DMA_STAT_TU (_ADI_MSK(0x00000004,uint32_t)) /* Transmit Buffer Unavailable */
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#define BITM_EMAC_DMA_STAT_TPS (_ADI_MSK(0x00000002,uint32_t)) /* Transmit Process Stopped */
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#define BITM_EMAC_DMA_STAT_TI (_ADI_MSK(0x00000001,uint32_t)) /* Transmit Interrupt */
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/* ------------------------------------------------------------------------------------------------------------------------
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EMAC_DMA_OPMODE Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_EMAC_DMA_OPMODE_DT 26 /* Disable Dropping TCP/IP Errors */
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#define BITP_EMAC_DMA_OPMODE_RSF 25 /* Receive Store and Forward */
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#define BITP_EMAC_DMA_OPMODE_DFF 24 /* Disable Flushing of received Frames */
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#define BITP_EMAC_DMA_OPMODE_TSF 21 /* Transmit Store and Forward */
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#define BITP_EMAC_DMA_OPMODE_FTF 20 /* Flush Transmit FIFO */
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#define BITP_EMAC_DMA_OPMODE_TTC 14 /* Transmit Threshold Control */
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#define BITP_EMAC_DMA_OPMODE_ST 13 /* Start/Stop Transmission */
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#define BITP_EMAC_DMA_OPMODE_FEF 7 /* Forward Error Frames */
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#define BITP_EMAC_DMA_OPMODE_FUF 6 /* Forward Undersized good Frames */
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#define BITP_EMAC_DMA_OPMODE_RTC 3 /* Receive Threshold Control */
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#define BITP_EMAC_DMA_OPMODE_OSF 2 /* Operate on Second Frame */
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#define BITP_EMAC_DMA_OPMODE_SR 1 /* Start/Stop Receive */
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#define BITM_EMAC_DMA_OPMODE_DT (_ADI_MSK(0x04000000,uint32_t)) /* Disable Dropping TCP/IP Errors */
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#define BITM_EMAC_DMA_OPMODE_RSF (_ADI_MSK(0x02000000,uint32_t)) /* Receive Store and Forward */
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#define BITM_EMAC_DMA_OPMODE_DFF (_ADI_MSK(0x01000000,uint32_t)) /* Disable Flushing of received Frames */
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#define BITM_EMAC_DMA_OPMODE_TSF (_ADI_MSK(0x00200000,uint32_t)) /* Transmit Store and Forward */
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#define BITM_EMAC_DMA_OPMODE_FTF (_ADI_MSK(0x00100000,uint32_t)) /* Flush Transmit FIFO */
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#define BITM_EMAC_DMA_OPMODE_TTC (_ADI_MSK(0x0001C000,uint32_t)) /* Transmit Threshold Control */
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#define ENUM_EMAC_DMA_OPMODE_TTC_64 (_ADI_MSK(0x00000000,uint32_t)) /* TTC: 64 */
|
|
#define ENUM_EMAC_DMA_OPMODE_TTC_128 (_ADI_MSK(0x00004000,uint32_t)) /* TTC: 128 */
|
|
#define ENUM_EMAC_DMA_OPMODE_TTC_192 (_ADI_MSK(0x00008000,uint32_t)) /* TTC: 192 */
|
|
#define ENUM_EMAC_DMA_OPMODE_TTC_256 (_ADI_MSK(0x0000C000,uint32_t)) /* TTC: 256 */
|
|
#define ENUM_EMAC_DMA_OPMODE_TTC_40 (_ADI_MSK(0x00010000,uint32_t)) /* TTC: 40 */
|
|
#define ENUM_EMAC_DMA_OPMODE_TTC_32 (_ADI_MSK(0x00014000,uint32_t)) /* TTC: 32 */
|
|
#define ENUM_EMAC_DMA_OPMODE_TTC_24 (_ADI_MSK(0x00018000,uint32_t)) /* TTC: 24 */
|
|
#define ENUM_EMAC_DMA_OPMODE_TTC_16 (_ADI_MSK(0x0001C000,uint32_t)) /* TTC: 16 */
|
|
#define BITM_EMAC_DMA_OPMODE_ST (_ADI_MSK(0x00002000,uint32_t)) /* Start/Stop Transmission */
|
|
#define BITM_EMAC_DMA_OPMODE_FEF (_ADI_MSK(0x00000080,uint32_t)) /* Forward Error Frames */
|
|
#define BITM_EMAC_DMA_OPMODE_FUF (_ADI_MSK(0x00000040,uint32_t)) /* Forward Undersized good Frames */
|
|
|
|
#define BITM_EMAC_DMA_OPMODE_RTC (_ADI_MSK(0x00000018,uint32_t)) /* Receive Threshold Control */
|
|
#define ENUM_EMAC_DMA_OPMODE_RTC_64 (_ADI_MSK(0x00000000,uint32_t)) /* RTC: 64 */
|
|
#define ENUM_EMAC_DMA_OPMODE_RTC_32 (_ADI_MSK(0x00000008,uint32_t)) /* RTC: 32 */
|
|
#define ENUM_EMAC_DMA_OPMODE_RTC_96 (_ADI_MSK(0x00000010,uint32_t)) /* RTC: 96 */
|
|
#define ENUM_EMAC_DMA_OPMODE_RTC_128 (_ADI_MSK(0x00000018,uint32_t)) /* RTC: 128 */
|
|
#define BITM_EMAC_DMA_OPMODE_OSF (_ADI_MSK(0x00000004,uint32_t)) /* Operate on Second Frame */
|
|
#define BITM_EMAC_DMA_OPMODE_SR (_ADI_MSK(0x00000002,uint32_t)) /* Start/Stop Receive */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EMAC_DMA_IEN Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EMAC_DMA_IEN_NIS 16 /* Normal Interrupt Summary Enable */
|
|
#define BITP_EMAC_DMA_IEN_AIS 15 /* Abnormal Interrupt Summary Enable */
|
|
#define BITP_EMAC_DMA_IEN_ERI 14 /* Early Receive Interrupt Enable */
|
|
#define BITP_EMAC_DMA_IEN_FBI 13 /* Fatal Bus Error Enable */
|
|
#define BITP_EMAC_DMA_IEN_ETI 10 /* Early Transmit Interrupt Enable */
|
|
#define BITP_EMAC_DMA_IEN_RWT 9 /* Receive WatchdogTimeout Enable */
|
|
#define BITP_EMAC_DMA_IEN_RPS 8 /* Receive Stopped Enable */
|
|
#define BITP_EMAC_DMA_IEN_RU 7 /* Receive Buffer Unavailable Enable */
|
|
#define BITP_EMAC_DMA_IEN_RI 6 /* Receive Interrupt Enable */
|
|
#define BITP_EMAC_DMA_IEN_UNF 5 /* Underflow Interrupt Enable */
|
|
#define BITP_EMAC_DMA_IEN_OVF 4 /* Overflow Interrupt Enable */
|
|
#define BITP_EMAC_DMA_IEN_TJT 3 /* Transmit Jabber Timeout Enable */
|
|
#define BITP_EMAC_DMA_IEN_TU 2 /* Transmit Buffer Unavailable Enable */
|
|
#define BITP_EMAC_DMA_IEN_TPS 1 /* Transmit Stopped Enable */
|
|
#define BITP_EMAC_DMA_IEN_TI 0 /* Transmit Interrupt Enable */
|
|
#define BITM_EMAC_DMA_IEN_NIS (_ADI_MSK(0x00010000,uint32_t)) /* Normal Interrupt Summary Enable */
|
|
#define BITM_EMAC_DMA_IEN_AIS (_ADI_MSK(0x00008000,uint32_t)) /* Abnormal Interrupt Summary Enable */
|
|
#define BITM_EMAC_DMA_IEN_ERI (_ADI_MSK(0x00004000,uint32_t)) /* Early Receive Interrupt Enable */
|
|
#define BITM_EMAC_DMA_IEN_FBI (_ADI_MSK(0x00002000,uint32_t)) /* Fatal Bus Error Enable */
|
|
#define BITM_EMAC_DMA_IEN_ETI (_ADI_MSK(0x00000400,uint32_t)) /* Early Transmit Interrupt Enable */
|
|
#define BITM_EMAC_DMA_IEN_RWT (_ADI_MSK(0x00000200,uint32_t)) /* Receive WatchdogTimeout Enable */
|
|
#define BITM_EMAC_DMA_IEN_RPS (_ADI_MSK(0x00000100,uint32_t)) /* Receive Stopped Enable */
|
|
#define BITM_EMAC_DMA_IEN_RU (_ADI_MSK(0x00000080,uint32_t)) /* Receive Buffer Unavailable Enable */
|
|
#define BITM_EMAC_DMA_IEN_RI (_ADI_MSK(0x00000040,uint32_t)) /* Receive Interrupt Enable */
|
|
#define BITM_EMAC_DMA_IEN_UNF (_ADI_MSK(0x00000020,uint32_t)) /* Underflow Interrupt Enable */
|
|
#define BITM_EMAC_DMA_IEN_OVF (_ADI_MSK(0x00000010,uint32_t)) /* Overflow Interrupt Enable */
|
|
#define BITM_EMAC_DMA_IEN_TJT (_ADI_MSK(0x00000008,uint32_t)) /* Transmit Jabber Timeout Enable */
|
|
#define BITM_EMAC_DMA_IEN_TU (_ADI_MSK(0x00000004,uint32_t)) /* Transmit Buffer Unavailable Enable */
|
|
#define BITM_EMAC_DMA_IEN_TPS (_ADI_MSK(0x00000002,uint32_t)) /* Transmit Stopped Enable */
|
|
#define BITM_EMAC_DMA_IEN_TI (_ADI_MSK(0x00000001,uint32_t)) /* Transmit Interrupt Enable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EMAC_DMA_MISS_FRM Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EMAC_DMA_MISS_FRM_OVFFIFO 28 /* Overflow bit for FIFO Overflow Counter */
|
|
#define BITP_EMAC_DMA_MISS_FRM_MISSFROV 17 /* Missed Frames Buffer Overflow */
|
|
#define BITP_EMAC_DMA_MISS_FRM_OVFMISS 16 /* Overflow bit for Missed Frame Counter */
|
|
#define BITP_EMAC_DMA_MISS_FRM_MISSFRUN 0 /* Missed Frames Unavailable Buffer */
|
|
#define BITM_EMAC_DMA_MISS_FRM_OVFFIFO (_ADI_MSK(0x10000000,uint32_t)) /* Overflow bit for FIFO Overflow Counter */
|
|
#define BITM_EMAC_DMA_MISS_FRM_MISSFROV (_ADI_MSK(0x0FFE0000,uint32_t)) /* Missed Frames Buffer Overflow */
|
|
#define BITM_EMAC_DMA_MISS_FRM_OVFMISS (_ADI_MSK(0x00010000,uint32_t)) /* Overflow bit for Missed Frame Counter */
|
|
#define BITM_EMAC_DMA_MISS_FRM_MISSFRUN (_ADI_MSK(0x0000FFFF,uint32_t)) /* Missed Frames Unavailable Buffer */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EMAC_DMA_RXIWDOG Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EMAC_DMA_RXIWDOG_RIWT 0 /* RI WatchDog Timer Count */
|
|
#define BITM_EMAC_DMA_RXIWDOG_RIWT (_ADI_MSK(0x000000FF,uint32_t)) /* RI WatchDog Timer Count */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EMAC_DMA_BMMODE Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EMAC_DMA_BMMODE_WROSRLMT 20 /* SCB Maximum Write Outstanding Request */
|
|
#define BITP_EMAC_DMA_BMMODE_RDOSRLMT 16 /* SCB Maximum Read Outstanding Request */
|
|
#define BITP_EMAC_DMA_BMMODE_AAL 12 /* Address Aligned Beats */
|
|
#define BITP_EMAC_DMA_BMMODE_BLEN16 3 /* SCB Burst Length 16 */
|
|
#define BITP_EMAC_DMA_BMMODE_BLEN8 2 /* SCB Burst Length 8 */
|
|
#define BITP_EMAC_DMA_BMMODE_BLEN4 1 /* SCB Burst Length 4 */
|
|
#define BITP_EMAC_DMA_BMMODE_UNDEF 0 /* SCB Undefined Burst Length */
|
|
#define BITM_EMAC_DMA_BMMODE_WROSRLMT (_ADI_MSK(0x00700000,uint32_t)) /* SCB Maximum Write Outstanding Request */
|
|
#define BITM_EMAC_DMA_BMMODE_RDOSRLMT (_ADI_MSK(0x00070000,uint32_t)) /* SCB Maximum Read Outstanding Request */
|
|
#define BITM_EMAC_DMA_BMMODE_AAL (_ADI_MSK(0x00001000,uint32_t)) /* Address Aligned Beats */
|
|
#define BITM_EMAC_DMA_BMMODE_BLEN16 (_ADI_MSK(0x00000008,uint32_t)) /* SCB Burst Length 16 */
|
|
#define BITM_EMAC_DMA_BMMODE_BLEN8 (_ADI_MSK(0x00000004,uint32_t)) /* SCB Burst Length 8 */
|
|
#define BITM_EMAC_DMA_BMMODE_BLEN4 (_ADI_MSK(0x00000002,uint32_t)) /* SCB Burst Length 4 */
|
|
#define BITM_EMAC_DMA_BMMODE_UNDEF (_ADI_MSK(0x00000001,uint32_t)) /* SCB Undefined Burst Length */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EMAC_DMA_BMSTAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EMAC_DMA_BMSTAT_BUSRD 1 /* Bus (SCB master) Read Active */
|
|
#define BITP_EMAC_DMA_BMSTAT_BUSWR 0 /* Bus (SCB master) Write Active */
|
|
#define BITM_EMAC_DMA_BMSTAT_BUSRD (_ADI_MSK(0x00000002,uint32_t)) /* Bus (SCB master) Read Active */
|
|
#define BITM_EMAC_DMA_BMSTAT_BUSWR (_ADI_MSK(0x00000001,uint32_t)) /* Bus (SCB master) Write Active */
|
|
|
|
/* ==================================================
|
|
Serial Port Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
SPORT0
|
|
========================= */
|
|
#define REG_SPORT0_CTL_A 0xFFC40000 /* SPORT0 Half SPORT 'A' Control Register */
|
|
#define REG_SPORT0_DIV_A 0xFFC40004 /* SPORT0 Half SPORT 'A' Divisor Register */
|
|
#define REG_SPORT0_MCTL_A 0xFFC40008 /* SPORT0 Half SPORT 'A' Multi-channel Control Register */
|
|
#define REG_SPORT0_CS0_A 0xFFC4000C /* SPORT0 Half SPORT 'A' Multi-channel 0-31 Select Register */
|
|
#define REG_SPORT0_CS1_A 0xFFC40010 /* SPORT0 Half SPORT 'A' Multi-channel 32-63 Select Register */
|
|
#define REG_SPORT0_CS2_A 0xFFC40014 /* SPORT0 Half SPORT 'A' Multi-channel 64-95 Select Register */
|
|
#define REG_SPORT0_CS3_A 0xFFC40018 /* SPORT0 Half SPORT 'A' Multi-channel 96-127 Select Register */
|
|
#define REG_SPORT0_ERR_A 0xFFC40020 /* SPORT0 Half SPORT 'A' Error Register */
|
|
#define REG_SPORT0_MSTAT_A 0xFFC40024 /* SPORT0 Half SPORT 'A' Multi-channel Status Register */
|
|
#define REG_SPORT0_CTL2_A 0xFFC40028 /* SPORT0 Half SPORT 'A' Control 2 Register */
|
|
#define REG_SPORT0_TXPRI_A 0xFFC40040 /* SPORT0 Half SPORT 'A' Tx Buffer (Primary) Register */
|
|
#define REG_SPORT0_RXPRI_A 0xFFC40044 /* SPORT0 Half SPORT 'A' Rx Buffer (Primary) Register */
|
|
#define REG_SPORT0_TXSEC_A 0xFFC40048 /* SPORT0 Half SPORT 'A' Tx Buffer (Secondary) Register */
|
|
#define REG_SPORT0_RXSEC_A 0xFFC4004C /* SPORT0 Half SPORT 'A' Rx Buffer (Secondary) Register */
|
|
#define REG_SPORT0_CTL_B 0xFFC40080 /* SPORT0 Half SPORT 'B' Control Register */
|
|
#define REG_SPORT0_DIV_B 0xFFC40084 /* SPORT0 Half SPORT 'B' Divisor Register */
|
|
#define REG_SPORT0_MCTL_B 0xFFC40088 /* SPORT0 Half SPORT 'B' Multi-channel Control Register */
|
|
#define REG_SPORT0_CS0_B 0xFFC4008C /* SPORT0 Half SPORT 'B' Multi-channel 0-31 Select Register */
|
|
#define REG_SPORT0_CS1_B 0xFFC40090 /* SPORT0 Half SPORT 'B' Multi-channel 32-63 Select Register */
|
|
#define REG_SPORT0_CS2_B 0xFFC40094 /* SPORT0 Half SPORT 'B' Multichannel 64-95 Select Register */
|
|
#define REG_SPORT0_CS3_B 0xFFC40098 /* SPORT0 Half SPORT 'B' Multichannel 96-127 Select Register */
|
|
#define REG_SPORT0_ERR_B 0xFFC400A0 /* SPORT0 Half SPORT 'B' Error Register */
|
|
#define REG_SPORT0_MSTAT_B 0xFFC400A4 /* SPORT0 Half SPORT 'B' Multi-channel Status Register */
|
|
#define REG_SPORT0_CTL2_B 0xFFC400A8 /* SPORT0 Half SPORT 'B' Control 2 Register */
|
|
#define REG_SPORT0_TXPRI_B 0xFFC400C0 /* SPORT0 Half SPORT 'B' Tx Buffer (Primary) Register */
|
|
#define REG_SPORT0_RXPRI_B 0xFFC400C4 /* SPORT0 Half SPORT 'B' Rx Buffer (Primary) Register */
|
|
#define REG_SPORT0_TXSEC_B 0xFFC400C8 /* SPORT0 Half SPORT 'B' Tx Buffer (Secondary) Register */
|
|
#define REG_SPORT0_RXSEC_B 0xFFC400CC /* SPORT0 Half SPORT 'B' Rx Buffer (Secondary) Register */
|
|
|
|
/* =========================
|
|
SPORT1
|
|
========================= */
|
|
#define REG_SPORT1_CTL_A 0xFFC40100 /* SPORT1 Half SPORT 'A' Control Register */
|
|
#define REG_SPORT1_DIV_A 0xFFC40104 /* SPORT1 Half SPORT 'A' Divisor Register */
|
|
#define REG_SPORT1_MCTL_A 0xFFC40108 /* SPORT1 Half SPORT 'A' Multi-channel Control Register */
|
|
#define REG_SPORT1_CS0_A 0xFFC4010C /* SPORT1 Half SPORT 'A' Multi-channel 0-31 Select Register */
|
|
#define REG_SPORT1_CS1_A 0xFFC40110 /* SPORT1 Half SPORT 'A' Multi-channel 32-63 Select Register */
|
|
#define REG_SPORT1_CS2_A 0xFFC40114 /* SPORT1 Half SPORT 'A' Multi-channel 64-95 Select Register */
|
|
#define REG_SPORT1_CS3_A 0xFFC40118 /* SPORT1 Half SPORT 'A' Multi-channel 96-127 Select Register */
|
|
#define REG_SPORT1_ERR_A 0xFFC40120 /* SPORT1 Half SPORT 'A' Error Register */
|
|
#define REG_SPORT1_MSTAT_A 0xFFC40124 /* SPORT1 Half SPORT 'A' Multi-channel Status Register */
|
|
#define REG_SPORT1_CTL2_A 0xFFC40128 /* SPORT1 Half SPORT 'A' Control 2 Register */
|
|
#define REG_SPORT1_TXPRI_A 0xFFC40140 /* SPORT1 Half SPORT 'A' Tx Buffer (Primary) Register */
|
|
#define REG_SPORT1_RXPRI_A 0xFFC40144 /* SPORT1 Half SPORT 'A' Rx Buffer (Primary) Register */
|
|
#define REG_SPORT1_TXSEC_A 0xFFC40148 /* SPORT1 Half SPORT 'A' Tx Buffer (Secondary) Register */
|
|
#define REG_SPORT1_RXSEC_A 0xFFC4014C /* SPORT1 Half SPORT 'A' Rx Buffer (Secondary) Register */
|
|
#define REG_SPORT1_CTL_B 0xFFC40180 /* SPORT1 Half SPORT 'B' Control Register */
|
|
#define REG_SPORT1_DIV_B 0xFFC40184 /* SPORT1 Half SPORT 'B' Divisor Register */
|
|
#define REG_SPORT1_MCTL_B 0xFFC40188 /* SPORT1 Half SPORT 'B' Multi-channel Control Register */
|
|
#define REG_SPORT1_CS0_B 0xFFC4018C /* SPORT1 Half SPORT 'B' Multi-channel 0-31 Select Register */
|
|
#define REG_SPORT1_CS1_B 0xFFC40190 /* SPORT1 Half SPORT 'B' Multi-channel 32-63 Select Register */
|
|
#define REG_SPORT1_CS2_B 0xFFC40194 /* SPORT1 Half SPORT 'B' Multichannel 64-95 Select Register */
|
|
#define REG_SPORT1_CS3_B 0xFFC40198 /* SPORT1 Half SPORT 'B' Multichannel 96-127 Select Register */
|
|
#define REG_SPORT1_ERR_B 0xFFC401A0 /* SPORT1 Half SPORT 'B' Error Register */
|
|
#define REG_SPORT1_MSTAT_B 0xFFC401A4 /* SPORT1 Half SPORT 'B' Multi-channel Status Register */
|
|
#define REG_SPORT1_CTL2_B 0xFFC401A8 /* SPORT1 Half SPORT 'B' Control 2 Register */
|
|
#define REG_SPORT1_TXPRI_B 0xFFC401C0 /* SPORT1 Half SPORT 'B' Tx Buffer (Primary) Register */
|
|
#define REG_SPORT1_RXPRI_B 0xFFC401C4 /* SPORT1 Half SPORT 'B' Rx Buffer (Primary) Register */
|
|
#define REG_SPORT1_TXSEC_B 0xFFC401C8 /* SPORT1 Half SPORT 'B' Tx Buffer (Secondary) Register */
|
|
#define REG_SPORT1_RXSEC_B 0xFFC401CC /* SPORT1 Half SPORT 'B' Rx Buffer (Secondary) Register */
|
|
|
|
/* =========================
|
|
SPORT2
|
|
========================= */
|
|
#define REG_SPORT2_CTL_A 0xFFC40200 /* SPORT2 Half SPORT 'A' Control Register */
|
|
#define REG_SPORT2_DIV_A 0xFFC40204 /* SPORT2 Half SPORT 'A' Divisor Register */
|
|
#define REG_SPORT2_MCTL_A 0xFFC40208 /* SPORT2 Half SPORT 'A' Multi-channel Control Register */
|
|
#define REG_SPORT2_CS0_A 0xFFC4020C /* SPORT2 Half SPORT 'A' Multi-channel 0-31 Select Register */
|
|
#define REG_SPORT2_CS1_A 0xFFC40210 /* SPORT2 Half SPORT 'A' Multi-channel 32-63 Select Register */
|
|
#define REG_SPORT2_CS2_A 0xFFC40214 /* SPORT2 Half SPORT 'A' Multi-channel 64-95 Select Register */
|
|
#define REG_SPORT2_CS3_A 0xFFC40218 /* SPORT2 Half SPORT 'A' Multi-channel 96-127 Select Register */
|
|
#define REG_SPORT2_ERR_A 0xFFC40220 /* SPORT2 Half SPORT 'A' Error Register */
|
|
#define REG_SPORT2_MSTAT_A 0xFFC40224 /* SPORT2 Half SPORT 'A' Multi-channel Status Register */
|
|
#define REG_SPORT2_CTL2_A 0xFFC40228 /* SPORT2 Half SPORT 'A' Control 2 Register */
|
|
#define REG_SPORT2_TXPRI_A 0xFFC40240 /* SPORT2 Half SPORT 'A' Tx Buffer (Primary) Register */
|
|
#define REG_SPORT2_RXPRI_A 0xFFC40244 /* SPORT2 Half SPORT 'A' Rx Buffer (Primary) Register */
|
|
#define REG_SPORT2_TXSEC_A 0xFFC40248 /* SPORT2 Half SPORT 'A' Tx Buffer (Secondary) Register */
|
|
#define REG_SPORT2_RXSEC_A 0xFFC4024C /* SPORT2 Half SPORT 'A' Rx Buffer (Secondary) Register */
|
|
#define REG_SPORT2_CTL_B 0xFFC40280 /* SPORT2 Half SPORT 'B' Control Register */
|
|
#define REG_SPORT2_DIV_B 0xFFC40284 /* SPORT2 Half SPORT 'B' Divisor Register */
|
|
#define REG_SPORT2_MCTL_B 0xFFC40288 /* SPORT2 Half SPORT 'B' Multi-channel Control Register */
|
|
#define REG_SPORT2_CS0_B 0xFFC4028C /* SPORT2 Half SPORT 'B' Multi-channel 0-31 Select Register */
|
|
#define REG_SPORT2_CS1_B 0xFFC40290 /* SPORT2 Half SPORT 'B' Multi-channel 32-63 Select Register */
|
|
#define REG_SPORT2_CS2_B 0xFFC40294 /* SPORT2 Half SPORT 'B' Multichannel 64-95 Select Register */
|
|
#define REG_SPORT2_CS3_B 0xFFC40298 /* SPORT2 Half SPORT 'B' Multichannel 96-127 Select Register */
|
|
#define REG_SPORT2_ERR_B 0xFFC402A0 /* SPORT2 Half SPORT 'B' Error Register */
|
|
#define REG_SPORT2_MSTAT_B 0xFFC402A4 /* SPORT2 Half SPORT 'B' Multi-channel Status Register */
|
|
#define REG_SPORT2_CTL2_B 0xFFC402A8 /* SPORT2 Half SPORT 'B' Control 2 Register */
|
|
#define REG_SPORT2_TXPRI_B 0xFFC402C0 /* SPORT2 Half SPORT 'B' Tx Buffer (Primary) Register */
|
|
#define REG_SPORT2_RXPRI_B 0xFFC402C4 /* SPORT2 Half SPORT 'B' Rx Buffer (Primary) Register */
|
|
#define REG_SPORT2_TXSEC_B 0xFFC402C8 /* SPORT2 Half SPORT 'B' Tx Buffer (Secondary) Register */
|
|
#define REG_SPORT2_RXSEC_B 0xFFC402CC /* SPORT2 Half SPORT 'B' Rx Buffer (Secondary) Register */
|
|
|
|
/* =========================
|
|
SPORT
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SPORT_CTL_A Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SPORT_CTL_A_DXSPRI 30 /* Data Transfer Buffer Status (Primary) */
|
|
#define BITP_SPORT_CTL_DXSPRI 30 /* Data Transfer Buffer Status (Primary) */
|
|
#define BITP_SPORT_CTL_A_DERRPRI 29 /* Data Error Status (Primary) */
|
|
#define BITP_SPORT_CTL_DERRPRI 29 /* Data Error Status (Primary) */
|
|
#define BITP_SPORT_CTL_A_DXSSEC 27 /* Data Transfer Buffer Status (Secondary) */
|
|
#define BITP_SPORT_CTL_DXSSEC 27 /* Data Transfer Buffer Status (Secondary) */
|
|
#define BITP_SPORT_CTL_A_DERRSEC 26 /* Data Error Status (Secondary) */
|
|
#define BITP_SPORT_CTL_DERRSEC 26 /* Data Error Status (Secondary) */
|
|
#define BITP_SPORT_CTL_A_SPTRAN 25 /* Serial Port Transfer Direction */
|
|
#define BITP_SPORT_CTL_SPTRAN 25 /* Serial Port Transfer Direction */
|
|
#define BITP_SPORT_CTL_A_SPENSEC 24 /* Serial Port Enable (Secondary) */
|
|
#define BITP_SPORT_CTL_SPENSEC 24 /* Serial Port Enable (Secondary) */
|
|
#define BITP_SPORT_CTL_A_GCLKEN 21 /* Gated Clock Enable */
|
|
#define BITP_SPORT_CTL_GCLKEN 21 /* Gated Clock Enable */
|
|
#define BITP_SPORT_CTL_A_TFIEN 20 /* Transmit Finish Interrupt Enable */
|
|
#define BITP_SPORT_CTL_TFIEN 20 /* Transmit Finish Interrupt Enable */
|
|
#define BITP_SPORT_CTL_A_FSED 19 /* Frame Sync Edge Detect */
|
|
#define BITP_SPORT_CTL_FSED 19 /* Frame Sync Edge Detect */
|
|
#define BITP_SPORT_CTL_A_RJUST 18 /* Right-Justified Operation Mode */
|
|
#define BITP_SPORT_CTL_RJUST 18 /* Right-Justified Operation Mode */
|
|
#define BITP_SPORT_CTL_A_LAFS 17 /* Late Frame Sync / OPMODE2 */
|
|
#define BITP_SPORT_CTL_LAFS 17 /* Late Frame Sync / OPMODE2 */
|
|
#define BITP_SPORT_CTL_A_LFS 16 /* Active-Low Frame Sync / L_FIRST / PLFS */
|
|
#define BITP_SPORT_CTL_LFS 16 /* Active-Low Frame Sync / L_FIRST / PLFS */
|
|
#define BITP_SPORT_CTL_A_DIFS 15 /* Data-Independent Frame Sync */
|
|
#define BITP_SPORT_CTL_DIFS 15 /* Data-Independent Frame Sync */
|
|
#define BITP_SPORT_CTL_A_IFS 14 /* Internal Frame Sync */
|
|
#define BITP_SPORT_CTL_IFS 14 /* Internal Frame Sync */
|
|
#define BITP_SPORT_CTL_A_FSR 13 /* Frame Sync Required */
|
|
#define BITP_SPORT_CTL_FSR 13 /* Frame Sync Required */
|
|
#define BITP_SPORT_CTL_A_CKRE 12 /* Clock Rising Edge */
|
|
#define BITP_SPORT_CTL_CKRE 12 /* Clock Rising Edge */
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#define BITP_SPORT_CTL_A_OPMODE 11 /* Operation mode */
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#define BITP_SPORT_CTL_OPMODE 11 /* Operation mode */
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#define BITP_SPORT_CTL_A_ICLK 10 /* Internal Clock */
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#define BITP_SPORT_CTL_ICLK 10 /* Internal Clock */
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#define BITP_SPORT_CTL_A_PACK 9 /* Packing Enable */
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#define BITP_SPORT_CTL_PACK 9 /* Packing Enable */
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#define BITP_SPORT_CTL_A_SLEN 4 /* Serial Word Length */
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#define BITP_SPORT_CTL_SLEN 4 /* Serial Word Length */
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#define BITP_SPORT_CTL_A_LSBF 3 /* Least-Significant Bit First */
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#define BITP_SPORT_CTL_LSBF 3 /* Least-Significant Bit First */
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#define BITP_SPORT_CTL_A_DTYPE 1 /* Data Type */
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#define BITP_SPORT_CTL_DTYPE 1 /* Data Type */
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#define BITP_SPORT_CTL_A_SPENPRI 0 /* Serial Port Enable (Primary) */
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#define BITP_SPORT_CTL_SPENPRI 0 /* Serial Port Enable (Primary) */
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#define BITM_SPORT_CTL_A_DXSPRI (_ADI_MSK(0xC0000000,uint32_t)) /* Data Transfer Buffer Status (Primary) */
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#define BITM_SPORT_CTL_DXSPRI (_ADI_MSK(0xC0000000,uint32_t)) /* Data Transfer Buffer Status (Primary) */
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#define ENUM_SPORT_CTL_PRM_EMPTY (_ADI_MSK(0x00000000,uint32_t)) /* DXSPRI: Empty */
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#define ENUM_SPORT_CTL_PRM_PART_FULL (_ADI_MSK(0x80000000,uint32_t)) /* DXSPRI: Partially full */
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#define ENUM_SPORT_CTL_PRM_FULL (_ADI_MSK(0xC0000000,uint32_t)) /* DXSPRI: Full */
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#define BITM_SPORT_CTL_A_DERRPRI (_ADI_MSK(0x20000000,uint32_t)) /* Data Error Status (Primary) */
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#define BITM_SPORT_CTL_DERRPRI (_ADI_MSK(0x20000000,uint32_t)) /* Data Error Status (Primary) */
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#define ENUM_SPORT_CTL_PRM_NO_ERR (_ADI_MSK(0x00000000,uint32_t)) /* DERRPRI: No error */
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#define ENUM_SPORT_CTL_PRM_ERR (_ADI_MSK(0x20000000,uint32_t)) /* DERRPRI: Error (Tx underflow or Rx overflow) */
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#define BITM_SPORT_CTL_A_DXSSEC (_ADI_MSK(0x18000000,uint32_t)) /* Data Transfer Buffer Status (Secondary) */
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#define BITM_SPORT_CTL_DXSSEC (_ADI_MSK(0x18000000,uint32_t)) /* Data Transfer Buffer Status (Secondary) */
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#define ENUM_SPORT_CTL_SEC_EMPTY (_ADI_MSK(0x00000000,uint32_t)) /* DXSSEC: Empty */
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#define ENUM_SPORT_CTL_SEC_PART_FULL (_ADI_MSK(0x10000000,uint32_t)) /* DXSSEC: Partially full */
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#define ENUM_SPORT_CTL_SEC_FULL (_ADI_MSK(0x18000000,uint32_t)) /* DXSSEC: Full */
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#define BITM_SPORT_CTL_A_DERRSEC (_ADI_MSK(0x04000000,uint32_t)) /* Data Error Status (Secondary) */
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#define BITM_SPORT_CTL_DERRSEC (_ADI_MSK(0x04000000,uint32_t)) /* Data Error Status (Secondary) */
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#define ENUM_SPORT_CTL_SEC_NO_ERR (_ADI_MSK(0x00000000,uint32_t)) /* DERRSEC: No error */
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#define ENUM_SPORT_CTL_SEC_ERR (_ADI_MSK(0x04000000,uint32_t)) /* DERRSEC: Error (Tx underflow or Rx overflow) */
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#define BITM_SPORT_CTL_A_SPTRAN (_ADI_MSK(0x02000000,uint32_t)) /* Serial Port Transfer Direction */
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#define BITM_SPORT_CTL_SPTRAN (_ADI_MSK(0x02000000,uint32_t)) /* Serial Port Transfer Direction */
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#define ENUM_SPORT_CTL_RX (_ADI_MSK(0x00000000,uint32_t)) /* SPTRAN: Receive */
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#define ENUM_SPORT_CTL_TX (_ADI_MSK(0x02000000,uint32_t)) /* SPTRAN: Transmit */
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#define BITM_SPORT_CTL_A_SPENSEC (_ADI_MSK(0x01000000,uint32_t)) /* Serial Port Enable (Secondary) */
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#define BITM_SPORT_CTL_SPENSEC (_ADI_MSK(0x01000000,uint32_t)) /* Serial Port Enable (Secondary) */
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#define ENUM_SPORT_CTL_SECONDARY_DIS (_ADI_MSK(0x00000000,uint32_t)) /* SPENSEC: Disable */
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#define ENUM_SPORT_CTL_SECONDARY_EN (_ADI_MSK(0x01000000,uint32_t)) /* SPENSEC: Enable */
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#define BITM_SPORT_CTL_A_GCLKEN (_ADI_MSK(0x00200000,uint32_t)) /* Gated Clock Enable */
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#define BITM_SPORT_CTL_GCLKEN (_ADI_MSK(0x00200000,uint32_t)) /* Gated Clock Enable */
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#define ENUM_SPORT_CTL_GCLK_DIS (_ADI_MSK(0x00000000,uint32_t)) /* GCLKEN: Disable */
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#define ENUM_SPORT_CTL_GCLK_EN (_ADI_MSK(0x00200000,uint32_t)) /* GCLKEN: Enable */
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#define BITM_SPORT_CTL_A_TFIEN (_ADI_MSK(0x00100000,uint32_t)) /* Transmit Finish Interrupt Enable */
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#define BITM_SPORT_CTL_TFIEN (_ADI_MSK(0x00100000,uint32_t)) /* Transmit Finish Interrupt Enable */
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#define ENUM_SPORT_CTL_TXFIN_DIS (_ADI_MSK(0x00000000,uint32_t)) /* TFIEN: Last word sent (DMA count done) interrupt */
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#define ENUM_SPORT_CTL_TXFIN_EN (_ADI_MSK(0x00100000,uint32_t)) /* TFIEN: Last bit sent (Tx buffer done) interrupt */
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#define BITM_SPORT_CTL_A_FSED (_ADI_MSK(0x00080000,uint32_t)) /* Frame Sync Edge Detect */
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#define BITM_SPORT_CTL_FSED (_ADI_MSK(0x00080000,uint32_t)) /* Frame Sync Edge Detect */
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#define ENUM_SPORT_CTL_LEVEL_FS (_ADI_MSK(0x00000000,uint32_t)) /* FSED: Level detect frame sync */
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#define ENUM_SPORT_CTL_EDGE_FS (_ADI_MSK(0x00080000,uint32_t)) /* FSED: Edge detect frame sync */
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#define BITM_SPORT_CTL_A_RJUST (_ADI_MSK(0x00040000,uint32_t)) /* Right-Justified Operation Mode */
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#define BITM_SPORT_CTL_RJUST (_ADI_MSK(0x00040000,uint32_t)) /* Right-Justified Operation Mode */
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#define ENUM_SPORT_CTL_RJUST_DIS (_ADI_MSK(0x00000000,uint32_t)) /* RJUST: Disable */
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#define ENUM_SPORT_CTL_RJUST_EN (_ADI_MSK(0x00040000,uint32_t)) /* RJUST: Enable */
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#define BITM_SPORT_CTL_A_LAFS (_ADI_MSK(0x00020000,uint32_t)) /* Late Frame Sync / OPMODE2 */
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#define BITM_SPORT_CTL_LAFS (_ADI_MSK(0x00020000,uint32_t)) /* Late Frame Sync / OPMODE2 */
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#define ENUM_SPORT_CTL_EARLY_FS (_ADI_MSK(0x00000000,uint32_t)) /* LAFS: Early frame sync */
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#define ENUM_SPORT_CTL_LATE_FS (_ADI_MSK(0x00020000,uint32_t)) /* LAFS: Late frame sync */
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#define BITM_SPORT_CTL_A_LFS (_ADI_MSK(0x00010000,uint32_t)) /* Active-Low Frame Sync / L_FIRST / PLFS */
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#define BITM_SPORT_CTL_LFS (_ADI_MSK(0x00010000,uint32_t)) /* Active-Low Frame Sync / L_FIRST / PLFS */
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#define ENUM_SPORT_CTL_FS_LO (_ADI_MSK(0x00000000,uint32_t)) /* LFS: Active high frame sync (DSP standard mode) */
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#define ENUM_SPORT_CTL_FS_HI (_ADI_MSK(0x00010000,uint32_t)) /* LFS: Active low frame sync (DSP standard mode) */
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#define BITM_SPORT_CTL_A_DIFS (_ADI_MSK(0x00008000,uint32_t)) /* Data-Independent Frame Sync */
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#define BITM_SPORT_CTL_DIFS (_ADI_MSK(0x00008000,uint32_t)) /* Data-Independent Frame Sync */
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#define ENUM_SPORT_CTL_DATA_DEP_FS (_ADI_MSK(0x00000000,uint32_t)) /* DIFS: Data-dependent frame sync */
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#define ENUM_SPORT_CTL_DATA_INDP_FS (_ADI_MSK(0x00008000,uint32_t)) /* DIFS: Data-independent frame sync */
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#define BITM_SPORT_CTL_A_IFS (_ADI_MSK(0x00004000,uint32_t)) /* Internal Frame Sync */
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#define BITM_SPORT_CTL_IFS (_ADI_MSK(0x00004000,uint32_t)) /* Internal Frame Sync */
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#define ENUM_SPORT_CTL_EXTERNAL_FS (_ADI_MSK(0x00000000,uint32_t)) /* IFS: External frame sync */
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#define ENUM_SPORT_CTL_INTERNAL_FS (_ADI_MSK(0x00004000,uint32_t)) /* IFS: Internal frame sync */
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#define BITM_SPORT_CTL_A_FSR (_ADI_MSK(0x00002000,uint32_t)) /* Frame Sync Required */
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#define BITM_SPORT_CTL_FSR (_ADI_MSK(0x00002000,uint32_t)) /* Frame Sync Required */
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#define ENUM_SPORT_CTL_FS_NOT_REQ (_ADI_MSK(0x00000000,uint32_t)) /* FSR: No frame sync required */
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#define ENUM_SPORT_CTL_FS_REQ (_ADI_MSK(0x00002000,uint32_t)) /* FSR: Frame sync required */
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#define BITM_SPORT_CTL_A_CKRE (_ADI_MSK(0x00001000,uint32_t)) /* Clock Rising Edge */
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#define BITM_SPORT_CTL_CKRE (_ADI_MSK(0x00001000,uint32_t)) /* Clock Rising Edge */
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#define ENUM_SPORT_CTL_CLK_FALL_EDGE (_ADI_MSK(0x00000000,uint32_t)) /* CKRE: Clock falling edge */
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#define ENUM_SPORT_CTL_CLK_RISE_EDGE (_ADI_MSK(0x00001000,uint32_t)) /* CKRE: Clock rising edge */
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#define BITM_SPORT_CTL_A_OPMODE (_ADI_MSK(0x00000800,uint32_t)) /* Operation mode */
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#define BITM_SPORT_CTL_OPMODE (_ADI_MSK(0x00000800,uint32_t)) /* Operation mode */
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#define ENUM_SPORT_CTL_SERIAL_MC_MODE (_ADI_MSK(0x00000000,uint32_t)) /* OPMODE: DSP standard/multi-channel mode */
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#define ENUM_SPORT_CTL_I2S_MODE (_ADI_MSK(0x00000800,uint32_t)) /* OPMODE: I2S/packed/left-justified mode */
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#define BITM_SPORT_CTL_A_ICLK (_ADI_MSK(0x00000400,uint32_t)) /* Internal Clock */
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#define BITM_SPORT_CTL_ICLK (_ADI_MSK(0x00000400,uint32_t)) /* Internal Clock */
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#define ENUM_SPORT_CTL_EXTERNAL_CLK (_ADI_MSK(0x00000000,uint32_t)) /* ICLK: External clock */
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#define ENUM_SPORT_CTL_INTERNAL_CLK (_ADI_MSK(0x00000400,uint32_t)) /* ICLK: Internal clock */
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#define BITM_SPORT_CTL_A_PACK (_ADI_MSK(0x00000200,uint32_t)) /* Packing Enable */
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#define BITM_SPORT_CTL_PACK (_ADI_MSK(0x00000200,uint32_t)) /* Packing Enable */
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#define ENUM_SPORT_CTL_PACK_DIS (_ADI_MSK(0x00000000,uint32_t)) /* PACK: Disable */
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#define ENUM_SPORT_CTL_PACK_EN (_ADI_MSK(0x00000200,uint32_t)) /* PACK: Enable */
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#define BITM_SPORT_CTL_A_SLEN (_ADI_MSK(0x000001F0,uint32_t)) /* Serial Word Length */
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#define BITM_SPORT_CTL_SLEN (_ADI_MSK(0x000001F0,uint32_t)) /* Serial Word Length */
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#define BITM_SPORT_CTL_A_LSBF (_ADI_MSK(0x00000008,uint32_t)) /* Least-Significant Bit First */
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#define BITM_SPORT_CTL_LSBF (_ADI_MSK(0x00000008,uint32_t)) /* Least-Significant Bit First */
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#define ENUM_SPORT_CTL_MSB_FIRST (_ADI_MSK(0x00000000,uint32_t)) /* LSBF: MSB first sent/received (big endian) */
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#define ENUM_SPORT_CTL_LSB_FIRST (_ADI_MSK(0x00000008,uint32_t)) /* LSBF: LSB first sent/received (little endian) */
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#define BITM_SPORT_CTL_A_DTYPE (_ADI_MSK(0x00000006,uint32_t)) /* Data Type */
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#define BITM_SPORT_CTL_DTYPE (_ADI_MSK(0x00000006,uint32_t)) /* Data Type */
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#define ENUM_SPORT_CTL_RJUSTIFY_ZFILL (_ADI_MSK(0x00000000,uint32_t)) /* DTYPE: Right-justify data, zero-fill unused MSBs */
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#define ENUM_SPORT_CTL_RJUSTIFY_SFILL (_ADI_MSK(0x00000002,uint32_t)) /* DTYPE: Right-justify data, sign-extend unused MSBs */
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#define ENUM_SPORT_CTL_USE_U_LAW (_ADI_MSK(0x00000004,uint32_t)) /* DTYPE: m-law compand data */
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#define ENUM_SPORT_CTL_USE_A_LAW (_ADI_MSK(0x00000006,uint32_t)) /* DTYPE: A-law compand data */
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#define BITM_SPORT_CTL_A_SPENPRI (_ADI_MSK(0x00000001,uint32_t)) /* Serial Port Enable (Primary) */
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#define BITM_SPORT_CTL_SPENPRI (_ADI_MSK(0x00000001,uint32_t)) /* Serial Port Enable (Primary) */
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#define ENUM_SPORT_CTL_DIS (_ADI_MSK(0x00000000,uint32_t)) /* SPENPRI: Disable */
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#define ENUM_SPORT_CTL_EN (_ADI_MSK(0x00000001,uint32_t)) /* SPENPRI: Enable */
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/* ------------------------------------------------------------------------------------------------------------------------
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SPORT_DIV_A Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_SPORT_DIV_A_FSDIV 16 /* Frame Sync Divisor */
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#define BITP_SPORT_DIV_FSDIV 16 /* Frame Sync Divisor */
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#define BITP_SPORT_DIV_A_CLKDIV 0 /* Clock Divisor */
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#define BITP_SPORT_DIV_CLKDIV 0 /* Clock Divisor */
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#define BITM_SPORT_DIV_A_FSDIV (_ADI_MSK(0xFFFF0000,uint32_t)) /* Frame Sync Divisor */
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#define BITM_SPORT_DIV_FSDIV (_ADI_MSK(0xFFFF0000,uint32_t)) /* Frame Sync Divisor */
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#define BITM_SPORT_DIV_A_CLKDIV (_ADI_MSK(0x0000FFFF,uint32_t)) /* Clock Divisor */
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#define BITM_SPORT_DIV_CLKDIV (_ADI_MSK(0x0000FFFF,uint32_t)) /* Clock Divisor */
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/* ------------------------------------------------------------------------------------------------------------------------
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SPORT_MCTL_A Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_SPORT_MCTL_A_WOFFSET 16 /* Window Offset */
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#define BITP_SPORT_MCTL_WOFFSET 16 /* Window Offset */
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#define BITP_SPORT_MCTL_A_WSIZE 8 /* Window Size */
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#define BITP_SPORT_MCTL_WSIZE 8 /* Window Size */
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#define BITP_SPORT_MCTL_A_MFD 4 /* Multi-channel Frame Delay */
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#define BITP_SPORT_MCTL_MFD 4 /* Multi-channel Frame Delay */
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#define BITP_SPORT_MCTL_A_MCPDE 2 /* Multi-Channel Packing DMA Enable */
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#define BITP_SPORT_MCTL_MCPDE 2 /* Multi-Channel Packing DMA Enable */
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#define BITP_SPORT_MCTL_A_MCE 0 /* Multichannel enable */
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#define BITP_SPORT_MCTL_MCE 0 /* Multichannel enable */
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#define BITM_SPORT_MCTL_A_WOFFSET (_ADI_MSK(0x03FF0000,uint32_t)) /* Window Offset */
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#define BITM_SPORT_MCTL_WOFFSET (_ADI_MSK(0x03FF0000,uint32_t)) /* Window Offset */
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#define BITM_SPORT_MCTL_A_WSIZE (_ADI_MSK(0x00007F00,uint32_t)) /* Window Size */
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#define BITM_SPORT_MCTL_WSIZE (_ADI_MSK(0x00007F00,uint32_t)) /* Window Size */
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#define BITM_SPORT_MCTL_A_MFD (_ADI_MSK(0x000000F0,uint32_t)) /* Multi-channel Frame Delay */
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#define BITM_SPORT_MCTL_MFD (_ADI_MSK(0x000000F0,uint32_t)) /* Multi-channel Frame Delay */
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#define BITM_SPORT_MCTL_A_MCPDE (_ADI_MSK(0x00000004,uint32_t)) /* Multi-Channel Packing DMA Enable */
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#define BITM_SPORT_MCTL_MCPDE (_ADI_MSK(0x00000004,uint32_t)) /* Multi-Channel Packing DMA Enable */
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#define ENUM_SPORT_MCTL_MCPD_DIS (_ADI_MSK(0x00000000,uint32_t)) /* MCPDE: Disable */
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#define ENUM_SPORT_MCTL_MCPD_EN (_ADI_MSK(0x00000004,uint32_t)) /* MCPDE: Enable */
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#define BITM_SPORT_MCTL_A_MCE (_ADI_MSK(0x00000001,uint32_t)) /* Multichannel enable */
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#define BITM_SPORT_MCTL_MCE (_ADI_MSK(0x00000001,uint32_t)) /* Multichannel enable */
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#define ENUM_SPORT_MCTL_DIS (_ADI_MSK(0x00000000,uint32_t)) /* MCE: Disable */
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#define ENUM_SPORT_MCTL_EN (_ADI_MSK(0x00000001,uint32_t)) /* MCE: Enable */
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/* ------------------------------------------------------------------------------------------------------------------------
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SPORT_ERR_A Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_SPORT_ERR_A_FSERRSTAT 6 /* Frame Sync Error Status */
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#define BITP_SPORT_ERR_FSERRSTAT 6 /* Frame Sync Error Status */
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#define BITP_SPORT_ERR_A_DERRSSTAT 5 /* Data Error Secondary Status */
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#define BITP_SPORT_ERR_DERRSSTAT 5 /* Data Error Secondary Status */
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#define BITP_SPORT_ERR_A_DERRPSTAT 4 /* Data Error Primary Status */
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#define BITP_SPORT_ERR_DERRPSTAT 4 /* Data Error Primary Status */
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#define BITP_SPORT_ERR_A_FSERRMSK 2 /* Frame Sync Error (Interrupt) Mask */
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#define BITP_SPORT_ERR_FSERRMSK 2 /* Frame Sync Error (Interrupt) Mask */
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#define BITP_SPORT_ERR_A_DERRSMSK 1 /* Data Error Secondary (Interrupt) Mask */
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#define BITP_SPORT_ERR_DERRSMSK 1 /* Data Error Secondary (Interrupt) Mask */
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#define BITP_SPORT_ERR_A_DERRPMSK 0 /* Data Error Primary (Interrupt) Mask */
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#define BITP_SPORT_ERR_DERRPMSK 0 /* Data Error Primary (Interrupt) Mask */
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#define BITM_SPORT_ERR_A_FSERRSTAT (_ADI_MSK(0x00000040,uint32_t)) /* Frame Sync Error Status */
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#define BITM_SPORT_ERR_FSERRSTAT (_ADI_MSK(0x00000040,uint32_t)) /* Frame Sync Error Status */
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#define BITM_SPORT_ERR_A_DERRSSTAT (_ADI_MSK(0x00000020,uint32_t)) /* Data Error Secondary Status */
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#define BITM_SPORT_ERR_DERRSSTAT (_ADI_MSK(0x00000020,uint32_t)) /* Data Error Secondary Status */
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#define BITM_SPORT_ERR_A_DERRPSTAT (_ADI_MSK(0x00000010,uint32_t)) /* Data Error Primary Status */
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#define BITM_SPORT_ERR_DERRPSTAT (_ADI_MSK(0x00000010,uint32_t)) /* Data Error Primary Status */
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#define BITM_SPORT_ERR_A_FSERRMSK (_ADI_MSK(0x00000004,uint32_t)) /* Frame Sync Error (Interrupt) Mask */
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#define BITM_SPORT_ERR_FSERRMSK (_ADI_MSK(0x00000004,uint32_t)) /* Frame Sync Error (Interrupt) Mask */
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#define BITM_SPORT_ERR_A_DERRSMSK (_ADI_MSK(0x00000002,uint32_t)) /* Data Error Secondary (Interrupt) Mask */
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#define BITM_SPORT_ERR_DERRSMSK (_ADI_MSK(0x00000002,uint32_t)) /* Data Error Secondary (Interrupt) Mask */
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#define BITM_SPORT_ERR_A_DERRPMSK (_ADI_MSK(0x00000001,uint32_t)) /* Data Error Primary (Interrupt) Mask */
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#define BITM_SPORT_ERR_DERRPMSK (_ADI_MSK(0x00000001,uint32_t)) /* Data Error Primary (Interrupt) Mask */
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/* ------------------------------------------------------------------------------------------------------------------------
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SPORT_MSTAT_A Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_SPORT_MSTAT_A_CURCHAN 0 /* Current Channel */
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#define BITP_SPORT_MSTAT_CURCHAN 0 /* Current Channel */
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#define BITM_SPORT_MSTAT_A_CURCHAN (_ADI_MSK(0x000003FF,uint32_t)) /* Current Channel */
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#define BITM_SPORT_MSTAT_CURCHAN (_ADI_MSK(0x000003FF,uint32_t)) /* Current Channel */
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/* ------------------------------------------------------------------------------------------------------------------------
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SPORT_CTL2_A Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_SPORT_CTL2_A_CKMUXSEL 1 /* Clock Multiplexer Select */
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#define BITP_SPORT_CTL2_CKMUXSEL 1 /* Clock Multiplexer Select */
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#define BITP_SPORT_CTL2_A_FSMUXSEL 0 /* Frame Sync Multiplexer Select */
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#define BITP_SPORT_CTL2_FSMUXSEL 0 /* Frame Sync Multiplexer Select */
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#define BITM_SPORT_CTL2_A_CKMUXSEL (_ADI_MSK(0x00000002,uint32_t)) /* Clock Multiplexer Select */
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#define BITM_SPORT_CTL2_CKMUXSEL (_ADI_MSK(0x00000002,uint32_t)) /* Clock Multiplexer Select */
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#define ENUM_SPORT_CTL2_CLK_MUX_DIS (_ADI_MSK(0x00000000,uint32_t)) /* CKMUXSEL: Disable serial clock multiplexing */
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#define ENUM_SPORT_CTL2_CLK_MUX_EN (_ADI_MSK(0x00000002,uint32_t)) /* CKMUXSEL: Enable serial clock multiplexing */
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#define BITM_SPORT_CTL2_A_FSMUXSEL (_ADI_MSK(0x00000001,uint32_t)) /* Frame Sync Multiplexer Select */
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#define BITM_SPORT_CTL2_FSMUXSEL (_ADI_MSK(0x00000001,uint32_t)) /* Frame Sync Multiplexer Select */
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#define ENUM_SPORT_CTL2_FS_MUX_DIS (_ADI_MSK(0x00000000,uint32_t)) /* FSMUXSEL: Disable frame sync multiplexing */
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#define ENUM_SPORT_CTL2_FS_MUX_EN (_ADI_MSK(0x00000001,uint32_t)) /* FSMUXSEL: Enable frame sync multiplexing */
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/* ------------------------------------------------------------------------------------------------------------------------
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SPORT_CTL_B Pos/Masks Description
|
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_SPORT_CTL_B_DXSPRI 30 /* Data Transfer Buffer Status (Primary) */
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#define BITP_SPORT_CTL_B_DERRPRI 29 /* Data Error Status (Primary) */
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#define BITP_SPORT_CTL_B_DXSSEC 27 /* Data Transfer Buffer Status (Secondary) */
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#define BITP_SPORT_CTL_B_DERRSEC 26 /* Data Error Status (Secondary) */
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#define BITP_SPORT_CTL_B_SPTRAN 25 /* Serial Port Transfer Direction */
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#define BITP_SPORT_CTL_B_SPENSEC 24 /* Serial Port Enable (Secondary) */
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#define BITP_SPORT_CTL_B_GCLKEN 21 /* Gated Clock Enable */
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#define BITP_SPORT_CTL_B_TFIEN 20 /* Transmit Finish Interrupt Enable */
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#define BITP_SPORT_CTL_B_FSED 19 /* Frame Sync Edge Detect */
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#define BITP_SPORT_CTL_B_RJUST 18 /* Right-Justified Operation Mode */
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#define BITP_SPORT_CTL_B_LAFS 17 /* Late Frame Sync / OPMODE2 */
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#define BITP_SPORT_CTL_B_LFS 16 /* Active-Low Frame Sync / L_FIRST / PLFS */
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#define BITP_SPORT_CTL_B_DIFS 15 /* Data-Independent Frame Sync */
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#define BITP_SPORT_CTL_B_IFS 14 /* Internal Frame Sync */
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#define BITP_SPORT_CTL_B_FSR 13 /* Frame Sync Required */
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#define BITP_SPORT_CTL_B_CKRE 12 /* Clock Rising Edge */
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#define BITP_SPORT_CTL_B_OPMODE 11 /* Operation mode */
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#define BITP_SPORT_CTL_B_ICLK 10 /* Internal Clock */
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#define BITP_SPORT_CTL_B_PACK 9 /* Packing Enable */
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#define BITP_SPORT_CTL_B_SLEN 4 /* Serial Word Length */
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#define BITP_SPORT_CTL_B_LSBF 3 /* Least-Significant Bit First */
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#define BITP_SPORT_CTL_B_DTYPE 1 /* Data Type */
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#define BITP_SPORT_CTL_B_SPENPRI 0 /* Serial Port Enable (Primary) */
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/* The fields and enumerations for SPORT_CTL_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_CTL_A */
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#define BITM_SPORT_CTL_B_DXSPRI (_ADI_MSK(0xC0000000,uint32_t)) /* Data Transfer Buffer Status (Primary) */
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#define BITM_SPORT_CTL_B_DERRPRI (_ADI_MSK(0x20000000,uint32_t)) /* Data Error Status (Primary) */
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#define BITM_SPORT_CTL_B_DXSSEC (_ADI_MSK(0x18000000,uint32_t)) /* Data Transfer Buffer Status (Secondary) */
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#define BITM_SPORT_CTL_B_DERRSEC (_ADI_MSK(0x04000000,uint32_t)) /* Data Error Status (Secondary) */
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#define BITM_SPORT_CTL_B_SPTRAN (_ADI_MSK(0x02000000,uint32_t)) /* Serial Port Transfer Direction */
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#define BITM_SPORT_CTL_B_SPENSEC (_ADI_MSK(0x01000000,uint32_t)) /* Serial Port Enable (Secondary) */
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#define BITM_SPORT_CTL_B_GCLKEN (_ADI_MSK(0x00200000,uint32_t)) /* Gated Clock Enable */
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#define BITM_SPORT_CTL_B_TFIEN (_ADI_MSK(0x00100000,uint32_t)) /* Transmit Finish Interrupt Enable */
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#define BITM_SPORT_CTL_B_FSED (_ADI_MSK(0x00080000,uint32_t)) /* Frame Sync Edge Detect */
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#define BITM_SPORT_CTL_B_RJUST (_ADI_MSK(0x00040000,uint32_t)) /* Right-Justified Operation Mode */
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#define BITM_SPORT_CTL_B_LAFS (_ADI_MSK(0x00020000,uint32_t)) /* Late Frame Sync / OPMODE2 */
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#define BITM_SPORT_CTL_B_LFS (_ADI_MSK(0x00010000,uint32_t)) /* Active-Low Frame Sync / L_FIRST / PLFS */
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#define BITM_SPORT_CTL_B_DIFS (_ADI_MSK(0x00008000,uint32_t)) /* Data-Independent Frame Sync */
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#define BITM_SPORT_CTL_B_IFS (_ADI_MSK(0x00004000,uint32_t)) /* Internal Frame Sync */
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#define BITM_SPORT_CTL_B_FSR (_ADI_MSK(0x00002000,uint32_t)) /* Frame Sync Required */
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#define BITM_SPORT_CTL_B_CKRE (_ADI_MSK(0x00001000,uint32_t)) /* Clock Rising Edge */
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#define BITM_SPORT_CTL_B_OPMODE (_ADI_MSK(0x00000800,uint32_t)) /* Operation mode */
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#define BITM_SPORT_CTL_B_ICLK (_ADI_MSK(0x00000400,uint32_t)) /* Internal Clock */
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#define BITM_SPORT_CTL_B_PACK (_ADI_MSK(0x00000200,uint32_t)) /* Packing Enable */
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#define BITM_SPORT_CTL_B_SLEN (_ADI_MSK(0x000001F0,uint32_t)) /* Serial Word Length */
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#define BITM_SPORT_CTL_B_LSBF (_ADI_MSK(0x00000008,uint32_t)) /* Least-Significant Bit First */
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#define BITM_SPORT_CTL_B_DTYPE (_ADI_MSK(0x00000006,uint32_t)) /* Data Type */
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#define BITM_SPORT_CTL_B_SPENPRI (_ADI_MSK(0x00000001,uint32_t)) /* Serial Port Enable (Primary) */
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/* ------------------------------------------------------------------------------------------------------------------------
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SPORT_DIV_B Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_SPORT_DIV_B_FSDIV 16 /* Frame Sync Divisor */
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#define BITP_SPORT_DIV_B_CLKDIV 0 /* Clock Divisor */
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/* The fields and enumerations for SPORT_DIV_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_DIV_A */
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#define BITM_SPORT_DIV_B_FSDIV (_ADI_MSK(0xFFFF0000,uint32_t)) /* Frame Sync Divisor */
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#define BITM_SPORT_DIV_B_CLKDIV (_ADI_MSK(0x0000FFFF,uint32_t)) /* Clock Divisor */
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/* ------------------------------------------------------------------------------------------------------------------------
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SPORT_MCTL_B Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_SPORT_MCTL_B_WOFFSET 16 /* Window Offset */
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#define BITP_SPORT_MCTL_B_WSIZE 8 /* Window Size */
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#define BITP_SPORT_MCTL_B_MFD 4 /* Multi-channel Frame Delay */
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#define BITP_SPORT_MCTL_B_MCPDE 2 /* Multi-Channel Packing DMA Enable */
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#define BITP_SPORT_MCTL_B_MCE 0 /* Multi-Channel Enable */
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/* The fields and enumerations for SPORT_MCTL_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_MCTL_A */
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#define BITM_SPORT_MCTL_B_WOFFSET (_ADI_MSK(0x03FF0000,uint32_t)) /* Window Offset */
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#define BITM_SPORT_MCTL_B_WSIZE (_ADI_MSK(0x00007F00,uint32_t)) /* Window Size */
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#define BITM_SPORT_MCTL_B_MFD (_ADI_MSK(0x000000F0,uint32_t)) /* Multi-channel Frame Delay */
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#define BITM_SPORT_MCTL_B_MCPDE (_ADI_MSK(0x00000004,uint32_t)) /* Multi-Channel Packing DMA Enable */
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#define BITM_SPORT_MCTL_B_MCE (_ADI_MSK(0x00000001,uint32_t)) /* Multi-Channel Enable */
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/* ------------------------------------------------------------------------------------------------------------------------
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SPORT_ERR_B Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_SPORT_ERR_B_FSERRSTAT 6 /* Frame Sync Error Status */
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#define BITP_SPORT_ERR_B_DERRSSTAT 5 /* Data Error Secondary Status */
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#define BITP_SPORT_ERR_B_DERRPSTAT 4 /* Data Error Primary Status */
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#define BITP_SPORT_ERR_B_FSERRMSK 2 /* Frame Sync Error (Interrupt) Mask */
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#define BITP_SPORT_ERR_B_DERRSMSK 1 /* Data Error Secondary (Interrupt) Mask */
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#define BITP_SPORT_ERR_B_DERRPMSK 0 /* Data Error Primary (Interrupt) Mask */
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/* The fields and enumerations for SPORT_ERR_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_ERR_A */
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#define BITM_SPORT_ERR_B_FSERRSTAT (_ADI_MSK(0x00000040,uint32_t)) /* Frame Sync Error Status */
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#define BITM_SPORT_ERR_B_DERRSSTAT (_ADI_MSK(0x00000020,uint32_t)) /* Data Error Secondary Status */
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#define BITM_SPORT_ERR_B_DERRPSTAT (_ADI_MSK(0x00000010,uint32_t)) /* Data Error Primary Status */
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#define BITM_SPORT_ERR_B_FSERRMSK (_ADI_MSK(0x00000004,uint32_t)) /* Frame Sync Error (Interrupt) Mask */
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#define BITM_SPORT_ERR_B_DERRSMSK (_ADI_MSK(0x00000002,uint32_t)) /* Data Error Secondary (Interrupt) Mask */
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#define BITM_SPORT_ERR_B_DERRPMSK (_ADI_MSK(0x00000001,uint32_t)) /* Data Error Primary (Interrupt) Mask */
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
SPORT_MSTAT_B Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_SPORT_MSTAT_B_CURCHAN 0 /* Current Channel */
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/* The fields and enumerations for SPORT_MSTAT_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_MSTAT_A */
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#define BITM_SPORT_MSTAT_B_CURCHAN (_ADI_MSK(0x000003FF,uint32_t)) /* Current Channel */
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
SPORT_CTL2_B Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_SPORT_CTL2_B_CKMUXSEL 1 /* Clock Multiplexer Select */
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#define BITP_SPORT_CTL2_B_FSMUXSEL 0 /* Frame Sync Multiplexer Select */
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/* The fields and enumerations for SPORT_CTL2_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_CTL2_A */
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#define BITM_SPORT_CTL2_B_CKMUXSEL (_ADI_MSK(0x00000002,uint32_t)) /* Clock Multiplexer Select */
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#define BITM_SPORT_CTL2_B_FSMUXSEL (_ADI_MSK(0x00000001,uint32_t)) /* Frame Sync Multiplexer Select */
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/* ==================================================
|
|
Serial Peripheral Interface Registers
|
|
================================================== */
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|
|
|
/* =========================
|
|
SPI0
|
|
========================= */
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|
#define REG_SPI0_CTL 0xFFC40404 /* SPI0 Control Register */
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#define REG_SPI0_RXCTL 0xFFC40408 /* SPI0 Receive Control Register */
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#define REG_SPI0_TXCTL 0xFFC4040C /* SPI0 Transmit Control Register */
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#define REG_SPI0_CLK 0xFFC40410 /* SPI0 Clock Rate Register */
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#define REG_SPI0_DLY 0xFFC40414 /* SPI0 Delay Register */
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#define REG_SPI0_SLVSEL 0xFFC40418 /* SPI0 Slave Select Register */
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#define REG_SPI0_RWC 0xFFC4041C /* SPI0 Received Word Count Register */
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#define REG_SPI0_RWCR 0xFFC40420 /* SPI0 Received Word Count Reload Register */
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#define REG_SPI0_TWC 0xFFC40424 /* SPI0 Transmitted Word Count Register */
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#define REG_SPI0_TWCR 0xFFC40428 /* SPI0 Transmitted Word Count Reload Register */
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#define REG_SPI0_IMSK 0xFFC40430 /* SPI0 Interrupt Mask Register */
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#define REG_SPI0_IMSK_CLR 0xFFC40434 /* SPI0 Interrupt Mask Clear Register */
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#define REG_SPI0_IMSK_SET 0xFFC40438 /* SPI0 Interrupt Mask Set Register */
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#define REG_SPI0_STAT 0xFFC40440 /* SPI0 Status Register */
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#define REG_SPI0_ILAT 0xFFC40444 /* SPI0 Masked Interrupt Condition Register */
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#define REG_SPI0_ILAT_CLR 0xFFC40448 /* SPI0 Masked Interrupt Clear Register */
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#define REG_SPI0_RFIFO 0xFFC40450 /* SPI0 Receive FIFO Data Register */
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#define REG_SPI0_TFIFO 0xFFC40458 /* SPI0 Transmit FIFO Data Register */
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|
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/* =========================
|
|
SPI1
|
|
========================= */
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#define REG_SPI1_CTL 0xFFC40504 /* SPI1 Control Register */
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#define REG_SPI1_RXCTL 0xFFC40508 /* SPI1 Receive Control Register */
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#define REG_SPI1_TXCTL 0xFFC4050C /* SPI1 Transmit Control Register */
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#define REG_SPI1_CLK 0xFFC40510 /* SPI1 Clock Rate Register */
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#define REG_SPI1_DLY 0xFFC40514 /* SPI1 Delay Register */
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#define REG_SPI1_SLVSEL 0xFFC40518 /* SPI1 Slave Select Register */
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#define REG_SPI1_RWC 0xFFC4051C /* SPI1 Received Word Count Register */
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#define REG_SPI1_RWCR 0xFFC40520 /* SPI1 Received Word Count Reload Register */
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#define REG_SPI1_TWC 0xFFC40524 /* SPI1 Transmitted Word Count Register */
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#define REG_SPI1_TWCR 0xFFC40528 /* SPI1 Transmitted Word Count Reload Register */
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#define REG_SPI1_IMSK 0xFFC40530 /* SPI1 Interrupt Mask Register */
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#define REG_SPI1_IMSK_CLR 0xFFC40534 /* SPI1 Interrupt Mask Clear Register */
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#define REG_SPI1_IMSK_SET 0xFFC40538 /* SPI1 Interrupt Mask Set Register */
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#define REG_SPI1_STAT 0xFFC40540 /* SPI1 Status Register */
|
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#define REG_SPI1_ILAT 0xFFC40544 /* SPI1 Masked Interrupt Condition Register */
|
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#define REG_SPI1_ILAT_CLR 0xFFC40548 /* SPI1 Masked Interrupt Clear Register */
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#define REG_SPI1_RFIFO 0xFFC40550 /* SPI1 Receive FIFO Data Register */
|
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#define REG_SPI1_TFIFO 0xFFC40558 /* SPI1 Transmit FIFO Data Register */
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|
|
/* =========================
|
|
SPI
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SPI_CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
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#define BITP_SPI_CTL_SOSI 22 /* Start on MOSI */
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#define BITP_SPI_CTL_MIOM 20 /* Multiple I/O Mode */
|
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#define BITP_SPI_CTL_FMODE 18 /* Fast-Mode Enable */
|
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#define BITP_SPI_CTL_FCWM 16 /* Flow Control Watermark */
|
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#define BITP_SPI_CTL_FCPL 15 /* Flow Control Polarity */
|
|
#define BITP_SPI_CTL_FCCH 14 /* Flow Control Channel Selection */
|
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#define BITP_SPI_CTL_FCEN 13 /* Flow Control Enable */
|
|
#define BITP_SPI_CTL_LSBF 12 /* Least Significant Bit First */
|
|
#define BITP_SPI_CTL_SIZE 9 /* Word Transfer Size */
|
|
#define BITP_SPI_CTL_EMISO 8 /* Enable MISO */
|
|
#define BITP_SPI_CTL_SELST 7 /* Slave Select Polarity Between Transfers */
|
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#define BITP_SPI_CTL_ASSEL 6 /* Slave Select Pin Control */
|
|
#define BITP_SPI_CTL_CPOL 5 /* Clock Polarity */
|
|
#define BITP_SPI_CTL_CPHA 4 /* Clock Phase */
|
|
#define BITP_SPI_CTL_ODM 3 /* Open Drain Mode */
|
|
#define BITP_SPI_CTL_PSSE 2 /* Protected Slave Select Enable */
|
|
#define BITP_SPI_CTL_MSTR 1 /* Master / Slave */
|
|
#define BITP_SPI_CTL_EN 0 /* Enable */
|
|
|
|
#define BITM_SPI_CTL_SOSI (_ADI_MSK(0x00400000,uint32_t)) /* Start on MOSI */
|
|
#define ENUM_SPI_CTL_STMISO (_ADI_MSK(0x00000000,uint32_t)) /* SOSI: Bit 1 on MISO (DIOM) or on D3 (QIOM) */
|
|
#define ENUM_SPI_CTL_STMOSI (_ADI_MSK(0x00400000,uint32_t)) /* SOSI: Bit 1 on MOSI (DIOM and QIOM) */
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|
|
|
#define BITM_SPI_CTL_MIOM (_ADI_MSK(0x00300000,uint32_t)) /* Multiple I/O Mode */
|
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#define ENUM_SPI_CTL_MIO_DIS (_ADI_MSK(0x00000000,uint32_t)) /* MIOM: No MIOM (disabled) */
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#define ENUM_SPI_CTL_MIO_DUAL (_ADI_MSK(0x00100000,uint32_t)) /* MIOM: DIOM operation */
|
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#define ENUM_SPI_CTL_MIO_QUAD (_ADI_MSK(0x00200000,uint32_t)) /* MIOM: QIOM operation */
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|
|
|
#define BITM_SPI_CTL_FMODE (_ADI_MSK(0x00040000,uint32_t)) /* Fast-Mode Enable */
|
|
#define ENUM_SPI_CTL_FAST_DIS (_ADI_MSK(0x00000000,uint32_t)) /* FMODE: Disable */
|
|
#define ENUM_SPI_CTL_FAST_EN (_ADI_MSK(0x00040000,uint32_t)) /* FMODE: Enable */
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|
|
#define BITM_SPI_CTL_FCWM (_ADI_MSK(0x00030000,uint32_t)) /* Flow Control Watermark */
|
|
#define ENUM_SPI_CTL_FIFO0 (_ADI_MSK(0x00000000,uint32_t)) /* FCWM: TFIFO empty or RFIFO full */
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|
#define ENUM_SPI_CTL_FIFO1 (_ADI_MSK(0x00010000,uint32_t)) /* FCWM: TFIFO 75% or more empty, or RFIFO full */
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#define ENUM_SPI_CTL_FIFO2 (_ADI_MSK(0x00020000,uint32_t)) /* FCWM: TFIFO 50% or more empty, or RFIFO full */
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|
|
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#define BITM_SPI_CTL_FCPL (_ADI_MSK(0x00008000,uint32_t)) /* Flow Control Polarity */
|
|
#define ENUM_SPI_CTL_FLOW_LO (_ADI_MSK(0x00000000,uint32_t)) /* FCPL: Active-low RDY */
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#define ENUM_SPI_CTL_FLOW_HI (_ADI_MSK(0x00008000,uint32_t)) /* FCPL: Active-high RDY */
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|
|
|
#define BITM_SPI_CTL_FCCH (_ADI_MSK(0x00004000,uint32_t)) /* Flow Control Channel Selection */
|
|
#define ENUM_SPI_CTL_FLOW_RX (_ADI_MSK(0x00000000,uint32_t)) /* FCCH: Flow control on RX buffer */
|
|
#define ENUM_SPI_CTL_FLOW_TX (_ADI_MSK(0x00004000,uint32_t)) /* FCCH: Flow control on TX buffer */
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|
|
|
#define BITM_SPI_CTL_FCEN (_ADI_MSK(0x00002000,uint32_t)) /* Flow Control Enable */
|
|
#define ENUM_SPI_CTL_FLOW_DIS (_ADI_MSK(0x00000000,uint32_t)) /* FCEN: Disable */
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|
#define ENUM_SPI_CTL_FLOW_EN (_ADI_MSK(0x00002000,uint32_t)) /* FCEN: Enable */
|
|
|
|
#define BITM_SPI_CTL_LSBF (_ADI_MSK(0x00001000,uint32_t)) /* Least Significant Bit First */
|
|
#define ENUM_SPI_CTL_MSB_FIRST (_ADI_MSK(0x00000000,uint32_t)) /* LSBF: MSB sent/received first (big endian) */
|
|
#define ENUM_SPI_CTL_LSB_FIRST (_ADI_MSK(0x00001000,uint32_t)) /* LSBF: LSB sent/received first (little endian) */
|
|
|
|
#define BITM_SPI_CTL_SIZE (_ADI_MSK(0x00000600,uint32_t)) /* Word Transfer Size */
|
|
#define ENUM_SPI_CTL_SIZE08 (_ADI_MSK(0x00000000,uint32_t)) /* SIZE: 8-bit word */
|
|
#define ENUM_SPI_CTL_SIZE16 (_ADI_MSK(0x00000200,uint32_t)) /* SIZE: 16-bit word */
|
|
#define ENUM_SPI_CTL_SIZE32 (_ADI_MSK(0x00000400,uint32_t)) /* SIZE: 32-bit word */
|
|
|
|
#define BITM_SPI_CTL_EMISO (_ADI_MSK(0x00000100,uint32_t)) /* Enable MISO */
|
|
#define ENUM_SPI_CTL_MISO_DIS (_ADI_MSK(0x00000000,uint32_t)) /* EMISO: Disable */
|
|
#define ENUM_SPI_CTL_MISO_EN (_ADI_MSK(0x00000100,uint32_t)) /* EMISO: Enable */
|
|
|
|
#define BITM_SPI_CTL_SELST (_ADI_MSK(0x00000080,uint32_t)) /* Slave Select Polarity Between Transfers */
|
|
#define ENUM_SPI_CTL_DEASSRT_SSEL (_ADI_MSK(0x00000000,uint32_t)) /* SELST: De-assert slave select (high) */
|
|
#define ENUM_SPI_CTL_ASSRT_SSEL (_ADI_MSK(0x00000080,uint32_t)) /* SELST: Assert slave select (low) */
|
|
|
|
#define BITM_SPI_CTL_ASSEL (_ADI_MSK(0x00000040,uint32_t)) /* Slave Select Pin Control */
|
|
#define ENUM_SPI_CTL_SW_SSEL (_ADI_MSK(0x00000000,uint32_t)) /* ASSEL: Software Slave Select Control */
|
|
#define ENUM_SPI_CTL_HW_SSEL (_ADI_MSK(0x00000040,uint32_t)) /* ASSEL: Hardware Slave Select Control */
|
|
|
|
#define BITM_SPI_CTL_CPOL (_ADI_MSK(0x00000020,uint32_t)) /* Clock Polarity */
|
|
#define ENUM_SPI_CTL_SCKHI (_ADI_MSK(0x00000000,uint32_t)) /* CPOL: Active-high SPI CLK */
|
|
#define ENUM_SPI_CTL_SCKLO (_ADI_MSK(0x00000020,uint32_t)) /* CPOL: Active-low SPI CLK */
|
|
|
|
#define BITM_SPI_CTL_CPHA (_ADI_MSK(0x00000010,uint32_t)) /* Clock Phase */
|
|
#define ENUM_SPI_CTL_SCKMID (_ADI_MSK(0x00000000,uint32_t)) /* CPHA: SPI CLK toggles from middle */
|
|
#define ENUM_SPI_CTL_SCKBEG (_ADI_MSK(0x00000010,uint32_t)) /* CPHA: SPI CLK toggles from start */
|
|
|
|
#define BITM_SPI_CTL_ODM (_ADI_MSK(0x00000008,uint32_t)) /* Open Drain Mode */
|
|
#define ENUM_SPI_CTL_ODM_DIS (_ADI_MSK(0x00000000,uint32_t)) /* ODM: Disable */
|
|
#define ENUM_SPI_CTL_ODM_EN (_ADI_MSK(0x00000008,uint32_t)) /* ODM: Enable */
|
|
|
|
#define BITM_SPI_CTL_PSSE (_ADI_MSK(0x00000004,uint32_t)) /* Protected Slave Select Enable */
|
|
#define ENUM_SPI_CTL_PSSE_DIS (_ADI_MSK(0x00000000,uint32_t)) /* PSSE: Disable */
|
|
#define ENUM_SPI_CTL_PSSE_EN (_ADI_MSK(0x00000004,uint32_t)) /* PSSE: Enable */
|
|
|
|
#define BITM_SPI_CTL_MSTR (_ADI_MSK(0x00000002,uint32_t)) /* Master / Slave */
|
|
#define ENUM_SPI_CTL_SLAVE (_ADI_MSK(0x00000000,uint32_t)) /* MSTR: Slave */
|
|
#define ENUM_SPI_CTL_MASTER (_ADI_MSK(0x00000002,uint32_t)) /* MSTR: Master */
|
|
|
|
#define BITM_SPI_CTL_EN (_ADI_MSK(0x00000001,uint32_t)) /* Enable */
|
|
#define ENUM_SPI_CTL_DIS (_ADI_MSK(0x00000000,uint32_t)) /* EN: Disable SPI module */
|
|
#define ENUM_SPI_CTL_EN (_ADI_MSK(0x00000001,uint32_t)) /* EN: Enable */
|
|
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/* ------------------------------------------------------------------------------------------------------------------------
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SPI_RXCTL Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_SPI_RXCTL_RUWM 16 /* Receive FIFO Urgent Watermark */
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#define BITP_SPI_RXCTL_RRWM 12 /* Receive FIFO Regular Watermark */
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#define BITP_SPI_RXCTL_RDO 8 /* Receive Data Overrun */
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#define BITP_SPI_RXCTL_RDR 4 /* Receive Data Request */
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#define BITP_SPI_RXCTL_RWCEN 3 /* Receive Word Counter Enable */
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#define BITP_SPI_RXCTL_RTI 2 /* Receive Transfer Initiate */
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#define BITP_SPI_RXCTL_REN 0 /* Receive Enable */
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#define BITM_SPI_RXCTL_RUWM (_ADI_MSK(0x00070000,uint32_t)) /* Receive FIFO Urgent Watermark */
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#define ENUM_SPI_RXCTL_UWM_DIS (_ADI_MSK(0x00000000,uint32_t)) /* RUWM: Disabled */
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#define ENUM_SPI_RXCTL_UWM_25 (_ADI_MSK(0x00010000,uint32_t)) /* RUWM: 25% full RFIFO */
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#define ENUM_SPI_RXCTL_UWM_50 (_ADI_MSK(0x00020000,uint32_t)) /* RUWM: 50% full RFIFO */
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#define ENUM_SPI_RXCTL_UWM_75 (_ADI_MSK(0x00030000,uint32_t)) /* RUWM: 75% full RFIFO */
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#define ENUM_SPI_RXCTL_UWM_FULL (_ADI_MSK(0x00040000,uint32_t)) /* RUWM: Full RFIFO */
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#define BITM_SPI_RXCTL_RRWM (_ADI_MSK(0x00003000,uint32_t)) /* Receive FIFO Regular Watermark */
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#define ENUM_SPI_RXCTL_RWM_0 (_ADI_MSK(0x00000000,uint32_t)) /* RRWM: Empty RFIFO */
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#define ENUM_SPI_RXCTL_RWM_25 (_ADI_MSK(0x00001000,uint32_t)) /* RRWM: 25% full RFIFO */
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#define ENUM_SPI_RXCTL_RWM_50 (_ADI_MSK(0x00002000,uint32_t)) /* RRWM: 50% full RFIFO */
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#define ENUM_SPI_RXCTL_RWM_75 (_ADI_MSK(0x00003000,uint32_t)) /* RRWM: 75% full RFIFO */
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#define BITM_SPI_RXCTL_RDO (_ADI_MSK(0x00000100,uint32_t)) /* Receive Data Overrun */
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#define ENUM_SPI_RXCTL_DISCARD (_ADI_MSK(0x00000000,uint32_t)) /* RDO: KeDiscard incoming data if SPI_RFIFO is full */
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#define ENUM_SPI_RXCTL_OVERWRITE (_ADI_MSK(0x00000100,uint32_t)) /* RDO: Overwrite old data if SPI_RFIFO is full */
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#define BITM_SPI_RXCTL_RDR (_ADI_MSK(0x00000070,uint32_t)) /* Receive Data Request */
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#define ENUM_SPI_RXCTL_RDR_DIS (_ADI_MSK(0x00000000,uint32_t)) /* RDR: Disabled */
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#define ENUM_SPI_RXCTL_RDR_NE (_ADI_MSK(0x00000010,uint32_t)) /* RDR: Not empty RFIFO */
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#define ENUM_SPI_RXCTL_RDR_25 (_ADI_MSK(0x00000020,uint32_t)) /* RDR: 25% full RFIFO */
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#define ENUM_SPI_RXCTL_RDR_50 (_ADI_MSK(0x00000030,uint32_t)) /* RDR: 50% full RFIFO */
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#define ENUM_SPI_RXCTL_RDR_75 (_ADI_MSK(0x00000040,uint32_t)) /* RDR: 75% full RFIFO */
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#define ENUM_SPI_RXCTL_RDR_FULL (_ADI_MSK(0x00000050,uint32_t)) /* RDR: Full RFIFO */
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#define BITM_SPI_RXCTL_RWCEN (_ADI_MSK(0x00000008,uint32_t)) /* Receive Word Counter Enable */
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#define ENUM_SPI_RXCTL_RWC_DIS (_ADI_MSK(0x00000000,uint32_t)) /* RWCEN: Disable */
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#define ENUM_SPI_RXCTL_RWC_EN (_ADI_MSK(0x00000008,uint32_t)) /* RWCEN: Enable */
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#define BITM_SPI_RXCTL_RTI (_ADI_MSK(0x00000004,uint32_t)) /* Receive Transfer Initiate */
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#define ENUM_SPI_RXCTL_RTI_DIS (_ADI_MSK(0x00000000,uint32_t)) /* RTI: Disable */
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#define ENUM_SPI_RXCTL_RTI_EN (_ADI_MSK(0x00000004,uint32_t)) /* RTI: Enable */
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#define BITM_SPI_RXCTL_REN (_ADI_MSK(0x00000001,uint32_t)) /* Receive Enable */
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#define ENUM_SPI_RXCTL_RX_DIS (_ADI_MSK(0x00000000,uint32_t)) /* REN: Disable */
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#define ENUM_SPI_RXCTL_RX_EN (_ADI_MSK(0x00000001,uint32_t)) /* REN: Enable */
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/* ------------------------------------------------------------------------------------------------------------------------
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SPI_TXCTL Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_SPI_TXCTL_TUWM 16 /* FIFO Urgent Watermark */
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#define BITP_SPI_TXCTL_TRWM 12 /* FIFO Regular Watermark */
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#define BITP_SPI_TXCTL_TDU 8 /* Transmit Data Under-run */
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#define BITP_SPI_TXCTL_TDR 4 /* Transmit Data Request */
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#define BITP_SPI_TXCTL_TWCEN 3 /* Transmit Word Counter Enable */
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#define BITP_SPI_TXCTL_TTI 2 /* Transmit Transfer Initiate */
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#define BITP_SPI_TXCTL_TEN 0 /* Transmit Enable */
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#define BITM_SPI_TXCTL_TUWM (_ADI_MSK(0x00070000,uint32_t)) /* FIFO Urgent Watermark */
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#define ENUM_SPI_TXCTL_UWM_DIS (_ADI_MSK(0x00000000,uint32_t)) /* TUWM: Disabled */
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#define ENUM_SPI_TXCTL_UWM_25 (_ADI_MSK(0x00010000,uint32_t)) /* TUWM: 25% empty TFIFO */
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#define ENUM_SPI_TXCTL_UWM_50 (_ADI_MSK(0x00020000,uint32_t)) /* TUWM: 50% empty TFIFO */
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#define ENUM_SPI_TXCTL_UWM_75 (_ADI_MSK(0x00030000,uint32_t)) /* TUWM: 75% empty TFIFO */
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#define ENUM_SPI_TXCTL_UWM_EMPTY (_ADI_MSK(0x00040000,uint32_t)) /* TUWM: Empty TFIFO */
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#define BITM_SPI_TXCTL_TRWM (_ADI_MSK(0x00003000,uint32_t)) /* FIFO Regular Watermark */
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#define ENUM_SPI_TXCTL_RWM_FULL (_ADI_MSK(0x00000000,uint32_t)) /* TRWM: Full TFIFO */
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#define ENUM_SPI_TXCTL_RWM_25 (_ADI_MSK(0x00001000,uint32_t)) /* TRWM: 25% empty TFIFO */
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#define ENUM_SPI_TXCTL_RWM_50 (_ADI_MSK(0x00002000,uint32_t)) /* TRWM: 50% empty TFIFO */
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#define ENUM_SPI_TXCTL_RWM_75 (_ADI_MSK(0x00003000,uint32_t)) /* TRWM: 75% empty TFIFO */
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#define BITM_SPI_TXCTL_TDU (_ADI_MSK(0x00000100,uint32_t)) /* Transmit Data Under-run */
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#define ENUM_SPI_TXCTL_LASTWD (_ADI_MSK(0x00000000,uint32_t)) /* TDU: Send last word when SPI_TFIFO is empty */
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#define ENUM_SPI_TXCTL_ZERO (_ADI_MSK(0x00000100,uint32_t)) /* TDU: Send zeros when SPI_TFIFO is empty */
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#define BITM_SPI_TXCTL_TDR (_ADI_MSK(0x00000070,uint32_t)) /* Transmit Data Request */
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#define ENUM_SPI_TXCTL_TDR_DIS (_ADI_MSK(0x00000000,uint32_t)) /* TDR: Disabled */
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#define ENUM_SPI_TXCTL_TDR_NF (_ADI_MSK(0x00000010,uint32_t)) /* TDR: Not full TFIFO */
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#define ENUM_SPI_TXCTL_TDR_25 (_ADI_MSK(0x00000020,uint32_t)) /* TDR: 25% empty TFIFO */
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#define ENUM_SPI_TXCTL_TDR_50 (_ADI_MSK(0x00000030,uint32_t)) /* TDR: 50% empty TFIFO */
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#define ENUM_SPI_TXCTL_TDR_75 (_ADI_MSK(0x00000040,uint32_t)) /* TDR: 75% empty TFIFO */
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#define ENUM_SPI_TXCTL_TDR_EMPTY (_ADI_MSK(0x00000050,uint32_t)) /* TDR: Empty TFIFO */
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#define BITM_SPI_TXCTL_TWCEN (_ADI_MSK(0x00000008,uint32_t)) /* Transmit Word Counter Enable */
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#define ENUM_SPI_TXCTL_TWC_DIS (_ADI_MSK(0x00000000,uint32_t)) /* TWCEN: Disable */
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#define ENUM_SPI_TXCTL_TWC_EN (_ADI_MSK(0x00000008,uint32_t)) /* TWCEN: Enable */
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#define BITM_SPI_TXCTL_TTI (_ADI_MSK(0x00000004,uint32_t)) /* Transmit Transfer Initiate */
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#define ENUM_SPI_TXCTL_TTI_DIS (_ADI_MSK(0x00000000,uint32_t)) /* TTI: Disable */
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#define ENUM_SPI_TXCTL_TTI_EN (_ADI_MSK(0x00000004,uint32_t)) /* TTI: Enable */
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#define BITM_SPI_TXCTL_TEN (_ADI_MSK(0x00000001,uint32_t)) /* Transmit Enable */
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#define ENUM_SPI_TXCTL_TX_DIS (_ADI_MSK(0x00000000,uint32_t)) /* TEN: Disable */
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#define ENUM_SPI_TXCTL_TX_EN (_ADI_MSK(0x00000001,uint32_t)) /* TEN: Enable */
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/* ------------------------------------------------------------------------------------------------------------------------
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SPI_CLK Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_SPI_CLK_BAUD 0 /* Baud Rate */
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#define BITM_SPI_CLK_BAUD (_ADI_MSK(0x0000FFFF,uint32_t)) /* Baud Rate */
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/* ------------------------------------------------------------------------------------------------------------------------
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SPI_DLY Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_SPI_DLY_LAGX 9 /* Extended SPI Clock Lag Control */
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#define BITP_SPI_DLY_LEADX 8 /* Extended SPI Clock Lead Control */
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#define BITP_SPI_DLY_STOP 0 /* Transfer delay time in multiples of SPI clock period */
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#define BITM_SPI_DLY_LAGX (_ADI_MSK(0x00000200,uint32_t)) /* Extended SPI Clock Lag Control */
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#define BITM_SPI_DLY_LEADX (_ADI_MSK(0x00000100,uint32_t)) /* Extended SPI Clock Lead Control */
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#define BITM_SPI_DLY_STOP (_ADI_MSK(0x000000FF,uint32_t)) /* Transfer delay time in multiples of SPI clock period */
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/* ------------------------------------------------------------------------------------------------------------------------
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SPI_SLVSEL Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_SPI_SLVSEL_SSEL7 15 /* Slave Select 7 Input */
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#define BITP_SPI_SLVSEL_SSEL6 14 /* Slave Select 6 Input */
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#define BITP_SPI_SLVSEL_SSEL5 13 /* Slave Select 5 Input */
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#define BITP_SPI_SLVSEL_SSEL4 12 /* Slave Select 4 Input */
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#define BITP_SPI_SLVSEL_SSEL3 11 /* Slave Select 3 Input */
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#define BITP_SPI_SLVSEL_SSEL2 10 /* Slave Select 2 Input */
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#define BITP_SPI_SLVSEL_SSEL1 9 /* Slave Select 1 Input */
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#define BITP_SPI_SLVSEL_SSE7 7 /* Slave Select 7 Enable */
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#define BITP_SPI_SLVSEL_SSE6 6 /* Slave Select 6 Enable */
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#define BITP_SPI_SLVSEL_SSE5 5 /* Slave Select 5 Enable */
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#define BITP_SPI_SLVSEL_SSE4 4 /* Slave Select 4 Enable */
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#define BITP_SPI_SLVSEL_SSE3 3 /* Slave Select 3 Enable */
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#define BITP_SPI_SLVSEL_SSE2 2 /* Slave Select 2 Enable */
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#define BITP_SPI_SLVSEL_SSE1 1 /* Slave Select 1 Enable */
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#define BITM_SPI_SLVSEL_SSEL7 (_ADI_MSK(0x00008000,uint32_t)) /* Slave Select 7 Input */
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#define ENUM_SPI_SLVSEL_SSEL7_LO (_ADI_MSK(0x00000000,uint32_t)) /* SSEL7: Low */
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#define ENUM_SPI_SLVSEL_SSEL7_HI (_ADI_MSK(0x00008000,uint32_t)) /* SSEL7: High */
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#define BITM_SPI_SLVSEL_SSEL6 (_ADI_MSK(0x00004000,uint32_t)) /* Slave Select 6 Input */
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#define ENUM_SPI_SLVSEL_SSEL6_LO (_ADI_MSK(0x00000000,uint32_t)) /* SSEL6: Low */
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#define ENUM_SPI_SLVSEL_SSEL6_HI (_ADI_MSK(0x00004000,uint32_t)) /* SSEL6: High */
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#define BITM_SPI_SLVSEL_SSEL5 (_ADI_MSK(0x00002000,uint32_t)) /* Slave Select 5 Input */
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#define ENUM_SPI_SLVSEL_SSEL5_LO (_ADI_MSK(0x00000000,uint32_t)) /* SSEL5: Low */
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#define ENUM_SPI_SLVSEL_SSEL5_HI (_ADI_MSK(0x00002000,uint32_t)) /* SSEL5: High */
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#define BITM_SPI_SLVSEL_SSEL4 (_ADI_MSK(0x00001000,uint32_t)) /* Slave Select 4 Input */
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#define ENUM_SPI_SLVSEL_SSEL4_LO (_ADI_MSK(0x00000000,uint32_t)) /* SSEL4: Low */
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#define ENUM_SPI_SLVSEL_SSEL4_HI (_ADI_MSK(0x00001000,uint32_t)) /* SSEL4: High */
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#define BITM_SPI_SLVSEL_SSEL3 (_ADI_MSK(0x00000800,uint32_t)) /* Slave Select 3 Input */
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#define ENUM_SPI_SLVSEL_SSEL3_LO (_ADI_MSK(0x00000000,uint32_t)) /* SSEL3: Low */
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#define ENUM_SPI_SLVSEL_SSEL3_HI (_ADI_MSK(0x00000800,uint32_t)) /* SSEL3: High */
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#define BITM_SPI_SLVSEL_SSEL2 (_ADI_MSK(0x00000400,uint32_t)) /* Slave Select 2 Input */
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#define ENUM_SPI_SLVSEL_SSEL2_LO (_ADI_MSK(0x00000000,uint32_t)) /* SSEL2: Low */
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#define ENUM_SPI_SLVSEL_SSEL2_HI (_ADI_MSK(0x00000400,uint32_t)) /* SSEL2: High */
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#define BITM_SPI_SLVSEL_SSEL1 (_ADI_MSK(0x00000200,uint32_t)) /* Slave Select 1 Input */
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#define ENUM_SPI_SLVSEL_SSEL1_LO (_ADI_MSK(0x00000000,uint32_t)) /* SSEL1: Low */
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#define ENUM_SPI_SLVSEL_SSEL1_HI (_ADI_MSK(0x00000200,uint32_t)) /* SSEL1: High */
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#define BITM_SPI_SLVSEL_SSE7 (_ADI_MSK(0x00000080,uint32_t)) /* Slave Select 7 Enable */
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#define ENUM_SPI_SLVSEL_SSEL7_DIS (_ADI_MSK(0x00000000,uint32_t)) /* SSE7: Disable */
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#define ENUM_SPI_SLVSEL_SSEL7_EN (_ADI_MSK(0x00000080,uint32_t)) /* SSE7: Enable */
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#define BITM_SPI_SLVSEL_SSE6 (_ADI_MSK(0x00000040,uint32_t)) /* Slave Select 6 Enable */
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#define ENUM_SPI_SLVSEL_SSEL6_DIS (_ADI_MSK(0x00000000,uint32_t)) /* SSE6: Disable */
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#define ENUM_SPI_SLVSEL_SSEL6_EN (_ADI_MSK(0x00000040,uint32_t)) /* SSE6: Enable */
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#define BITM_SPI_SLVSEL_SSE5 (_ADI_MSK(0x00000020,uint32_t)) /* Slave Select 5 Enable */
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#define ENUM_SPI_SLVSEL_SSEL5_DIS (_ADI_MSK(0x00000000,uint32_t)) /* SSE5: Disable */
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#define ENUM_SPI_SLVSEL_SSEL5_EN (_ADI_MSK(0x00000020,uint32_t)) /* SSE5: Enable */
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#define BITM_SPI_SLVSEL_SSE4 (_ADI_MSK(0x00000010,uint32_t)) /* Slave Select 4 Enable */
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#define ENUM_SPI_SLVSEL_SSEL4_DIS (_ADI_MSK(0x00000000,uint32_t)) /* SSE4: Disable */
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#define ENUM_SPI_SLVSEL_SSEL4_EN (_ADI_MSK(0x00000010,uint32_t)) /* SSE4: Enable */
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#define BITM_SPI_SLVSEL_SSE3 (_ADI_MSK(0x00000008,uint32_t)) /* Slave Select 3 Enable */
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#define ENUM_SPI_SLVSEL_SSEL3_DIS (_ADI_MSK(0x00000000,uint32_t)) /* SSE3: Disable */
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#define ENUM_SPI_SLVSEL_SSEL3_EN (_ADI_MSK(0x00000008,uint32_t)) /* SSE3: Enable */
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#define BITM_SPI_SLVSEL_SSE2 (_ADI_MSK(0x00000004,uint32_t)) /* Slave Select 2 Enable */
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#define ENUM_SPI_SLVSEL_SSEL2_DIS (_ADI_MSK(0x00000000,uint32_t)) /* SSE2: Disable */
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#define ENUM_SPI_SLVSEL_SSEL2_EN (_ADI_MSK(0x00000004,uint32_t)) /* SSE2: Enable */
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#define BITM_SPI_SLVSEL_SSE1 (_ADI_MSK(0x00000002,uint32_t)) /* Slave Select 1 Enable */
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#define ENUM_SPI_SLVSEL_SSEL1_DIS (_ADI_MSK(0x00000000,uint32_t)) /* SSE1: Disable */
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#define ENUM_SPI_SLVSEL_SSEL1_EN (_ADI_MSK(0x00000002,uint32_t)) /* SSE1: Enable */
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/* ------------------------------------------------------------------------------------------------------------------------
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SPI_RWC Pos/Masks Description
|
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_SPI_RWC_VALUE 0 /* Received Word Count */
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#define BITM_SPI_RWC_VALUE (_ADI_MSK(0x0000FFFF,uint32_t)) /* Received Word Count */
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/* ------------------------------------------------------------------------------------------------------------------------
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SPI_RWCR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_SPI_RWCR_VALUE 0 /* Received Word Count Reload */
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#define BITM_SPI_RWCR_VALUE (_ADI_MSK(0x0000FFFF,uint32_t)) /* Received Word Count Reload */
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
SPI_TWC Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_SPI_TWC_VALUE 0 /* Transmitted Word Count */
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#define BITM_SPI_TWC_VALUE (_ADI_MSK(0x0000FFFF,uint32_t)) /* Transmitted Word Count */
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
SPI_TWCR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_SPI_TWCR_VALUE 0 /* Transmitted Word Count Reload */
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#define BITM_SPI_TWCR_VALUE (_ADI_MSK(0x0000FFFF,uint32_t)) /* Transmitted Word Count Reload */
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
SPI_IMSK Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_SPI_IMSK_TF 11 /* Transmit Finish Interrupt Mask */
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#define BITP_SPI_IMSK_RF 10 /* Receive Finish Interrupt Mask */
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#define BITP_SPI_IMSK_TS 9 /* Transmit Start Interrupt Mask */
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#define BITP_SPI_IMSK_RS 8 /* Receive Start Interrupt Mask */
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#define BITP_SPI_IMSK_MF 7 /* Mode Fault Interrupt Mask */
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#define BITP_SPI_IMSK_TC 6 /* Transmit Collision Interrupt Mask */
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#define BITP_SPI_IMSK_TUR 5 /* Transmit Underrun Interrupt Mask */
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#define BITP_SPI_IMSK_ROR 4 /* Receive Overrun Interrupt Mask */
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#define BITP_SPI_IMSK_TUWM 2 /* Transmit Urgent Watermark Interrupt Mask */
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#define BITP_SPI_IMSK_RUWM 1 /* Receive Urgent Watermark Interrupt Mask */
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#define BITM_SPI_IMSK_TF (_ADI_MSK(0x00000800,uint32_t)) /* Transmit Finish Interrupt Mask */
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#define ENUM_SPI_TF_LO (_ADI_MSK(0x00000000,uint32_t)) /* TF: Disable (mask) interrupt */
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#define ENUM_SPI_TF_HI (_ADI_MSK(0x00000800,uint32_t)) /* TF: Enable (unmask) interrupt */
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#define BITM_SPI_IMSK_RF (_ADI_MSK(0x00000400,uint32_t)) /* Receive Finish Interrupt Mask */
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#define ENUM_SPI_RF_LO (_ADI_MSK(0x00000000,uint32_t)) /* RF: Disable (mask) interrupt */
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#define ENUM_SPI_RF_HI (_ADI_MSK(0x00000400,uint32_t)) /* RF: Enable (unmask) interrupt */
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#define BITM_SPI_IMSK_TS (_ADI_MSK(0x00000200,uint32_t)) /* Transmit Start Interrupt Mask */
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#define ENUM_SPI_TS_LO (_ADI_MSK(0x00000000,uint32_t)) /* TS: Disable (mask) interrupt */
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#define ENUM_SPI_TS_HI (_ADI_MSK(0x00000200,uint32_t)) /* TS: Enable (unmask) interrupt */
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#define BITM_SPI_IMSK_RS (_ADI_MSK(0x00000100,uint32_t)) /* Receive Start Interrupt Mask */
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#define ENUM_SPI_RS_LO (_ADI_MSK(0x00000000,uint32_t)) /* RS: Disable (mask) interrupt */
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#define ENUM_SPI_RS_HI (_ADI_MSK(0x00000100,uint32_t)) /* RS: Enable (unmask) interrupt */
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|
|
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#define BITM_SPI_IMSK_MF (_ADI_MSK(0x00000080,uint32_t)) /* Mode Fault Interrupt Mask */
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|
#define ENUM_SPI_MF_LO (_ADI_MSK(0x00000000,uint32_t)) /* MF: Disable (mask) interrupt */
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#define ENUM_SPI_MF_HI (_ADI_MSK(0x00000080,uint32_t)) /* MF: Enable (unmask) interrupt */
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|
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#define BITM_SPI_IMSK_TC (_ADI_MSK(0x00000040,uint32_t)) /* Transmit Collision Interrupt Mask */
|
|
#define ENUM_SPI_TC_LO (_ADI_MSK(0x00000000,uint32_t)) /* TC: Disable (mask) interrupt */
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|
#define ENUM_SPI_TC_HI (_ADI_MSK(0x00000040,uint32_t)) /* TC: Enable (unmask) interrupt */
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|
|
|
#define BITM_SPI_IMSK_TUR (_ADI_MSK(0x00000020,uint32_t)) /* Transmit Underrun Interrupt Mask */
|
|
#define ENUM_SPI_TUR_LO (_ADI_MSK(0x00000000,uint32_t)) /* TUR: Disable (mask) interrupt */
|
|
#define ENUM_SPI_TUR_HI (_ADI_MSK(0x00000020,uint32_t)) /* TUR: Enable (unmask) interrupt */
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|
|
|
#define BITM_SPI_IMSK_ROR (_ADI_MSK(0x00000010,uint32_t)) /* Receive Overrun Interrupt Mask */
|
|
#define ENUM_SPI_ROR_LO (_ADI_MSK(0x00000000,uint32_t)) /* ROR: Disable (mask) interrupt */
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|
#define ENUM_SPI_ROR_HI (_ADI_MSK(0x00000010,uint32_t)) /* ROR: Enable (unmask) interrupt */
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|
|
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#define BITM_SPI_IMSK_TUWM (_ADI_MSK(0x00000004,uint32_t)) /* Transmit Urgent Watermark Interrupt Mask */
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#define ENUM_SPI_TUWM_LO (_ADI_MSK(0x00000000,uint32_t)) /* TUWM: Disable (mask) interrupt */
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#define ENUM_SPI_TUWM_HI (_ADI_MSK(0x00000004,uint32_t)) /* TUWM: Enable (unmask) interrupt */
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|
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#define BITM_SPI_IMSK_RUWM (_ADI_MSK(0x00000002,uint32_t)) /* Receive Urgent Watermark Interrupt Mask */
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|
#define ENUM_SPI_RUWM_LO (_ADI_MSK(0x00000000,uint32_t)) /* RUWM: Disable (mask) interrupt */
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|
#define ENUM_SPI_RUWM_HI (_ADI_MSK(0x00000002,uint32_t)) /* RUWM: Enable (unmask) interrupt */
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|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SPI_IMSK_CLR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SPI_IMSK_CLR_TF 11 /* Clear Transmit Finish Interrupt Mask */
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|
#define BITP_SPI_IMSK_CLR_RF 10 /* Clear Receive Finish Interrupt Mask */
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#define BITP_SPI_IMSK_CLR_TS 9 /* Clear Transmit Start Interrupt Mask */
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|
#define BITP_SPI_IMSK_CLR_RS 8 /* Clear Receive Start Interrupt Mask */
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#define BITP_SPI_IMSK_CLR_MF 7 /* Clear Mode Fault Interrupt Mask */
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#define BITP_SPI_IMSK_CLR_TC 6 /* Clear Transmit Collision Interrupt Mask */
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#define BITP_SPI_IMSK_CLR_TUR 5 /* Clear Transmit Under-run Interrupt Mask */
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|
#define BITP_SPI_IMSK_CLR_ROR 4 /* Clear Receive Overrun Interrupt Mask */
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|
#define BITP_SPI_IMSK_CLR_TUWM 2 /* Clear Transmit Urgent Watermark Interrupt Mask */
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|
#define BITP_SPI_IMSK_CLR_RUWM 1 /* Clear Receive Urgent Watermark Interrupt Mask */
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|
|
|
/* The fields and enumerations for SPI_IMSK_CLR are also in SPI - see the common set of ENUM_SPI_* #defines located with register SPI_IMSK */
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|
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#define BITM_SPI_IMSK_CLR_TF (_ADI_MSK(0x00000800,uint32_t)) /* Clear Transmit Finish Interrupt Mask */
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#define BITM_SPI_IMSK_CLR_RF (_ADI_MSK(0x00000400,uint32_t)) /* Clear Receive Finish Interrupt Mask */
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#define BITM_SPI_IMSK_CLR_TS (_ADI_MSK(0x00000200,uint32_t)) /* Clear Transmit Start Interrupt Mask */
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#define BITM_SPI_IMSK_CLR_RS (_ADI_MSK(0x00000100,uint32_t)) /* Clear Receive Start Interrupt Mask */
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#define BITM_SPI_IMSK_CLR_MF (_ADI_MSK(0x00000080,uint32_t)) /* Clear Mode Fault Interrupt Mask */
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#define BITM_SPI_IMSK_CLR_TC (_ADI_MSK(0x00000040,uint32_t)) /* Clear Transmit Collision Interrupt Mask */
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#define BITM_SPI_IMSK_CLR_TUR (_ADI_MSK(0x00000020,uint32_t)) /* Clear Transmit Under-run Interrupt Mask */
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#define BITM_SPI_IMSK_CLR_ROR (_ADI_MSK(0x00000010,uint32_t)) /* Clear Receive Overrun Interrupt Mask */
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#define BITM_SPI_IMSK_CLR_TUWM (_ADI_MSK(0x00000004,uint32_t)) /* Clear Transmit Urgent Watermark Interrupt Mask */
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#define BITM_SPI_IMSK_CLR_RUWM (_ADI_MSK(0x00000002,uint32_t)) /* Clear Receive Urgent Watermark Interrupt Mask */
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|
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
SPI_IMSK_SET Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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|
#define BITP_SPI_IMSK_SET_TF 11 /* Set Transmit Finish Interrupt Mask */
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#define BITP_SPI_IMSK_SET_RF 10 /* Set Receive Finish Interrupt Mask */
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#define BITP_SPI_IMSK_SET_TS 9 /* Set Transmit Start Interrupt Mask */
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#define BITP_SPI_IMSK_SET_RS 8 /* Set Receive Start Interrupt Mask */
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#define BITP_SPI_IMSK_SET_MF 7 /* Set Mode Fault Interrupt Mask */
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#define BITP_SPI_IMSK_SET_TC 6 /* Set Transmit Collision Interrupt Mask */
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#define BITP_SPI_IMSK_SET_TUR 5 /* Set Transmit Under-run Interrupt Mask */
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#define BITP_SPI_IMSK_SET_ROR 4 /* Set Receive Overrun Interrupt Mask */
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#define BITP_SPI_IMSK_SET_TUWM 2 /* Set Transmit Urgent Watermark Interrupt Mask */
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#define BITP_SPI_IMSK_SET_RUWM 1 /* Set Receive Urgent Watermark Interrupt Mask */
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/* The fields and enumerations for SPI_IMSK_SET are also in SPI - see the common set of ENUM_SPI_* #defines located with register SPI_IMSK */
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#define BITM_SPI_IMSK_SET_TF (_ADI_MSK(0x00000800,uint32_t)) /* Set Transmit Finish Interrupt Mask */
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#define BITM_SPI_IMSK_SET_RF (_ADI_MSK(0x00000400,uint32_t)) /* Set Receive Finish Interrupt Mask */
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#define BITM_SPI_IMSK_SET_TS (_ADI_MSK(0x00000200,uint32_t)) /* Set Transmit Start Interrupt Mask */
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#define BITM_SPI_IMSK_SET_RS (_ADI_MSK(0x00000100,uint32_t)) /* Set Receive Start Interrupt Mask */
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#define BITM_SPI_IMSK_SET_MF (_ADI_MSK(0x00000080,uint32_t)) /* Set Mode Fault Interrupt Mask */
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#define BITM_SPI_IMSK_SET_TC (_ADI_MSK(0x00000040,uint32_t)) /* Set Transmit Collision Interrupt Mask */
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#define BITM_SPI_IMSK_SET_TUR (_ADI_MSK(0x00000020,uint32_t)) /* Set Transmit Under-run Interrupt Mask */
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#define BITM_SPI_IMSK_SET_ROR (_ADI_MSK(0x00000010,uint32_t)) /* Set Receive Overrun Interrupt Mask */
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#define BITM_SPI_IMSK_SET_TUWM (_ADI_MSK(0x00000004,uint32_t)) /* Set Transmit Urgent Watermark Interrupt Mask */
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#define BITM_SPI_IMSK_SET_RUWM (_ADI_MSK(0x00000002,uint32_t)) /* Set Receive Urgent Watermark Interrupt Mask */
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|
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
SPI_STAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SPI_STAT_TFF 23 /* SPI_TFIFO Full */
|
|
#define BITP_SPI_STAT_RFE 22 /* SPI_RFIFO Empty */
|
|
#define BITP_SPI_STAT_FCS 20 /* Flow Control Stall Indication */
|
|
#define BITP_SPI_STAT_TFS 16 /* SPI_TFIFO Status */
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|
#define BITP_SPI_STAT_RFS 12 /* SPI_RFIFO Status */
|
|
#define BITP_SPI_STAT_TF 11 /* Transmit Finish Indication */
|
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#define BITP_SPI_STAT_RF 10 /* Receive Finish Indication */
|
|
#define BITP_SPI_STAT_TS 9 /* Transmit Start */
|
|
#define BITP_SPI_STAT_RS 8 /* Receive Start */
|
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#define BITP_SPI_STAT_MF 7 /* Mode Fault Indication */
|
|
#define BITP_SPI_STAT_TC 6 /* Transmit Collision Indication */
|
|
#define BITP_SPI_STAT_TUR 5 /* Transmit Underrun Indication */
|
|
#define BITP_SPI_STAT_ROR 4 /* Receive Overrun Indication */
|
|
#define BITP_SPI_STAT_TUWM 2 /* Transmit Urgent Watermark Breached */
|
|
#define BITP_SPI_STAT_RUWM 1 /* Receive Urgent Watermark Breached */
|
|
#define BITP_SPI_STAT_SPIF 0 /* SPI Finished */
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|
|
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#define BITM_SPI_STAT_TFF (_ADI_MSK(0x00800000,uint32_t)) /* SPI_TFIFO Full */
|
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#define ENUM_SPI_STAT_TFIFO_NF (_ADI_MSK(0x00000000,uint32_t)) /* TFF: Not full Tx FIFO */
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|
#define ENUM_SPI_STAT_TFIFO_F (_ADI_MSK(0x00800000,uint32_t)) /* TFF: Full Tx FIFO */
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#define BITM_SPI_STAT_RFE (_ADI_MSK(0x00400000,uint32_t)) /* SPI_RFIFO Empty */
|
|
#define ENUM_SPI_STAT_RFIFO_E (_ADI_MSK(0x00000000,uint32_t)) /* RFE: Empty Rx FIFO */
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|
#define ENUM_SPI_STAT_RFIFO_NE (_ADI_MSK(0x00400000,uint32_t)) /* RFE: Not empty Rx FIFO */
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|
|
|
#define BITM_SPI_STAT_FCS (_ADI_MSK(0x00100000,uint32_t)) /* Flow Control Stall Indication */
|
|
#define ENUM_SPI_STAT_STALL (_ADI_MSK(0x00000000,uint32_t)) /* FCS: Stall (RDY pin asserted) */
|
|
#define ENUM_SPI_STAT_NOSTALL (_ADI_MSK(0x00100000,uint32_t)) /* FCS: No stall (RDY pin de-asserted) */
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|
|
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#define BITM_SPI_STAT_TFS (_ADI_MSK(0x00070000,uint32_t)) /* SPI_TFIFO Status */
|
|
#define ENUM_SPI_STAT_TFIFO_FULL (_ADI_MSK(0x00000000,uint32_t)) /* TFS: Full TFIFO */
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|
#define ENUM_SPI_STAT_TFIFO_25 (_ADI_MSK(0x00010000,uint32_t)) /* TFS: 25% empty TFIFO */
|
|
#define ENUM_SPI_STAT_TFIFO_50 (_ADI_MSK(0x00020000,uint32_t)) /* TFS: 50% empty TFIFO */
|
|
#define ENUM_SPI_STAT_TFIFO_75 (_ADI_MSK(0x00030000,uint32_t)) /* TFS: 75% empty TFIFO */
|
|
#define ENUM_SPI_STAT_TFIFO_EMPTY (_ADI_MSK(0x00040000,uint32_t)) /* TFS: Empty TFIFO */
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|
|
|
#define BITM_SPI_STAT_RFS (_ADI_MSK(0x00007000,uint32_t)) /* SPI_RFIFO Status */
|
|
#define ENUM_SPI_STAT_RFIFO_EMPTY (_ADI_MSK(0x00000000,uint32_t)) /* RFS: Empty RFIFO */
|
|
#define ENUM_SPI_STAT_RFIFO_25 (_ADI_MSK(0x00001000,uint32_t)) /* RFS: 25% full RFIFO */
|
|
#define ENUM_SPI_STAT_RFIFO_50 (_ADI_MSK(0x00002000,uint32_t)) /* RFS: 50% full RFIFO */
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|
#define ENUM_SPI_STAT_RFIFO_75 (_ADI_MSK(0x00003000,uint32_t)) /* RFS: 75% full RFIFO */
|
|
#define ENUM_SPI_STAT_RFIFO_FULL (_ADI_MSK(0x00004000,uint32_t)) /* RFS: Full RFIFO */
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|
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#define BITM_SPI_STAT_TF (_ADI_MSK(0x00000800,uint32_t)) /* Transmit Finish Indication */
|
|
#define ENUM_SPI_STAT_TF_LO (_ADI_MSK(0x00000000,uint32_t)) /* TF: No status */
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#define ENUM_SPI_STAT_TF_HI (_ADI_MSK(0x00000800,uint32_t)) /* TF: Transmit finish detected */
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#define BITM_SPI_STAT_RF (_ADI_MSK(0x00000400,uint32_t)) /* Receive Finish Indication */
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|
#define ENUM_SPI_STAT_RF_LO (_ADI_MSK(0x00000000,uint32_t)) /* RF: No status */
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#define ENUM_SPI_STAT_RF_HI (_ADI_MSK(0x00000400,uint32_t)) /* RF: Receive finish detected */
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|
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#define BITM_SPI_STAT_TS (_ADI_MSK(0x00000200,uint32_t)) /* Transmit Start */
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#define ENUM_SPI_STAT_TS_LO (_ADI_MSK(0x00000000,uint32_t)) /* TS: No status */
|
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#define ENUM_SPI_STAT_TS_HI (_ADI_MSK(0x00000200,uint32_t)) /* TS: Transmit start detected */
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|
|
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#define BITM_SPI_STAT_RS (_ADI_MSK(0x00000100,uint32_t)) /* Receive Start */
|
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#define ENUM_SPI_STAT_RS_LO (_ADI_MSK(0x00000000,uint32_t)) /* RS: No status */
|
|
#define ENUM_SPI_STAT_RS_HI (_ADI_MSK(0x00000100,uint32_t)) /* RS: Receive start detected */
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|
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#define BITM_SPI_STAT_MF (_ADI_MSK(0x00000080,uint32_t)) /* Mode Fault Indication */
|
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#define ENUM_SPI_STAT_MF_LO (_ADI_MSK(0x00000000,uint32_t)) /* MF: No status */
|
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#define ENUM_SPI_STAT_MF_HI (_ADI_MSK(0x00000080,uint32_t)) /* MF: Mode fault occurred */
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|
|
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#define BITM_SPI_STAT_TC (_ADI_MSK(0x00000040,uint32_t)) /* Transmit Collision Indication */
|
|
#define ENUM_SPI_STAT_TC_LO (_ADI_MSK(0x00000000,uint32_t)) /* TC: No status */
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#define ENUM_SPI_STAT_TC_HI (_ADI_MSK(0x00000040,uint32_t)) /* TC: Transmit collision occurred */
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|
|
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#define BITM_SPI_STAT_TUR (_ADI_MSK(0x00000020,uint32_t)) /* Transmit Underrun Indication */
|
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#define ENUM_SPI_STAT_TUR_LO (_ADI_MSK(0x00000000,uint32_t)) /* TUR: No status */
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#define ENUM_SPI_STAT_TUR_HI (_ADI_MSK(0x00000020,uint32_t)) /* TUR: Transmit underrun occurred */
|
|
|
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#define BITM_SPI_STAT_ROR (_ADI_MSK(0x00000010,uint32_t)) /* Receive Overrun Indication */
|
|
#define ENUM_SPI_STAT_ROR_LO (_ADI_MSK(0x00000000,uint32_t)) /* ROR: No status */
|
|
#define ENUM_SPI_STAT_ROR_HI (_ADI_MSK(0x00000010,uint32_t)) /* ROR: Receive overrun occurred */
|
|
|
|
#define BITM_SPI_STAT_TUWM (_ADI_MSK(0x00000004,uint32_t)) /* Transmit Urgent Watermark Breached */
|
|
#define ENUM_SPI_STAT_TUWM_LO (_ADI_MSK(0x00000000,uint32_t)) /* TUWM: TX Regular Watermark reached */
|
|
#define ENUM_SPI_STAT_TUWM_HI (_ADI_MSK(0x00000004,uint32_t)) /* TUWM: TX Urgent Watermark breached */
|
|
|
|
#define BITM_SPI_STAT_RUWM (_ADI_MSK(0x00000002,uint32_t)) /* Receive Urgent Watermark Breached */
|
|
#define ENUM_SPI_STAT_RUWM_LO (_ADI_MSK(0x00000000,uint32_t)) /* RUWM: RX Regular Watermark reached */
|
|
#define ENUM_SPI_STAT_RUWM_HI (_ADI_MSK(0x00000002,uint32_t)) /* RUWM: RX Urgent Watermark breached */
|
|
|
|
#define BITM_SPI_STAT_SPIF (_ADI_MSK(0x00000001,uint32_t)) /* SPI Finished */
|
|
#define ENUM_SPI_STAT_SPIF_LO (_ADI_MSK(0x00000000,uint32_t)) /* SPIF: No status */
|
|
#define ENUM_SPI_STAT_SPIF_HI (_ADI_MSK(0x00000001,uint32_t)) /* SPIF: Completed single-word transfer */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SPI_ILAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SPI_ILAT_TF 11 /* Transmit Finish Interrupt Latch */
|
|
#define BITP_SPI_ILAT_RF 10 /* Receive Finish Interrupt Latch */
|
|
#define BITP_SPI_ILAT_TS 9 /* Transmit Start Interrupt Latch */
|
|
#define BITP_SPI_ILAT_RS 8 /* Receive Start Interrupt Latch */
|
|
#define BITP_SPI_ILAT_MF 7 /* Mode Fault Interrupt Latch */
|
|
#define BITP_SPI_ILAT_TC 6 /* Transmit Collision Interrupt Latch */
|
|
#define BITP_SPI_ILAT_TUR 5 /* Transmit Under-run Interrupt Latch */
|
|
#define BITP_SPI_ILAT_ROR 4 /* Receive Overrun Interrupt Latch */
|
|
#define BITP_SPI_ILAT_TUWM 2 /* Transmit Urgent Watermark Interrupt Latch */
|
|
#define BITP_SPI_ILAT_RUWM 1 /* Receive Urgent Watermark Interrupt Latch */
|
|
|
|
/* The fields and enumerations for SPI_ILAT are also in SPI - see the common set of ENUM_SPI_* #defines located with register SPI_IMSK */
|
|
|
|
|
|
#define BITM_SPI_ILAT_TF (_ADI_MSK(0x00000800,uint32_t)) /* Transmit Finish Interrupt Latch */
|
|
#define ENUM_SPI_ILAT_TF_LO (_ADI_MSK(0x00000000,uint32_t)) /* TF: No interrupt */
|
|
#define ENUM_SPI_ILAT_TF_HI (_ADI_MSK(0x00000800,uint32_t)) /* TF: Latched interrupt */
|
|
|
|
#define BITM_SPI_ILAT_RF (_ADI_MSK(0x00000400,uint32_t)) /* Receive Finish Interrupt Latch */
|
|
#define ENUM_SPI_ILAT_RF_LO (_ADI_MSK(0x00000000,uint32_t)) /* RF: No interrupt */
|
|
#define ENUM_SPI_ILAT_RF_HI (_ADI_MSK(0x00000400,uint32_t)) /* RF: Latched interrupt */
|
|
|
|
#define BITM_SPI_ILAT_TS (_ADI_MSK(0x00000200,uint32_t)) /* Transmit Start Interrupt Latch */
|
|
#define ENUM_SPI_ILAT_TS_LO (_ADI_MSK(0x00000000,uint32_t)) /* TS: No interrupt */
|
|
#define ENUM_SPI_ILAT_TS_HI (_ADI_MSK(0x00000200,uint32_t)) /* TS: Latched interrupt */
|
|
|
|
#define BITM_SPI_ILAT_RS (_ADI_MSK(0x00000100,uint32_t)) /* Receive Start Interrupt Latch */
|
|
#define ENUM_SPI_ILAT_RS_LO (_ADI_MSK(0x00000000,uint32_t)) /* RS: No interrupt */
|
|
#define ENUM_SPI_ILAT_RS_HI (_ADI_MSK(0x00000100,uint32_t)) /* RS: Latched interrupt */
|
|
|
|
#define BITM_SPI_ILAT_MF (_ADI_MSK(0x00000080,uint32_t)) /* Mode Fault Interrupt Latch */
|
|
#define ENUM_SPI_ILAT_MF_LO (_ADI_MSK(0x00000000,uint32_t)) /* MF: No interrupt */
|
|
#define ENUM_SPI_ILAT_MF_HI (_ADI_MSK(0x00000080,uint32_t)) /* MF: Latched interrupt */
|
|
|
|
#define BITM_SPI_ILAT_TC (_ADI_MSK(0x00000040,uint32_t)) /* Transmit Collision Interrupt Latch */
|
|
#define ENUM_SPI_ILAT_TC_LO (_ADI_MSK(0x00000000,uint32_t)) /* TC: No interrupt */
|
|
#define ENUM_SPI_ILAT_TC_HI (_ADI_MSK(0x00000040,uint32_t)) /* TC: Latched interrupt */
|
|
|
|
#define BITM_SPI_ILAT_TUR (_ADI_MSK(0x00000020,uint32_t)) /* Transmit Under-run Interrupt Latch */
|
|
#define ENUM_SPI_ILAT_TUR_LO (_ADI_MSK(0x00000000,uint32_t)) /* TUR: No interrupt */
|
|
#define ENUM_SPI_ILAT_TUR_HI (_ADI_MSK(0x00000020,uint32_t)) /* TUR: Latched interrupt */
|
|
|
|
#define BITM_SPI_ILAT_ROR (_ADI_MSK(0x00000010,uint32_t)) /* Receive Overrun Interrupt Latch */
|
|
#define ENUM_SPI_ILAT_ROR_LO (_ADI_MSK(0x00000000,uint32_t)) /* ROR: No interrupt */
|
|
#define ENUM_SPI_ILAT_ROR_HI (_ADI_MSK(0x00000010,uint32_t)) /* ROR: Latched interrupt */
|
|
|
|
#define BITM_SPI_ILAT_TUWM (_ADI_MSK(0x00000004,uint32_t)) /* Transmit Urgent Watermark Interrupt Latch */
|
|
#define ENUM_SPI_ILAT_TUWM_LO (_ADI_MSK(0x00000000,uint32_t)) /* TUWM: No interrupt */
|
|
#define ENUM_SPI_ILAT_TUWM_HI (_ADI_MSK(0x00000004,uint32_t)) /* TUWM: Latched interrupt */
|
|
|
|
#define BITM_SPI_ILAT_RUWM (_ADI_MSK(0x00000002,uint32_t)) /* Receive Urgent Watermark Interrupt Latch */
|
|
#define ENUM_SPI_ILAT_RUWM_LO (_ADI_MSK(0x00000000,uint32_t)) /* RUWM: No interrupt */
|
|
#define ENUM_SPI_ILAT_RUWM_HI (_ADI_MSK(0x00000002,uint32_t)) /* RUWM: Latched interrupt */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SPI_ILAT_CLR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SPI_ILAT_CLR_TF 11 /* Clear Transmit Finish Interrupt Latch */
|
|
#define BITP_SPI_ILAT_CLR_RF 10 /* Clear Receive Finish Interrupt Latch */
|
|
#define BITP_SPI_ILAT_CLR_TS 9 /* Clear Transmit Start Interrupt Latch */
|
|
#define BITP_SPI_ILAT_CLR_RS 8 /* Clear Receive Start Interrupt Latch */
|
|
#define BITP_SPI_ILAT_CLR_MF 7 /* Clear Mode Fault Interrupt Latch */
|
|
#define BITP_SPI_ILAT_CLR_TC 6 /* Clear Transmit Collision Interrupt Latch */
|
|
#define BITP_SPI_ILAT_CLR_TUR 5 /* Clear Transmit Under-run Interrupt Latch */
|
|
#define BITP_SPI_ILAT_CLR_ROR 4 /* Clear Receive Overrun Interrupt Latch */
|
|
#define BITP_SPI_ILAT_CLR_TUWM 2 /* Clear Transmit Urgent Watermark Interrupt Latch */
|
|
#define BITP_SPI_ILAT_CLR_RUWM 1 /* Clear Receive Urgent Watermark Interrupt Latch */
|
|
|
|
/* The fields and enumerations for SPI_ILAT_CLR are also in SPI - see the common set of ENUM_SPI_* #defines located with register SPI_IMSK */
|
|
|
|
#define BITM_SPI_ILAT_CLR_TF (_ADI_MSK(0x00000800,uint32_t)) /* Clear Transmit Finish Interrupt Latch */
|
|
#define BITM_SPI_ILAT_CLR_RF (_ADI_MSK(0x00000400,uint32_t)) /* Clear Receive Finish Interrupt Latch */
|
|
#define BITM_SPI_ILAT_CLR_TS (_ADI_MSK(0x00000200,uint32_t)) /* Clear Transmit Start Interrupt Latch */
|
|
#define BITM_SPI_ILAT_CLR_RS (_ADI_MSK(0x00000100,uint32_t)) /* Clear Receive Start Interrupt Latch */
|
|
#define BITM_SPI_ILAT_CLR_MF (_ADI_MSK(0x00000080,uint32_t)) /* Clear Mode Fault Interrupt Latch */
|
|
#define BITM_SPI_ILAT_CLR_TC (_ADI_MSK(0x00000040,uint32_t)) /* Clear Transmit Collision Interrupt Latch */
|
|
#define BITM_SPI_ILAT_CLR_TUR (_ADI_MSK(0x00000020,uint32_t)) /* Clear Transmit Under-run Interrupt Latch */
|
|
#define BITM_SPI_ILAT_CLR_ROR (_ADI_MSK(0x00000010,uint32_t)) /* Clear Receive Overrun Interrupt Latch */
|
|
#define BITM_SPI_ILAT_CLR_TUWM (_ADI_MSK(0x00000004,uint32_t)) /* Clear Transmit Urgent Watermark Interrupt Latch */
|
|
#define BITM_SPI_ILAT_CLR_RUWM (_ADI_MSK(0x00000002,uint32_t)) /* Clear Receive Urgent Watermark Interrupt Latch */
|
|
|
|
/* ==================================================
|
|
DMA Channel Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
DMA0
|
|
========================= */
|
|
#define REG_DMA0_DSCPTR_NXT 0xFFC41000 /* DMA0 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA0_ADDRSTART 0xFFC41004 /* DMA0 Start Address of Current Buffer */
|
|
#define REG_DMA0_CFG 0xFFC41008 /* DMA0 Configuration Register */
|
|
#define REG_DMA0_XCNT 0xFFC4100C /* DMA0 Inner Loop Count Start Value */
|
|
#define REG_DMA0_XMOD 0xFFC41010 /* DMA0 Inner Loop Address Increment */
|
|
#define REG_DMA0_YCNT 0xFFC41014 /* DMA0 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA0_YMOD 0xFFC41018 /* DMA0 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA0_DSCPTR_CUR 0xFFC41024 /* DMA0 Current Descriptor Pointer */
|
|
#define REG_DMA0_DSCPTR_PRV 0xFFC41028 /* DMA0 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA0_ADDR_CUR 0xFFC4102C /* DMA0 Current Address */
|
|
#define REG_DMA0_STAT 0xFFC41030 /* DMA0 Status Register */
|
|
#define REG_DMA0_XCNT_CUR 0xFFC41034 /* DMA0 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA0_YCNT_CUR 0xFFC41038 /* DMA0 Current Row Count (2D only) */
|
|
#define REG_DMA0_BWLCNT 0xFFC41040 /* DMA0 Bandwidth Limit Count */
|
|
#define REG_DMA0_BWLCNT_CUR 0xFFC41044 /* DMA0 Bandwidth Limit Count Current */
|
|
#define REG_DMA0_BWMCNT 0xFFC41048 /* DMA0 Bandwidth Monitor Count */
|
|
#define REG_DMA0_BWMCNT_CUR 0xFFC4104C /* DMA0 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA1
|
|
========================= */
|
|
#define REG_DMA1_DSCPTR_NXT 0xFFC41080 /* DMA1 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA1_ADDRSTART 0xFFC41084 /* DMA1 Start Address of Current Buffer */
|
|
#define REG_DMA1_CFG 0xFFC41088 /* DMA1 Configuration Register */
|
|
#define REG_DMA1_XCNT 0xFFC4108C /* DMA1 Inner Loop Count Start Value */
|
|
#define REG_DMA1_XMOD 0xFFC41090 /* DMA1 Inner Loop Address Increment */
|
|
#define REG_DMA1_YCNT 0xFFC41094 /* DMA1 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA1_YMOD 0xFFC41098 /* DMA1 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA1_DSCPTR_CUR 0xFFC410A4 /* DMA1 Current Descriptor Pointer */
|
|
#define REG_DMA1_DSCPTR_PRV 0xFFC410A8 /* DMA1 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA1_ADDR_CUR 0xFFC410AC /* DMA1 Current Address */
|
|
#define REG_DMA1_STAT 0xFFC410B0 /* DMA1 Status Register */
|
|
#define REG_DMA1_XCNT_CUR 0xFFC410B4 /* DMA1 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA1_YCNT_CUR 0xFFC410B8 /* DMA1 Current Row Count (2D only) */
|
|
#define REG_DMA1_BWLCNT 0xFFC410C0 /* DMA1 Bandwidth Limit Count */
|
|
#define REG_DMA1_BWLCNT_CUR 0xFFC410C4 /* DMA1 Bandwidth Limit Count Current */
|
|
#define REG_DMA1_BWMCNT 0xFFC410C8 /* DMA1 Bandwidth Monitor Count */
|
|
#define REG_DMA1_BWMCNT_CUR 0xFFC410CC /* DMA1 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA2
|
|
========================= */
|
|
#define REG_DMA2_DSCPTR_NXT 0xFFC41100 /* DMA2 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA2_ADDRSTART 0xFFC41104 /* DMA2 Start Address of Current Buffer */
|
|
#define REG_DMA2_CFG 0xFFC41108 /* DMA2 Configuration Register */
|
|
#define REG_DMA2_XCNT 0xFFC4110C /* DMA2 Inner Loop Count Start Value */
|
|
#define REG_DMA2_XMOD 0xFFC41110 /* DMA2 Inner Loop Address Increment */
|
|
#define REG_DMA2_YCNT 0xFFC41114 /* DMA2 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA2_YMOD 0xFFC41118 /* DMA2 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA2_DSCPTR_CUR 0xFFC41124 /* DMA2 Current Descriptor Pointer */
|
|
#define REG_DMA2_DSCPTR_PRV 0xFFC41128 /* DMA2 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA2_ADDR_CUR 0xFFC4112C /* DMA2 Current Address */
|
|
#define REG_DMA2_STAT 0xFFC41130 /* DMA2 Status Register */
|
|
#define REG_DMA2_XCNT_CUR 0xFFC41134 /* DMA2 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA2_YCNT_CUR 0xFFC41138 /* DMA2 Current Row Count (2D only) */
|
|
#define REG_DMA2_BWLCNT 0xFFC41140 /* DMA2 Bandwidth Limit Count */
|
|
#define REG_DMA2_BWLCNT_CUR 0xFFC41144 /* DMA2 Bandwidth Limit Count Current */
|
|
#define REG_DMA2_BWMCNT 0xFFC41148 /* DMA2 Bandwidth Monitor Count */
|
|
#define REG_DMA2_BWMCNT_CUR 0xFFC4114C /* DMA2 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA3
|
|
========================= */
|
|
#define REG_DMA3_DSCPTR_NXT 0xFFC41180 /* DMA3 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA3_ADDRSTART 0xFFC41184 /* DMA3 Start Address of Current Buffer */
|
|
#define REG_DMA3_CFG 0xFFC41188 /* DMA3 Configuration Register */
|
|
#define REG_DMA3_XCNT 0xFFC4118C /* DMA3 Inner Loop Count Start Value */
|
|
#define REG_DMA3_XMOD 0xFFC41190 /* DMA3 Inner Loop Address Increment */
|
|
#define REG_DMA3_YCNT 0xFFC41194 /* DMA3 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA3_YMOD 0xFFC41198 /* DMA3 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA3_DSCPTR_CUR 0xFFC411A4 /* DMA3 Current Descriptor Pointer */
|
|
#define REG_DMA3_DSCPTR_PRV 0xFFC411A8 /* DMA3 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA3_ADDR_CUR 0xFFC411AC /* DMA3 Current Address */
|
|
#define REG_DMA3_STAT 0xFFC411B0 /* DMA3 Status Register */
|
|
#define REG_DMA3_XCNT_CUR 0xFFC411B4 /* DMA3 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA3_YCNT_CUR 0xFFC411B8 /* DMA3 Current Row Count (2D only) */
|
|
#define REG_DMA3_BWLCNT 0xFFC411C0 /* DMA3 Bandwidth Limit Count */
|
|
#define REG_DMA3_BWLCNT_CUR 0xFFC411C4 /* DMA3 Bandwidth Limit Count Current */
|
|
#define REG_DMA3_BWMCNT 0xFFC411C8 /* DMA3 Bandwidth Monitor Count */
|
|
#define REG_DMA3_BWMCNT_CUR 0xFFC411CC /* DMA3 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA4
|
|
========================= */
|
|
#define REG_DMA4_DSCPTR_NXT 0xFFC41200 /* DMA4 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA4_ADDRSTART 0xFFC41204 /* DMA4 Start Address of Current Buffer */
|
|
#define REG_DMA4_CFG 0xFFC41208 /* DMA4 Configuration Register */
|
|
#define REG_DMA4_XCNT 0xFFC4120C /* DMA4 Inner Loop Count Start Value */
|
|
#define REG_DMA4_XMOD 0xFFC41210 /* DMA4 Inner Loop Address Increment */
|
|
#define REG_DMA4_YCNT 0xFFC41214 /* DMA4 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA4_YMOD 0xFFC41218 /* DMA4 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA4_DSCPTR_CUR 0xFFC41224 /* DMA4 Current Descriptor Pointer */
|
|
#define REG_DMA4_DSCPTR_PRV 0xFFC41228 /* DMA4 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA4_ADDR_CUR 0xFFC4122C /* DMA4 Current Address */
|
|
#define REG_DMA4_STAT 0xFFC41230 /* DMA4 Status Register */
|
|
#define REG_DMA4_XCNT_CUR 0xFFC41234 /* DMA4 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA4_YCNT_CUR 0xFFC41238 /* DMA4 Current Row Count (2D only) */
|
|
#define REG_DMA4_BWLCNT 0xFFC41240 /* DMA4 Bandwidth Limit Count */
|
|
#define REG_DMA4_BWLCNT_CUR 0xFFC41244 /* DMA4 Bandwidth Limit Count Current */
|
|
#define REG_DMA4_BWMCNT 0xFFC41248 /* DMA4 Bandwidth Monitor Count */
|
|
#define REG_DMA4_BWMCNT_CUR 0xFFC4124C /* DMA4 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA5
|
|
========================= */
|
|
#define REG_DMA5_DSCPTR_NXT 0xFFC41280 /* DMA5 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA5_ADDRSTART 0xFFC41284 /* DMA5 Start Address of Current Buffer */
|
|
#define REG_DMA5_CFG 0xFFC41288 /* DMA5 Configuration Register */
|
|
#define REG_DMA5_XCNT 0xFFC4128C /* DMA5 Inner Loop Count Start Value */
|
|
#define REG_DMA5_XMOD 0xFFC41290 /* DMA5 Inner Loop Address Increment */
|
|
#define REG_DMA5_YCNT 0xFFC41294 /* DMA5 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA5_YMOD 0xFFC41298 /* DMA5 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA5_DSCPTR_CUR 0xFFC412A4 /* DMA5 Current Descriptor Pointer */
|
|
#define REG_DMA5_DSCPTR_PRV 0xFFC412A8 /* DMA5 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA5_ADDR_CUR 0xFFC412AC /* DMA5 Current Address */
|
|
#define REG_DMA5_STAT 0xFFC412B0 /* DMA5 Status Register */
|
|
#define REG_DMA5_XCNT_CUR 0xFFC412B4 /* DMA5 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA5_YCNT_CUR 0xFFC412B8 /* DMA5 Current Row Count (2D only) */
|
|
#define REG_DMA5_BWLCNT 0xFFC412C0 /* DMA5 Bandwidth Limit Count */
|
|
#define REG_DMA5_BWLCNT_CUR 0xFFC412C4 /* DMA5 Bandwidth Limit Count Current */
|
|
#define REG_DMA5_BWMCNT 0xFFC412C8 /* DMA5 Bandwidth Monitor Count */
|
|
#define REG_DMA5_BWMCNT_CUR 0xFFC412CC /* DMA5 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA6
|
|
========================= */
|
|
#define REG_DMA6_DSCPTR_NXT 0xFFC41300 /* DMA6 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA6_ADDRSTART 0xFFC41304 /* DMA6 Start Address of Current Buffer */
|
|
#define REG_DMA6_CFG 0xFFC41308 /* DMA6 Configuration Register */
|
|
#define REG_DMA6_XCNT 0xFFC4130C /* DMA6 Inner Loop Count Start Value */
|
|
#define REG_DMA6_XMOD 0xFFC41310 /* DMA6 Inner Loop Address Increment */
|
|
#define REG_DMA6_YCNT 0xFFC41314 /* DMA6 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA6_YMOD 0xFFC41318 /* DMA6 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA6_DSCPTR_CUR 0xFFC41324 /* DMA6 Current Descriptor Pointer */
|
|
#define REG_DMA6_DSCPTR_PRV 0xFFC41328 /* DMA6 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA6_ADDR_CUR 0xFFC4132C /* DMA6 Current Address */
|
|
#define REG_DMA6_STAT 0xFFC41330 /* DMA6 Status Register */
|
|
#define REG_DMA6_XCNT_CUR 0xFFC41334 /* DMA6 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA6_YCNT_CUR 0xFFC41338 /* DMA6 Current Row Count (2D only) */
|
|
#define REG_DMA6_BWLCNT 0xFFC41340 /* DMA6 Bandwidth Limit Count */
|
|
#define REG_DMA6_BWLCNT_CUR 0xFFC41344 /* DMA6 Bandwidth Limit Count Current */
|
|
#define REG_DMA6_BWMCNT 0xFFC41348 /* DMA6 Bandwidth Monitor Count */
|
|
#define REG_DMA6_BWMCNT_CUR 0xFFC4134C /* DMA6 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA7
|
|
========================= */
|
|
#define REG_DMA7_DSCPTR_NXT 0xFFC41380 /* DMA7 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA7_ADDRSTART 0xFFC41384 /* DMA7 Start Address of Current Buffer */
|
|
#define REG_DMA7_CFG 0xFFC41388 /* DMA7 Configuration Register */
|
|
#define REG_DMA7_XCNT 0xFFC4138C /* DMA7 Inner Loop Count Start Value */
|
|
#define REG_DMA7_XMOD 0xFFC41390 /* DMA7 Inner Loop Address Increment */
|
|
#define REG_DMA7_YCNT 0xFFC41394 /* DMA7 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA7_YMOD 0xFFC41398 /* DMA7 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA7_DSCPTR_CUR 0xFFC413A4 /* DMA7 Current Descriptor Pointer */
|
|
#define REG_DMA7_DSCPTR_PRV 0xFFC413A8 /* DMA7 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA7_ADDR_CUR 0xFFC413AC /* DMA7 Current Address */
|
|
#define REG_DMA7_STAT 0xFFC413B0 /* DMA7 Status Register */
|
|
#define REG_DMA7_XCNT_CUR 0xFFC413B4 /* DMA7 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA7_YCNT_CUR 0xFFC413B8 /* DMA7 Current Row Count (2D only) */
|
|
#define REG_DMA7_BWLCNT 0xFFC413C0 /* DMA7 Bandwidth Limit Count */
|
|
#define REG_DMA7_BWLCNT_CUR 0xFFC413C4 /* DMA7 Bandwidth Limit Count Current */
|
|
#define REG_DMA7_BWMCNT 0xFFC413C8 /* DMA7 Bandwidth Monitor Count */
|
|
#define REG_DMA7_BWMCNT_CUR 0xFFC413CC /* DMA7 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA8
|
|
========================= */
|
|
#define REG_DMA8_DSCPTR_NXT 0xFFC41400 /* DMA8 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA8_ADDRSTART 0xFFC41404 /* DMA8 Start Address of Current Buffer */
|
|
#define REG_DMA8_CFG 0xFFC41408 /* DMA8 Configuration Register */
|
|
#define REG_DMA8_XCNT 0xFFC4140C /* DMA8 Inner Loop Count Start Value */
|
|
#define REG_DMA8_XMOD 0xFFC41410 /* DMA8 Inner Loop Address Increment */
|
|
#define REG_DMA8_YCNT 0xFFC41414 /* DMA8 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA8_YMOD 0xFFC41418 /* DMA8 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA8_DSCPTR_CUR 0xFFC41424 /* DMA8 Current Descriptor Pointer */
|
|
#define REG_DMA8_DSCPTR_PRV 0xFFC41428 /* DMA8 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA8_ADDR_CUR 0xFFC4142C /* DMA8 Current Address */
|
|
#define REG_DMA8_STAT 0xFFC41430 /* DMA8 Status Register */
|
|
#define REG_DMA8_XCNT_CUR 0xFFC41434 /* DMA8 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA8_YCNT_CUR 0xFFC41438 /* DMA8 Current Row Count (2D only) */
|
|
#define REG_DMA8_BWLCNT 0xFFC41440 /* DMA8 Bandwidth Limit Count */
|
|
#define REG_DMA8_BWLCNT_CUR 0xFFC41444 /* DMA8 Bandwidth Limit Count Current */
|
|
#define REG_DMA8_BWMCNT 0xFFC41448 /* DMA8 Bandwidth Monitor Count */
|
|
#define REG_DMA8_BWMCNT_CUR 0xFFC4144C /* DMA8 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA9
|
|
========================= */
|
|
#define REG_DMA9_DSCPTR_NXT 0xFFC41480 /* DMA9 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA9_ADDRSTART 0xFFC41484 /* DMA9 Start Address of Current Buffer */
|
|
#define REG_DMA9_CFG 0xFFC41488 /* DMA9 Configuration Register */
|
|
#define REG_DMA9_XCNT 0xFFC4148C /* DMA9 Inner Loop Count Start Value */
|
|
#define REG_DMA9_XMOD 0xFFC41490 /* DMA9 Inner Loop Address Increment */
|
|
#define REG_DMA9_YCNT 0xFFC41494 /* DMA9 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA9_YMOD 0xFFC41498 /* DMA9 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA9_DSCPTR_CUR 0xFFC414A4 /* DMA9 Current Descriptor Pointer */
|
|
#define REG_DMA9_DSCPTR_PRV 0xFFC414A8 /* DMA9 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA9_ADDR_CUR 0xFFC414AC /* DMA9 Current Address */
|
|
#define REG_DMA9_STAT 0xFFC414B0 /* DMA9 Status Register */
|
|
#define REG_DMA9_XCNT_CUR 0xFFC414B4 /* DMA9 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA9_YCNT_CUR 0xFFC414B8 /* DMA9 Current Row Count (2D only) */
|
|
#define REG_DMA9_BWLCNT 0xFFC414C0 /* DMA9 Bandwidth Limit Count */
|
|
#define REG_DMA9_BWLCNT_CUR 0xFFC414C4 /* DMA9 Bandwidth Limit Count Current */
|
|
#define REG_DMA9_BWMCNT 0xFFC414C8 /* DMA9 Bandwidth Monitor Count */
|
|
#define REG_DMA9_BWMCNT_CUR 0xFFC414CC /* DMA9 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA10
|
|
========================= */
|
|
#define REG_DMA10_DSCPTR_NXT 0xFFC05000 /* DMA10 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA10_ADDRSTART 0xFFC05004 /* DMA10 Start Address of Current Buffer */
|
|
#define REG_DMA10_CFG 0xFFC05008 /* DMA10 Configuration Register */
|
|
#define REG_DMA10_XCNT 0xFFC0500C /* DMA10 Inner Loop Count Start Value */
|
|
#define REG_DMA10_XMOD 0xFFC05010 /* DMA10 Inner Loop Address Increment */
|
|
#define REG_DMA10_YCNT 0xFFC05014 /* DMA10 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA10_YMOD 0xFFC05018 /* DMA10 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA10_DSCPTR_CUR 0xFFC05024 /* DMA10 Current Descriptor Pointer */
|
|
#define REG_DMA10_DSCPTR_PRV 0xFFC05028 /* DMA10 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA10_ADDR_CUR 0xFFC0502C /* DMA10 Current Address */
|
|
#define REG_DMA10_STAT 0xFFC05030 /* DMA10 Status Register */
|
|
#define REG_DMA10_XCNT_CUR 0xFFC05034 /* DMA10 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA10_YCNT_CUR 0xFFC05038 /* DMA10 Current Row Count (2D only) */
|
|
#define REG_DMA10_BWLCNT 0xFFC05040 /* DMA10 Bandwidth Limit Count */
|
|
#define REG_DMA10_BWLCNT_CUR 0xFFC05044 /* DMA10 Bandwidth Limit Count Current */
|
|
#define REG_DMA10_BWMCNT 0xFFC05048 /* DMA10 Bandwidth Monitor Count */
|
|
#define REG_DMA10_BWMCNT_CUR 0xFFC0504C /* DMA10 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA11
|
|
========================= */
|
|
#define REG_DMA11_DSCPTR_NXT 0xFFC05080 /* DMA11 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA11_ADDRSTART 0xFFC05084 /* DMA11 Start Address of Current Buffer */
|
|
#define REG_DMA11_CFG 0xFFC05088 /* DMA11 Configuration Register */
|
|
#define REG_DMA11_XCNT 0xFFC0508C /* DMA11 Inner Loop Count Start Value */
|
|
#define REG_DMA11_XMOD 0xFFC05090 /* DMA11 Inner Loop Address Increment */
|
|
#define REG_DMA11_YCNT 0xFFC05094 /* DMA11 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA11_YMOD 0xFFC05098 /* DMA11 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA11_DSCPTR_CUR 0xFFC050A4 /* DMA11 Current Descriptor Pointer */
|
|
#define REG_DMA11_DSCPTR_PRV 0xFFC050A8 /* DMA11 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA11_ADDR_CUR 0xFFC050AC /* DMA11 Current Address */
|
|
#define REG_DMA11_STAT 0xFFC050B0 /* DMA11 Status Register */
|
|
#define REG_DMA11_XCNT_CUR 0xFFC050B4 /* DMA11 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA11_YCNT_CUR 0xFFC050B8 /* DMA11 Current Row Count (2D only) */
|
|
#define REG_DMA11_BWLCNT 0xFFC050C0 /* DMA11 Bandwidth Limit Count */
|
|
#define REG_DMA11_BWLCNT_CUR 0xFFC050C4 /* DMA11 Bandwidth Limit Count Current */
|
|
#define REG_DMA11_BWMCNT 0xFFC050C8 /* DMA11 Bandwidth Monitor Count */
|
|
#define REG_DMA11_BWMCNT_CUR 0xFFC050CC /* DMA11 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA12
|
|
========================= */
|
|
#define REG_DMA12_DSCPTR_NXT 0xFFC05100 /* DMA12 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA12_ADDRSTART 0xFFC05104 /* DMA12 Start Address of Current Buffer */
|
|
#define REG_DMA12_CFG 0xFFC05108 /* DMA12 Configuration Register */
|
|
#define REG_DMA12_XCNT 0xFFC0510C /* DMA12 Inner Loop Count Start Value */
|
|
#define REG_DMA12_XMOD 0xFFC05110 /* DMA12 Inner Loop Address Increment */
|
|
#define REG_DMA12_YCNT 0xFFC05114 /* DMA12 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA12_YMOD 0xFFC05118 /* DMA12 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA12_DSCPTR_CUR 0xFFC05124 /* DMA12 Current Descriptor Pointer */
|
|
#define REG_DMA12_DSCPTR_PRV 0xFFC05128 /* DMA12 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA12_ADDR_CUR 0xFFC0512C /* DMA12 Current Address */
|
|
#define REG_DMA12_STAT 0xFFC05130 /* DMA12 Status Register */
|
|
#define REG_DMA12_XCNT_CUR 0xFFC05134 /* DMA12 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA12_YCNT_CUR 0xFFC05138 /* DMA12 Current Row Count (2D only) */
|
|
#define REG_DMA12_BWLCNT 0xFFC05140 /* DMA12 Bandwidth Limit Count */
|
|
#define REG_DMA12_BWLCNT_CUR 0xFFC05144 /* DMA12 Bandwidth Limit Count Current */
|
|
#define REG_DMA12_BWMCNT 0xFFC05148 /* DMA12 Bandwidth Monitor Count */
|
|
#define REG_DMA12_BWMCNT_CUR 0xFFC0514C /* DMA12 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA13
|
|
========================= */
|
|
#define REG_DMA13_DSCPTR_NXT 0xFFC07000 /* DMA13 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA13_ADDRSTART 0xFFC07004 /* DMA13 Start Address of Current Buffer */
|
|
#define REG_DMA13_CFG 0xFFC07008 /* DMA13 Configuration Register */
|
|
#define REG_DMA13_XCNT 0xFFC0700C /* DMA13 Inner Loop Count Start Value */
|
|
#define REG_DMA13_XMOD 0xFFC07010 /* DMA13 Inner Loop Address Increment */
|
|
#define REG_DMA13_YCNT 0xFFC07014 /* DMA13 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA13_YMOD 0xFFC07018 /* DMA13 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA13_DSCPTR_CUR 0xFFC07024 /* DMA13 Current Descriptor Pointer */
|
|
#define REG_DMA13_DSCPTR_PRV 0xFFC07028 /* DMA13 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA13_ADDR_CUR 0xFFC0702C /* DMA13 Current Address */
|
|
#define REG_DMA13_STAT 0xFFC07030 /* DMA13 Status Register */
|
|
#define REG_DMA13_XCNT_CUR 0xFFC07034 /* DMA13 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA13_YCNT_CUR 0xFFC07038 /* DMA13 Current Row Count (2D only) */
|
|
#define REG_DMA13_BWLCNT 0xFFC07040 /* DMA13 Bandwidth Limit Count */
|
|
#define REG_DMA13_BWLCNT_CUR 0xFFC07044 /* DMA13 Bandwidth Limit Count Current */
|
|
#define REG_DMA13_BWMCNT 0xFFC07048 /* DMA13 Bandwidth Monitor Count */
|
|
#define REG_DMA13_BWMCNT_CUR 0xFFC0704C /* DMA13 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA14
|
|
========================= */
|
|
#define REG_DMA14_DSCPTR_NXT 0xFFC07080 /* DMA14 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA14_ADDRSTART 0xFFC07084 /* DMA14 Start Address of Current Buffer */
|
|
#define REG_DMA14_CFG 0xFFC07088 /* DMA14 Configuration Register */
|
|
#define REG_DMA14_XCNT 0xFFC0708C /* DMA14 Inner Loop Count Start Value */
|
|
#define REG_DMA14_XMOD 0xFFC07090 /* DMA14 Inner Loop Address Increment */
|
|
#define REG_DMA14_YCNT 0xFFC07094 /* DMA14 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA14_YMOD 0xFFC07098 /* DMA14 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA14_DSCPTR_CUR 0xFFC070A4 /* DMA14 Current Descriptor Pointer */
|
|
#define REG_DMA14_DSCPTR_PRV 0xFFC070A8 /* DMA14 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA14_ADDR_CUR 0xFFC070AC /* DMA14 Current Address */
|
|
#define REG_DMA14_STAT 0xFFC070B0 /* DMA14 Status Register */
|
|
#define REG_DMA14_XCNT_CUR 0xFFC070B4 /* DMA14 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA14_YCNT_CUR 0xFFC070B8 /* DMA14 Current Row Count (2D only) */
|
|
#define REG_DMA14_BWLCNT 0xFFC070C0 /* DMA14 Bandwidth Limit Count */
|
|
#define REG_DMA14_BWLCNT_CUR 0xFFC070C4 /* DMA14 Bandwidth Limit Count Current */
|
|
#define REG_DMA14_BWMCNT 0xFFC070C8 /* DMA14 Bandwidth Monitor Count */
|
|
#define REG_DMA14_BWMCNT_CUR 0xFFC070CC /* DMA14 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA15
|
|
========================= */
|
|
#define REG_DMA15_DSCPTR_NXT 0xFFC07100 /* DMA15 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA15_ADDRSTART 0xFFC07104 /* DMA15 Start Address of Current Buffer */
|
|
#define REG_DMA15_CFG 0xFFC07108 /* DMA15 Configuration Register */
|
|
#define REG_DMA15_XCNT 0xFFC0710C /* DMA15 Inner Loop Count Start Value */
|
|
#define REG_DMA15_XMOD 0xFFC07110 /* DMA15 Inner Loop Address Increment */
|
|
#define REG_DMA15_YCNT 0xFFC07114 /* DMA15 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA15_YMOD 0xFFC07118 /* DMA15 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA15_DSCPTR_CUR 0xFFC07124 /* DMA15 Current Descriptor Pointer */
|
|
#define REG_DMA15_DSCPTR_PRV 0xFFC07128 /* DMA15 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA15_ADDR_CUR 0xFFC0712C /* DMA15 Current Address */
|
|
#define REG_DMA15_STAT 0xFFC07130 /* DMA15 Status Register */
|
|
#define REG_DMA15_XCNT_CUR 0xFFC07134 /* DMA15 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA15_YCNT_CUR 0xFFC07138 /* DMA15 Current Row Count (2D only) */
|
|
#define REG_DMA15_BWLCNT 0xFFC07140 /* DMA15 Bandwidth Limit Count */
|
|
#define REG_DMA15_BWLCNT_CUR 0xFFC07144 /* DMA15 Bandwidth Limit Count Current */
|
|
#define REG_DMA15_BWMCNT 0xFFC07148 /* DMA15 Bandwidth Monitor Count */
|
|
#define REG_DMA15_BWMCNT_CUR 0xFFC0714C /* DMA15 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA16
|
|
========================= */
|
|
#define REG_DMA16_DSCPTR_NXT 0xFFC07180 /* DMA16 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA16_ADDRSTART 0xFFC07184 /* DMA16 Start Address of Current Buffer */
|
|
#define REG_DMA16_CFG 0xFFC07188 /* DMA16 Configuration Register */
|
|
#define REG_DMA16_XCNT 0xFFC0718C /* DMA16 Inner Loop Count Start Value */
|
|
#define REG_DMA16_XMOD 0xFFC07190 /* DMA16 Inner Loop Address Increment */
|
|
#define REG_DMA16_YCNT 0xFFC07194 /* DMA16 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA16_YMOD 0xFFC07198 /* DMA16 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA16_DSCPTR_CUR 0xFFC071A4 /* DMA16 Current Descriptor Pointer */
|
|
#define REG_DMA16_DSCPTR_PRV 0xFFC071A8 /* DMA16 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA16_ADDR_CUR 0xFFC071AC /* DMA16 Current Address */
|
|
#define REG_DMA16_STAT 0xFFC071B0 /* DMA16 Status Register */
|
|
#define REG_DMA16_XCNT_CUR 0xFFC071B4 /* DMA16 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA16_YCNT_CUR 0xFFC071B8 /* DMA16 Current Row Count (2D only) */
|
|
#define REG_DMA16_BWLCNT 0xFFC071C0 /* DMA16 Bandwidth Limit Count */
|
|
#define REG_DMA16_BWLCNT_CUR 0xFFC071C4 /* DMA16 Bandwidth Limit Count Current */
|
|
#define REG_DMA16_BWMCNT 0xFFC071C8 /* DMA16 Bandwidth Monitor Count */
|
|
#define REG_DMA16_BWMCNT_CUR 0xFFC071CC /* DMA16 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA17
|
|
========================= */
|
|
#define REG_DMA17_DSCPTR_NXT 0xFFC07200 /* DMA17 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA17_ADDRSTART 0xFFC07204 /* DMA17 Start Address of Current Buffer */
|
|
#define REG_DMA17_CFG 0xFFC07208 /* DMA17 Configuration Register */
|
|
#define REG_DMA17_XCNT 0xFFC0720C /* DMA17 Inner Loop Count Start Value */
|
|
#define REG_DMA17_XMOD 0xFFC07210 /* DMA17 Inner Loop Address Increment */
|
|
#define REG_DMA17_YCNT 0xFFC07214 /* DMA17 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA17_YMOD 0xFFC07218 /* DMA17 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA17_DSCPTR_CUR 0xFFC07224 /* DMA17 Current Descriptor Pointer */
|
|
#define REG_DMA17_DSCPTR_PRV 0xFFC07228 /* DMA17 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA17_ADDR_CUR 0xFFC0722C /* DMA17 Current Address */
|
|
#define REG_DMA17_STAT 0xFFC07230 /* DMA17 Status Register */
|
|
#define REG_DMA17_XCNT_CUR 0xFFC07234 /* DMA17 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA17_YCNT_CUR 0xFFC07238 /* DMA17 Current Row Count (2D only) */
|
|
#define REG_DMA17_BWLCNT 0xFFC07240 /* DMA17 Bandwidth Limit Count */
|
|
#define REG_DMA17_BWLCNT_CUR 0xFFC07244 /* DMA17 Bandwidth Limit Count Current */
|
|
#define REG_DMA17_BWMCNT 0xFFC07248 /* DMA17 Bandwidth Monitor Count */
|
|
#define REG_DMA17_BWMCNT_CUR 0xFFC0724C /* DMA17 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA18
|
|
========================= */
|
|
#define REG_DMA18_DSCPTR_NXT 0xFFC07280 /* DMA18 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA18_ADDRSTART 0xFFC07284 /* DMA18 Start Address of Current Buffer */
|
|
#define REG_DMA18_CFG 0xFFC07288 /* DMA18 Configuration Register */
|
|
#define REG_DMA18_XCNT 0xFFC0728C /* DMA18 Inner Loop Count Start Value */
|
|
#define REG_DMA18_XMOD 0xFFC07290 /* DMA18 Inner Loop Address Increment */
|
|
#define REG_DMA18_YCNT 0xFFC07294 /* DMA18 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA18_YMOD 0xFFC07298 /* DMA18 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA18_DSCPTR_CUR 0xFFC072A4 /* DMA18 Current Descriptor Pointer */
|
|
#define REG_DMA18_DSCPTR_PRV 0xFFC072A8 /* DMA18 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA18_ADDR_CUR 0xFFC072AC /* DMA18 Current Address */
|
|
#define REG_DMA18_STAT 0xFFC072B0 /* DMA18 Status Register */
|
|
#define REG_DMA18_XCNT_CUR 0xFFC072B4 /* DMA18 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA18_YCNT_CUR 0xFFC072B8 /* DMA18 Current Row Count (2D only) */
|
|
#define REG_DMA18_BWLCNT 0xFFC072C0 /* DMA18 Bandwidth Limit Count */
|
|
#define REG_DMA18_BWLCNT_CUR 0xFFC072C4 /* DMA18 Bandwidth Limit Count Current */
|
|
#define REG_DMA18_BWMCNT 0xFFC072C8 /* DMA18 Bandwidth Monitor Count */
|
|
#define REG_DMA18_BWMCNT_CUR 0xFFC072CC /* DMA18 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA19
|
|
========================= */
|
|
#define REG_DMA19_DSCPTR_NXT 0xFFC07300 /* DMA19 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA19_ADDRSTART 0xFFC07304 /* DMA19 Start Address of Current Buffer */
|
|
#define REG_DMA19_CFG 0xFFC07308 /* DMA19 Configuration Register */
|
|
#define REG_DMA19_XCNT 0xFFC0730C /* DMA19 Inner Loop Count Start Value */
|
|
#define REG_DMA19_XMOD 0xFFC07310 /* DMA19 Inner Loop Address Increment */
|
|
#define REG_DMA19_YCNT 0xFFC07314 /* DMA19 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA19_YMOD 0xFFC07318 /* DMA19 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA19_DSCPTR_CUR 0xFFC07324 /* DMA19 Current Descriptor Pointer */
|
|
#define REG_DMA19_DSCPTR_PRV 0xFFC07328 /* DMA19 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA19_ADDR_CUR 0xFFC0732C /* DMA19 Current Address */
|
|
#define REG_DMA19_STAT 0xFFC07330 /* DMA19 Status Register */
|
|
#define REG_DMA19_XCNT_CUR 0xFFC07334 /* DMA19 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA19_YCNT_CUR 0xFFC07338 /* DMA19 Current Row Count (2D only) */
|
|
#define REG_DMA19_BWLCNT 0xFFC07340 /* DMA19 Bandwidth Limit Count */
|
|
#define REG_DMA19_BWLCNT_CUR 0xFFC07344 /* DMA19 Bandwidth Limit Count Current */
|
|
#define REG_DMA19_BWMCNT 0xFFC07348 /* DMA19 Bandwidth Monitor Count */
|
|
#define REG_DMA19_BWMCNT_CUR 0xFFC0734C /* DMA19 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA20
|
|
========================= */
|
|
#define REG_DMA20_DSCPTR_NXT 0xFFC07380 /* DMA20 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA20_ADDRSTART 0xFFC07384 /* DMA20 Start Address of Current Buffer */
|
|
#define REG_DMA20_CFG 0xFFC07388 /* DMA20 Configuration Register */
|
|
#define REG_DMA20_XCNT 0xFFC0738C /* DMA20 Inner Loop Count Start Value */
|
|
#define REG_DMA20_XMOD 0xFFC07390 /* DMA20 Inner Loop Address Increment */
|
|
#define REG_DMA20_YCNT 0xFFC07394 /* DMA20 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA20_YMOD 0xFFC07398 /* DMA20 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA20_DSCPTR_CUR 0xFFC073A4 /* DMA20 Current Descriptor Pointer */
|
|
#define REG_DMA20_DSCPTR_PRV 0xFFC073A8 /* DMA20 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA20_ADDR_CUR 0xFFC073AC /* DMA20 Current Address */
|
|
#define REG_DMA20_STAT 0xFFC073B0 /* DMA20 Status Register */
|
|
#define REG_DMA20_XCNT_CUR 0xFFC073B4 /* DMA20 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA20_YCNT_CUR 0xFFC073B8 /* DMA20 Current Row Count (2D only) */
|
|
#define REG_DMA20_BWLCNT 0xFFC073C0 /* DMA20 Bandwidth Limit Count */
|
|
#define REG_DMA20_BWLCNT_CUR 0xFFC073C4 /* DMA20 Bandwidth Limit Count Current */
|
|
#define REG_DMA20_BWMCNT 0xFFC073C8 /* DMA20 Bandwidth Monitor Count */
|
|
#define REG_DMA20_BWMCNT_CUR 0xFFC073CC /* DMA20 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA21
|
|
========================= */
|
|
#define REG_DMA21_DSCPTR_NXT 0xFFC09000 /* DMA21 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA21_ADDRSTART 0xFFC09004 /* DMA21 Start Address of Current Buffer */
|
|
#define REG_DMA21_CFG 0xFFC09008 /* DMA21 Configuration Register */
|
|
#define REG_DMA21_XCNT 0xFFC0900C /* DMA21 Inner Loop Count Start Value */
|
|
#define REG_DMA21_XMOD 0xFFC09010 /* DMA21 Inner Loop Address Increment */
|
|
#define REG_DMA21_YCNT 0xFFC09014 /* DMA21 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA21_YMOD 0xFFC09018 /* DMA21 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA21_DSCPTR_CUR 0xFFC09024 /* DMA21 Current Descriptor Pointer */
|
|
#define REG_DMA21_DSCPTR_PRV 0xFFC09028 /* DMA21 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA21_ADDR_CUR 0xFFC0902C /* DMA21 Current Address */
|
|
#define REG_DMA21_STAT 0xFFC09030 /* DMA21 Status Register */
|
|
#define REG_DMA21_XCNT_CUR 0xFFC09034 /* DMA21 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA21_YCNT_CUR 0xFFC09038 /* DMA21 Current Row Count (2D only) */
|
|
#define REG_DMA21_BWLCNT 0xFFC09040 /* DMA21 Bandwidth Limit Count */
|
|
#define REG_DMA21_BWLCNT_CUR 0xFFC09044 /* DMA21 Bandwidth Limit Count Current */
|
|
#define REG_DMA21_BWMCNT 0xFFC09048 /* DMA21 Bandwidth Monitor Count */
|
|
#define REG_DMA21_BWMCNT_CUR 0xFFC0904C /* DMA21 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA22
|
|
========================= */
|
|
#define REG_DMA22_DSCPTR_NXT 0xFFC09080 /* DMA22 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA22_ADDRSTART 0xFFC09084 /* DMA22 Start Address of Current Buffer */
|
|
#define REG_DMA22_CFG 0xFFC09088 /* DMA22 Configuration Register */
|
|
#define REG_DMA22_XCNT 0xFFC0908C /* DMA22 Inner Loop Count Start Value */
|
|
#define REG_DMA22_XMOD 0xFFC09090 /* DMA22 Inner Loop Address Increment */
|
|
#define REG_DMA22_YCNT 0xFFC09094 /* DMA22 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA22_YMOD 0xFFC09098 /* DMA22 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA22_DSCPTR_CUR 0xFFC090A4 /* DMA22 Current Descriptor Pointer */
|
|
#define REG_DMA22_DSCPTR_PRV 0xFFC090A8 /* DMA22 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA22_ADDR_CUR 0xFFC090AC /* DMA22 Current Address */
|
|
#define REG_DMA22_STAT 0xFFC090B0 /* DMA22 Status Register */
|
|
#define REG_DMA22_XCNT_CUR 0xFFC090B4 /* DMA22 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA22_YCNT_CUR 0xFFC090B8 /* DMA22 Current Row Count (2D only) */
|
|
#define REG_DMA22_BWLCNT 0xFFC090C0 /* DMA22 Bandwidth Limit Count */
|
|
#define REG_DMA22_BWLCNT_CUR 0xFFC090C4 /* DMA22 Bandwidth Limit Count Current */
|
|
#define REG_DMA22_BWMCNT 0xFFC090C8 /* DMA22 Bandwidth Monitor Count */
|
|
#define REG_DMA22_BWMCNT_CUR 0xFFC090CC /* DMA22 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA23
|
|
========================= */
|
|
#define REG_DMA23_DSCPTR_NXT 0xFFC09100 /* DMA23 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA23_ADDRSTART 0xFFC09104 /* DMA23 Start Address of Current Buffer */
|
|
#define REG_DMA23_CFG 0xFFC09108 /* DMA23 Configuration Register */
|
|
#define REG_DMA23_XCNT 0xFFC0910C /* DMA23 Inner Loop Count Start Value */
|
|
#define REG_DMA23_XMOD 0xFFC09110 /* DMA23 Inner Loop Address Increment */
|
|
#define REG_DMA23_YCNT 0xFFC09114 /* DMA23 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA23_YMOD 0xFFC09118 /* DMA23 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA23_DSCPTR_CUR 0xFFC09124 /* DMA23 Current Descriptor Pointer */
|
|
#define REG_DMA23_DSCPTR_PRV 0xFFC09128 /* DMA23 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA23_ADDR_CUR 0xFFC0912C /* DMA23 Current Address */
|
|
#define REG_DMA23_STAT 0xFFC09130 /* DMA23 Status Register */
|
|
#define REG_DMA23_XCNT_CUR 0xFFC09134 /* DMA23 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA23_YCNT_CUR 0xFFC09138 /* DMA23 Current Row Count (2D only) */
|
|
#define REG_DMA23_BWLCNT 0xFFC09140 /* DMA23 Bandwidth Limit Count */
|
|
#define REG_DMA23_BWLCNT_CUR 0xFFC09144 /* DMA23 Bandwidth Limit Count Current */
|
|
#define REG_DMA23_BWMCNT 0xFFC09148 /* DMA23 Bandwidth Monitor Count */
|
|
#define REG_DMA23_BWMCNT_CUR 0xFFC0914C /* DMA23 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA24
|
|
========================= */
|
|
#define REG_DMA24_DSCPTR_NXT 0xFFC09180 /* DMA24 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA24_ADDRSTART 0xFFC09184 /* DMA24 Start Address of Current Buffer */
|
|
#define REG_DMA24_CFG 0xFFC09188 /* DMA24 Configuration Register */
|
|
#define REG_DMA24_XCNT 0xFFC0918C /* DMA24 Inner Loop Count Start Value */
|
|
#define REG_DMA24_XMOD 0xFFC09190 /* DMA24 Inner Loop Address Increment */
|
|
#define REG_DMA24_YCNT 0xFFC09194 /* DMA24 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA24_YMOD 0xFFC09198 /* DMA24 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA24_DSCPTR_CUR 0xFFC091A4 /* DMA24 Current Descriptor Pointer */
|
|
#define REG_DMA24_DSCPTR_PRV 0xFFC091A8 /* DMA24 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA24_ADDR_CUR 0xFFC091AC /* DMA24 Current Address */
|
|
#define REG_DMA24_STAT 0xFFC091B0 /* DMA24 Status Register */
|
|
#define REG_DMA24_XCNT_CUR 0xFFC091B4 /* DMA24 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA24_YCNT_CUR 0xFFC091B8 /* DMA24 Current Row Count (2D only) */
|
|
#define REG_DMA24_BWLCNT 0xFFC091C0 /* DMA24 Bandwidth Limit Count */
|
|
#define REG_DMA24_BWLCNT_CUR 0xFFC091C4 /* DMA24 Bandwidth Limit Count Current */
|
|
#define REG_DMA24_BWMCNT 0xFFC091C8 /* DMA24 Bandwidth Monitor Count */
|
|
#define REG_DMA24_BWMCNT_CUR 0xFFC091CC /* DMA24 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA25
|
|
========================= */
|
|
#define REG_DMA25_DSCPTR_NXT 0xFFC09200 /* DMA25 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA25_ADDRSTART 0xFFC09204 /* DMA25 Start Address of Current Buffer */
|
|
#define REG_DMA25_CFG 0xFFC09208 /* DMA25 Configuration Register */
|
|
#define REG_DMA25_XCNT 0xFFC0920C /* DMA25 Inner Loop Count Start Value */
|
|
#define REG_DMA25_XMOD 0xFFC09210 /* DMA25 Inner Loop Address Increment */
|
|
#define REG_DMA25_YCNT 0xFFC09214 /* DMA25 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA25_YMOD 0xFFC09218 /* DMA25 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA25_DSCPTR_CUR 0xFFC09224 /* DMA25 Current Descriptor Pointer */
|
|
#define REG_DMA25_DSCPTR_PRV 0xFFC09228 /* DMA25 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA25_ADDR_CUR 0xFFC0922C /* DMA25 Current Address */
|
|
#define REG_DMA25_STAT 0xFFC09230 /* DMA25 Status Register */
|
|
#define REG_DMA25_XCNT_CUR 0xFFC09234 /* DMA25 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA25_YCNT_CUR 0xFFC09238 /* DMA25 Current Row Count (2D only) */
|
|
#define REG_DMA25_BWLCNT 0xFFC09240 /* DMA25 Bandwidth Limit Count */
|
|
#define REG_DMA25_BWLCNT_CUR 0xFFC09244 /* DMA25 Bandwidth Limit Count Current */
|
|
#define REG_DMA25_BWMCNT 0xFFC09248 /* DMA25 Bandwidth Monitor Count */
|
|
#define REG_DMA25_BWMCNT_CUR 0xFFC0924C /* DMA25 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA26
|
|
========================= */
|
|
#define REG_DMA26_DSCPTR_NXT 0xFFC09280 /* DMA26 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA26_ADDRSTART 0xFFC09284 /* DMA26 Start Address of Current Buffer */
|
|
#define REG_DMA26_CFG 0xFFC09288 /* DMA26 Configuration Register */
|
|
#define REG_DMA26_XCNT 0xFFC0928C /* DMA26 Inner Loop Count Start Value */
|
|
#define REG_DMA26_XMOD 0xFFC09290 /* DMA26 Inner Loop Address Increment */
|
|
#define REG_DMA26_YCNT 0xFFC09294 /* DMA26 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA26_YMOD 0xFFC09298 /* DMA26 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA26_DSCPTR_CUR 0xFFC092A4 /* DMA26 Current Descriptor Pointer */
|
|
#define REG_DMA26_DSCPTR_PRV 0xFFC092A8 /* DMA26 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA26_ADDR_CUR 0xFFC092AC /* DMA26 Current Address */
|
|
#define REG_DMA26_STAT 0xFFC092B0 /* DMA26 Status Register */
|
|
#define REG_DMA26_XCNT_CUR 0xFFC092B4 /* DMA26 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA26_YCNT_CUR 0xFFC092B8 /* DMA26 Current Row Count (2D only) */
|
|
#define REG_DMA26_BWLCNT 0xFFC092C0 /* DMA26 Bandwidth Limit Count */
|
|
#define REG_DMA26_BWLCNT_CUR 0xFFC092C4 /* DMA26 Bandwidth Limit Count Current */
|
|
#define REG_DMA26_BWMCNT 0xFFC092C8 /* DMA26 Bandwidth Monitor Count */
|
|
#define REG_DMA26_BWMCNT_CUR 0xFFC092CC /* DMA26 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA27
|
|
========================= */
|
|
#define REG_DMA27_DSCPTR_NXT 0xFFC09300 /* DMA27 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA27_ADDRSTART 0xFFC09304 /* DMA27 Start Address of Current Buffer */
|
|
#define REG_DMA27_CFG 0xFFC09308 /* DMA27 Configuration Register */
|
|
#define REG_DMA27_XCNT 0xFFC0930C /* DMA27 Inner Loop Count Start Value */
|
|
#define REG_DMA27_XMOD 0xFFC09310 /* DMA27 Inner Loop Address Increment */
|
|
#define REG_DMA27_YCNT 0xFFC09314 /* DMA27 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA27_YMOD 0xFFC09318 /* DMA27 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA27_DSCPTR_CUR 0xFFC09324 /* DMA27 Current Descriptor Pointer */
|
|
#define REG_DMA27_DSCPTR_PRV 0xFFC09328 /* DMA27 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA27_ADDR_CUR 0xFFC0932C /* DMA27 Current Address */
|
|
#define REG_DMA27_STAT 0xFFC09330 /* DMA27 Status Register */
|
|
#define REG_DMA27_XCNT_CUR 0xFFC09334 /* DMA27 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA27_YCNT_CUR 0xFFC09338 /* DMA27 Current Row Count (2D only) */
|
|
#define REG_DMA27_BWLCNT 0xFFC09340 /* DMA27 Bandwidth Limit Count */
|
|
#define REG_DMA27_BWLCNT_CUR 0xFFC09344 /* DMA27 Bandwidth Limit Count Current */
|
|
#define REG_DMA27_BWMCNT 0xFFC09348 /* DMA27 Bandwidth Monitor Count */
|
|
#define REG_DMA27_BWMCNT_CUR 0xFFC0934C /* DMA27 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA28
|
|
========================= */
|
|
#define REG_DMA28_DSCPTR_NXT 0xFFC09380 /* DMA28 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA28_ADDRSTART 0xFFC09384 /* DMA28 Start Address of Current Buffer */
|
|
#define REG_DMA28_CFG 0xFFC09388 /* DMA28 Configuration Register */
|
|
#define REG_DMA28_XCNT 0xFFC0938C /* DMA28 Inner Loop Count Start Value */
|
|
#define REG_DMA28_XMOD 0xFFC09390 /* DMA28 Inner Loop Address Increment */
|
|
#define REG_DMA28_YCNT 0xFFC09394 /* DMA28 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA28_YMOD 0xFFC09398 /* DMA28 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA28_DSCPTR_CUR 0xFFC093A4 /* DMA28 Current Descriptor Pointer */
|
|
#define REG_DMA28_DSCPTR_PRV 0xFFC093A8 /* DMA28 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA28_ADDR_CUR 0xFFC093AC /* DMA28 Current Address */
|
|
#define REG_DMA28_STAT 0xFFC093B0 /* DMA28 Status Register */
|
|
#define REG_DMA28_XCNT_CUR 0xFFC093B4 /* DMA28 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA28_YCNT_CUR 0xFFC093B8 /* DMA28 Current Row Count (2D only) */
|
|
#define REG_DMA28_BWLCNT 0xFFC093C0 /* DMA28 Bandwidth Limit Count */
|
|
#define REG_DMA28_BWLCNT_CUR 0xFFC093C4 /* DMA28 Bandwidth Limit Count Current */
|
|
#define REG_DMA28_BWMCNT 0xFFC093C8 /* DMA28 Bandwidth Monitor Count */
|
|
#define REG_DMA28_BWMCNT_CUR 0xFFC093CC /* DMA28 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA29
|
|
========================= */
|
|
#define REG_DMA29_DSCPTR_NXT 0xFFC0B000 /* DMA29 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA29_ADDRSTART 0xFFC0B004 /* DMA29 Start Address of Current Buffer */
|
|
#define REG_DMA29_CFG 0xFFC0B008 /* DMA29 Configuration Register */
|
|
#define REG_DMA29_XCNT 0xFFC0B00C /* DMA29 Inner Loop Count Start Value */
|
|
#define REG_DMA29_XMOD 0xFFC0B010 /* DMA29 Inner Loop Address Increment */
|
|
#define REG_DMA29_YCNT 0xFFC0B014 /* DMA29 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA29_YMOD 0xFFC0B018 /* DMA29 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA29_DSCPTR_CUR 0xFFC0B024 /* DMA29 Current Descriptor Pointer */
|
|
#define REG_DMA29_DSCPTR_PRV 0xFFC0B028 /* DMA29 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA29_ADDR_CUR 0xFFC0B02C /* DMA29 Current Address */
|
|
#define REG_DMA29_STAT 0xFFC0B030 /* DMA29 Status Register */
|
|
#define REG_DMA29_XCNT_CUR 0xFFC0B034 /* DMA29 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA29_YCNT_CUR 0xFFC0B038 /* DMA29 Current Row Count (2D only) */
|
|
#define REG_DMA29_BWLCNT 0xFFC0B040 /* DMA29 Bandwidth Limit Count */
|
|
#define REG_DMA29_BWLCNT_CUR 0xFFC0B044 /* DMA29 Bandwidth Limit Count Current */
|
|
#define REG_DMA29_BWMCNT 0xFFC0B048 /* DMA29 Bandwidth Monitor Count */
|
|
#define REG_DMA29_BWMCNT_CUR 0xFFC0B04C /* DMA29 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA30
|
|
========================= */
|
|
#define REG_DMA30_DSCPTR_NXT 0xFFC0B080 /* DMA30 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA30_ADDRSTART 0xFFC0B084 /* DMA30 Start Address of Current Buffer */
|
|
#define REG_DMA30_CFG 0xFFC0B088 /* DMA30 Configuration Register */
|
|
#define REG_DMA30_XCNT 0xFFC0B08C /* DMA30 Inner Loop Count Start Value */
|
|
#define REG_DMA30_XMOD 0xFFC0B090 /* DMA30 Inner Loop Address Increment */
|
|
#define REG_DMA30_YCNT 0xFFC0B094 /* DMA30 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA30_YMOD 0xFFC0B098 /* DMA30 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA30_DSCPTR_CUR 0xFFC0B0A4 /* DMA30 Current Descriptor Pointer */
|
|
#define REG_DMA30_DSCPTR_PRV 0xFFC0B0A8 /* DMA30 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA30_ADDR_CUR 0xFFC0B0AC /* DMA30 Current Address */
|
|
#define REG_DMA30_STAT 0xFFC0B0B0 /* DMA30 Status Register */
|
|
#define REG_DMA30_XCNT_CUR 0xFFC0B0B4 /* DMA30 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA30_YCNT_CUR 0xFFC0B0B8 /* DMA30 Current Row Count (2D only) */
|
|
#define REG_DMA30_BWLCNT 0xFFC0B0C0 /* DMA30 Bandwidth Limit Count */
|
|
#define REG_DMA30_BWLCNT_CUR 0xFFC0B0C4 /* DMA30 Bandwidth Limit Count Current */
|
|
#define REG_DMA30_BWMCNT 0xFFC0B0C8 /* DMA30 Bandwidth Monitor Count */
|
|
#define REG_DMA30_BWMCNT_CUR 0xFFC0B0CC /* DMA30 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA31
|
|
========================= */
|
|
#define REG_DMA31_DSCPTR_NXT 0xFFC0B100 /* DMA31 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA31_ADDRSTART 0xFFC0B104 /* DMA31 Start Address of Current Buffer */
|
|
#define REG_DMA31_CFG 0xFFC0B108 /* DMA31 Configuration Register */
|
|
#define REG_DMA31_XCNT 0xFFC0B10C /* DMA31 Inner Loop Count Start Value */
|
|
#define REG_DMA31_XMOD 0xFFC0B110 /* DMA31 Inner Loop Address Increment */
|
|
#define REG_DMA31_YCNT 0xFFC0B114 /* DMA31 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA31_YMOD 0xFFC0B118 /* DMA31 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA31_DSCPTR_CUR 0xFFC0B124 /* DMA31 Current Descriptor Pointer */
|
|
#define REG_DMA31_DSCPTR_PRV 0xFFC0B128 /* DMA31 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA31_ADDR_CUR 0xFFC0B12C /* DMA31 Current Address */
|
|
#define REG_DMA31_STAT 0xFFC0B130 /* DMA31 Status Register */
|
|
#define REG_DMA31_XCNT_CUR 0xFFC0B134 /* DMA31 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA31_YCNT_CUR 0xFFC0B138 /* DMA31 Current Row Count (2D only) */
|
|
#define REG_DMA31_BWLCNT 0xFFC0B140 /* DMA31 Bandwidth Limit Count */
|
|
#define REG_DMA31_BWLCNT_CUR 0xFFC0B144 /* DMA31 Bandwidth Limit Count Current */
|
|
#define REG_DMA31_BWMCNT 0xFFC0B148 /* DMA31 Bandwidth Monitor Count */
|
|
#define REG_DMA31_BWMCNT_CUR 0xFFC0B14C /* DMA31 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA32
|
|
========================= */
|
|
#define REG_DMA32_DSCPTR_NXT 0xFFC0B180 /* DMA32 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA32_ADDRSTART 0xFFC0B184 /* DMA32 Start Address of Current Buffer */
|
|
#define REG_DMA32_CFG 0xFFC0B188 /* DMA32 Configuration Register */
|
|
#define REG_DMA32_XCNT 0xFFC0B18C /* DMA32 Inner Loop Count Start Value */
|
|
#define REG_DMA32_XMOD 0xFFC0B190 /* DMA32 Inner Loop Address Increment */
|
|
#define REG_DMA32_YCNT 0xFFC0B194 /* DMA32 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA32_YMOD 0xFFC0B198 /* DMA32 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA32_DSCPTR_CUR 0xFFC0B1A4 /* DMA32 Current Descriptor Pointer */
|
|
#define REG_DMA32_DSCPTR_PRV 0xFFC0B1A8 /* DMA32 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA32_ADDR_CUR 0xFFC0B1AC /* DMA32 Current Address */
|
|
#define REG_DMA32_STAT 0xFFC0B1B0 /* DMA32 Status Register */
|
|
#define REG_DMA32_XCNT_CUR 0xFFC0B1B4 /* DMA32 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA32_YCNT_CUR 0xFFC0B1B8 /* DMA32 Current Row Count (2D only) */
|
|
#define REG_DMA32_BWLCNT 0xFFC0B1C0 /* DMA32 Bandwidth Limit Count */
|
|
#define REG_DMA32_BWLCNT_CUR 0xFFC0B1C4 /* DMA32 Bandwidth Limit Count Current */
|
|
#define REG_DMA32_BWMCNT 0xFFC0B1C8 /* DMA32 Bandwidth Monitor Count */
|
|
#define REG_DMA32_BWMCNT_CUR 0xFFC0B1CC /* DMA32 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA33
|
|
========================= */
|
|
#define REG_DMA33_DSCPTR_NXT 0xFFC0D000 /* DMA33 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA33_ADDRSTART 0xFFC0D004 /* DMA33 Start Address of Current Buffer */
|
|
#define REG_DMA33_CFG 0xFFC0D008 /* DMA33 Configuration Register */
|
|
#define REG_DMA33_XCNT 0xFFC0D00C /* DMA33 Inner Loop Count Start Value */
|
|
#define REG_DMA33_XMOD 0xFFC0D010 /* DMA33 Inner Loop Address Increment */
|
|
#define REG_DMA33_YCNT 0xFFC0D014 /* DMA33 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA33_YMOD 0xFFC0D018 /* DMA33 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA33_DSCPTR_CUR 0xFFC0D024 /* DMA33 Current Descriptor Pointer */
|
|
#define REG_DMA33_DSCPTR_PRV 0xFFC0D028 /* DMA33 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA33_ADDR_CUR 0xFFC0D02C /* DMA33 Current Address */
|
|
#define REG_DMA33_STAT 0xFFC0D030 /* DMA33 Status Register */
|
|
#define REG_DMA33_XCNT_CUR 0xFFC0D034 /* DMA33 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA33_YCNT_CUR 0xFFC0D038 /* DMA33 Current Row Count (2D only) */
|
|
#define REG_DMA33_BWLCNT 0xFFC0D040 /* DMA33 Bandwidth Limit Count */
|
|
#define REG_DMA33_BWLCNT_CUR 0xFFC0D044 /* DMA33 Bandwidth Limit Count Current */
|
|
#define REG_DMA33_BWMCNT 0xFFC0D048 /* DMA33 Bandwidth Monitor Count */
|
|
#define REG_DMA33_BWMCNT_CUR 0xFFC0D04C /* DMA33 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA34
|
|
========================= */
|
|
#define REG_DMA34_DSCPTR_NXT 0xFFC0D080 /* DMA34 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA34_ADDRSTART 0xFFC0D084 /* DMA34 Start Address of Current Buffer */
|
|
#define REG_DMA34_CFG 0xFFC0D088 /* DMA34 Configuration Register */
|
|
#define REG_DMA34_XCNT 0xFFC0D08C /* DMA34 Inner Loop Count Start Value */
|
|
#define REG_DMA34_XMOD 0xFFC0D090 /* DMA34 Inner Loop Address Increment */
|
|
#define REG_DMA34_YCNT 0xFFC0D094 /* DMA34 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA34_YMOD 0xFFC0D098 /* DMA34 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA34_DSCPTR_CUR 0xFFC0D0A4 /* DMA34 Current Descriptor Pointer */
|
|
#define REG_DMA34_DSCPTR_PRV 0xFFC0D0A8 /* DMA34 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA34_ADDR_CUR 0xFFC0D0AC /* DMA34 Current Address */
|
|
#define REG_DMA34_STAT 0xFFC0D0B0 /* DMA34 Status Register */
|
|
#define REG_DMA34_XCNT_CUR 0xFFC0D0B4 /* DMA34 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA34_YCNT_CUR 0xFFC0D0B8 /* DMA34 Current Row Count (2D only) */
|
|
#define REG_DMA34_BWLCNT 0xFFC0D0C0 /* DMA34 Bandwidth Limit Count */
|
|
#define REG_DMA34_BWLCNT_CUR 0xFFC0D0C4 /* DMA34 Bandwidth Limit Count Current */
|
|
#define REG_DMA34_BWMCNT 0xFFC0D0C8 /* DMA34 Bandwidth Monitor Count */
|
|
#define REG_DMA34_BWMCNT_CUR 0xFFC0D0CC /* DMA34 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA35
|
|
========================= */
|
|
#define REG_DMA35_DSCPTR_NXT 0xFFC10000 /* DMA35 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA35_ADDRSTART 0xFFC10004 /* DMA35 Start Address of Current Buffer */
|
|
#define REG_DMA35_CFG 0xFFC10008 /* DMA35 Configuration Register */
|
|
#define REG_DMA35_XCNT 0xFFC1000C /* DMA35 Inner Loop Count Start Value */
|
|
#define REG_DMA35_XMOD 0xFFC10010 /* DMA35 Inner Loop Address Increment */
|
|
#define REG_DMA35_YCNT 0xFFC10014 /* DMA35 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA35_YMOD 0xFFC10018 /* DMA35 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA35_DSCPTR_CUR 0xFFC10024 /* DMA35 Current Descriptor Pointer */
|
|
#define REG_DMA35_DSCPTR_PRV 0xFFC10028 /* DMA35 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA35_ADDR_CUR 0xFFC1002C /* DMA35 Current Address */
|
|
#define REG_DMA35_STAT 0xFFC10030 /* DMA35 Status Register */
|
|
#define REG_DMA35_XCNT_CUR 0xFFC10034 /* DMA35 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA35_YCNT_CUR 0xFFC10038 /* DMA35 Current Row Count (2D only) */
|
|
#define REG_DMA35_BWLCNT 0xFFC10040 /* DMA35 Bandwidth Limit Count */
|
|
#define REG_DMA35_BWLCNT_CUR 0xFFC10044 /* DMA35 Bandwidth Limit Count Current */
|
|
#define REG_DMA35_BWMCNT 0xFFC10048 /* DMA35 Bandwidth Monitor Count */
|
|
#define REG_DMA35_BWMCNT_CUR 0xFFC1004C /* DMA35 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA36
|
|
========================= */
|
|
#define REG_DMA36_DSCPTR_NXT 0xFFC10080 /* DMA36 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA36_ADDRSTART 0xFFC10084 /* DMA36 Start Address of Current Buffer */
|
|
#define REG_DMA36_CFG 0xFFC10088 /* DMA36 Configuration Register */
|
|
#define REG_DMA36_XCNT 0xFFC1008C /* DMA36 Inner Loop Count Start Value */
|
|
#define REG_DMA36_XMOD 0xFFC10090 /* DMA36 Inner Loop Address Increment */
|
|
#define REG_DMA36_YCNT 0xFFC10094 /* DMA36 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA36_YMOD 0xFFC10098 /* DMA36 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA36_DSCPTR_CUR 0xFFC100A4 /* DMA36 Current Descriptor Pointer */
|
|
#define REG_DMA36_DSCPTR_PRV 0xFFC100A8 /* DMA36 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA36_ADDR_CUR 0xFFC100AC /* DMA36 Current Address */
|
|
#define REG_DMA36_STAT 0xFFC100B0 /* DMA36 Status Register */
|
|
#define REG_DMA36_XCNT_CUR 0xFFC100B4 /* DMA36 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA36_YCNT_CUR 0xFFC100B8 /* DMA36 Current Row Count (2D only) */
|
|
#define REG_DMA36_BWLCNT 0xFFC100C0 /* DMA36 Bandwidth Limit Count */
|
|
#define REG_DMA36_BWLCNT_CUR 0xFFC100C4 /* DMA36 Bandwidth Limit Count Current */
|
|
#define REG_DMA36_BWMCNT 0xFFC100C8 /* DMA36 Bandwidth Monitor Count */
|
|
#define REG_DMA36_BWMCNT_CUR 0xFFC100CC /* DMA36 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA37
|
|
========================= */
|
|
#define REG_DMA37_DSCPTR_NXT 0xFFC10100 /* DMA37 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA37_ADDRSTART 0xFFC10104 /* DMA37 Start Address of Current Buffer */
|
|
#define REG_DMA37_CFG 0xFFC10108 /* DMA37 Configuration Register */
|
|
#define REG_DMA37_XCNT 0xFFC1010C /* DMA37 Inner Loop Count Start Value */
|
|
#define REG_DMA37_XMOD 0xFFC10110 /* DMA37 Inner Loop Address Increment */
|
|
#define REG_DMA37_YCNT 0xFFC10114 /* DMA37 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA37_YMOD 0xFFC10118 /* DMA37 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA37_DSCPTR_CUR 0xFFC10124 /* DMA37 Current Descriptor Pointer */
|
|
#define REG_DMA37_DSCPTR_PRV 0xFFC10128 /* DMA37 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA37_ADDR_CUR 0xFFC1012C /* DMA37 Current Address */
|
|
#define REG_DMA37_STAT 0xFFC10130 /* DMA37 Status Register */
|
|
#define REG_DMA37_XCNT_CUR 0xFFC10134 /* DMA37 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA37_YCNT_CUR 0xFFC10138 /* DMA37 Current Row Count (2D only) */
|
|
#define REG_DMA37_BWLCNT 0xFFC10140 /* DMA37 Bandwidth Limit Count */
|
|
#define REG_DMA37_BWLCNT_CUR 0xFFC10144 /* DMA37 Bandwidth Limit Count Current */
|
|
#define REG_DMA37_BWMCNT 0xFFC10148 /* DMA37 Bandwidth Monitor Count */
|
|
#define REG_DMA37_BWMCNT_CUR 0xFFC1014C /* DMA37 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA38
|
|
========================= */
|
|
#define REG_DMA38_DSCPTR_NXT 0xFFC12000 /* DMA38 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA38_ADDRSTART 0xFFC12004 /* DMA38 Start Address of Current Buffer */
|
|
#define REG_DMA38_CFG 0xFFC12008 /* DMA38 Configuration Register */
|
|
#define REG_DMA38_XCNT 0xFFC1200C /* DMA38 Inner Loop Count Start Value */
|
|
#define REG_DMA38_XMOD 0xFFC12010 /* DMA38 Inner Loop Address Increment */
|
|
#define REG_DMA38_YCNT 0xFFC12014 /* DMA38 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA38_YMOD 0xFFC12018 /* DMA38 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA38_DSCPTR_CUR 0xFFC12024 /* DMA38 Current Descriptor Pointer */
|
|
#define REG_DMA38_DSCPTR_PRV 0xFFC12028 /* DMA38 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA38_ADDR_CUR 0xFFC1202C /* DMA38 Current Address */
|
|
#define REG_DMA38_STAT 0xFFC12030 /* DMA38 Status Register */
|
|
#define REG_DMA38_XCNT_CUR 0xFFC12034 /* DMA38 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA38_YCNT_CUR 0xFFC12038 /* DMA38 Current Row Count (2D only) */
|
|
#define REG_DMA38_BWLCNT 0xFFC12040 /* DMA38 Bandwidth Limit Count */
|
|
#define REG_DMA38_BWLCNT_CUR 0xFFC12044 /* DMA38 Bandwidth Limit Count Current */
|
|
#define REG_DMA38_BWMCNT 0xFFC12048 /* DMA38 Bandwidth Monitor Count */
|
|
#define REG_DMA38_BWMCNT_CUR 0xFFC1204C /* DMA38 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA39
|
|
========================= */
|
|
#define REG_DMA39_DSCPTR_NXT 0xFFC12080 /* DMA39 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA39_ADDRSTART 0xFFC12084 /* DMA39 Start Address of Current Buffer */
|
|
#define REG_DMA39_CFG 0xFFC12088 /* DMA39 Configuration Register */
|
|
#define REG_DMA39_XCNT 0xFFC1208C /* DMA39 Inner Loop Count Start Value */
|
|
#define REG_DMA39_XMOD 0xFFC12090 /* DMA39 Inner Loop Address Increment */
|
|
#define REG_DMA39_YCNT 0xFFC12094 /* DMA39 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA39_YMOD 0xFFC12098 /* DMA39 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA39_DSCPTR_CUR 0xFFC120A4 /* DMA39 Current Descriptor Pointer */
|
|
#define REG_DMA39_DSCPTR_PRV 0xFFC120A8 /* DMA39 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA39_ADDR_CUR 0xFFC120AC /* DMA39 Current Address */
|
|
#define REG_DMA39_STAT 0xFFC120B0 /* DMA39 Status Register */
|
|
#define REG_DMA39_XCNT_CUR 0xFFC120B4 /* DMA39 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA39_YCNT_CUR 0xFFC120B8 /* DMA39 Current Row Count (2D only) */
|
|
#define REG_DMA39_BWLCNT 0xFFC120C0 /* DMA39 Bandwidth Limit Count */
|
|
#define REG_DMA39_BWLCNT_CUR 0xFFC120C4 /* DMA39 Bandwidth Limit Count Current */
|
|
#define REG_DMA39_BWMCNT 0xFFC120C8 /* DMA39 Bandwidth Monitor Count */
|
|
#define REG_DMA39_BWMCNT_CUR 0xFFC120CC /* DMA39 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA40
|
|
========================= */
|
|
#define REG_DMA40_DSCPTR_NXT 0xFFC12100 /* DMA40 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA40_ADDRSTART 0xFFC12104 /* DMA40 Start Address of Current Buffer */
|
|
#define REG_DMA40_CFG 0xFFC12108 /* DMA40 Configuration Register */
|
|
#define REG_DMA40_XCNT 0xFFC1210C /* DMA40 Inner Loop Count Start Value */
|
|
#define REG_DMA40_XMOD 0xFFC12110 /* DMA40 Inner Loop Address Increment */
|
|
#define REG_DMA40_YCNT 0xFFC12114 /* DMA40 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA40_YMOD 0xFFC12118 /* DMA40 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA40_DSCPTR_CUR 0xFFC12124 /* DMA40 Current Descriptor Pointer */
|
|
#define REG_DMA40_DSCPTR_PRV 0xFFC12128 /* DMA40 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA40_ADDR_CUR 0xFFC1212C /* DMA40 Current Address */
|
|
#define REG_DMA40_STAT 0xFFC12130 /* DMA40 Status Register */
|
|
#define REG_DMA40_XCNT_CUR 0xFFC12134 /* DMA40 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA40_YCNT_CUR 0xFFC12138 /* DMA40 Current Row Count (2D only) */
|
|
#define REG_DMA40_BWLCNT 0xFFC12140 /* DMA40 Bandwidth Limit Count */
|
|
#define REG_DMA40_BWLCNT_CUR 0xFFC12144 /* DMA40 Bandwidth Limit Count Current */
|
|
#define REG_DMA40_BWMCNT 0xFFC12148 /* DMA40 Bandwidth Monitor Count */
|
|
#define REG_DMA40_BWMCNT_CUR 0xFFC1214C /* DMA40 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA41
|
|
========================= */
|
|
#define REG_DMA41_DSCPTR_NXT 0xFFC12180 /* DMA41 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA41_ADDRSTART 0xFFC12184 /* DMA41 Start Address of Current Buffer */
|
|
#define REG_DMA41_CFG 0xFFC12188 /* DMA41 Configuration Register */
|
|
#define REG_DMA41_XCNT 0xFFC1218C /* DMA41 Inner Loop Count Start Value */
|
|
#define REG_DMA41_XMOD 0xFFC12190 /* DMA41 Inner Loop Address Increment */
|
|
#define REG_DMA41_YCNT 0xFFC12194 /* DMA41 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA41_YMOD 0xFFC12198 /* DMA41 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA41_DSCPTR_CUR 0xFFC121A4 /* DMA41 Current Descriptor Pointer */
|
|
#define REG_DMA41_DSCPTR_PRV 0xFFC121A8 /* DMA41 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA41_ADDR_CUR 0xFFC121AC /* DMA41 Current Address */
|
|
#define REG_DMA41_STAT 0xFFC121B0 /* DMA41 Status Register */
|
|
#define REG_DMA41_XCNT_CUR 0xFFC121B4 /* DMA41 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA41_YCNT_CUR 0xFFC121B8 /* DMA41 Current Row Count (2D only) */
|
|
#define REG_DMA41_BWLCNT 0xFFC121C0 /* DMA41 Bandwidth Limit Count */
|
|
#define REG_DMA41_BWLCNT_CUR 0xFFC121C4 /* DMA41 Bandwidth Limit Count Current */
|
|
#define REG_DMA41_BWMCNT 0xFFC121C8 /* DMA41 Bandwidth Monitor Count */
|
|
#define REG_DMA41_BWMCNT_CUR 0xFFC121CC /* DMA41 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA42
|
|
========================= */
|
|
#define REG_DMA42_DSCPTR_NXT 0xFFC14000 /* DMA42 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA42_ADDRSTART 0xFFC14004 /* DMA42 Start Address of Current Buffer */
|
|
#define REG_DMA42_CFG 0xFFC14008 /* DMA42 Configuration Register */
|
|
#define REG_DMA42_XCNT 0xFFC1400C /* DMA42 Inner Loop Count Start Value */
|
|
#define REG_DMA42_XMOD 0xFFC14010 /* DMA42 Inner Loop Address Increment */
|
|
#define REG_DMA42_YCNT 0xFFC14014 /* DMA42 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA42_YMOD 0xFFC14018 /* DMA42 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA42_DSCPTR_CUR 0xFFC14024 /* DMA42 Current Descriptor Pointer */
|
|
#define REG_DMA42_DSCPTR_PRV 0xFFC14028 /* DMA42 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA42_ADDR_CUR 0xFFC1402C /* DMA42 Current Address */
|
|
#define REG_DMA42_STAT 0xFFC14030 /* DMA42 Status Register */
|
|
#define REG_DMA42_XCNT_CUR 0xFFC14034 /* DMA42 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA42_YCNT_CUR 0xFFC14038 /* DMA42 Current Row Count (2D only) */
|
|
#define REG_DMA42_BWLCNT 0xFFC14040 /* DMA42 Bandwidth Limit Count */
|
|
#define REG_DMA42_BWLCNT_CUR 0xFFC14044 /* DMA42 Bandwidth Limit Count Current */
|
|
#define REG_DMA42_BWMCNT 0xFFC14048 /* DMA42 Bandwidth Monitor Count */
|
|
#define REG_DMA42_BWMCNT_CUR 0xFFC1404C /* DMA42 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA43
|
|
========================= */
|
|
#define REG_DMA43_DSCPTR_NXT 0xFFC14080 /* DMA43 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA43_ADDRSTART 0xFFC14084 /* DMA43 Start Address of Current Buffer */
|
|
#define REG_DMA43_CFG 0xFFC14088 /* DMA43 Configuration Register */
|
|
#define REG_DMA43_XCNT 0xFFC1408C /* DMA43 Inner Loop Count Start Value */
|
|
#define REG_DMA43_XMOD 0xFFC14090 /* DMA43 Inner Loop Address Increment */
|
|
#define REG_DMA43_YCNT 0xFFC14094 /* DMA43 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA43_YMOD 0xFFC14098 /* DMA43 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA43_DSCPTR_CUR 0xFFC140A4 /* DMA43 Current Descriptor Pointer */
|
|
#define REG_DMA43_DSCPTR_PRV 0xFFC140A8 /* DMA43 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA43_ADDR_CUR 0xFFC140AC /* DMA43 Current Address */
|
|
#define REG_DMA43_STAT 0xFFC140B0 /* DMA43 Status Register */
|
|
#define REG_DMA43_XCNT_CUR 0xFFC140B4 /* DMA43 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA43_YCNT_CUR 0xFFC140B8 /* DMA43 Current Row Count (2D only) */
|
|
#define REG_DMA43_BWLCNT 0xFFC140C0 /* DMA43 Bandwidth Limit Count */
|
|
#define REG_DMA43_BWLCNT_CUR 0xFFC140C4 /* DMA43 Bandwidth Limit Count Current */
|
|
#define REG_DMA43_BWMCNT 0xFFC140C8 /* DMA43 Bandwidth Monitor Count */
|
|
#define REG_DMA43_BWMCNT_CUR 0xFFC140CC /* DMA43 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA44
|
|
========================= */
|
|
#define REG_DMA44_DSCPTR_NXT 0xFFC14100 /* DMA44 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA44_ADDRSTART 0xFFC14104 /* DMA44 Start Address of Current Buffer */
|
|
#define REG_DMA44_CFG 0xFFC14108 /* DMA44 Configuration Register */
|
|
#define REG_DMA44_XCNT 0xFFC1410C /* DMA44 Inner Loop Count Start Value */
|
|
#define REG_DMA44_XMOD 0xFFC14110 /* DMA44 Inner Loop Address Increment */
|
|
#define REG_DMA44_YCNT 0xFFC14114 /* DMA44 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA44_YMOD 0xFFC14118 /* DMA44 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA44_DSCPTR_CUR 0xFFC14124 /* DMA44 Current Descriptor Pointer */
|
|
#define REG_DMA44_DSCPTR_PRV 0xFFC14128 /* DMA44 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA44_ADDR_CUR 0xFFC1412C /* DMA44 Current Address */
|
|
#define REG_DMA44_STAT 0xFFC14130 /* DMA44 Status Register */
|
|
#define REG_DMA44_XCNT_CUR 0xFFC14134 /* DMA44 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA44_YCNT_CUR 0xFFC14138 /* DMA44 Current Row Count (2D only) */
|
|
#define REG_DMA44_BWLCNT 0xFFC14140 /* DMA44 Bandwidth Limit Count */
|
|
#define REG_DMA44_BWLCNT_CUR 0xFFC14144 /* DMA44 Bandwidth Limit Count Current */
|
|
#define REG_DMA44_BWMCNT 0xFFC14148 /* DMA44 Bandwidth Monitor Count */
|
|
#define REG_DMA44_BWMCNT_CUR 0xFFC1414C /* DMA44 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA45
|
|
========================= */
|
|
#define REG_DMA45_DSCPTR_NXT 0xFFC14180 /* DMA45 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA45_ADDRSTART 0xFFC14184 /* DMA45 Start Address of Current Buffer */
|
|
#define REG_DMA45_CFG 0xFFC14188 /* DMA45 Configuration Register */
|
|
#define REG_DMA45_XCNT 0xFFC1418C /* DMA45 Inner Loop Count Start Value */
|
|
#define REG_DMA45_XMOD 0xFFC14190 /* DMA45 Inner Loop Address Increment */
|
|
#define REG_DMA45_YCNT 0xFFC14194 /* DMA45 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA45_YMOD 0xFFC14198 /* DMA45 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA45_DSCPTR_CUR 0xFFC141A4 /* DMA45 Current Descriptor Pointer */
|
|
#define REG_DMA45_DSCPTR_PRV 0xFFC141A8 /* DMA45 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA45_ADDR_CUR 0xFFC141AC /* DMA45 Current Address */
|
|
#define REG_DMA45_STAT 0xFFC141B0 /* DMA45 Status Register */
|
|
#define REG_DMA45_XCNT_CUR 0xFFC141B4 /* DMA45 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA45_YCNT_CUR 0xFFC141B8 /* DMA45 Current Row Count (2D only) */
|
|
#define REG_DMA45_BWLCNT 0xFFC141C0 /* DMA45 Bandwidth Limit Count */
|
|
#define REG_DMA45_BWLCNT_CUR 0xFFC141C4 /* DMA45 Bandwidth Limit Count Current */
|
|
#define REG_DMA45_BWMCNT 0xFFC141C8 /* DMA45 Bandwidth Monitor Count */
|
|
#define REG_DMA45_BWMCNT_CUR 0xFFC141CC /* DMA45 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA46
|
|
========================= */
|
|
#define REG_DMA46_DSCPTR_NXT 0xFFC14200 /* DMA46 Pointer to Next Initial Descriptor */
|
|
#define REG_DMA46_ADDRSTART 0xFFC14204 /* DMA46 Start Address of Current Buffer */
|
|
#define REG_DMA46_CFG 0xFFC14208 /* DMA46 Configuration Register */
|
|
#define REG_DMA46_XCNT 0xFFC1420C /* DMA46 Inner Loop Count Start Value */
|
|
#define REG_DMA46_XMOD 0xFFC14210 /* DMA46 Inner Loop Address Increment */
|
|
#define REG_DMA46_YCNT 0xFFC14214 /* DMA46 Outer Loop Count Start Value (2D only) */
|
|
#define REG_DMA46_YMOD 0xFFC14218 /* DMA46 Outer Loop Address Increment (2D only) */
|
|
#define REG_DMA46_DSCPTR_CUR 0xFFC14224 /* DMA46 Current Descriptor Pointer */
|
|
#define REG_DMA46_DSCPTR_PRV 0xFFC14228 /* DMA46 Previous Initial Descriptor Pointer */
|
|
#define REG_DMA46_ADDR_CUR 0xFFC1422C /* DMA46 Current Address */
|
|
#define REG_DMA46_STAT 0xFFC14230 /* DMA46 Status Register */
|
|
#define REG_DMA46_XCNT_CUR 0xFFC14234 /* DMA46 Current Count(1D) or intra-row XCNT (2D) */
|
|
#define REG_DMA46_YCNT_CUR 0xFFC14238 /* DMA46 Current Row Count (2D only) */
|
|
#define REG_DMA46_BWLCNT 0xFFC14240 /* DMA46 Bandwidth Limit Count */
|
|
#define REG_DMA46_BWLCNT_CUR 0xFFC14244 /* DMA46 Bandwidth Limit Count Current */
|
|
#define REG_DMA46_BWMCNT 0xFFC14248 /* DMA46 Bandwidth Monitor Count */
|
|
#define REG_DMA46_BWMCNT_CUR 0xFFC1424C /* DMA46 Bandwidth Monitor Count Current */
|
|
|
|
/* =========================
|
|
DMA
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DMA_CFG Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DMA_CFG_PDRF 28 /* Peripheral Data Request Forward */
|
|
#define BITP_DMA_CFG_TWOD 26 /* Two Dimension Addressing Enable */
|
|
#define BITP_DMA_CFG_DESCIDCPY 25 /* Descriptor ID Copy Control */
|
|
#define BITP_DMA_CFG_TOVEN 24 /* Trigger Overrun Error Enable */
|
|
#define BITP_DMA_CFG_TRIG 22 /* Generate Outgoing Trigger */
|
|
#define BITP_DMA_CFG_INT 20 /* Generate Interrupt */
|
|
#define BITP_DMA_CFG_NDSIZE 16 /* Next Descriptor Set Size */
|
|
#define BITP_DMA_CFG_TWAIT 15 /* Wait for Trigger */
|
|
#define BITP_DMA_CFG_FLOW 12 /* Next Operation */
|
|
#define BITP_DMA_CFG_MSIZE 8 /* Memory Transfer Word Size */
|
|
#define BITP_DMA_CFG_PSIZE 4 /* Peripheral Transfer Word Size */
|
|
#define BITP_DMA_CFG_CADDR 3 /* Use Current Address */
|
|
#define BITP_DMA_CFG_SYNC 2 /* Synchronize Work Unit Transitions */
|
|
#define BITP_DMA_CFG_WNR 1 /* Write/Read Channel Direction */
|
|
#define BITP_DMA_CFG_EN 0 /* DMA Channel Enable */
|
|
|
|
#define BITM_DMA_CFG_PDRF (_ADI_MSK(0x10000000,uint32_t)) /* Peripheral Data Request Forward */
|
|
#define ENUM_DMA_CFG_PDAT_NOTFWD (_ADI_MSK(0x00000000,uint32_t)) /* PDRF: Peripheral Data Request Not Forwarded */
|
|
#define ENUM_DMA_CFG_PDAT_FWD (_ADI_MSK(0x10000000,uint32_t)) /* PDRF: Peripheral Data Request Forwarded */
|
|
|
|
#define BITM_DMA_CFG_TWOD (_ADI_MSK(0x04000000,uint32_t)) /* Two Dimension Addressing Enable */
|
|
#define ENUM_DMA_CFG_ADDR1D (_ADI_MSK(0x00000000,uint32_t)) /* TWOD: One-Dimensional Addressing */
|
|
#define ENUM_DMA_CFG_ADDR2D (_ADI_MSK(0x04000000,uint32_t)) /* TWOD: Two-Dimensional Addressing */
|
|
|
|
#define BITM_DMA_CFG_DESCIDCPY (_ADI_MSK(0x02000000,uint32_t)) /* Descriptor ID Copy Control */
|
|
#define ENUM_DMA_CFG_NO_COPY (_ADI_MSK(0x00000000,uint32_t)) /* DESCIDCPY: Never Copy */
|
|
#define ENUM_DMA_CFG_COPY (_ADI_MSK(0x02000000,uint32_t)) /* DESCIDCPY: Copy on Work Unit Complete */
|
|
|
|
#define BITM_DMA_CFG_TOVEN (_ADI_MSK(0x01000000,uint32_t)) /* Trigger Overrun Error Enable */
|
|
#define ENUM_DMA_CFG_TOV_DIS (_ADI_MSK(0x00000000,uint32_t)) /* TOVEN: Ignore Trigger Overrun */
|
|
#define ENUM_DMA_CFG_TOV_EN (_ADI_MSK(0x01000000,uint32_t)) /* TOVEN: Error on Trigger Overrun */
|
|
|
|
#define BITM_DMA_CFG_TRIG (_ADI_MSK(0x00C00000,uint32_t)) /* Generate Outgoing Trigger */
|
|
#define ENUM_DMA_CFG_NO_TRIG (_ADI_MSK(0x00000000,uint32_t)) /* TRIG: Never assert Trigger */
|
|
#define ENUM_DMA_CFG_XCNT_TRIG (_ADI_MSK(0x00400000,uint32_t)) /* TRIG: Trigger when XCNTCUR reaches 0 */
|
|
#define ENUM_DMA_CFG_YCNT_TRIG (_ADI_MSK(0x00800000,uint32_t)) /* TRIG: Trigger when YCNTCUR reaches 0 */
|
|
|
|
#define BITM_DMA_CFG_INT (_ADI_MSK(0x00300000,uint32_t)) /* Generate Interrupt */
|
|
#define ENUM_DMA_CFG_NO_INT (_ADI_MSK(0x00000000,uint32_t)) /* INT: Never assert Interrupt */
|
|
#define ENUM_DMA_CFG_XCNT_INT (_ADI_MSK(0x00100000,uint32_t)) /* INT: Interrupt when X Count Expires */
|
|
#define ENUM_DMA_CFG_YCNT_INT (_ADI_MSK(0x00200000,uint32_t)) /* INT: Interrupt when Y Count Expires */
|
|
#define ENUM_DMA_CFG_PERIPH_INT (_ADI_MSK(0x00300000,uint32_t)) /* INT: Peripheral Interrupt */
|
|
|
|
#define BITM_DMA_CFG_NDSIZE (_ADI_MSK(0x00070000,uint32_t)) /* Next Descriptor Set Size */
|
|
#define ENUM_DMA_CFG_FETCH01 (_ADI_MSK(0x00000000,uint32_t)) /* NDSIZE: Fetch one Descriptor Element */
|
|
#define ENUM_DMA_CFG_FETCH02 (_ADI_MSK(0x00010000,uint32_t)) /* NDSIZE: Fetch two Descriptor Elements */
|
|
#define ENUM_DMA_CFG_FETCH03 (_ADI_MSK(0x00020000,uint32_t)) /* NDSIZE: Fetch three Descriptor Elements */
|
|
#define ENUM_DMA_CFG_FETCH04 (_ADI_MSK(0x00030000,uint32_t)) /* NDSIZE: Fetch four Descriptor Elements */
|
|
#define ENUM_DMA_CFG_FETCH05 (_ADI_MSK(0x00040000,uint32_t)) /* NDSIZE: Fetch five Descriptor Elements */
|
|
#define ENUM_DMA_CFG_FETCH06 (_ADI_MSK(0x00050000,uint32_t)) /* NDSIZE: Fetch six Descriptor Elements */
|
|
#define ENUM_DMA_CFG_FETCH07 (_ADI_MSK(0x00060000,uint32_t)) /* NDSIZE: Fetch seven Descriptor Elements */
|
|
|
|
#define BITM_DMA_CFG_TWAIT (_ADI_MSK(0x00008000,uint32_t)) /* Wait for Trigger */
|
|
#define ENUM_DMA_CFG_NO_TRGWAIT (_ADI_MSK(0x00000000,uint32_t)) /* TWAIT: Begin Work Unit Automatically (No Wait) */
|
|
#define ENUM_DMA_CFG_TRGWAIT (_ADI_MSK(0x00008000,uint32_t)) /* TWAIT: Wait for Trigger (Halt before Work Unit) */
|
|
|
|
#define BITM_DMA_CFG_FLOW (_ADI_MSK(0x00007000,uint32_t)) /* Next Operation */
|
|
#define ENUM_DMA_CFG_STOP (_ADI_MSK(0x00000000,uint32_t)) /* FLOW: STOP - Stop */
|
|
#define ENUM_DMA_CFG_AUTO (_ADI_MSK(0x00001000,uint32_t)) /* FLOW: AUTO - Autobuffer */
|
|
#define ENUM_DMA_CFG_DSCLIST (_ADI_MSK(0x00004000,uint32_t)) /* FLOW: DSCL - Descriptor List */
|
|
#define ENUM_DMA_CFG_DSCARRAY (_ADI_MSK(0x00005000,uint32_t)) /* FLOW: DSCA - Descriptor Array */
|
|
#define ENUM_DMA_CFG_DODLIST (_ADI_MSK(0x00006000,uint32_t)) /* FLOW: Descriptor On Demand List */
|
|
#define ENUM_DMA_CFG_DODARRAY (_ADI_MSK(0x00007000,uint32_t)) /* FLOW: Descriptor On Demand Array */
|
|
|
|
#define BITM_DMA_CFG_MSIZE (_ADI_MSK(0x00000700,uint32_t)) /* Memory Transfer Word Size */
|
|
#define ENUM_DMA_CFG_MSIZE01 (_ADI_MSK(0x00000000,uint32_t)) /* MSIZE: 1 Byte */
|
|
#define ENUM_DMA_CFG_MSIZE02 (_ADI_MSK(0x00000100,uint32_t)) /* MSIZE: 2 Bytes */
|
|
#define ENUM_DMA_CFG_MSIZE04 (_ADI_MSK(0x00000200,uint32_t)) /* MSIZE: 4 Bytes */
|
|
#define ENUM_DMA_CFG_MSIZE08 (_ADI_MSK(0x00000300,uint32_t)) /* MSIZE: 8 Bytes */
|
|
#define ENUM_DMA_CFG_MSIZE16 (_ADI_MSK(0x00000400,uint32_t)) /* MSIZE: 16 Bytes */
|
|
#define ENUM_DMA_CFG_MSIZE32 (_ADI_MSK(0x00000500,uint32_t)) /* MSIZE: 32 Bytes */
|
|
|
|
#define BITM_DMA_CFG_PSIZE (_ADI_MSK(0x00000070,uint32_t)) /* Peripheral Transfer Word Size */
|
|
#define ENUM_DMA_CFG_PSIZE01 (_ADI_MSK(0x00000000,uint32_t)) /* PSIZE: 1 Byte */
|
|
#define ENUM_DMA_CFG_PSIZE02 (_ADI_MSK(0x00000010,uint32_t)) /* PSIZE: 2 Bytes */
|
|
#define ENUM_DMA_CFG_PSIZE04 (_ADI_MSK(0x00000020,uint32_t)) /* PSIZE: 4 Bytes */
|
|
#define ENUM_DMA_CFG_PSIZE08 (_ADI_MSK(0x00000030,uint32_t)) /* PSIZE: 8 Bytes */
|
|
|
|
#define BITM_DMA_CFG_CADDR (_ADI_MSK(0x00000008,uint32_t)) /* Use Current Address */
|
|
#define ENUM_DMA_CFG_LD_STARTADDR (_ADI_MSK(0x00000000,uint32_t)) /* CADDR: Load Starting Address */
|
|
#define ENUM_DMA_CFG_LD_CURADDR (_ADI_MSK(0x00000008,uint32_t)) /* CADDR: Use Current Address */
|
|
|
|
#define BITM_DMA_CFG_SYNC (_ADI_MSK(0x00000004,uint32_t)) /* Synchronize Work Unit Transitions */
|
|
#define ENUM_DMA_CFG_NO_SYNC (_ADI_MSK(0x00000000,uint32_t)) /* SYNC: No Synchronization */
|
|
#define ENUM_DMA_CFG_SYNC (_ADI_MSK(0x00000004,uint32_t)) /* SYNC: Synchronize Channel */
|
|
|
|
#define BITM_DMA_CFG_WNR (_ADI_MSK(0x00000002,uint32_t)) /* Write/Read Channel Direction */
|
|
#define ENUM_DMA_CFG_READ (_ADI_MSK(0x00000000,uint32_t)) /* WNR: Transmit (Read from memory) */
|
|
#define ENUM_DMA_CFG_WRITE (_ADI_MSK(0x00000002,uint32_t)) /* WNR: Receive (Write to memory) */
|
|
|
|
#define BITM_DMA_CFG_EN (_ADI_MSK(0x00000001,uint32_t)) /* DMA Channel Enable */
|
|
#define ENUM_DMA_CFG_DIS (_ADI_MSK(0x00000000,uint32_t)) /* EN: Disable */
|
|
#define ENUM_DMA_CFG_EN (_ADI_MSK(0x00000001,uint32_t)) /* EN: Enable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DMA_DSCPTR_PRV Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DMA_DSCPTR_PRV_DESCPPREV 2 /* Pointer for Previous Descriptor Element */
|
|
#define BITP_DMA_DSCPTR_PRV_PDPO 0 /* Previous Descriptor Pointer Overrun */
|
|
#define BITM_DMA_DSCPTR_PRV_DESCPPREV (_ADI_MSK(0xFFFFFFFC,uint32_t)) /* Pointer for Previous Descriptor Element */
|
|
#define BITM_DMA_DSCPTR_PRV_PDPO (_ADI_MSK(0x00000001,uint32_t)) /* Previous Descriptor Pointer Overrun */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DMA_STAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DMA_STAT_TWAIT 20 /* Trigger Wait Status */
|
|
#define BITP_DMA_STAT_FIFOFILL 16 /* FIFO Fill Status */
|
|
#define BITP_DMA_STAT_MBWID 14 /* Memory Bus Width */
|
|
#define BITP_DMA_STAT_PBWID 12 /* Peripheral Bus Width */
|
|
#define BITP_DMA_STAT_RUN 8 /* Run Status */
|
|
#define BITP_DMA_STAT_ERRC 4 /* Error Cause */
|
|
#define BITP_DMA_STAT_PIRQ 2 /* Peripheral Interrupt Request */
|
|
#define BITP_DMA_STAT_IRQERR 1 /* Error Interrupt */
|
|
#define BITP_DMA_STAT_IRQDONE 0 /* Work Unit/Row Done Interrupt */
|
|
|
|
#define BITM_DMA_STAT_TWAIT (_ADI_MSK(0x00100000,uint32_t)) /* Trigger Wait Status */
|
|
#define ENUM_DMA_STAT_NOTRIGRX (_ADI_MSK(0x00000000,uint32_t)) /* TWAIT: No trigger received */
|
|
#define ENUM_DMA_STAT_TRIGRX (_ADI_MSK(0x00100000,uint32_t)) /* TWAIT: Trigger received */
|
|
|
|
#define BITM_DMA_STAT_FIFOFILL (_ADI_MSK(0x00070000,uint32_t)) /* FIFO Fill Status */
|
|
#define ENUM_DMA_STAT_FIFOEMPTY (_ADI_MSK(0x00000000,uint32_t)) /* FIFOFILL: Empty */
|
|
#define ENUM_DMA_STAT_FIFO25 (_ADI_MSK(0x00010000,uint32_t)) /* FIFOFILL: Empty < FIFO = 1/4 Full */
|
|
#define ENUM_DMA_STAT_FIFO50 (_ADI_MSK(0x00020000,uint32_t)) /* FIFOFILL: 1/4 Full < FIFO = 1/2 Full */
|
|
#define ENUM_DMA_STAT_FIFO75 (_ADI_MSK(0x00030000,uint32_t)) /* FIFOFILL: 1/2 Full < FIFO = 3/4 Full */
|
|
#define ENUM_DMA_STAT_FIFONEARFULL (_ADI_MSK(0x00040000,uint32_t)) /* FIFOFILL: 3/4 Full < FIFO = Full */
|
|
#define ENUM_DMA_STAT_FIFOFULL (_ADI_MSK(0x00070000,uint32_t)) /* FIFOFILL: Full */
|
|
|
|
#define BITM_DMA_STAT_MBWID (_ADI_MSK(0x0000C000,uint32_t)) /* Memory Bus Width */
|
|
#define ENUM_DMA_STAT_MBUS02 (_ADI_MSK(0x00000000,uint32_t)) /* MBWID: 2 Bytes */
|
|
#define ENUM_DMA_STAT_MBUS04 (_ADI_MSK(0x00004000,uint32_t)) /* MBWID: 4 Bytes */
|
|
#define ENUM_DMA_STAT_MBUS08 (_ADI_MSK(0x00008000,uint32_t)) /* MBWID: 8 Bytes */
|
|
#define ENUM_DMA_STAT_MBUS16 (_ADI_MSK(0x0000C000,uint32_t)) /* MBWID: 16 Bytes */
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|
|
|
#define BITM_DMA_STAT_PBWID (_ADI_MSK(0x00003000,uint32_t)) /* Peripheral Bus Width */
|
|
#define ENUM_DMA_STAT_PBUS01 (_ADI_MSK(0x00000000,uint32_t)) /* PBWID: 1 Byte */
|
|
#define ENUM_DMA_STAT_PBUS02 (_ADI_MSK(0x00001000,uint32_t)) /* PBWID: 2 Bytes */
|
|
#define ENUM_DMA_STAT_PBUS04 (_ADI_MSK(0x00002000,uint32_t)) /* PBWID: 4 Bytes */
|
|
#define ENUM_DMA_STAT_PBUS08 (_ADI_MSK(0x00003000,uint32_t)) /* PBWID: 8 Bytes */
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|
|
|
#define BITM_DMA_STAT_RUN (_ADI_MSK(0x00000700,uint32_t)) /* Run Status */
|
|
#define ENUM_DMA_STAT_STOPPED (_ADI_MSK(0x00000000,uint32_t)) /* RUN: Idle/Stop State */
|
|
#define ENUM_DMA_STAT_DSCFETCH (_ADI_MSK(0x00000100,uint32_t)) /* RUN: Descriptor Fetch */
|
|
#define ENUM_DMA_STAT_DATAXFER (_ADI_MSK(0x00000200,uint32_t)) /* RUN: Data Transfer */
|
|
#define ENUM_DMA_STAT_TRGWAIT (_ADI_MSK(0x00000300,uint32_t)) /* RUN: Waiting for Trigger */
|
|
#define ENUM_DMA_STAT_ACKWAIT (_ADI_MSK(0x00000400,uint32_t)) /* RUN: Waiting for Write ACK/FIFO Drain to Peripheral */
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|
|
|
#define BITM_DMA_STAT_ERRC (_ADI_MSK(0x00000070,uint32_t)) /* Error Cause */
|
|
#define ENUM_DMA_STAT_CFGERR (_ADI_MSK(0x00000000,uint32_t)) /* ERRC: Configuration Error */
|
|
#define ENUM_DMA_STAT_ILLWRERR (_ADI_MSK(0x00000010,uint32_t)) /* ERRC: Illegal Write Occurred While Channel Running */
|
|
#define ENUM_DMA_STAT_ALGNERR (_ADI_MSK(0x00000020,uint32_t)) /* ERRC: Address Alignment Error */
|
|
#define ENUM_DMA_STAT_MEMERR (_ADI_MSK(0x00000030,uint32_t)) /* ERRC: Memory Access/Fabric Error */
|
|
#define ENUM_DMA_STAT_TRGOVERR (_ADI_MSK(0x00000050,uint32_t)) /* ERRC: Trigger Overrun */
|
|
#define ENUM_DMA_STAT_BWMONERR (_ADI_MSK(0x00000060,uint32_t)) /* ERRC: Bandwidth Monitor Error */
|
|
|
|
#define BITM_DMA_STAT_PIRQ (_ADI_MSK(0x00000004,uint32_t)) /* Peripheral Interrupt Request */
|
|
#define ENUM_DMA_STAT_NO_PIRQ (_ADI_MSK(0x00000000,uint32_t)) /* PIRQ: No Interrupt */
|
|
#define ENUM_DMA_STAT_PIRQ (_ADI_MSK(0x00000004,uint32_t)) /* PIRQ: Interrupt Signaled by Peripheral */
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|
|
|
#define BITM_DMA_STAT_IRQERR (_ADI_MSK(0x00000002,uint32_t)) /* Error Interrupt */
|
|
#define ENUM_DMA_STAT_NO_IRQERR (_ADI_MSK(0x00000000,uint32_t)) /* IRQERR: No Error */
|
|
#define ENUM_DMA_STAT_IRQERR (_ADI_MSK(0x00000002,uint32_t)) /* IRQERR: Error Occurred */
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|
|
|
#define BITM_DMA_STAT_IRQDONE (_ADI_MSK(0x00000001,uint32_t)) /* Work Unit/Row Done Interrupt */
|
|
#define ENUM_DMA_STAT_NO_IRQ (_ADI_MSK(0x00000000,uint32_t)) /* IRQDONE: Inactive */
|
|
#define ENUM_DMA_STAT_IRQDONE (_ADI_MSK(0x00000001,uint32_t)) /* IRQDONE: Active */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DMA_BWLCNT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DMA_BWLCNT_VALUE 0 /* Bandwidth Limit Count */
|
|
#define BITM_DMA_BWLCNT_VALUE (_ADI_MSK(0x0000FFFF,uint32_t)) /* Bandwidth Limit Count */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DMA_BWLCNT_CUR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DMA_BWLCNT_CUR_VALUE 0 /* Bandwidth Limit Count Current */
|
|
#define BITM_DMA_BWLCNT_CUR_VALUE (_ADI_MSK(0x0000FFFF,uint32_t)) /* Bandwidth Limit Count Current */
|
|
|
|
/* ==================================================
|
|
ACM Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
ACM0
|
|
========================= */
|
|
#define REG_ACM0_CTL 0xFFC45000 /* ACM0 ACM Control Register */
|
|
#define REG_ACM0_TC0 0xFFC45004 /* ACM0 ACM Timing Configuration 0 Register */
|
|
#define REG_ACM0_TC1 0xFFC45008 /* ACM0 ACM Timing Configuration 1 Register */
|
|
#define REG_ACM0_STAT 0xFFC4500C /* ACM0 ACM Status Register */
|
|
#define REG_ACM0_EVSTAT 0xFFC45010 /* ACM0 ACM Event Status Register */
|
|
#define REG_ACM0_EVMSK 0xFFC45014 /* ACM0 ACM Completed Event Interrupt Mask Register */
|
|
#define REG_ACM0_MEVSTAT 0xFFC45018 /* ACM0 ACM Missed Event Status Register */
|
|
#define REG_ACM0_MEVMSK 0xFFC4501C /* ACM0 ACM Missed Event Interrupt Mask Register */
|
|
#define REG_ACM0_EVCTL0 0xFFC45020 /* ACM0 ACM Eventn Control Register */
|
|
#define REG_ACM0_EVCTL1 0xFFC45024 /* ACM0 ACM Eventn Control Register */
|
|
#define REG_ACM0_EVCTL2 0xFFC45028 /* ACM0 ACM Eventn Control Register */
|
|
#define REG_ACM0_EVCTL3 0xFFC4502C /* ACM0 ACM Eventn Control Register */
|
|
#define REG_ACM0_EVCTL4 0xFFC45030 /* ACM0 ACM Eventn Control Register */
|
|
#define REG_ACM0_EVCTL5 0xFFC45034 /* ACM0 ACM Eventn Control Register */
|
|
#define REG_ACM0_EVCTL6 0xFFC45038 /* ACM0 ACM Eventn Control Register */
|
|
#define REG_ACM0_EVCTL7 0xFFC4503C /* ACM0 ACM Eventn Control Register */
|
|
#define REG_ACM0_EVCTL8 0xFFC45040 /* ACM0 ACM Eventn Control Register */
|
|
#define REG_ACM0_EVCTL9 0xFFC45044 /* ACM0 ACM Eventn Control Register */
|
|
#define REG_ACM0_EVCTL10 0xFFC45048 /* ACM0 ACM Eventn Control Register */
|
|
#define REG_ACM0_EVCTL11 0xFFC4504C /* ACM0 ACM Eventn Control Register */
|
|
#define REG_ACM0_EVCTL12 0xFFC45050 /* ACM0 ACM Eventn Control Register */
|
|
#define REG_ACM0_EVCTL13 0xFFC45054 /* ACM0 ACM Eventn Control Register */
|
|
#define REG_ACM0_EVCTL14 0xFFC45058 /* ACM0 ACM Eventn Control Register */
|
|
#define REG_ACM0_EVCTL15 0xFFC4505C /* ACM0 ACM Eventn Control Register */
|
|
#define REG_ACM0_EVTIME0 0xFFC45060 /* ACM0 ACM Eventn Time Register */
|
|
#define REG_ACM0_EVTIME1 0xFFC45064 /* ACM0 ACM Eventn Time Register */
|
|
#define REG_ACM0_EVTIME2 0xFFC45068 /* ACM0 ACM Eventn Time Register */
|
|
#define REG_ACM0_EVTIME3 0xFFC4506C /* ACM0 ACM Eventn Time Register */
|
|
#define REG_ACM0_EVTIME4 0xFFC45070 /* ACM0 ACM Eventn Time Register */
|
|
#define REG_ACM0_EVTIME5 0xFFC45074 /* ACM0 ACM Eventn Time Register */
|
|
#define REG_ACM0_EVTIME6 0xFFC45078 /* ACM0 ACM Eventn Time Register */
|
|
#define REG_ACM0_EVTIME7 0xFFC4507C /* ACM0 ACM Eventn Time Register */
|
|
#define REG_ACM0_EVTIME8 0xFFC45080 /* ACM0 ACM Eventn Time Register */
|
|
#define REG_ACM0_EVTIME9 0xFFC45084 /* ACM0 ACM Eventn Time Register */
|
|
#define REG_ACM0_EVTIME10 0xFFC45088 /* ACM0 ACM Eventn Time Register */
|
|
#define REG_ACM0_EVTIME11 0xFFC4508C /* ACM0 ACM Eventn Time Register */
|
|
#define REG_ACM0_EVTIME12 0xFFC45090 /* ACM0 ACM Eventn Time Register */
|
|
#define REG_ACM0_EVTIME13 0xFFC45094 /* ACM0 ACM Eventn Time Register */
|
|
#define REG_ACM0_EVTIME14 0xFFC45098 /* ACM0 ACM Eventn Time Register */
|
|
#define REG_ACM0_EVTIME15 0xFFC4509C /* ACM0 ACM Eventn Time Register */
|
|
#define REG_ACM0_EVORD0 0xFFC450A0 /* ACM0 ACM Eventn Order Register */
|
|
#define REG_ACM0_EVORD1 0xFFC450A4 /* ACM0 ACM Eventn Order Register */
|
|
#define REG_ACM0_EVORD2 0xFFC450A8 /* ACM0 ACM Eventn Order Register */
|
|
#define REG_ACM0_EVORD3 0xFFC450AC /* ACM0 ACM Eventn Order Register */
|
|
#define REG_ACM0_EVORD4 0xFFC450B0 /* ACM0 ACM Eventn Order Register */
|
|
#define REG_ACM0_EVORD5 0xFFC450B4 /* ACM0 ACM Eventn Order Register */
|
|
#define REG_ACM0_EVORD6 0xFFC450B8 /* ACM0 ACM Eventn Order Register */
|
|
#define REG_ACM0_EVORD7 0xFFC450BC /* ACM0 ACM Eventn Order Register */
|
|
#define REG_ACM0_EVORD8 0xFFC450C0 /* ACM0 ACM Eventn Order Register */
|
|
#define REG_ACM0_EVORD9 0xFFC450C4 /* ACM0 ACM Eventn Order Register */
|
|
#define REG_ACM0_EVORD10 0xFFC450C8 /* ACM0 ACM Eventn Order Register */
|
|
#define REG_ACM0_EVORD11 0xFFC450CC /* ACM0 ACM Eventn Order Register */
|
|
#define REG_ACM0_EVORD12 0xFFC450D0 /* ACM0 ACM Eventn Order Register */
|
|
#define REG_ACM0_EVORD13 0xFFC450D4 /* ACM0 ACM Eventn Order Register */
|
|
#define REG_ACM0_EVORD14 0xFFC450D8 /* ACM0 ACM Eventn Order Register */
|
|
#define REG_ACM0_EVORD15 0xFFC450DC /* ACM0 ACM Eventn Order Register */
|
|
#define REG_ACM0_TMR0 0xFFC450E8 /* ACM0 ACM Timer 0 Register */
|
|
#define REG_ACM0_TMR1 0xFFC450EC /* ACM0 ACM Timer 1 Register */
|
|
|
|
/* =========================
|
|
ACM
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
ACM_CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_ACM_CTL_EPS 15 /* External Peripheral Select */
|
|
#define BITP_ACM_CTL_OTSEL 14 /* Trigger Select for Order Register Reset */
|
|
#define BITP_ACM_CTL_AOREN 13 /* Automatic Order Reset Enable */
|
|
#define BITP_ACM_CTL_ORST 12 /* Order Register Reset Bit */
|
|
#define BITP_ACM_CTL_CLKMOD 11 /* ADC Clock Mode */
|
|
#define BITP_ACM_CTL_CLKPOL 10 /* ADC_CLK Polarity */
|
|
#define BITP_ACM_CTL_CSPOL 9 /* CS Polarity */
|
|
#define BITP_ACM_CTL_TRGPOL1 8 /* Trigger Polarity for Timer1 Triggers */
|
|
#define BITP_ACM_CTL_TRGPOL0 7 /* Trigger Polarity for Timer0 Triggers */
|
|
#define BITP_ACM_CTL_TRGSEL1 5 /* Trigger Select 1 */
|
|
#define BITP_ACM_CTL_TRGSEL0 3 /* Trigger Select 0 */
|
|
#define BITP_ACM_CTL_TMR1EN 2 /* Enable ACM Timer1 */
|
|
#define BITP_ACM_CTL_TMR0EN 1 /* Enable ACM Timer0 */
|
|
#define BITP_ACM_CTL_EN 0 /* ACM Enable */
|
|
#define BITM_ACM_CTL_EPS (_ADI_MSK(0x00008000,uint32_t)) /* External Peripheral Select */
|
|
#define BITM_ACM_CTL_OTSEL (_ADI_MSK(0x00004000,uint32_t)) /* Trigger Select for Order Register Reset */
|
|
#define BITM_ACM_CTL_AOREN (_ADI_MSK(0x00002000,uint32_t)) /* Automatic Order Reset Enable */
|
|
#define BITM_ACM_CTL_ORST (_ADI_MSK(0x00001000,uint32_t)) /* Order Register Reset Bit */
|
|
#define BITM_ACM_CTL_CLKMOD (_ADI_MSK(0x00000800,uint32_t)) /* ADC Clock Mode */
|
|
#define BITM_ACM_CTL_CLKPOL (_ADI_MSK(0x00000400,uint32_t)) /* ADC_CLK Polarity */
|
|
#define BITM_ACM_CTL_CSPOL (_ADI_MSK(0x00000200,uint32_t)) /* CS Polarity */
|
|
#define BITM_ACM_CTL_TRGPOL1 (_ADI_MSK(0x00000100,uint32_t)) /* Trigger Polarity for Timer1 Triggers */
|
|
#define BITM_ACM_CTL_TRGPOL0 (_ADI_MSK(0x00000080,uint32_t)) /* Trigger Polarity for Timer0 Triggers */
|
|
#define BITM_ACM_CTL_TRGSEL1 (_ADI_MSK(0x00000060,uint32_t)) /* Trigger Select 1 */
|
|
#define BITM_ACM_CTL_TRGSEL0 (_ADI_MSK(0x00000018,uint32_t)) /* Trigger Select 0 */
|
|
#define BITM_ACM_CTL_TMR1EN (_ADI_MSK(0x00000004,uint32_t)) /* Enable ACM Timer1 */
|
|
#define BITM_ACM_CTL_TMR0EN (_ADI_MSK(0x00000002,uint32_t)) /* Enable ACM Timer0 */
|
|
#define BITM_ACM_CTL_EN (_ADI_MSK(0x00000001,uint32_t)) /* ACM Enable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
ACM_TC0 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_ACM_TC0_SC 16 /* Setup Cycle - ADC Control setup in SCLK cycles */
|
|
#define BITP_ACM_TC0_CKDIV 0 /* Serial Clock Divide Modulus[7:0] CKDIV=0 is Reserved */
|
|
#define BITM_ACM_TC0_SC (_ADI_MSK(0x0FFF0000,uint32_t)) /* Setup Cycle - ADC Control setup in SCLK cycles */
|
|
#define BITM_ACM_TC0_CKDIV (_ADI_MSK(0x000000FF,uint32_t)) /* Serial Clock Divide Modulus[7:0] CKDIV=0 is Reserved */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
ACM_TC1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_ACM_TC1_ZC 12 /* Zero Cycle - ADC Control zero duration */
|
|
#define BITP_ACM_TC1_HC 8 /* Hold Cycle - ADC Control hold in ACLK cycle */
|
|
#define BITP_ACM_TC1_CSW 0 /* CS Width. Active duration of CS in ACLK cycles */
|
|
#define BITM_ACM_TC1_ZC (_ADI_MSK(0x0000F000,uint32_t)) /* Zero Cycle - ADC Control zero duration */
|
|
#define BITM_ACM_TC1_HC (_ADI_MSK(0x00000F00,uint32_t)) /* Hold Cycle - ADC Control hold in ACLK cycle */
|
|
#define BITM_ACM_TC1_CSW (_ADI_MSK(0x000000FF,uint32_t)) /* CS Width. Active duration of CS in ACLK cycles */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
ACM_STAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_ACM_STAT_CEVNT 4 /* Current Event. */
|
|
#define BITP_ACM_STAT_ECOM1 3 /* ACM Timer1 Event Completion. This bit gets cleared with each trigger. */
|
|
#define BITP_ACM_STAT_ECOM0 2 /* ACM Timer0 Event Completion. This bit gets cleared with each trigger. */
|
|
#define BITP_ACM_STAT_EMISS 1 /* Event Missed This bit will be set if any of the bits in MEVSTAT is set, this bit has to be cleared by writing into the MEVSTAT register */
|
|
#define BITP_ACM_STAT_BSY 0 /* ACM Busy */
|
|
#define BITM_ACM_STAT_CEVNT (_ADI_MSK(0x000000F0,uint32_t)) /* Current Event. */
|
|
#define BITM_ACM_STAT_ECOM1 (_ADI_MSK(0x00000008,uint32_t)) /* ACM Timer1 Event Completion. This bit gets cleared with each trigger. */
|
|
#define BITM_ACM_STAT_ECOM0 (_ADI_MSK(0x00000004,uint32_t)) /* ACM Timer0 Event Completion. This bit gets cleared with each trigger. */
|
|
#define BITM_ACM_STAT_EMISS (_ADI_MSK(0x00000002,uint32_t)) /* Event Missed This bit will be set if any of the bits in MEVSTAT is set, this bit has to be cleared by writing into the MEVSTAT register */
|
|
#define BITM_ACM_STAT_BSY (_ADI_MSK(0x00000001,uint32_t)) /* ACM Busy */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
ACM_EVSTAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_ACM_EVSTAT_ECOM1S 17 /* Reflects the ECOM1 bit of ACM_STAT register but this bit will not be cleared by trigger. W1C bit */
|
|
#define BITP_ACM_EVSTAT_ECOM0S 16 /* Reflects the ECOM0 bit of ACM_STAT register but this bit will not be cleared by trigger. W1C bit */
|
|
#define BITP_ACM_EVSTAT_EV15 15 /* Event15 Status. W1C bit. */
|
|
#define BITP_ACM_EVSTAT_EV14 14 /* Event14 Status. W1C bit. */
|
|
#define BITP_ACM_EVSTAT_EV13 13 /* Event13 Status. W1C bit. */
|
|
#define BITP_ACM_EVSTAT_EV12 12 /* Event12 Status. W1C bit. */
|
|
#define BITP_ACM_EVSTAT_EV11 11 /* Event11 Status. W1C bit. */
|
|
#define BITP_ACM_EVSTAT_EV10 10 /* Event10 Status. W1C bit. */
|
|
#define BITP_ACM_EVSTAT_EV9 9 /* Event9 Status. W1C bit. */
|
|
#define BITP_ACM_EVSTAT_EV8 8 /* Event8 Status. W1C bit. */
|
|
#define BITP_ACM_EVSTAT_EV7 7 /* Event7 Status. W1C bit. */
|
|
#define BITP_ACM_EVSTAT_EV6 6 /* Event6 Status. W1C bit. */
|
|
#define BITP_ACM_EVSTAT_EV5 5 /* Event5 Status. W1C bit. */
|
|
#define BITP_ACM_EVSTAT_EV4 4 /* Event4 Status. W1C bit. */
|
|
#define BITP_ACM_EVSTAT_EV3 3 /* Event3 Status. W1C bit. */
|
|
#define BITP_ACM_EVSTAT_EV2 2 /* Event2 Status. W1C bit. */
|
|
#define BITP_ACM_EVSTAT_EV1 1 /* Event1 Status. W1C bit. */
|
|
#define BITP_ACM_EVSTAT_EV0 0 /* Event0 Status. W1C bit. Creates an interrupt if corresponding bit in EVMSK register is set. */
|
|
#define BITM_ACM_EVSTAT_ECOM1S (_ADI_MSK(0x00020000,uint32_t)) /* Reflects the ECOM1 bit of ACM_STAT register but this bit will not be cleared by trigger. W1C bit */
|
|
#define BITM_ACM_EVSTAT_ECOM0S (_ADI_MSK(0x00010000,uint32_t)) /* Reflects the ECOM0 bit of ACM_STAT register but this bit will not be cleared by trigger. W1C bit */
|
|
#define BITM_ACM_EVSTAT_EV15 (_ADI_MSK(0x00008000,uint32_t)) /* Event15 Status. W1C bit. */
|
|
#define BITM_ACM_EVSTAT_EV14 (_ADI_MSK(0x00004000,uint32_t)) /* Event14 Status. W1C bit. */
|
|
#define BITM_ACM_EVSTAT_EV13 (_ADI_MSK(0x00002000,uint32_t)) /* Event13 Status. W1C bit. */
|
|
#define BITM_ACM_EVSTAT_EV12 (_ADI_MSK(0x00001000,uint32_t)) /* Event12 Status. W1C bit. */
|
|
#define BITM_ACM_EVSTAT_EV11 (_ADI_MSK(0x00000800,uint32_t)) /* Event11 Status. W1C bit. */
|
|
#define BITM_ACM_EVSTAT_EV10 (_ADI_MSK(0x00000400,uint32_t)) /* Event10 Status. W1C bit. */
|
|
#define BITM_ACM_EVSTAT_EV9 (_ADI_MSK(0x00000200,uint32_t)) /* Event9 Status. W1C bit. */
|
|
#define BITM_ACM_EVSTAT_EV8 (_ADI_MSK(0x00000100,uint32_t)) /* Event8 Status. W1C bit. */
|
|
#define BITM_ACM_EVSTAT_EV7 (_ADI_MSK(0x00000080,uint32_t)) /* Event7 Status. W1C bit. */
|
|
#define BITM_ACM_EVSTAT_EV6 (_ADI_MSK(0x00000040,uint32_t)) /* Event6 Status. W1C bit. */
|
|
#define BITM_ACM_EVSTAT_EV5 (_ADI_MSK(0x00000020,uint32_t)) /* Event5 Status. W1C bit. */
|
|
#define BITM_ACM_EVSTAT_EV4 (_ADI_MSK(0x00000010,uint32_t)) /* Event4 Status. W1C bit. */
|
|
#define BITM_ACM_EVSTAT_EV3 (_ADI_MSK(0x00000008,uint32_t)) /* Event3 Status. W1C bit. */
|
|
#define BITM_ACM_EVSTAT_EV2 (_ADI_MSK(0x00000004,uint32_t)) /* Event2 Status. W1C bit. */
|
|
#define BITM_ACM_EVSTAT_EV1 (_ADI_MSK(0x00000002,uint32_t)) /* Event1 Status. W1C bit. */
|
|
#define BITM_ACM_EVSTAT_EV0 (_ADI_MSK(0x00000001,uint32_t)) /* Event0 Status. W1C bit. Creates an interrupt if corresponding bit in EVMSK register is set. */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
ACM_EVMSK Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_ACM_EVMSK_IECOM1 17 /* Timer1 Event Completion Status Interrupt Enable */
|
|
#define BITP_ACM_EVMSK_IECOM0 16 /* Timer0 Event Completion Status Interrupt Enable */
|
|
#define BITP_ACM_EVMSK_EV15 15 /* Event15 Status Interrupt Enable */
|
|
#define BITP_ACM_EVMSK_EV14 14 /* Event14 Status Interrupt Enable */
|
|
#define BITP_ACM_EVMSK_EV13 13 /* Event13 Status Interrupt Enable */
|
|
#define BITP_ACM_EVMSK_EV12 12 /* Event12 Status Interrupt Enable */
|
|
#define BITP_ACM_EVMSK_EV11 11 /* Event11 Status Interrupt Enable */
|
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#define BITP_ACM_EVMSK_EV10 10 /* Event10 Status Interrupt Enable */
|
|
#define BITP_ACM_EVMSK_EV9 9 /* Event9 Status Interrupt Enable */
|
|
#define BITP_ACM_EVMSK_EV8 8 /* Event8 Status Interrupt Enable */
|
|
#define BITP_ACM_EVMSK_EV7 7 /* Event7 Status Interrupt Enable */
|
|
#define BITP_ACM_EVMSK_EV6 6 /* Event6 Status Interrupt Enable */
|
|
#define BITP_ACM_EVMSK_EV5 5 /* Event5 Status Interrupt Enable */
|
|
#define BITP_ACM_EVMSK_EV4 4 /* Event4 Status Interrupt Enable */
|
|
#define BITP_ACM_EVMSK_EV3 3 /* Event3 Status Interrupt Enable */
|
|
#define BITP_ACM_EVMSK_EV2 2 /* Event2 Status Interrupt Enable */
|
|
#define BITP_ACM_EVMSK_EV1 1 /* Event1 Status Interrupt Enable */
|
|
#define BITP_ACM_EVMSK_EV0 0 /* Event0 Status Interrupt Enable */
|
|
#define BITM_ACM_EVMSK_IECOM1 (_ADI_MSK(0x00020000,uint32_t)) /* Timer1 Event Completion Status Interrupt Enable */
|
|
#define BITM_ACM_EVMSK_IECOM0 (_ADI_MSK(0x00010000,uint32_t)) /* Timer0 Event Completion Status Interrupt Enable */
|
|
#define BITM_ACM_EVMSK_EV15 (_ADI_MSK(0x00008000,uint32_t)) /* Event15 Status Interrupt Enable */
|
|
#define BITM_ACM_EVMSK_EV14 (_ADI_MSK(0x00004000,uint32_t)) /* Event14 Status Interrupt Enable */
|
|
#define BITM_ACM_EVMSK_EV13 (_ADI_MSK(0x00002000,uint32_t)) /* Event13 Status Interrupt Enable */
|
|
#define BITM_ACM_EVMSK_EV12 (_ADI_MSK(0x00001000,uint32_t)) /* Event12 Status Interrupt Enable */
|
|
#define BITM_ACM_EVMSK_EV11 (_ADI_MSK(0x00000800,uint32_t)) /* Event11 Status Interrupt Enable */
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|
#define BITM_ACM_EVMSK_EV10 (_ADI_MSK(0x00000400,uint32_t)) /* Event10 Status Interrupt Enable */
|
|
#define BITM_ACM_EVMSK_EV9 (_ADI_MSK(0x00000200,uint32_t)) /* Event9 Status Interrupt Enable */
|
|
#define BITM_ACM_EVMSK_EV8 (_ADI_MSK(0x00000100,uint32_t)) /* Event8 Status Interrupt Enable */
|
|
#define BITM_ACM_EVMSK_EV7 (_ADI_MSK(0x00000080,uint32_t)) /* Event7 Status Interrupt Enable */
|
|
#define BITM_ACM_EVMSK_EV6 (_ADI_MSK(0x00000040,uint32_t)) /* Event6 Status Interrupt Enable */
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|
#define BITM_ACM_EVMSK_EV5 (_ADI_MSK(0x00000020,uint32_t)) /* Event5 Status Interrupt Enable */
|
|
#define BITM_ACM_EVMSK_EV4 (_ADI_MSK(0x00000010,uint32_t)) /* Event4 Status Interrupt Enable */
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|
#define BITM_ACM_EVMSK_EV3 (_ADI_MSK(0x00000008,uint32_t)) /* Event3 Status Interrupt Enable */
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#define BITM_ACM_EVMSK_EV2 (_ADI_MSK(0x00000004,uint32_t)) /* Event2 Status Interrupt Enable */
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#define BITM_ACM_EVMSK_EV1 (_ADI_MSK(0x00000002,uint32_t)) /* Event1 Status Interrupt Enable */
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#define BITM_ACM_EVMSK_EV0 (_ADI_MSK(0x00000001,uint32_t)) /* Event0 Status Interrupt Enable */
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|
|
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
ACM_MEVSTAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_ACM_MEVSTAT_EV15 15 /* Event15 Missed. W1C bit. */
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#define BITP_ACM_MEVSTAT_EV14 14 /* Event14 Missed. W1C bit. */
|
|
#define BITP_ACM_MEVSTAT_EV13 13 /* Event13 Missed. W1C bit. */
|
|
#define BITP_ACM_MEVSTAT_EV12 12 /* Event12 Missed. W1C bit. */
|
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#define BITP_ACM_MEVSTAT_EV11 11 /* Event11 Missed. W1C bit. */
|
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#define BITP_ACM_MEVSTAT_EV10 10 /* Event10 Missed. W1C bit. */
|
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#define BITP_ACM_MEVSTAT_EV9 9 /* Event9 Missed. W1C bit. */
|
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#define BITP_ACM_MEVSTAT_EV8 8 /* Event8 Missed. W1C bit. */
|
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#define BITP_ACM_MEVSTAT_EV7 7 /* Event7 Missed. W1C bit. */
|
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#define BITP_ACM_MEVSTAT_EV6 6 /* Event6 Missed. W1C bit. */
|
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#define BITP_ACM_MEVSTAT_EV5 5 /* Event5 Missed. W1C bit. */
|
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#define BITP_ACM_MEVSTAT_EV4 4 /* Event4 Missed. W1C bit. */
|
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#define BITP_ACM_MEVSTAT_EV3 3 /* Event3 Missed. W1C bit. */
|
|
#define BITP_ACM_MEVSTAT_EV2 2 /* Event2 Missed. W1C bit. */
|
|
#define BITP_ACM_MEVSTAT_EV1 1 /* Event1 Missed. W1C bit. */
|
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#define BITP_ACM_MEVSTAT_EV0 0 /* Event0 Missed. W1C bit. Creates an interrupt if corresponding bit in MEVMSK register is set. */
|
|
#define BITM_ACM_MEVSTAT_EV15 (_ADI_MSK(0x00008000,uint32_t)) /* Event15 Missed. W1C bit. */
|
|
#define BITM_ACM_MEVSTAT_EV14 (_ADI_MSK(0x00004000,uint32_t)) /* Event14 Missed. W1C bit. */
|
|
#define BITM_ACM_MEVSTAT_EV13 (_ADI_MSK(0x00002000,uint32_t)) /* Event13 Missed. W1C bit. */
|
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#define BITM_ACM_MEVSTAT_EV12 (_ADI_MSK(0x00001000,uint32_t)) /* Event12 Missed. W1C bit. */
|
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#define BITM_ACM_MEVSTAT_EV11 (_ADI_MSK(0x00000800,uint32_t)) /* Event11 Missed. W1C bit. */
|
|
#define BITM_ACM_MEVSTAT_EV10 (_ADI_MSK(0x00000400,uint32_t)) /* Event10 Missed. W1C bit. */
|
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#define BITM_ACM_MEVSTAT_EV9 (_ADI_MSK(0x00000200,uint32_t)) /* Event9 Missed. W1C bit. */
|
|
#define BITM_ACM_MEVSTAT_EV8 (_ADI_MSK(0x00000100,uint32_t)) /* Event8 Missed. W1C bit. */
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|
#define BITM_ACM_MEVSTAT_EV7 (_ADI_MSK(0x00000080,uint32_t)) /* Event7 Missed. W1C bit. */
|
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#define BITM_ACM_MEVSTAT_EV6 (_ADI_MSK(0x00000040,uint32_t)) /* Event6 Missed. W1C bit. */
|
|
#define BITM_ACM_MEVSTAT_EV5 (_ADI_MSK(0x00000020,uint32_t)) /* Event5 Missed. W1C bit. */
|
|
#define BITM_ACM_MEVSTAT_EV4 (_ADI_MSK(0x00000010,uint32_t)) /* Event4 Missed. W1C bit. */
|
|
#define BITM_ACM_MEVSTAT_EV3 (_ADI_MSK(0x00000008,uint32_t)) /* Event3 Missed. W1C bit. */
|
|
#define BITM_ACM_MEVSTAT_EV2 (_ADI_MSK(0x00000004,uint32_t)) /* Event2 Missed. W1C bit. */
|
|
#define BITM_ACM_MEVSTAT_EV1 (_ADI_MSK(0x00000002,uint32_t)) /* Event1 Missed. W1C bit. */
|
|
#define BITM_ACM_MEVSTAT_EV0 (_ADI_MSK(0x00000001,uint32_t)) /* Event0 Missed. W1C bit. Creates an interrupt if corresponding bit in MEVMSK register is set. */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
ACM_MEVMSK Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_ACM_MEVMSK_EV15 15 /* Event15 Missed Interrupt Enable */
|
|
#define BITP_ACM_MEVMSK_EV14 14 /* Event14 Missed Interrupt Enable */
|
|
#define BITP_ACM_MEVMSK_EV13 13 /* Event13 Missed Interrupt Enable */
|
|
#define BITP_ACM_MEVMSK_EV12 12 /* Event12 Missed Interrupt Enable */
|
|
#define BITP_ACM_MEVMSK_EV11 11 /* Event11 Missed Interrupt Enable */
|
|
#define BITP_ACM_MEVMSK_EV10 10 /* Event10 Missed Interrupt Enable */
|
|
#define BITP_ACM_MEVMSK_EV9 9 /* Event9 Missed Interrupt Enable */
|
|
#define BITP_ACM_MEVMSK_EV8 8 /* Event8 Missed Interrupt Enable */
|
|
#define BITP_ACM_MEVMSK_EV7 7 /* Event7 Missed Interrupt Enable */
|
|
#define BITP_ACM_MEVMSK_EV6 6 /* Event6 Missed Interrupt Enable */
|
|
#define BITP_ACM_MEVMSK_EV5 5 /* Event5 Missed Interrupt Enable */
|
|
#define BITP_ACM_MEVMSK_EV4 4 /* Event4 Missed Interrupt Enable */
|
|
#define BITP_ACM_MEVMSK_EV3 3 /* Event3 Missed Interrupt Enable */
|
|
#define BITP_ACM_MEVMSK_EV2 2 /* Event2 Missed Interrupt Enable */
|
|
#define BITP_ACM_MEVMSK_EV1 1 /* Event1 Missed Interrupt Enable */
|
|
#define BITP_ACM_MEVMSK_EV0 0 /* Event0 Missed Interrupt Enable */
|
|
#define BITM_ACM_MEVMSK_EV15 (_ADI_MSK(0x00008000,uint32_t)) /* Event15 Missed Interrupt Enable */
|
|
#define BITM_ACM_MEVMSK_EV14 (_ADI_MSK(0x00004000,uint32_t)) /* Event14 Missed Interrupt Enable */
|
|
#define BITM_ACM_MEVMSK_EV13 (_ADI_MSK(0x00002000,uint32_t)) /* Event13 Missed Interrupt Enable */
|
|
#define BITM_ACM_MEVMSK_EV12 (_ADI_MSK(0x00001000,uint32_t)) /* Event12 Missed Interrupt Enable */
|
|
#define BITM_ACM_MEVMSK_EV11 (_ADI_MSK(0x00000800,uint32_t)) /* Event11 Missed Interrupt Enable */
|
|
#define BITM_ACM_MEVMSK_EV10 (_ADI_MSK(0x00000400,uint32_t)) /* Event10 Missed Interrupt Enable */
|
|
#define BITM_ACM_MEVMSK_EV9 (_ADI_MSK(0x00000200,uint32_t)) /* Event9 Missed Interrupt Enable */
|
|
#define BITM_ACM_MEVMSK_EV8 (_ADI_MSK(0x00000100,uint32_t)) /* Event8 Missed Interrupt Enable */
|
|
#define BITM_ACM_MEVMSK_EV7 (_ADI_MSK(0x00000080,uint32_t)) /* Event7 Missed Interrupt Enable */
|
|
#define BITM_ACM_MEVMSK_EV6 (_ADI_MSK(0x00000040,uint32_t)) /* Event6 Missed Interrupt Enable */
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|
#define BITM_ACM_MEVMSK_EV5 (_ADI_MSK(0x00000020,uint32_t)) /* Event5 Missed Interrupt Enable */
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|
#define BITM_ACM_MEVMSK_EV4 (_ADI_MSK(0x00000010,uint32_t)) /* Event4 Missed Interrupt Enable */
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#define BITM_ACM_MEVMSK_EV3 (_ADI_MSK(0x00000008,uint32_t)) /* Event3 Missed Interrupt Enable */
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|
#define BITM_ACM_MEVMSK_EV2 (_ADI_MSK(0x00000004,uint32_t)) /* Event2 Missed Interrupt Enable */
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|
#define BITM_ACM_MEVMSK_EV1 (_ADI_MSK(0x00000002,uint32_t)) /* Event1 Missed Interrupt Enable */
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|
#define BITM_ACM_MEVMSK_EV0 (_ADI_MSK(0x00000001,uint32_t)) /* Event0 Missed Interrupt Enable */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
ACM_EVCTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_ACM_EVCTL_EPF 1 /* Event Parameter Field. All EPF[4:0] has same external pin timing. */
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|
#define BITP_ACM_EVCTL_ENAEV 0 /* Enable Event */
|
|
#define BITM_ACM_EVCTL_EPF (_ADI_MSK(0x0000003E,uint32_t)) /* Event Parameter Field. All EPF[4:0] has same external pin timing. */
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|
#define BITM_ACM_EVCTL_ENAEV (_ADI_MSK(0x00000001,uint32_t)) /* Enable Event */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
ACM_EVORD Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_ACM_EVORD_EVSTAT 17 /* Reflects the EVSTATn Bit in the EVSTAT Register */
|
|
#define BITP_ACM_EVORD_MEVSTAT 16 /* Reflects the MEVSTATn Bit in the MEVSTAT Register */
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#define BITP_ACM_EVORD_ORD 0 /* Order of Event Completion */
|
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#define BITM_ACM_EVORD_EVSTAT (_ADI_MSK(0x00020000,uint32_t)) /* Reflects the EVSTATn Bit in the EVSTAT Register */
|
|
#define BITM_ACM_EVORD_MEVSTAT (_ADI_MSK(0x00010000,uint32_t)) /* Reflects the MEVSTATn Bit in the MEVSTAT Register */
|
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#define BITM_ACM_EVORD_ORD (_ADI_MSK(0x000000FF,uint32_t)) /* Order of Event Completion */
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|
|
|
/* ==================================================
|
|
DDR Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
DMC0
|
|
========================= */
|
|
#define REG_DMC0_CTL 0xFFC80004 /* DMC0 Control Register */
|
|
#define REG_DMC0_STAT 0xFFC80008 /* DMC0 Status Register */
|
|
#define REG_DMC0_EFFCTL 0xFFC8000C /* DMC0 Efficiency Control Register */
|
|
#define REG_DMC0_PRIO 0xFFC80010 /* DMC0 Priority ID Register */
|
|
#define REG_DMC0_PRIOMSK 0xFFC80014 /* DMC0 Priority ID Mask Register */
|
|
#define REG_DMC0_CFG 0xFFC80040 /* DMC0 Configuration Register */
|
|
#define REG_DMC0_TR0 0xFFC80044 /* DMC0 Timing 0 Register */
|
|
#define REG_DMC0_TR1 0xFFC80048 /* DMC0 Timing 1 Register */
|
|
#define REG_DMC0_TR2 0xFFC8004C /* DMC0 Timing 2 Register */
|
|
#define REG_DMC0_MSK 0xFFC8005C /* DMC0 Mask (Mode Register Shadow) Register */
|
|
#define REG_DMC0_MR 0xFFC80060 /* DMC0 Shadow MR Register */
|
|
#define REG_DMC0_EMR1 0xFFC80064 /* DMC0 Shadow EMR1 Register */
|
|
#define REG_DMC0_EMR2 0xFFC80068 /* DMC0 Shadow EMR2 Register */
|
|
#define REG_DMC0_EMR3 0xFFC8006C /* DMC0 Shadow EMR3 Register */
|
|
#define REG_DMC0_DLLCTL 0xFFC80080 /* DMC0 DLL Control Register */
|
|
#define REG_DMC0_PHY_CTL0 0xFFC80090 /* DMC0 PHY Control 0 Register */
|
|
#define REG_DMC0_PHY_CTL1 0xFFC80094 /* DMC0 PHY Control 1 Register */
|
|
#define REG_DMC0_PHY_CTL2 0xFFC80098 /* DMC0 PHY Control 2 Register */
|
|
#define REG_DMC0_PHY_CTL3 0xFFC8009C /* DMC0 PHY Control 3 Register */
|
|
#define REG_DMC0_PADCTL 0xFFC800C0 /* DMC0 PAD Control Register */
|
|
|
|
/* =========================
|
|
DMC
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DMC_CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DMC_CTL_DLLCAL 13 /* DLL Calibration Start */
|
|
#define BITP_DMC_CTL_PPREF 12 /* Postpone Refresh */
|
|
#define BITP_DMC_CTL_RDTOWR 9 /* Read-to-Write Cycle */
|
|
#define BITP_DMC_CTL_ADDRMODE 8 /* Addressing (Page/Bank) Mode */
|
|
#define BITP_DMC_CTL_PREC 6 /* Precharge */
|
|
#define BITP_DMC_CTL_DPDREQ 5 /* Deep Power Down Request */
|
|
#define BITP_DMC_CTL_PDREQ 4 /* Power Down Request */
|
|
#define BITP_DMC_CTL_SRREQ 3 /* Self Refresh Request */
|
|
#define BITP_DMC_CTL_INIT 2 /* Initialize DRAM Start */
|
|
#define BITP_DMC_CTL_LPDDR 1 /* Low Power DDR Mode */
|
|
#define BITM_DMC_CTL_DLLCAL (_ADI_MSK(0x00002000,uint32_t)) /* DLL Calibration Start */
|
|
#define BITM_DMC_CTL_PPREF (_ADI_MSK(0x00001000,uint32_t)) /* Postpone Refresh */
|
|
|
|
#define BITM_DMC_CTL_RDTOWR (_ADI_MSK(0x00000E00,uint32_t)) /* Read-to-Write Cycle */
|
|
#define ENUM_DMC_CTL_RDTOWR0 (_ADI_MSK(0x00000000,uint32_t)) /* RDTOWR: 0 Cycles Added */
|
|
#define ENUM_DMC_CTL_RDTOWR1 (_ADI_MSK(0x00000200,uint32_t)) /* RDTOWR: 1 Cycle Added */
|
|
#define ENUM_DMC_CTL_RDTOWR2 (_ADI_MSK(0x00000400,uint32_t)) /* RDTOWR: 2 Cycles Added */
|
|
#define ENUM_DMC_CTL_RDTOWR3 (_ADI_MSK(0x00000600,uint32_t)) /* RDTOWR: 3 Cycles Added */
|
|
#define ENUM_DMC_CTL_RDTOWR4 (_ADI_MSK(0x00000800,uint32_t)) /* RDTOWR: 4 Cycles Added */
|
|
#define BITM_DMC_CTL_ADDRMODE (_ADI_MSK(0x00000100,uint32_t)) /* Addressing (Page/Bank) Mode */
|
|
#define BITM_DMC_CTL_PREC (_ADI_MSK(0x00000040,uint32_t)) /* Precharge */
|
|
#define BITM_DMC_CTL_DPDREQ (_ADI_MSK(0x00000020,uint32_t)) /* Deep Power Down Request */
|
|
#define BITM_DMC_CTL_PDREQ (_ADI_MSK(0x00000010,uint32_t)) /* Power Down Request */
|
|
#define BITM_DMC_CTL_SRREQ (_ADI_MSK(0x00000008,uint32_t)) /* Self Refresh Request */
|
|
#define BITM_DMC_CTL_INIT (_ADI_MSK(0x00000004,uint32_t)) /* Initialize DRAM Start */
|
|
#define BITM_DMC_CTL_LPDDR (_ADI_MSK(0x00000002,uint32_t)) /* Low Power DDR Mode */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DMC_STAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DMC_STAT_PHYRDPHASE 20 /* PHY Read Phase */
|
|
#define BITP_DMC_STAT_PENDREF 16 /* Pending Refresh */
|
|
#define BITP_DMC_STAT_DLLCALDONE 13 /* DLL Calibration Done */
|
|
#define BITP_DMC_STAT_DPDACK 5 /* Deep Powerdown Acknowledge */
|
|
#define BITP_DMC_STAT_PDACK 4 /* Power Down Acknowledge */
|
|
#define BITP_DMC_STAT_SRACK 3 /* Self Refresh Acknowledge */
|
|
#define BITP_DMC_STAT_MEMINITDONE 1 /* Memory Initialization Done */
|
|
#define BITP_DMC_STAT_IDLE 0 /* Idle State */
|
|
#define BITM_DMC_STAT_PHYRDPHASE (_ADI_MSK(0x00F00000,uint32_t)) /* PHY Read Phase */
|
|
#define BITM_DMC_STAT_PENDREF (_ADI_MSK(0x000F0000,uint32_t)) /* Pending Refresh */
|
|
#define BITM_DMC_STAT_DLLCALDONE (_ADI_MSK(0x00002000,uint32_t)) /* DLL Calibration Done */
|
|
#define BITM_DMC_STAT_DPDACK (_ADI_MSK(0x00000020,uint32_t)) /* Deep Powerdown Acknowledge */
|
|
#define BITM_DMC_STAT_PDACK (_ADI_MSK(0x00000010,uint32_t)) /* Power Down Acknowledge */
|
|
#define BITM_DMC_STAT_SRACK (_ADI_MSK(0x00000008,uint32_t)) /* Self Refresh Acknowledge */
|
|
#define BITM_DMC_STAT_MEMINITDONE (_ADI_MSK(0x00000002,uint32_t)) /* Memory Initialization Done */
|
|
#define BITM_DMC_STAT_IDLE (_ADI_MSK(0x00000001,uint32_t)) /* Idle State */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DMC_EFFCTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DMC_EFFCTL_IDLECYC 20 /* Idle Cycle */
|
|
#define BITP_DMC_EFFCTL_NUMREF 16 /* Number of Refresh Commands */
|
|
#define BITP_DMC_EFFCTL_PRECBANK7 15 /* Precharge Bank 7 */
|
|
#define BITP_DMC_EFFCTL_PRECBANK6 14 /* Precharge Bank 6 */
|
|
#define BITP_DMC_EFFCTL_PRECBANK5 13 /* Precharge Bank 5 */
|
|
#define BITP_DMC_EFFCTL_PRECBANK4 12 /* Precharge Bank 4 */
|
|
#define BITP_DMC_EFFCTL_PRECBANK3 11 /* Precharge Bank 3 */
|
|
#define BITP_DMC_EFFCTL_PRECBANK2 10 /* Precharge Bank 2 */
|
|
#define BITP_DMC_EFFCTL_PRECBANK1 9 /* Precharge Bank 1 */
|
|
#define BITP_DMC_EFFCTL_PRECBANK0 8 /* Precharge Bank 0 */
|
|
#define BITP_DMC_EFFCTL_WAITWRDATA 7 /* Wait in Write Data Snapshot */
|
|
#define BITP_DMC_EFFCTL_FULLWRDATA 6 /* Wait for Full Write Data */
|
|
#define BITM_DMC_EFFCTL_IDLECYC (_ADI_MSK(0x00F00000,uint32_t)) /* Idle Cycle */
|
|
#define BITM_DMC_EFFCTL_NUMREF (_ADI_MSK(0x000F0000,uint32_t)) /* Number of Refresh Commands */
|
|
#define BITM_DMC_EFFCTL_PRECBANK7 (_ADI_MSK(0x00008000,uint32_t)) /* Precharge Bank 7 */
|
|
#define BITM_DMC_EFFCTL_PRECBANK6 (_ADI_MSK(0x00004000,uint32_t)) /* Precharge Bank 6 */
|
|
#define BITM_DMC_EFFCTL_PRECBANK5 (_ADI_MSK(0x00002000,uint32_t)) /* Precharge Bank 5 */
|
|
#define BITM_DMC_EFFCTL_PRECBANK4 (_ADI_MSK(0x00001000,uint32_t)) /* Precharge Bank 4 */
|
|
#define BITM_DMC_EFFCTL_PRECBANK3 (_ADI_MSK(0x00000800,uint32_t)) /* Precharge Bank 3 */
|
|
#define BITM_DMC_EFFCTL_PRECBANK2 (_ADI_MSK(0x00000400,uint32_t)) /* Precharge Bank 2 */
|
|
#define BITM_DMC_EFFCTL_PRECBANK1 (_ADI_MSK(0x00000200,uint32_t)) /* Precharge Bank 1 */
|
|
#define BITM_DMC_EFFCTL_PRECBANK0 (_ADI_MSK(0x00000100,uint32_t)) /* Precharge Bank 0 */
|
|
#define BITM_DMC_EFFCTL_WAITWRDATA (_ADI_MSK(0x00000080,uint32_t)) /* Wait in Write Data Snapshot */
|
|
#define BITM_DMC_EFFCTL_FULLWRDATA (_ADI_MSK(0x00000040,uint32_t)) /* Wait for Full Write Data */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DMC_PRIO Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DMC_PRIO_ID2 16 /* ID2 Requiring Elevated Priority */
|
|
#define BITP_DMC_PRIO_ID1 0 /* ID1 Requiring Elevated Priority */
|
|
#define BITM_DMC_PRIO_ID2 (_ADI_MSK(0xFFFF0000,uint32_t)) /* ID2 Requiring Elevated Priority */
|
|
#define BITM_DMC_PRIO_ID1 (_ADI_MSK(0x0000FFFF,uint32_t)) /* ID1 Requiring Elevated Priority */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DMC_PRIOMSK Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DMC_PRIOMSK_ID2MSK 16 /* Mask for ID2 */
|
|
#define BITP_DMC_PRIOMSK_ID1MSK 0 /* Mask for ID1 */
|
|
#define BITM_DMC_PRIOMSK_ID2MSK (_ADI_MSK(0xFFFF0000,uint32_t)) /* Mask for ID2 */
|
|
#define BITM_DMC_PRIOMSK_ID1MSK (_ADI_MSK(0x0000FFFF,uint32_t)) /* Mask for ID1 */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DMC_CFG Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DMC_CFG_EXTBANK 12 /* External Banks */
|
|
#define BITP_DMC_CFG_SDRSIZE 8 /* SDRAM Size */
|
|
#define BITP_DMC_CFG_SDRWID 4 /* SDRAM Width */
|
|
#define BITP_DMC_CFG_IFWID 0 /* Interface Width */
|
|
|
|
#define BITM_DMC_CFG_EXTBANK (_ADI_MSK(0x0000F000,uint32_t)) /* External Banks */
|
|
#define ENUM_DMC_CFG_EXTBANK1 (_ADI_MSK(0x00000000,uint32_t)) /* EXTBANK: 1 External Bank */
|
|
|
|
#define BITM_DMC_CFG_SDRSIZE (_ADI_MSK(0x00000F00,uint32_t)) /* SDRAM Size */
|
|
#define ENUM_DMC_CFG_SDRSIZE64 (_ADI_MSK(0x00000000,uint32_t)) /* SDRSIZE: 64M Bit SDRAM (LPDDR Only) */
|
|
#define ENUM_DMC_CFG_SDRSIZE128 (_ADI_MSK(0x00000100,uint32_t)) /* SDRSIZE: 128M Bit SDRAM (LPDDR Only) */
|
|
#define ENUM_DMC_CFG_SDRSIZE256 (_ADI_MSK(0x00000200,uint32_t)) /* SDRSIZE: 256M Bit SDRAM */
|
|
#define ENUM_DMC_CFG_SDRSIZE512 (_ADI_MSK(0x00000300,uint32_t)) /* SDRSIZE: 512M Bit SDRAM */
|
|
#define ENUM_DMC_CFG_SDRSIZE1G (_ADI_MSK(0x00000400,uint32_t)) /* SDRSIZE: 1G Bit SDRAM */
|
|
#define ENUM_DMC_CFG_SDRSIZE2G (_ADI_MSK(0x00000500,uint32_t)) /* SDRSIZE: 2G Bit SDRAM */
|
|
|
|
#define BITM_DMC_CFG_SDRWID (_ADI_MSK(0x000000F0,uint32_t)) /* SDRAM Width */
|
|
#define ENUM_DMC_CFG_SDRWID16 (_ADI_MSK(0x00000020,uint32_t)) /* SDRWID: 16-Bit Wide SDRAM */
|
|
|
|
#define BITM_DMC_CFG_IFWID (_ADI_MSK(0x0000000F,uint32_t)) /* Interface Width */
|
|
#define ENUM_DMC_CFG_IFWID16 (_ADI_MSK(0x00000002,uint32_t)) /* IFWID: 16-Bit Wide Interface */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DMC_TR0 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DMC_TR0_TMRD 28 /* Timing Mode Register Delay */
|
|
#define BITP_DMC_TR0_TRC 20 /* Timing Row Cycle */
|
|
#define BITP_DMC_TR0_TRAS 12 /* Timing Row Active Time */
|
|
#define BITP_DMC_TR0_TRP 8 /* Timing RAS Precharge. */
|
|
#define BITP_DMC_TR0_TWTR 4 /* Timing Write to Read */
|
|
#define BITP_DMC_TR0_TRCD 0 /* Timing RAS to CAS Delay */
|
|
#define BITM_DMC_TR0_TMRD (_ADI_MSK(0xF0000000,uint32_t)) /* Timing Mode Register Delay */
|
|
#define BITM_DMC_TR0_TRC (_ADI_MSK(0x03F00000,uint32_t)) /* Timing Row Cycle */
|
|
#define BITM_DMC_TR0_TRAS (_ADI_MSK(0x0001F000,uint32_t)) /* Timing Row Active Time */
|
|
#define BITM_DMC_TR0_TRP (_ADI_MSK(0x00000F00,uint32_t)) /* Timing RAS Precharge. */
|
|
#define BITM_DMC_TR0_TWTR (_ADI_MSK(0x000000F0,uint32_t)) /* Timing Write to Read */
|
|
#define BITM_DMC_TR0_TRCD (_ADI_MSK(0x0000000F,uint32_t)) /* Timing RAS to CAS Delay */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DMC_TR1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DMC_TR1_TRRD 28 /* Timing Read-Read Delay */
|
|
#define BITP_DMC_TR1_TRFC 16 /* Timing Refresh-to-Command */
|
|
#define BITP_DMC_TR1_TREF 0 /* Timing Refresh Interval */
|
|
#define BITM_DMC_TR1_TRRD (_ADI_MSK(0x70000000,uint32_t)) /* Timing Read-Read Delay */
|
|
#define BITM_DMC_TR1_TRFC (_ADI_MSK(0x00FF0000,uint32_t)) /* Timing Refresh-to-Command */
|
|
#define BITM_DMC_TR1_TREF (_ADI_MSK(0x00003FFF,uint32_t)) /* Timing Refresh Interval */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DMC_TR2 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DMC_TR2_TCKE 20 /* Timing Clock Enable */
|
|
#define BITP_DMC_TR2_TXP 16 /* Timing Exit Powerdown */
|
|
#define BITP_DMC_TR2_TWR 12 /* Timing Write Recovery */
|
|
#define BITP_DMC_TR2_TRTP 8 /* Timing Read-to-Precharge */
|
|
#define BITP_DMC_TR2_TFAW 0 /* Timing Four-Activated-Window */
|
|
#define BITM_DMC_TR2_TCKE (_ADI_MSK(0x00F00000,uint32_t)) /* Timing Clock Enable */
|
|
#define BITM_DMC_TR2_TXP (_ADI_MSK(0x000F0000,uint32_t)) /* Timing Exit Powerdown */
|
|
#define BITM_DMC_TR2_TWR (_ADI_MSK(0x0000F000,uint32_t)) /* Timing Write Recovery */
|
|
#define BITM_DMC_TR2_TRTP (_ADI_MSK(0x00000F00,uint32_t)) /* Timing Read-to-Precharge */
|
|
#define BITM_DMC_TR2_TFAW (_ADI_MSK(0x0000001F,uint32_t)) /* Timing Four-Activated-Window */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DMC_MSK Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DMC_MSK_EMR3 11 /* Shadow EMR3 Unmask */
|
|
#define BITP_DMC_MSK_EMR2 10 /* Shadow EMR2 Unmask */
|
|
#define BITP_DMC_MSK_EMR1 9 /* Shadow EMR1 Unmask */
|
|
#define BITP_DMC_MSK_MR 8 /* Shadow MR Unmask */
|
|
#define BITM_DMC_MSK_EMR3 (_ADI_MSK(0x00000800,uint32_t)) /* Shadow EMR3 Unmask */
|
|
#define BITM_DMC_MSK_EMR2 (_ADI_MSK(0x00000400,uint32_t)) /* Shadow EMR2 Unmask */
|
|
#define BITM_DMC_MSK_EMR1 (_ADI_MSK(0x00000200,uint32_t)) /* Shadow EMR1 Unmask */
|
|
#define BITM_DMC_MSK_MR (_ADI_MSK(0x00000100,uint32_t)) /* Shadow MR Unmask */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DMC_MR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DMC_MR_PD 12 /* Active Powerdown Mode */
|
|
#define BITP_DMC_MR_WRRECOV 9 /* Write Recovery */
|
|
#define BITP_DMC_MR_DLLRST 8 /* DLL Reset */
|
|
#define BITP_DMC_MR_CL 4 /* CAS Latency */
|
|
#define BITP_DMC_MR_BLEN 0 /* Burst Length */
|
|
#define BITM_DMC_MR_PD (_ADI_MSK(0x00001000,uint32_t)) /* Active Powerdown Mode */
|
|
#define BITM_DMC_MR_WRRECOV (_ADI_MSK(0x00000E00,uint32_t)) /* Write Recovery */
|
|
#define BITM_DMC_MR_DLLRST (_ADI_MSK(0x00000100,uint32_t)) /* DLL Reset */
|
|
|
|
#define BITM_DMC_MR_CL (_ADI_MSK(0x00000070,uint32_t)) /* CAS Latency */
|
|
#define ENUM_DMC_MR_CL2 (_ADI_MSK(0x00000020,uint32_t)) /* CL: 2 clock cycle latency */
|
|
#define ENUM_DMC_MR_CL3 (_ADI_MSK(0x00000030,uint32_t)) /* CL: 3 clock cycle latency */
|
|
#define ENUM_DMC_MR_CL4 (_ADI_MSK(0x00000040,uint32_t)) /* CL: 4 clock cycle latency (DDR2) */
|
|
#define ENUM_DMC_MR_CL5 (_ADI_MSK(0x00000050,uint32_t)) /* CL: 5 clock cycle latency (DDR2) */
|
|
#define ENUM_DMC_MR_CL6 (_ADI_MSK(0x00000060,uint32_t)) /* CL: 6 clock cycle latency (DDR2) */
|
|
|
|
#define BITM_DMC_MR_BLEN (_ADI_MSK(0x00000007,uint32_t)) /* Burst Length */
|
|
#define ENUM_DMC_MR_BLEN4 (_ADI_MSK(0x00000002,uint32_t)) /* BLEN: 4-Bit Burst Length */
|
|
#define ENUM_DMC_MR_BLEN8 (_ADI_MSK(0x00000003,uint32_t)) /* BLEN: 8-Bit Burst Length */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DMC_EMR1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DMC_EMR1_QOFF 12 /* Output Buffer Enable */
|
|
#define BITP_DMC_EMR1_DQS 10 /* DQS Enable */
|
|
#define BITP_DMC_EMR1_RTT1 6 /* Termination Resistance 1 */
|
|
#define BITP_DMC_EMR1_AL 3 /* Additive Latency */
|
|
#define BITP_DMC_EMR1_RTT0 2 /* Termination Resistance 0. */
|
|
#define BITP_DMC_EMR1_DIC 1 /* Output Driver Impedance Control */
|
|
#define BITP_DMC_EMR1_DLLEN 0 /* DLL Enable */
|
|
#define BITM_DMC_EMR1_QOFF (_ADI_MSK(0x00001000,uint32_t)) /* Output Buffer Enable */
|
|
#define BITM_DMC_EMR1_DQS (_ADI_MSK(0x00000400,uint32_t)) /* DQS Enable */
|
|
|
|
#define BITM_DMC_EMR1_RTT1 (_ADI_MSK(0x00000040,uint32_t)) /* Termination Resistance 1 */
|
|
#define ENUM_DMC_EMR1_RTT1_0 (_ADI_MSK(0x00000000,uint32_t)) /* RTT1: Disable RTT1 */
|
|
#define ENUM_DMC_EMR1_RTT1_1 (_ADI_MSK(0x00000040,uint32_t)) /* RTT1: Enable RTT1 */
|
|
#define BITM_DMC_EMR1_AL (_ADI_MSK(0x00000038,uint32_t)) /* Additive Latency */
|
|
|
|
#define BITM_DMC_EMR1_RTT0 (_ADI_MSK(0x00000004,uint32_t)) /* Termination Resistance 0. */
|
|
#define ENUM_DMC_EMR1_RTT0_0 (_ADI_MSK(0x00000000,uint32_t)) /* RTT0: Disable RTT0 */
|
|
#define ENUM_DMC_EMR1_RTT0_1 (_ADI_MSK(0x00000004,uint32_t)) /* RTT0: Enable RTT0 */
|
|
#define BITM_DMC_EMR1_DIC (_ADI_MSK(0x00000002,uint32_t)) /* Output Driver Impedance Control */
|
|
#define BITM_DMC_EMR1_DLLEN (_ADI_MSK(0x00000001,uint32_t)) /* DLL Enable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DMC_EMR2 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DMC_EMR2_SRF 7 /* High Temp. Self Refresh */
|
|
#define BITP_DMC_EMR2_DS 5 /* Drive Strength */
|
|
#define BITP_DMC_EMR2_TCSR 3 /* Temp. Comp. Self Refresh */
|
|
#define BITP_DMC_EMR2_PASR 0 /* Partial Array Self Refresh */
|
|
#define BITM_DMC_EMR2_SRF (_ADI_MSK(0x00000080,uint32_t)) /* High Temp. Self Refresh */
|
|
#define BITM_DMC_EMR2_DS (_ADI_MSK(0x00000060,uint32_t)) /* Drive Strength */
|
|
#define BITM_DMC_EMR2_TCSR (_ADI_MSK(0x00000018,uint32_t)) /* Temp. Comp. Self Refresh */
|
|
#define BITM_DMC_EMR2_PASR (_ADI_MSK(0x00000007,uint32_t)) /* Partial Array Self Refresh */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DMC_DLLCTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DMC_DLLCTL_DATACYC 8 /* Data Cycles */
|
|
#define BITP_DMC_DLLCTL_DLLCALRDCNT 0 /* DLL Calibration RD Count */
|
|
|
|
#define BITM_DMC_DLLCTL_DATACYC (_ADI_MSK(0x00000F00,uint32_t)) /* Data Cycles */
|
|
#define ENUM_DMC_DLLCTL_DATACYC2 (_ADI_MSK(0x00000200,uint32_t)) /* DATACYC: 2 Clock Cycles Latency */
|
|
#define ENUM_DMC_DLLCTL_DATACYC3 (_ADI_MSK(0x00000300,uint32_t)) /* DATACYC: 3 Clock Cycles Latency */
|
|
#define ENUM_DMC_DLLCTL_DATACYC4 (_ADI_MSK(0x00000400,uint32_t)) /* DATACYC: 4 Clock Cycles Latency */
|
|
#define ENUM_DMC_DLLCTL_DATACYC5 (_ADI_MSK(0x00000500,uint32_t)) /* DATACYC: 5 Clock Cycles Latency */
|
|
#define BITM_DMC_DLLCTL_DLLCALRDCNT (_ADI_MSK(0x000000FF,uint32_t)) /* DLL Calibration RD Count */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DMC_PHY_CTL1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DMC_PHY_CTL1_CONTODTVAL 19 /* Select ODT value on controller */
|
|
|
|
#define BITM_DMC_PHY_CTL1_CONTODTVAL (_ADI_MSK(0x00080000,uint32_t)) /* Select ODT value on controller */
|
|
#define ENUM_DMC_PHY_CTL1_ODT_75 (_ADI_MSK(0x00000000,uint32_t)) /* CONTODTVAL: 75 Ohms Termination */
|
|
#define ENUM_DMC_PHY_CTL1_ODT_150 (_ADI_MSK(0x00080000,uint32_t)) /* CONTODTVAL: 150 Ohms Termination */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DMC_PHY_CTL3 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DMC_PHY_CTL3_OFST1 26 /* Offset Parameter 1 */
|
|
#define BITP_DMC_PHY_CTL3_OFST0 24 /* Offset Parameter 0 */
|
|
#define BITP_DMC_PHY_CTL3_ENODTDQS 10 /* Enables controller ODT on read of DQS */
|
|
#define BITP_DMC_PHY_CTL3_TMG1 7 /* Timing Parameter 1 */
|
|
#define BITP_DMC_PHY_CTL3_TMG0 6 /* Timing Parameter 0 */
|
|
#define BITP_DMC_PHY_CTL3_ENODTDQ 2 /* Enables controller ODT on read of DQ */
|
|
#define BITM_DMC_PHY_CTL3_OFST1 (_ADI_MSK(0x04000000,uint32_t)) /* Offset Parameter 1 */
|
|
#define BITM_DMC_PHY_CTL3_OFST0 (_ADI_MSK(0x01000000,uint32_t)) /* Offset Parameter 0 */
|
|
#define BITM_DMC_PHY_CTL3_ENODTDQS (_ADI_MSK(0x00000400,uint32_t)) /* Enables controller ODT on read of DQS */
|
|
#define BITM_DMC_PHY_CTL3_TMG1 (_ADI_MSK(0x00000080,uint32_t)) /* Timing Parameter 1 */
|
|
#define BITM_DMC_PHY_CTL3_TMG0 (_ADI_MSK(0x00000040,uint32_t)) /* Timing Parameter 0 */
|
|
#define BITM_DMC_PHY_CTL3_ENODTDQ (_ADI_MSK(0x00000004,uint32_t)) /* Enables controller ODT on read of DQ */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DMC_PADCTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DMC_PADCTL_CKEOE 19 /* CKE Output Enable */
|
|
#define BITP_DMC_PADCTL_CKEPWD 18 /* CKE pad receiver power down. */
|
|
#define BITP_DMC_PADCTL_CKEODS 16 /* CKE Output Drive Strength */
|
|
#define BITP_DMC_PADCTL_CMDOE 15 /* CMD Output Enable */
|
|
#define BITP_DMC_PADCTL_CMDPWD 14 /* CMD Powerdown */
|
|
#define BITP_DMC_PADCTL_CMDODS 12 /* CMD Output Drive Strength */
|
|
#define BITP_DMC_PADCTL_CLKOE 11 /* CLK Output Enable */
|
|
#define BITP_DMC_PADCTL_CLKPWD 10 /* CLK Powerdown */
|
|
#define BITP_DMC_PADCTL_CLKODS 8 /* Clock Output Drive Strength */
|
|
#define BITP_DMC_PADCTL_DQSPWD 6 /* DQ/DQS Powerdown */
|
|
#define BITP_DMC_PADCTL_DQSODS 4 /* DQS Output Drive Strength */
|
|
#define BITP_DMC_PADCTL_DQPWD 2 /* DQ Powerdown. */
|
|
#define BITP_DMC_PADCTL_DQODS 0 /* DQ Output Drive Strength */
|
|
#define BITM_DMC_PADCTL_CKEOE (_ADI_MSK(0x00080000,uint32_t)) /* CKE Output Enable */
|
|
#define BITM_DMC_PADCTL_CKEPWD (_ADI_MSK(0x00040000,uint32_t)) /* CKE pad receiver power down. */
|
|
#define BITM_DMC_PADCTL_CKEODS (_ADI_MSK(0x00030000,uint32_t)) /* CKE Output Drive Strength */
|
|
#define BITM_DMC_PADCTL_CMDOE (_ADI_MSK(0x00008000,uint32_t)) /* CMD Output Enable */
|
|
#define BITM_DMC_PADCTL_CMDPWD (_ADI_MSK(0x00004000,uint32_t)) /* CMD Powerdown */
|
|
#define BITM_DMC_PADCTL_CMDODS (_ADI_MSK(0x00003000,uint32_t)) /* CMD Output Drive Strength */
|
|
#define BITM_DMC_PADCTL_CLKOE (_ADI_MSK(0x00000800,uint32_t)) /* CLK Output Enable */
|
|
#define BITM_DMC_PADCTL_CLKPWD (_ADI_MSK(0x00000400,uint32_t)) /* CLK Powerdown */
|
|
#define BITM_DMC_PADCTL_CLKODS (_ADI_MSK(0x00000300,uint32_t)) /* Clock Output Drive Strength */
|
|
#define BITM_DMC_PADCTL_DQSPWD (_ADI_MSK(0x00000040,uint32_t)) /* DQ/DQS Powerdown */
|
|
#define BITM_DMC_PADCTL_DQSODS (_ADI_MSK(0x00000030,uint32_t)) /* DQS Output Drive Strength */
|
|
#define BITM_DMC_PADCTL_DQPWD (_ADI_MSK(0x00000004,uint32_t)) /* DQ Powerdown. */
|
|
#define BITM_DMC_PADCTL_DQODS (_ADI_MSK(0x00000003,uint32_t)) /* DQ Output Drive Strength */
|
|
|
|
/* ==================================================
|
|
System Cross Bar Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
SCB0
|
|
========================= */
|
|
#define REG_SCB0_ARBR0 0xFFCA2408 /* SCB0 Arbitration Read Channel Master Interface n Register */
|
|
#define REG_SCB0_ARBR1 0xFFCA2428 /* SCB0 Arbitration Read Channel Master Interface n Register */
|
|
#define REG_SCB0_ARBR2 0xFFCA2448 /* SCB0 Arbitration Read Channel Master Interface n Register */
|
|
#define REG_SCB0_ARBR3 0xFFCA2468 /* SCB0 Arbitration Read Channel Master Interface n Register */
|
|
#define REG_SCB0_ARBR4 0xFFCA2488 /* SCB0 Arbitration Read Channel Master Interface n Register */
|
|
#define REG_SCB0_ARBR5 0xFFCA24A8 /* SCB0 Arbitration Read Channel Master Interface n Register */
|
|
#define REG_SCB0_ARBW0 0xFFCA240C /* SCB0 Arbitration Write Channel Master Interface n Register */
|
|
#define REG_SCB0_ARBW1 0xFFCA242C /* SCB0 Arbitration Write Channel Master Interface n Register */
|
|
#define REG_SCB0_ARBW2 0xFFCA244C /* SCB0 Arbitration Write Channel Master Interface n Register */
|
|
#define REG_SCB0_ARBW3 0xFFCA246C /* SCB0 Arbitration Write Channel Master Interface n Register */
|
|
#define REG_SCB0_ARBW4 0xFFCA248C /* SCB0 Arbitration Write Channel Master Interface n Register */
|
|
#define REG_SCB0_ARBW5 0xFFCA24AC /* SCB0 Arbitration Write Channel Master Interface n Register */
|
|
#define REG_SCB0_SLAVES 0xFFCA2FC0 /* SCB0 Slave Interfaces Number Register */
|
|
#define REG_SCB0_MASTERS 0xFFCA2FC4 /* SCB0 Master Interfaces Number Register */
|
|
|
|
/* =========================
|
|
SCB1
|
|
========================= */
|
|
#define REG_SCB1_ARBR0 0xFFC42408 /* SCB1 Arbitration Read Channel Master Interface n Register */
|
|
#define REG_SCB1_ARBW0 0xFFC4240C /* SCB1 Arbitration Write Channel Master Interface n Register */
|
|
#define REG_SCB1_SLAVES 0xFFC42FC0 /* SCB1 Slave Interfaces Number Register */
|
|
#define REG_SCB1_MASTERS 0xFFC42FC4 /* SCB1 Master Interfaces Number Register */
|
|
|
|
/* =========================
|
|
SCB2
|
|
========================= */
|
|
#define REG_SCB2_ARBR0 0xFFC06408 /* SCB2 Arbitration Read Channel Master Interface n Register */
|
|
#define REG_SCB2_ARBW0 0xFFC0640C /* SCB2 Arbitration Write Channel Master Interface n Register */
|
|
#define REG_SCB2_SLAVES 0xFFC06FC0 /* SCB2 Slave Interfaces Number Register */
|
|
#define REG_SCB2_MASTERS 0xFFC06FC4 /* SCB2 Master Interfaces Number Register */
|
|
|
|
/* =========================
|
|
SCB3
|
|
========================= */
|
|
#define REG_SCB3_ARBR0 0xFFC08408 /* SCB3 Arbitration Read Channel Master Interface n Register */
|
|
#define REG_SCB3_ARBW0 0xFFC0840C /* SCB3 Arbitration Write Channel Master Interface n Register */
|
|
#define REG_SCB3_SLAVES 0xFFC08FC0 /* SCB3 Slave Interfaces Number Register */
|
|
#define REG_SCB3_MASTERS 0xFFC08FC4 /* SCB3 Master Interfaces Number Register */
|
|
|
|
/* =========================
|
|
SCB4
|
|
========================= */
|
|
#define REG_SCB4_ARBR0 0xFFC0A408 /* SCB4 Arbitration Read Channel Master Interface n Register */
|
|
#define REG_SCB4_ARBW0 0xFFC0A40C /* SCB4 Arbitration Write Channel Master Interface n Register */
|
|
#define REG_SCB4_SLAVES 0xFFC0AFC0 /* SCB4 Slave Interfaces Number Register */
|
|
#define REG_SCB4_MASTERS 0xFFC0AFC4 /* SCB4 Master Interfaces Number Register */
|
|
|
|
/* =========================
|
|
SCB5
|
|
========================= */
|
|
#define REG_SCB5_ARBR0 0xFFC0C408 /* SCB5 Arbitration Read Channel Master Interface n Register */
|
|
#define REG_SCB5_ARBW0 0xFFC0C40C /* SCB5 Arbitration Write Channel Master Interface n Register */
|
|
#define REG_SCB5_SLAVES 0xFFC0CFC0 /* SCB5 Slave Interfaces Number Register */
|
|
#define REG_SCB5_MASTERS 0xFFC0CFC4 /* SCB5 Master Interfaces Number Register */
|
|
|
|
/* =========================
|
|
SCB6
|
|
========================= */
|
|
#define REG_SCB6_ARBR0 0xFFC0E408 /* SCB6 Arbitration Read Channel Master Interface n Register */
|
|
#define REG_SCB6_ARBW0 0xFFC0E40C /* SCB6 Arbitration Write Channel Master Interface n Register */
|
|
#define REG_SCB6_SLAVES 0xFFC0EFC0 /* SCB6 Slave Interfaces Number Register */
|
|
#define REG_SCB6_MASTERS 0xFFC0EFC4 /* SCB6 Master Interfaces Number Register */
|
|
|
|
/* =========================
|
|
SCB7
|
|
========================= */
|
|
#define REG_SCB7_ARBR0 0xFFC11408 /* SCB7 Arbitration Read Channel Master Interface n Register */
|
|
#define REG_SCB7_ARBW0 0xFFC1140C /* SCB7 Arbitration Write Channel Master Interface n Register */
|
|
#define REG_SCB7_SLAVES 0xFFC11FC0 /* SCB7 Slave Interfaces Number Register */
|
|
#define REG_SCB7_MASTERS 0xFFC11FC4 /* SCB7 Master Interfaces Number Register */
|
|
|
|
/* =========================
|
|
SCB8
|
|
========================= */
|
|
#define REG_SCB8_ARBR0 0xFFC13408 /* SCB8 Arbitration Read Channel Master Interface n Register */
|
|
#define REG_SCB8_ARBW0 0xFFC1340C /* SCB8 Arbitration Write Channel Master Interface n Register */
|
|
#define REG_SCB8_SLAVES 0xFFC13FC0 /* SCB8 Slave Interfaces Number Register */
|
|
#define REG_SCB8_MASTERS 0xFFC13FC4 /* SCB8 Master Interfaces Number Register */
|
|
|
|
/* =========================
|
|
SCB9
|
|
========================= */
|
|
#define REG_SCB9_ARBR0 0xFFC15408 /* SCB9 Arbitration Read Channel Master Interface n Register */
|
|
#define REG_SCB9_ARBW0 0xFFC1540C /* SCB9 Arbitration Write Channel Master Interface n Register */
|
|
#define REG_SCB9_SLAVES 0xFFC15FC0 /* SCB9 Slave Interfaces Number Register */
|
|
#define REG_SCB9_MASTERS 0xFFC15FC4 /* SCB9 Master Interfaces Number Register */
|
|
|
|
/* =========================
|
|
SCB10
|
|
========================= */
|
|
#define REG_SCB10_ARBR0 0xFFCA1408 /* SCB10 Arbitration Read Channel Master Interface n Register */
|
|
#define REG_SCB10_ARBR1 0xFFCA1428 /* SCB10 Arbitration Read Channel Master Interface n Register */
|
|
#define REG_SCB10_ARBR2 0xFFCA1448 /* SCB10 Arbitration Read Channel Master Interface n Register */
|
|
#define REG_SCB10_ARBW0 0xFFCA140C /* SCB10 Arbitration Write Channel Master Interface n Register */
|
|
#define REG_SCB10_ARBW1 0xFFCA142C /* SCB10 Arbitration Write Channel Master Interface n Register */
|
|
#define REG_SCB10_ARBW2 0xFFCA144C /* SCB10 Arbitration Write Channel Master Interface n Register */
|
|
#define REG_SCB10_SLAVES 0xFFCA1FC0 /* SCB10 Slave Interfaces Number Register */
|
|
#define REG_SCB10_MASTERS 0xFFCA1FC4 /* SCB10 Master Interfaces Number Register */
|
|
|
|
/* =========================
|
|
SCB11
|
|
========================= */
|
|
#define REG_SCB11_ARBR0 0xFFCA0408 /* SCB11 Arbitration Read Channel Master Interface n Register */
|
|
#define REG_SCB11_ARBR1 0xFFCA0428 /* SCB11 Arbitration Read Channel Master Interface n Register */
|
|
#define REG_SCB11_ARBR2 0xFFCA0448 /* SCB11 Arbitration Read Channel Master Interface n Register */
|
|
#define REG_SCB11_ARBR3 0xFFCA0468 /* SCB11 Arbitration Read Channel Master Interface n Register */
|
|
#define REG_SCB11_ARBR4 0xFFCA0488 /* SCB11 Arbitration Read Channel Master Interface n Register */
|
|
#define REG_SCB11_ARBR5 0xFFCA04A8 /* SCB11 Arbitration Read Channel Master Interface n Register */
|
|
#define REG_SCB11_ARBR6 0xFFCA04C8 /* SCB11 Arbitration Read Channel Master Interface n Register */
|
|
#define REG_SCB11_ARBW0 0xFFCA040C /* SCB11 Arbitration Write Channel Master Interface n Register */
|
|
#define REG_SCB11_ARBW1 0xFFCA042C /* SCB11 Arbitration Write Channel Master Interface n Register */
|
|
#define REG_SCB11_ARBW2 0xFFCA044C /* SCB11 Arbitration Write Channel Master Interface n Register */
|
|
#define REG_SCB11_ARBW3 0xFFCA046C /* SCB11 Arbitration Write Channel Master Interface n Register */
|
|
#define REG_SCB11_ARBW4 0xFFCA048C /* SCB11 Arbitration Write Channel Master Interface n Register */
|
|
#define REG_SCB11_ARBW5 0xFFCA04AC /* SCB11 Arbitration Write Channel Master Interface n Register */
|
|
#define REG_SCB11_ARBW6 0xFFCA04CC /* SCB11 Arbitration Write Channel Master Interface n Register */
|
|
#define REG_SCB11_SLAVES 0xFFCA0FC0 /* SCB11 Slave Interfaces Number Register */
|
|
#define REG_SCB11_MASTERS 0xFFCA0FC4 /* SCB11 Master Interfaces Number Register */
|
|
|
|
/* =========================
|
|
SCB
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SCB_ARBR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SCB_ARBR_SLOT 24 /* Slot Number */
|
|
#define BITP_SCB_ARBR_SLAVE 0 /* Slave Interface */
|
|
#define BITM_SCB_ARBR_SLOT (_ADI_MSK(0xFF000000,uint32_t)) /* Slot Number */
|
|
#define BITM_SCB_ARBR_SLAVE (_ADI_MSK(0x000000FF,uint32_t)) /* Slave Interface */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SCB_ARBW Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SCB_ARBW_SLOT 24 /* Slot Number */
|
|
#define BITP_SCB_ARBW_SLAVE 0 /* Slave Interface */
|
|
#define BITM_SCB_ARBW_SLOT (_ADI_MSK(0xFF000000,uint32_t)) /* Slot Number */
|
|
#define BITM_SCB_ARBW_SLAVE (_ADI_MSK(0x000000FF,uint32_t)) /* Slave Interface */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SCB_SLAVES Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SCB_SLAVES_SI 0 /* Slave Interface Value */
|
|
#define BITM_SCB_SLAVES_SI (_ADI_MSK(0x000000FF,uint32_t)) /* Slave Interface Value */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SCB_MASTERS Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SCB_MASTERS_MI 0 /* Master Interface Value */
|
|
#define BITM_SCB_MASTERS_MI (_ADI_MSK(0x000000FF,uint32_t)) /* Master Interface Value */
|
|
|
|
/* ==================================================
|
|
L2 Memory Controller Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
L2CTL0
|
|
========================= */
|
|
#define REG_L2CTL0_CTL 0xFFCA3000 /* L2CTL0 Control Register */
|
|
#define REG_L2CTL0_ACTL_C0 0xFFCA3004 /* L2CTL0 Access Control Core 0 Register */
|
|
#define REG_L2CTL0_ACTL_C1 0xFFCA3008 /* L2CTL0 Access Control Core 1 Register */
|
|
#define REG_L2CTL0_ACTL_SYS 0xFFCA300C /* L2CTL0 Access Control System Register */
|
|
#define REG_L2CTL0_STAT 0xFFCA3010 /* L2CTL0 Status Register */
|
|
#define REG_L2CTL0_RPCR 0xFFCA3014 /* L2CTL0 Read Priority Count Register */
|
|
#define REG_L2CTL0_WPCR 0xFFCA3018 /* L2CTL0 Write Priority Count Register */
|
|
#define REG_L2CTL0_RFA 0xFFCA3024 /* L2CTL0 Refresh Address Register */
|
|
#define REG_L2CTL0_ERRADDR0 0xFFCA3040 /* L2CTL0 ECC Error Address 0 Register */
|
|
#define REG_L2CTL0_ERRADDR1 0xFFCA3044 /* L2CTL0 ECC Error Address 1 Register */
|
|
#define REG_L2CTL0_ERRADDR2 0xFFCA3048 /* L2CTL0 ECC Error Address 2 Register */
|
|
#define REG_L2CTL0_ERRADDR3 0xFFCA304C /* L2CTL0 ECC Error Address 3 Register */
|
|
#define REG_L2CTL0_ERRADDR4 0xFFCA3050 /* L2CTL0 ECC Error Address 4 Register */
|
|
#define REG_L2CTL0_ERRADDR5 0xFFCA3054 /* L2CTL0 ECC Error Address 5 Register */
|
|
#define REG_L2CTL0_ERRADDR6 0xFFCA3058 /* L2CTL0 ECC Error Address 6 Register */
|
|
#define REG_L2CTL0_ERRADDR7 0xFFCA305C /* L2CTL0 ECC Error Address 7 Register */
|
|
#define REG_L2CTL0_ET0 0xFFCA3080 /* L2CTL0 Error Type 0 Register */
|
|
#define REG_L2CTL0_EADDR0 0xFFCA3084 /* L2CTL0 Error Type 0 Address Register */
|
|
#define REG_L2CTL0_ET1 0xFFCA3088 /* L2CTL0 Error Type 1 Register */
|
|
#define REG_L2CTL0_EADDR1 0xFFCA308C /* L2CTL0 Error Type 1 Address Register */
|
|
|
|
/* =========================
|
|
L2CTL
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
L2CTL_CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_L2CTL_CTL_LOCK 31 /* Lock */
|
|
#define BITP_L2CTL_CTL_DISURP 16 /* Disable Urgent Request Priority */
|
|
#define BITP_L2CTL_CTL_ECCMAP7 15 /* ECC Map Bank 7 */
|
|
#define BITP_L2CTL_CTL_ECCMAP6 14 /* ECC Map Bank 6 */
|
|
#define BITP_L2CTL_CTL_ECCMAP5 13 /* ECC Map Bank 5 */
|
|
#define BITP_L2CTL_CTL_ECCMAP4 12 /* ECC Map Bank 4 */
|
|
#define BITP_L2CTL_CTL_ECCMAP3 11 /* ECC Map Bank 3 */
|
|
#define BITP_L2CTL_CTL_ECCMAP2 10 /* ECC Map Bank 2 */
|
|
#define BITP_L2CTL_CTL_ECCMAP1 9 /* ECC Map Bank 1 */
|
|
#define BITP_L2CTL_CTL_ECCMAP0 8 /* ECC Map Bank 0 */
|
|
#define BITP_L2CTL_CTL_BK7EDIS 7 /* Bank 7 ECC Disable */
|
|
#define BITP_L2CTL_CTL_BK6EDIS 6 /* Bank 6 ECC Disable */
|
|
#define BITP_L2CTL_CTL_BK5EDIS 5 /* Bank 5 ECC Disable */
|
|
#define BITP_L2CTL_CTL_BK4EDIS 4 /* Bank 4 ECC Disable */
|
|
#define BITP_L2CTL_CTL_BK3EDIS 3 /* Bank 3 ECC Disable */
|
|
#define BITP_L2CTL_CTL_BK2EDIS 2 /* Bank 2 ECC Disable */
|
|
#define BITP_L2CTL_CTL_BK1EDIS 1 /* Bank 1 ECC Disable */
|
|
#define BITP_L2CTL_CTL_BK0EDIS 0 /* Bank 0 ECC Disable */
|
|
#define BITM_L2CTL_CTL_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
|
|
#define BITM_L2CTL_CTL_DISURP (_ADI_MSK(0x00010000,uint32_t)) /* Disable Urgent Request Priority */
|
|
#define BITM_L2CTL_CTL_ECCMAP7 (_ADI_MSK(0x00008000,uint32_t)) /* ECC Map Bank 7 */
|
|
#define BITM_L2CTL_CTL_ECCMAP6 (_ADI_MSK(0x00004000,uint32_t)) /* ECC Map Bank 6 */
|
|
#define BITM_L2CTL_CTL_ECCMAP5 (_ADI_MSK(0x00002000,uint32_t)) /* ECC Map Bank 5 */
|
|
#define BITM_L2CTL_CTL_ECCMAP4 (_ADI_MSK(0x00001000,uint32_t)) /* ECC Map Bank 4 */
|
|
#define BITM_L2CTL_CTL_ECCMAP3 (_ADI_MSK(0x00000800,uint32_t)) /* ECC Map Bank 3 */
|
|
#define BITM_L2CTL_CTL_ECCMAP2 (_ADI_MSK(0x00000400,uint32_t)) /* ECC Map Bank 2 */
|
|
#define BITM_L2CTL_CTL_ECCMAP1 (_ADI_MSK(0x00000200,uint32_t)) /* ECC Map Bank 1 */
|
|
#define BITM_L2CTL_CTL_ECCMAP0 (_ADI_MSK(0x00000100,uint32_t)) /* ECC Map Bank 0 */
|
|
#define BITM_L2CTL_CTL_BK7EDIS (_ADI_MSK(0x00000080,uint32_t)) /* Bank 7 ECC Disable */
|
|
#define BITM_L2CTL_CTL_BK6EDIS (_ADI_MSK(0x00000040,uint32_t)) /* Bank 6 ECC Disable */
|
|
#define BITM_L2CTL_CTL_BK5EDIS (_ADI_MSK(0x00000020,uint32_t)) /* Bank 5 ECC Disable */
|
|
#define BITM_L2CTL_CTL_BK4EDIS (_ADI_MSK(0x00000010,uint32_t)) /* Bank 4 ECC Disable */
|
|
#define BITM_L2CTL_CTL_BK3EDIS (_ADI_MSK(0x00000008,uint32_t)) /* Bank 3 ECC Disable */
|
|
#define BITM_L2CTL_CTL_BK2EDIS (_ADI_MSK(0x00000004,uint32_t)) /* Bank 2 ECC Disable */
|
|
#define BITM_L2CTL_CTL_BK1EDIS (_ADI_MSK(0x00000002,uint32_t)) /* Bank 1 ECC Disable */
|
|
#define BITM_L2CTL_CTL_BK0EDIS (_ADI_MSK(0x00000001,uint32_t)) /* Bank 0 ECC Disable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
L2CTL_ACTL_C0 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_L2CTL_ACTL_C0_LOCK 31 /* Lock */
|
|
#define BITP_L2CTL_ACTL_C0_BK7WDIS 7 /* Bank 7 Write Disable */
|
|
#define BITP_L2CTL_ACTL_C0_BK6WDIS 6 /* Bank 6 Write Disable */
|
|
#define BITP_L2CTL_ACTL_C0_BK5WDIS 5 /* Bank 5 Write Disable */
|
|
#define BITP_L2CTL_ACTL_C0_BK4WDIS 4 /* Bank 4 Write Disable */
|
|
#define BITP_L2CTL_ACTL_C0_BK3WDIS 3 /* Bank 3 Write Disable */
|
|
#define BITP_L2CTL_ACTL_C0_BK2WDIS 2 /* Bank 2 Write Disable */
|
|
#define BITP_L2CTL_ACTL_C0_BK1WDIS 1 /* Bank 1 Write Disable */
|
|
#define BITP_L2CTL_ACTL_C0_BK0WDIS 0 /* Bank 0 Write Disable */
|
|
#define BITM_L2CTL_ACTL_C0_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
|
|
#define BITM_L2CTL_ACTL_C0_BK7WDIS (_ADI_MSK(0x00000080,uint32_t)) /* Bank 7 Write Disable */
|
|
#define BITM_L2CTL_ACTL_C0_BK6WDIS (_ADI_MSK(0x00000040,uint32_t)) /* Bank 6 Write Disable */
|
|
#define BITM_L2CTL_ACTL_C0_BK5WDIS (_ADI_MSK(0x00000020,uint32_t)) /* Bank 5 Write Disable */
|
|
#define BITM_L2CTL_ACTL_C0_BK4WDIS (_ADI_MSK(0x00000010,uint32_t)) /* Bank 4 Write Disable */
|
|
#define BITM_L2CTL_ACTL_C0_BK3WDIS (_ADI_MSK(0x00000008,uint32_t)) /* Bank 3 Write Disable */
|
|
#define BITM_L2CTL_ACTL_C0_BK2WDIS (_ADI_MSK(0x00000004,uint32_t)) /* Bank 2 Write Disable */
|
|
#define BITM_L2CTL_ACTL_C0_BK1WDIS (_ADI_MSK(0x00000002,uint32_t)) /* Bank 1 Write Disable */
|
|
#define BITM_L2CTL_ACTL_C0_BK0WDIS (_ADI_MSK(0x00000001,uint32_t)) /* Bank 0 Write Disable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
L2CTL_ACTL_C1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_L2CTL_ACTL_C1_LOCK 31 /* Lock */
|
|
#define BITP_L2CTL_ACTL_C1_BK7WDIS 7 /* Bank 7 Write Disable */
|
|
#define BITP_L2CTL_ACTL_C1_BK6WDIS 6 /* Bank 6 Write Disable */
|
|
#define BITP_L2CTL_ACTL_C1_BK5WDIS 5 /* Bank 5 Write Disable */
|
|
#define BITP_L2CTL_ACTL_C1_BK4WDIS 4 /* Bank 4 Write Disable */
|
|
#define BITP_L2CTL_ACTL_C1_BK3WDIS 3 /* Bank 3 Write Disable */
|
|
#define BITP_L2CTL_ACTL_C1_BK2WDIS 2 /* Bank 2 Write Disable */
|
|
#define BITP_L2CTL_ACTL_C1_BK1WDIS 1 /* Bank 1 Write Disable */
|
|
#define BITP_L2CTL_ACTL_C1_BK0WDIS 0 /* Bank 0 Write Disable */
|
|
#define BITM_L2CTL_ACTL_C1_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
|
|
#define BITM_L2CTL_ACTL_C1_BK7WDIS (_ADI_MSK(0x00000080,uint32_t)) /* Bank 7 Write Disable */
|
|
#define BITM_L2CTL_ACTL_C1_BK6WDIS (_ADI_MSK(0x00000040,uint32_t)) /* Bank 6 Write Disable */
|
|
#define BITM_L2CTL_ACTL_C1_BK5WDIS (_ADI_MSK(0x00000020,uint32_t)) /* Bank 5 Write Disable */
|
|
#define BITM_L2CTL_ACTL_C1_BK4WDIS (_ADI_MSK(0x00000010,uint32_t)) /* Bank 4 Write Disable */
|
|
#define BITM_L2CTL_ACTL_C1_BK3WDIS (_ADI_MSK(0x00000008,uint32_t)) /* Bank 3 Write Disable */
|
|
#define BITM_L2CTL_ACTL_C1_BK2WDIS (_ADI_MSK(0x00000004,uint32_t)) /* Bank 2 Write Disable */
|
|
#define BITM_L2CTL_ACTL_C1_BK1WDIS (_ADI_MSK(0x00000002,uint32_t)) /* Bank 1 Write Disable */
|
|
#define BITM_L2CTL_ACTL_C1_BK0WDIS (_ADI_MSK(0x00000001,uint32_t)) /* Bank 0 Write Disable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
L2CTL_ACTL_SYS Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_L2CTL_ACTL_SYS_LOCK 31 /* Lock */
|
|
#define BITP_L2CTL_ACTL_SYS_BK7WDIS 7 /* Bank 7 Write Disable */
|
|
#define BITP_L2CTL_ACTL_SYS_BK6WDIS 6 /* Bank 6 Write Disable */
|
|
#define BITP_L2CTL_ACTL_SYS_BK5WDIS 5 /* Bank 5 Write Disable */
|
|
#define BITP_L2CTL_ACTL_SYS_BK4WDIS 4 /* Bank 4 Write Disable */
|
|
#define BITP_L2CTL_ACTL_SYS_BK3WDIS 3 /* Bank 3 Write Disable */
|
|
#define BITP_L2CTL_ACTL_SYS_BK2WDIS 2 /* Bank 2 Write Disable */
|
|
#define BITP_L2CTL_ACTL_SYS_BK1WDIS 1 /* Bank 1 Write Disable */
|
|
#define BITP_L2CTL_ACTL_SYS_BK0WDIS 0 /* Bank 0 Write Disable */
|
|
#define BITM_L2CTL_ACTL_SYS_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
|
|
#define BITM_L2CTL_ACTL_SYS_BK7WDIS (_ADI_MSK(0x00000080,uint32_t)) /* Bank 7 Write Disable */
|
|
#define BITM_L2CTL_ACTL_SYS_BK6WDIS (_ADI_MSK(0x00000040,uint32_t)) /* Bank 6 Write Disable */
|
|
#define BITM_L2CTL_ACTL_SYS_BK5WDIS (_ADI_MSK(0x00000020,uint32_t)) /* Bank 5 Write Disable */
|
|
#define BITM_L2CTL_ACTL_SYS_BK4WDIS (_ADI_MSK(0x00000010,uint32_t)) /* Bank 4 Write Disable */
|
|
#define BITM_L2CTL_ACTL_SYS_BK3WDIS (_ADI_MSK(0x00000008,uint32_t)) /* Bank 3 Write Disable */
|
|
#define BITM_L2CTL_ACTL_SYS_BK2WDIS (_ADI_MSK(0x00000004,uint32_t)) /* Bank 2 Write Disable */
|
|
#define BITM_L2CTL_ACTL_SYS_BK1WDIS (_ADI_MSK(0x00000002,uint32_t)) /* Bank 1 Write Disable */
|
|
#define BITM_L2CTL_ACTL_SYS_BK0WDIS (_ADI_MSK(0x00000001,uint32_t)) /* Bank 0 Write Disable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
L2CTL_STAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_L2CTL_STAT_ECCERR7 15 /* ECC Error Bank 7 */
|
|
#define BITP_L2CTL_STAT_ECCERR6 14 /* ECC Error Bank 6 */
|
|
#define BITP_L2CTL_STAT_ECCERR5 13 /* ECC Error Bank 5 */
|
|
#define BITP_L2CTL_STAT_ECCERR4 12 /* ECC Error Bank 4 */
|
|
#define BITP_L2CTL_STAT_ECCERR3 11 /* ECC Error Bank 3 */
|
|
#define BITP_L2CTL_STAT_ECCERR2 10 /* ECC Error Bank 2 */
|
|
#define BITP_L2CTL_STAT_ECCERR1 9 /* ECC Error Bank 1 */
|
|
#define BITP_L2CTL_STAT_ECCERR0 8 /* ECC Error Bank 0 */
|
|
#define BITP_L2CTL_STAT_RFRS 4 /* Refresh Register Status */
|
|
#define BITP_L2CTL_STAT_ERR1 1 /* Error Port 1 */
|
|
#define BITP_L2CTL_STAT_ERR0 0 /* Error Port 0 */
|
|
#define BITM_L2CTL_STAT_ECCERR7 (_ADI_MSK(0x00008000,uint32_t)) /* ECC Error Bank 7 */
|
|
#define BITM_L2CTL_STAT_ECCERR6 (_ADI_MSK(0x00004000,uint32_t)) /* ECC Error Bank 6 */
|
|
#define BITM_L2CTL_STAT_ECCERR5 (_ADI_MSK(0x00002000,uint32_t)) /* ECC Error Bank 5 */
|
|
#define BITM_L2CTL_STAT_ECCERR4 (_ADI_MSK(0x00001000,uint32_t)) /* ECC Error Bank 4 */
|
|
#define BITM_L2CTL_STAT_ECCERR3 (_ADI_MSK(0x00000800,uint32_t)) /* ECC Error Bank 3 */
|
|
#define BITM_L2CTL_STAT_ECCERR2 (_ADI_MSK(0x00000400,uint32_t)) /* ECC Error Bank 2 */
|
|
#define BITM_L2CTL_STAT_ECCERR1 (_ADI_MSK(0x00000200,uint32_t)) /* ECC Error Bank 1 */
|
|
#define BITM_L2CTL_STAT_ECCERR0 (_ADI_MSK(0x00000100,uint32_t)) /* ECC Error Bank 0 */
|
|
#define BITM_L2CTL_STAT_RFRS (_ADI_MSK(0x00000010,uint32_t)) /* Refresh Register Status */
|
|
#define BITM_L2CTL_STAT_ERR1 (_ADI_MSK(0x00000002,uint32_t)) /* Error Port 1 */
|
|
#define BITM_L2CTL_STAT_ERR0 (_ADI_MSK(0x00000001,uint32_t)) /* Error Port 0 */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
L2CTL_RPCR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_L2CTL_RPCR_RPC1 8 /* Read Priority Count 1 */
|
|
#define BITP_L2CTL_RPCR_RPC0 0 /* Read Priority Count 0 */
|
|
#define BITM_L2CTL_RPCR_RPC1 (_ADI_MSK(0x0000FF00,uint32_t)) /* Read Priority Count 1 */
|
|
#define BITM_L2CTL_RPCR_RPC0 (_ADI_MSK(0x000000FF,uint32_t)) /* Read Priority Count 0 */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
L2CTL_WPCR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_L2CTL_WPCR_WPC1 8 /* Write Priority Count 1 */
|
|
#define BITP_L2CTL_WPCR_WPC0 0 /* Write Priority Count 0 */
|
|
#define BITM_L2CTL_WPCR_WPC1 (_ADI_MSK(0x0000FF00,uint32_t)) /* Write Priority Count 1 */
|
|
#define BITM_L2CTL_WPCR_WPC0 (_ADI_MSK(0x000000FF,uint32_t)) /* Write Priority Count 0 */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
L2CTL_RFA Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_L2CTL_RFA_ADDRHI 16 /* Address High */
|
|
#define BITP_L2CTL_RFA_ADDRLO 0 /* Address Low */
|
|
#define BITM_L2CTL_RFA_ADDRHI (_ADI_MSK(0xFFFF0000,uint32_t)) /* Address High */
|
|
#define BITM_L2CTL_RFA_ADDRLO (_ADI_MSK(0x0000FFFF,uint32_t)) /* Address Low */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
L2CTL_ET0 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_L2CTL_ET0_ID 8 /* Error ID */
|
|
#define BITP_L2CTL_ET0_RDWR 4 /* Read/Write Error */
|
|
#define BITP_L2CTL_ET0_ECCERR 3 /* ECC Error */
|
|
#define BITP_L2CTL_ET0_ACCERR 2 /* Access Error */
|
|
#define BITP_L2CTL_ET0_RSVERR 1 /* Reserved Error */
|
|
#define BITP_L2CTL_ET0_ROMERR 0 /* ROM Error */
|
|
#define BITM_L2CTL_ET0_ID (_ADI_MSK(0x0000FF00,uint32_t)) /* Error ID */
|
|
#define BITM_L2CTL_ET0_RDWR (_ADI_MSK(0x00000010,uint32_t)) /* Read/Write Error */
|
|
#define BITM_L2CTL_ET0_ECCERR (_ADI_MSK(0x00000008,uint32_t)) /* ECC Error */
|
|
#define BITM_L2CTL_ET0_ACCERR (_ADI_MSK(0x00000004,uint32_t)) /* Access Error */
|
|
#define BITM_L2CTL_ET0_RSVERR (_ADI_MSK(0x00000002,uint32_t)) /* Reserved Error */
|
|
#define BITM_L2CTL_ET0_ROMERR (_ADI_MSK(0x00000001,uint32_t)) /* ROM Error */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
L2CTL_ET1 Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_L2CTL_ET1_ID 8 /* Error ID */
|
|
#define BITP_L2CTL_ET1_RDWR 4 /* Read/Write Error */
|
|
#define BITP_L2CTL_ET1_ECCERR 3 /* ECC Error */
|
|
#define BITP_L2CTL_ET1_ACCERR 2 /* Access Error */
|
|
#define BITP_L2CTL_ET1_RSVERR 1 /* Reserved Error */
|
|
#define BITP_L2CTL_ET1_ROMERR 0 /* ROM Error */
|
|
#define BITM_L2CTL_ET1_ID (_ADI_MSK(0x0000FF00,uint32_t)) /* Error ID */
|
|
#define BITM_L2CTL_ET1_RDWR (_ADI_MSK(0x00000010,uint32_t)) /* Read/Write Error */
|
|
#define BITM_L2CTL_ET1_ECCERR (_ADI_MSK(0x00000008,uint32_t)) /* ECC Error */
|
|
#define BITM_L2CTL_ET1_ACCERR (_ADI_MSK(0x00000004,uint32_t)) /* Access Error */
|
|
#define BITM_L2CTL_ET1_RSVERR (_ADI_MSK(0x00000002,uint32_t)) /* Reserved Error */
|
|
#define BITM_L2CTL_ET1_ROMERR (_ADI_MSK(0x00000001,uint32_t)) /* ROM Error */
|
|
|
|
/* ==================================================
|
|
System Event Controller Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
SEC0
|
|
========================= */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SEC Core Interface (SCI) Register Definitions
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define REG_SEC0_CCTL0 0xFFCA4400 /* SEC0 SCI Control Register n */
|
|
#define REG_SEC0_CCTL1 0xFFCA4440 /* SEC0 SCI Control Register n */
|
|
#define REG_SEC0_CSTAT0 0xFFCA4404 /* SEC0 SCI Status Register n */
|
|
#define REG_SEC0_CSTAT1 0xFFCA4444 /* SEC0 SCI Status Register n */
|
|
#define REG_SEC0_CPND0 0xFFCA4408 /* SEC0 Core Pending Register n */
|
|
#define REG_SEC0_CPND1 0xFFCA4448 /* SEC0 Core Pending Register n */
|
|
#define REG_SEC0_CACT0 0xFFCA440C /* SEC0 SCI Active Register n */
|
|
#define REG_SEC0_CACT1 0xFFCA444C /* SEC0 SCI Active Register n */
|
|
#define REG_SEC0_CPMSK0 0xFFCA4410 /* SEC0 SCI Priority Mask Register n */
|
|
#define REG_SEC0_CPMSK1 0xFFCA4450 /* SEC0 SCI Priority Mask Register n */
|
|
#define REG_SEC0_CGMSK0 0xFFCA4414 /* SEC0 SCI Group Mask Register n */
|
|
#define REG_SEC0_CGMSK1 0xFFCA4454 /* SEC0 SCI Group Mask Register n */
|
|
#define REG_SEC0_CPLVL0 0xFFCA4418 /* SEC0 SCI Priority Level Register n */
|
|
#define REG_SEC0_CPLVL1 0xFFCA4458 /* SEC0 SCI Priority Level Register n */
|
|
#define REG_SEC0_CSID0 0xFFCA441C /* SEC0 SCI Source ID Register n */
|
|
#define REG_SEC0_CSID1 0xFFCA445C /* SEC0 SCI Source ID Register n */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SEC Fault Management Interface (SFI) Register Definitions
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define REG_SEC0_FCTL 0xFFCA4010 /* SEC0 Fault Control Register */
|
|
#define REG_SEC0_FSTAT 0xFFCA4014 /* SEC0 Fault Status Register */
|
|
#define REG_SEC0_FSID 0xFFCA4018 /* SEC0 Fault Source ID Register */
|
|
#define REG_SEC0_FEND 0xFFCA401C /* SEC0 Fault End Register */
|
|
#define REG_SEC0_FDLY 0xFFCA4020 /* SEC0 Fault Delay Register */
|
|
#define REG_SEC0_FDLY_CUR 0xFFCA4024 /* SEC0 Fault Delay Current Register */
|
|
#define REG_SEC0_FSRDLY 0xFFCA4028 /* SEC0 Fault System Reset Delay Register */
|
|
#define REG_SEC0_FSRDLY_CUR 0xFFCA402C /* SEC0 Fault System Reset Delay Current Register */
|
|
#define REG_SEC0_FCOPP 0xFFCA4030 /* SEC0 Fault COP Period Register */
|
|
#define REG_SEC0_FCOPP_CUR 0xFFCA4034 /* SEC0 Fault COP Period Current Register */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SEC Global Register Definitions
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define REG_SEC0_GCTL 0xFFCA4000 /* SEC0 Global Control Register */
|
|
#define REG_SEC0_GSTAT 0xFFCA4004 /* SEC0 Global Status Register */
|
|
#define REG_SEC0_RAISE 0xFFCA4008 /* SEC0 Global Raise Register */
|
|
#define REG_SEC0_END 0xFFCA400C /* SEC0 Global End Register */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SEC Source Interface (SSI) Register Definitions
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define REG_SEC0_SCTL0 0xFFCA4800 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL1 0xFFCA4808 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL2 0xFFCA4810 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL3 0xFFCA4818 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL4 0xFFCA4820 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL5 0xFFCA4828 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL6 0xFFCA4830 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL7 0xFFCA4838 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL8 0xFFCA4840 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL9 0xFFCA4848 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL10 0xFFCA4850 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL11 0xFFCA4858 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL12 0xFFCA4860 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL13 0xFFCA4868 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL14 0xFFCA4870 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL15 0xFFCA4878 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL16 0xFFCA4880 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL17 0xFFCA4888 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL18 0xFFCA4890 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL19 0xFFCA4898 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL20 0xFFCA48A0 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL21 0xFFCA48A8 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL22 0xFFCA48B0 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL23 0xFFCA48B8 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL24 0xFFCA48C0 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL25 0xFFCA48C8 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL26 0xFFCA48D0 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL27 0xFFCA48D8 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL28 0xFFCA48E0 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL29 0xFFCA48E8 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL30 0xFFCA48F0 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL31 0xFFCA48F8 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL32 0xFFCA4900 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL33 0xFFCA4908 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL34 0xFFCA4910 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL35 0xFFCA4918 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL36 0xFFCA4920 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL37 0xFFCA4928 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL38 0xFFCA4930 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL39 0xFFCA4938 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL40 0xFFCA4940 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL41 0xFFCA4948 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL42 0xFFCA4950 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL43 0xFFCA4958 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL44 0xFFCA4960 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL45 0xFFCA4968 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL46 0xFFCA4970 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL47 0xFFCA4978 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL48 0xFFCA4980 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL49 0xFFCA4988 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL50 0xFFCA4990 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL51 0xFFCA4998 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL52 0xFFCA49A0 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL53 0xFFCA49A8 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL54 0xFFCA49B0 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL55 0xFFCA49B8 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL56 0xFFCA49C0 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL57 0xFFCA49C8 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL58 0xFFCA49D0 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL59 0xFFCA49D8 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL60 0xFFCA49E0 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL61 0xFFCA49E8 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL62 0xFFCA49F0 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL63 0xFFCA49F8 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL64 0xFFCA4A00 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL65 0xFFCA4A08 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL66 0xFFCA4A10 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL67 0xFFCA4A18 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL68 0xFFCA4A20 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL69 0xFFCA4A28 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL70 0xFFCA4A30 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL71 0xFFCA4A38 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL72 0xFFCA4A40 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL73 0xFFCA4A48 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL74 0xFFCA4A50 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL75 0xFFCA4A58 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL76 0xFFCA4A60 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL77 0xFFCA4A68 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL78 0xFFCA4A70 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL79 0xFFCA4A78 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL80 0xFFCA4A80 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL81 0xFFCA4A88 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL82 0xFFCA4A90 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL83 0xFFCA4A98 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL84 0xFFCA4AA0 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL85 0xFFCA4AA8 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL86 0xFFCA4AB0 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL87 0xFFCA4AB8 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL88 0xFFCA4AC0 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL89 0xFFCA4AC8 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL90 0xFFCA4AD0 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL91 0xFFCA4AD8 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL92 0xFFCA4AE0 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL93 0xFFCA4AE8 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL94 0xFFCA4AF0 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL95 0xFFCA4AF8 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL96 0xFFCA4B00 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL97 0xFFCA4B08 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL98 0xFFCA4B10 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL99 0xFFCA4B18 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL100 0xFFCA4B20 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL101 0xFFCA4B28 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL102 0xFFCA4B30 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL103 0xFFCA4B38 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL104 0xFFCA4B40 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL105 0xFFCA4B48 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL106 0xFFCA4B50 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL107 0xFFCA4B58 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL108 0xFFCA4B60 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL109 0xFFCA4B68 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL110 0xFFCA4B70 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL111 0xFFCA4B78 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL112 0xFFCA4B80 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL113 0xFFCA4B88 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL114 0xFFCA4B90 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL115 0xFFCA4B98 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL116 0xFFCA4BA0 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL117 0xFFCA4BA8 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL118 0xFFCA4BB0 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL119 0xFFCA4BB8 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL120 0xFFCA4BC0 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL121 0xFFCA4BC8 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL122 0xFFCA4BD0 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL123 0xFFCA4BD8 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL124 0xFFCA4BE0 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL125 0xFFCA4BE8 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL126 0xFFCA4BF0 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL127 0xFFCA4BF8 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL128 0xFFCA4C00 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL129 0xFFCA4C08 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL130 0xFFCA4C10 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL131 0xFFCA4C18 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL132 0xFFCA4C20 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL133 0xFFCA4C28 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL134 0xFFCA4C30 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL135 0xFFCA4C38 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL136 0xFFCA4C40 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL137 0xFFCA4C48 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL138 0xFFCA4C50 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SCTL139 0xFFCA4C58 /* SEC0 Source Control Register n */
|
|
#define REG_SEC0_SSTAT0 0xFFCA4804 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT1 0xFFCA480C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT2 0xFFCA4814 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT3 0xFFCA481C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT4 0xFFCA4824 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT5 0xFFCA482C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT6 0xFFCA4834 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT7 0xFFCA483C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT8 0xFFCA4844 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT9 0xFFCA484C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT10 0xFFCA4854 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT11 0xFFCA485C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT12 0xFFCA4864 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT13 0xFFCA486C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT14 0xFFCA4874 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT15 0xFFCA487C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT16 0xFFCA4884 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT17 0xFFCA488C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT18 0xFFCA4894 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT19 0xFFCA489C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT20 0xFFCA48A4 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT21 0xFFCA48AC /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT22 0xFFCA48B4 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT23 0xFFCA48BC /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT24 0xFFCA48C4 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT25 0xFFCA48CC /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT26 0xFFCA48D4 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT27 0xFFCA48DC /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT28 0xFFCA48E4 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT29 0xFFCA48EC /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT30 0xFFCA48F4 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT31 0xFFCA48FC /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT32 0xFFCA4904 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT33 0xFFCA490C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT34 0xFFCA4914 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT35 0xFFCA491C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT36 0xFFCA4924 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT37 0xFFCA492C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT38 0xFFCA4934 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT39 0xFFCA493C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT40 0xFFCA4944 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT41 0xFFCA494C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT42 0xFFCA4954 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT43 0xFFCA495C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT44 0xFFCA4964 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT45 0xFFCA496C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT46 0xFFCA4974 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT47 0xFFCA497C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT48 0xFFCA4984 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT49 0xFFCA498C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT50 0xFFCA4994 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT51 0xFFCA499C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT52 0xFFCA49A4 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT53 0xFFCA49AC /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT54 0xFFCA49B4 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT55 0xFFCA49BC /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT56 0xFFCA49C4 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT57 0xFFCA49CC /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT58 0xFFCA49D4 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT59 0xFFCA49DC /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT60 0xFFCA49E4 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT61 0xFFCA49EC /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT62 0xFFCA49F4 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT63 0xFFCA49FC /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT64 0xFFCA4A04 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT65 0xFFCA4A0C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT66 0xFFCA4A14 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT67 0xFFCA4A1C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT68 0xFFCA4A24 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT69 0xFFCA4A2C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT70 0xFFCA4A34 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT71 0xFFCA4A3C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT72 0xFFCA4A44 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT73 0xFFCA4A4C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT74 0xFFCA4A54 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT75 0xFFCA4A5C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT76 0xFFCA4A64 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT77 0xFFCA4A6C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT78 0xFFCA4A74 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT79 0xFFCA4A7C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT80 0xFFCA4A84 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT81 0xFFCA4A8C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT82 0xFFCA4A94 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT83 0xFFCA4A9C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT84 0xFFCA4AA4 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT85 0xFFCA4AAC /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT86 0xFFCA4AB4 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT87 0xFFCA4ABC /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT88 0xFFCA4AC4 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT89 0xFFCA4ACC /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT90 0xFFCA4AD4 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT91 0xFFCA4ADC /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT92 0xFFCA4AE4 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT93 0xFFCA4AEC /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT94 0xFFCA4AF4 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT95 0xFFCA4AFC /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT96 0xFFCA4B04 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT97 0xFFCA4B0C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT98 0xFFCA4B14 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT99 0xFFCA4B1C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT100 0xFFCA4B24 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT101 0xFFCA4B2C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT102 0xFFCA4B34 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT103 0xFFCA4B3C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT104 0xFFCA4B44 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT105 0xFFCA4B4C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT106 0xFFCA4B54 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT107 0xFFCA4B5C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT108 0xFFCA4B64 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT109 0xFFCA4B6C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT110 0xFFCA4B74 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT111 0xFFCA4B7C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT112 0xFFCA4B84 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT113 0xFFCA4B8C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT114 0xFFCA4B94 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT115 0xFFCA4B9C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT116 0xFFCA4BA4 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT117 0xFFCA4BAC /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT118 0xFFCA4BB4 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT119 0xFFCA4BBC /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT120 0xFFCA4BC4 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT121 0xFFCA4BCC /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT122 0xFFCA4BD4 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT123 0xFFCA4BDC /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT124 0xFFCA4BE4 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT125 0xFFCA4BEC /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT126 0xFFCA4BF4 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT127 0xFFCA4BFC /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT128 0xFFCA4C04 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT129 0xFFCA4C0C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT130 0xFFCA4C14 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT131 0xFFCA4C1C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT132 0xFFCA4C24 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT133 0xFFCA4C2C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT134 0xFFCA4C34 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT135 0xFFCA4C3C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT136 0xFFCA4C44 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT137 0xFFCA4C4C /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT138 0xFFCA4C54 /* SEC0 Source Status Register n */
|
|
#define REG_SEC0_SSTAT139 0xFFCA4C5C /* SEC0 Source Status Register n */
|
|
|
|
/* =========================
|
|
SEC
|
|
========================= */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SEC_CCTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SEC_CCTL_LOCK 31 /* Lock */
|
|
#define BITP_SEC_CCTL_NMIEN 16 /* NMI Enable */
|
|
#define BITP_SEC_CCTL_WFI 12 /* Wait For Idle */
|
|
#define BITP_SEC_CCTL_RESET 1 /* Reset */
|
|
#define BITP_SEC_CCTL_EN 0 /* Enable */
|
|
|
|
#define BITM_SEC_CCTL_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
|
|
#define ENUM_SEC_CCTL_UNLOCK (_ADI_MSK(0x00000000,uint32_t)) /* LOCK: Unlock */
|
|
#define ENUM_SEC_CCTL_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* LOCK: Lock */
|
|
|
|
#define BITM_SEC_CCTL_NMIEN (_ADI_MSK(0x00010000,uint32_t)) /* NMI Enable */
|
|
#define ENUM_SEC_CCTL_NMI_DIS (_ADI_MSK(0x00000000,uint32_t)) /* NMIEN: Disable */
|
|
#define ENUM_SEC_CCTL_NMI_EN (_ADI_MSK(0x00010000,uint32_t)) /* NMIEN: Enable */
|
|
|
|
#define BITM_SEC_CCTL_WFI (_ADI_MSK(0x00001000,uint32_t)) /* Wait For Idle */
|
|
#define ENUM_SEC_CCTL_NO_WAITIDLE (_ADI_MSK(0x00000000,uint32_t)) /* WFI: No Action */
|
|
#define ENUM_SEC_CCTL_WAITIDLE (_ADI_MSK(0x00001000,uint32_t)) /* WFI: Wait for Idle */
|
|
|
|
#define BITM_SEC_CCTL_RESET (_ADI_MSK(0x00000002,uint32_t)) /* Reset */
|
|
#define ENUM_SEC_CCTL_NO_RESET (_ADI_MSK(0x00000000,uint32_t)) /* RESET: No Action */
|
|
#define ENUM_SEC_CCTL_RESET (_ADI_MSK(0x00000002,uint32_t)) /* RESET: Reset */
|
|
|
|
#define BITM_SEC_CCTL_EN (_ADI_MSK(0x00000001,uint32_t)) /* Enable */
|
|
#define ENUM_SEC_CCTL_DIS (_ADI_MSK(0x00000000,uint32_t)) /* EN: Disable */
|
|
#define ENUM_SEC_CCTL_EN (_ADI_MSK(0x00000001,uint32_t)) /* EN: Enable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SEC_CSTAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SEC_CSTAT_NMI 16 /* NMI */
|
|
#define BITP_SEC_CSTAT_WFI 12 /* Wait For Idle */
|
|
#define BITP_SEC_CSTAT_SIDV 10 /* SID Valid */
|
|
#define BITP_SEC_CSTAT_ACTV 9 /* ACT Valid */
|
|
#define BITP_SEC_CSTAT_PNDV 8 /* PND Valid */
|
|
#define BITP_SEC_CSTAT_ERRC 4 /* Error Cause */
|
|
#define BITP_SEC_CSTAT_ERR 1 /* Error */
|
|
|
|
#define BITM_SEC_CSTAT_NMI (_ADI_MSK(0x00010000,uint32_t)) /* NMI */
|
|
#define ENUM_SEC_CSTAT_NO_NMI (_ADI_MSK(0x00000000,uint32_t)) /* NMI: No NMI Occured */
|
|
#define ENUM_SEC_CSTAT_NMI (_ADI_MSK(0x00010000,uint32_t)) /* NMI: NMI Occurred */
|
|
|
|
#define BITM_SEC_CSTAT_WFI (_ADI_MSK(0x00001000,uint32_t)) /* Wait For Idle */
|
|
#define ENUM_SEC_CSTAT_NOT_WAITING (_ADI_MSK(0x00000000,uint32_t)) /* WFI: Not Waiting */
|
|
#define ENUM_SEC_CSTAT_WAITING (_ADI_MSK(0x00001000,uint32_t)) /* WFI: Waiting */
|
|
|
|
#define BITM_SEC_CSTAT_SIDV (_ADI_MSK(0x00000400,uint32_t)) /* SID Valid */
|
|
#define ENUM_SEC_CSTAT_INVALID_SID (_ADI_MSK(0x00000000,uint32_t)) /* SIDV: Invalid */
|
|
#define ENUM_SEC_CSTAT_VALID_SID (_ADI_MSK(0x00000400,uint32_t)) /* SIDV: Valid */
|
|
|
|
#define BITM_SEC_CSTAT_ACTV (_ADI_MSK(0x00000200,uint32_t)) /* ACT Valid */
|
|
#define ENUM_SEC_CSTAT_INVALID_ACT (_ADI_MSK(0x00000000,uint32_t)) /* ACTV: Invalid */
|
|
#define ENUM_SEC_CSTAT_VALID_ACT (_ADI_MSK(0x00000200,uint32_t)) /* ACTV: Valid */
|
|
|
|
#define BITM_SEC_CSTAT_PNDV (_ADI_MSK(0x00000100,uint32_t)) /* PND Valid */
|
|
#define ENUM_SEC_CSTAT_INVALID_PND (_ADI_MSK(0x00000000,uint32_t)) /* PNDV: Invalid */
|
|
#define ENUM_SEC_CSTAT_VALID_PND (_ADI_MSK(0x00000100,uint32_t)) /* PNDV: Valid */
|
|
|
|
#define BITM_SEC_CSTAT_ERRC (_ADI_MSK(0x00000030,uint32_t)) /* Error Cause */
|
|
#define ENUM_SEC_CSTAT_ACKERR (_ADI_MSK(0x00000010,uint32_t)) /* ERRC: Acknowledge Error */
|
|
|
|
#define BITM_SEC_CSTAT_ERR (_ADI_MSK(0x00000002,uint32_t)) /* Error */
|
|
#define ENUM_SEC_CSTAT_NO_ERR (_ADI_MSK(0x00000000,uint32_t)) /* ERR: No Error */
|
|
#define ENUM_SEC_CSTAT_ERR (_ADI_MSK(0x00000002,uint32_t)) /* ERR: Error Occurred */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SEC_CPND Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SEC_CPND_PRIO 8 /* Highest Pending IRQ Priority */
|
|
#define BITP_SEC_CPND_SID 0 /* Highest Pending IRQ Source ID */
|
|
#define BITM_SEC_CPND_PRIO (_ADI_MSK(0x0000FF00,uint32_t)) /* Highest Pending IRQ Priority */
|
|
#define BITM_SEC_CPND_SID (_ADI_MSK(0x000000FF,uint32_t)) /* Highest Pending IRQ Source ID */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SEC_CACT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SEC_CACT_PRIO 8 /* Highest Active IRQ Priority */
|
|
#define BITP_SEC_CACT_SID 0 /* Highest Active IRQ Source ID */
|
|
#define BITM_SEC_CACT_PRIO (_ADI_MSK(0x0000FF00,uint32_t)) /* Highest Active IRQ Priority */
|
|
#define BITM_SEC_CACT_SID (_ADI_MSK(0x000000FF,uint32_t)) /* Highest Active IRQ Source ID */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SEC_CPMSK Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SEC_CPMSK_LOCK 31 /* Lock */
|
|
#define BITP_SEC_CPMSK_PRIO 0 /* IRQ Priority Mask */
|
|
|
|
#define BITM_SEC_CPMSK_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
|
|
#define ENUM_SEC_CPMSK_UNLOCK (_ADI_MSK(0x00000000,uint32_t)) /* LOCK: Unlock */
|
|
#define ENUM_SEC_CPMSK_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* LOCK: Lock */
|
|
#define BITM_SEC_CPMSK_PRIO (_ADI_MSK(0x000000FF,uint32_t)) /* IRQ Priority Mask */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SEC_CGMSK Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SEC_CGMSK_LOCK 31 /* Lock */
|
|
#define BITP_SEC_CGMSK_UGRP 8 /* Ungrouped Mask */
|
|
#define BITP_SEC_CGMSK_GRP 0 /* Grouped Mask */
|
|
|
|
#define BITM_SEC_CGMSK_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
|
|
#define ENUM_SEC_CGMSK_UNLOCK (_ADI_MSK(0x00000000,uint32_t)) /* LOCK: Unlock */
|
|
#define ENUM_SEC_CGMSK_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* LOCK: Lock */
|
|
|
|
#define BITM_SEC_CGMSK_UGRP (_ADI_MSK(0x00000100,uint32_t)) /* Ungrouped Mask */
|
|
#define ENUM_SEC_CGMSK_UNMASK (_ADI_MSK(0x00000000,uint32_t)) /* UGRP: Unmask Ungrouped Sources */
|
|
#define ENUM_SEC_CGMSK_MASK (_ADI_MSK(0x00000100,uint32_t)) /* UGRP: Mask Ungrouped Sources */
|
|
#define BITM_SEC_CGMSK_GRP (_ADI_MSK(0x0000000F,uint32_t)) /* Grouped Mask */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SEC_CPLVL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SEC_CPLVL_LOCK 31 /* Lock */
|
|
#define BITP_SEC_CPLVL_PLVL 0 /* Priority Levels */
|
|
|
|
#define BITM_SEC_CPLVL_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
|
|
#define ENUM_SEC_CPLVL_UNLOCK (_ADI_MSK(0x00000000,uint32_t)) /* LOCK: Unlock */
|
|
#define ENUM_SEC_CPLVL_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* LOCK: Lock */
|
|
#define BITM_SEC_CPLVL_PLVL (_ADI_MSK(0x00000007,uint32_t)) /* Priority Levels */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SEC_CSID Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SEC_CSID_SID 0 /* Source ID */
|
|
#define BITM_SEC_CSID_SID (_ADI_MSK(0x000000FF,uint32_t)) /* Source ID */
|
|
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SEC_FCTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SEC_FCTL_LOCK 31 /* Lock */
|
|
#define BITP_SEC_FCTL_TES 13 /* Trigger Event Select */
|
|
#define BITP_SEC_FCTL_CMS 12 /* COP Mode Select */
|
|
#define BITP_SEC_FCTL_FIEN 7 /* Fault Input Enable */
|
|
#define BITP_SEC_FCTL_SREN 6 /* System Reset Enable */
|
|
#define BITP_SEC_FCTL_TOEN 5 /* Trigger Output Enable */
|
|
#define BITP_SEC_FCTL_FOEN 4 /* Fault Output Enable */
|
|
#define BITP_SEC_FCTL_RESET 1 /* Reset */
|
|
#define BITP_SEC_FCTL_EN 0 /* Enable */
|
|
|
|
#define BITM_SEC_FCTL_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
|
|
#define ENUM_SEC_FCTL_UNLOCK (_ADI_MSK(0x00000000,uint32_t)) /* LOCK: UnLock */
|
|
#define ENUM_SEC_FCTL_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* LOCK: Lock */
|
|
|
|
#define BITM_SEC_FCTL_TES (_ADI_MSK(0x00002000,uint32_t)) /* Trigger Event Select */
|
|
#define ENUM_SEC_FCTL_FLTACT_MODE (_ADI_MSK(0x00000000,uint32_t)) /* TES: Fault Active Mode */
|
|
#define ENUM_SEC_FCTL_FLTPND_MODE (_ADI_MSK(0x00002000,uint32_t)) /* TES: Fault Pending Mode */
|
|
|
|
#define BITM_SEC_FCTL_CMS (_ADI_MSK(0x00001000,uint32_t)) /* COP Mode Select */
|
|
#define ENUM_SEC_FCTL_FLT_MODE (_ADI_MSK(0x00000000,uint32_t)) /* CMS: Fault Mode */
|
|
#define ENUM_SEC_FCTL_COP_MODE (_ADI_MSK(0x00001000,uint32_t)) /* CMS: COP Mode */
|
|
|
|
#define BITM_SEC_FCTL_FIEN (_ADI_MSK(0x00000080,uint32_t)) /* Fault Input Enable */
|
|
#define ENUM_SEC_FCTL_FLTIN_DIS (_ADI_MSK(0x00000000,uint32_t)) /* FIEN: Disable */
|
|
#define ENUM_SEC_FCTL_FLTIN_EN (_ADI_MSK(0x00000080,uint32_t)) /* FIEN: Enable */
|
|
|
|
#define BITM_SEC_FCTL_SREN (_ADI_MSK(0x00000040,uint32_t)) /* System Reset Enable */
|
|
#define ENUM_SEC_FCTL_SYSRST_DIS (_ADI_MSK(0x00000000,uint32_t)) /* SREN: Disable */
|
|
#define ENUM_SEC_FCTL_SYSRST_EN (_ADI_MSK(0x00000040,uint32_t)) /* SREN: Enable */
|
|
|
|
#define BITM_SEC_FCTL_TOEN (_ADI_MSK(0x00000020,uint32_t)) /* Trigger Output Enable */
|
|
#define ENUM_SEC_FCTL_TRGOUT_DIS (_ADI_MSK(0x00000000,uint32_t)) /* TOEN: Disable */
|
|
#define ENUM_SEC_FCTL_TRGOUT_EN (_ADI_MSK(0x00000020,uint32_t)) /* TOEN: Enable */
|
|
|
|
#define BITM_SEC_FCTL_FOEN (_ADI_MSK(0x00000010,uint32_t)) /* Fault Output Enable */
|
|
#define ENUM_SEC_FCTL_FLTOUT_DIS (_ADI_MSK(0x00000000,uint32_t)) /* FOEN: Disable */
|
|
#define ENUM_SEC_FCTL_FLTOUT_EN (_ADI_MSK(0x00000010,uint32_t)) /* FOEN: Enable */
|
|
|
|
#define BITM_SEC_FCTL_RESET (_ADI_MSK(0x00000002,uint32_t)) /* Reset */
|
|
#define ENUM_SEC_FCTL_NO_RESET (_ADI_MSK(0x00000000,uint32_t)) /* RESET: No Action */
|
|
#define ENUM_SEC_FCTL_RESET (_ADI_MSK(0x00000002,uint32_t)) /* RESET: Reset */
|
|
|
|
#define BITM_SEC_FCTL_EN (_ADI_MSK(0x00000001,uint32_t)) /* Enable */
|
|
#define ENUM_SEC_FCTL_DIS (_ADI_MSK(0x00000000,uint32_t)) /* EN: Disable */
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|
#define ENUM_SEC_FCTL_EN (_ADI_MSK(0x00000001,uint32_t)) /* EN: Enable */
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|
|
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
SEC_FSTAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SEC_FSTAT_NPND 10 /* Next Pending Fault */
|
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#define BITP_SEC_FSTAT_ACT 9 /* Fault Active */
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#define BITP_SEC_FSTAT_PND 8 /* Pending Fault */
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#define BITP_SEC_FSTAT_ERRC 4 /* Error Cause */
|
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#define BITP_SEC_FSTAT_ERR 1 /* Error */
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|
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#define BITM_SEC_FSTAT_NPND (_ADI_MSK(0x00000400,uint32_t)) /* Next Pending Fault */
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|
#define ENUM_SEC_FSTAT_NO_NXTFLT (_ADI_MSK(0x00000000,uint32_t)) /* NPND: Not Pending */
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|
#define ENUM_SEC_FSTAT_NXTFLT (_ADI_MSK(0x00000400,uint32_t)) /* NPND: Pending */
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|
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#define BITM_SEC_FSTAT_ACT (_ADI_MSK(0x00000200,uint32_t)) /* Fault Active */
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|
#define ENUM_SEC_FSTAT_NO_FLTACT (_ADI_MSK(0x00000000,uint32_t)) /* ACT: No Fault */
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|
#define ENUM_SEC_FSTAT_FLTACT (_ADI_MSK(0x00000200,uint32_t)) /* ACT: Active Fault */
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|
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#define BITM_SEC_FSTAT_PND (_ADI_MSK(0x00000100,uint32_t)) /* Pending Fault */
|
|
#define ENUM_SEC_FSTAT_NO_FLTPND (_ADI_MSK(0x00000000,uint32_t)) /* PND: Not Pending */
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|
#define ENUM_SEC_FSTAT_FLTPND (_ADI_MSK(0x00000100,uint32_t)) /* PND: Pending */
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|
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#define BITM_SEC_FSTAT_ERRC (_ADI_MSK(0x00000030,uint32_t)) /* Error Cause */
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|
#define ENUM_SEC_FSTAT_ENDERR (_ADI_MSK(0x00000020,uint32_t)) /* ERRC: End Error */
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|
|
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#define BITM_SEC_FSTAT_ERR (_ADI_MSK(0x00000002,uint32_t)) /* Error */
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|
#define ENUM_SEC_FSTAT_NO_ERR (_ADI_MSK(0x00000000,uint32_t)) /* ERR: No Error */
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|
#define ENUM_SEC_FSTAT_ERR (_ADI_MSK(0x00000002,uint32_t)) /* ERR: Error Occurred */
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|
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
SEC_FSID Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SEC_FSID_FEXT 16 /* Fault External */
|
|
#define BITP_SEC_FSID_SID 0 /* Source ID */
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|
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#define BITM_SEC_FSID_FEXT (_ADI_MSK(0x00010000,uint32_t)) /* Fault External */
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#define ENUM_SEC_FSID_SRC_INTFLT (_ADI_MSK(0x00000000,uint32_t)) /* FEXT: Fault Internal */
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|
#define ENUM_SEC_FSID_SRC_EXTFLT (_ADI_MSK(0x00010000,uint32_t)) /* FEXT: Fault External */
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|
#define BITM_SEC_FSID_SID (_ADI_MSK(0x000000FF,uint32_t)) /* Source ID */
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|
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
SEC_FEND Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SEC_FEND_FEXT 16 /* Fault External */
|
|
#define BITP_SEC_FEND_SID 0 /* Source ID */
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|
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#define BITM_SEC_FEND_FEXT (_ADI_MSK(0x00010000,uint32_t)) /* Fault External */
|
|
#define ENUM_SEC_FEND_END_INTFLT (_ADI_MSK(0x00000000,uint32_t)) /* FEXT: Fault Internal */
|
|
#define ENUM_SEC_FEND_END_EXTFLT (_ADI_MSK(0x00010000,uint32_t)) /* FEXT: Fault External */
|
|
#define BITM_SEC_FEND_SID (_ADI_MSK(0x000000FF,uint32_t)) /* Source ID */
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|
|
|
|
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
SEC_GCTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SEC_GCTL_LOCK 31 /* Lock */
|
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#define BITP_SEC_GCTL_RESET 1 /* Reset */
|
|
#define BITP_SEC_GCTL_EN 0 /* Enable */
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|
|
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#define BITM_SEC_GCTL_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
|
|
#define ENUM_SEC_GCTL_UNLOCK (_ADI_MSK(0x00000000,uint32_t)) /* LOCK: Unlock */
|
|
#define ENUM_SEC_GCTL_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* LOCK: Lock */
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|
|
|
#define BITM_SEC_GCTL_RESET (_ADI_MSK(0x00000002,uint32_t)) /* Reset */
|
|
#define ENUM_SEC_GCTL_NO_RESET (_ADI_MSK(0x00000000,uint32_t)) /* RESET: No Action */
|
|
#define ENUM_SEC_GCTL_RESET (_ADI_MSK(0x00000002,uint32_t)) /* RESET: Reset */
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|
|
|
#define BITM_SEC_GCTL_EN (_ADI_MSK(0x00000001,uint32_t)) /* Enable */
|
|
#define ENUM_SEC_GCTL_DIS (_ADI_MSK(0x00000000,uint32_t)) /* EN: Disable */
|
|
#define ENUM_SEC_GCTL_EN (_ADI_MSK(0x00000001,uint32_t)) /* EN: Enable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SEC_GSTAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SEC_GSTAT_LWERR 31 /* Lock Write Error */
|
|
#define BITP_SEC_GSTAT_ADRERR 30 /* Address Error */
|
|
#define BITP_SEC_GSTAT_SID 16 /* Source ID for SSI Error */
|
|
#define BITP_SEC_GSTAT_SCI 8 /* SCI ID for SCI Error */
|
|
#define BITP_SEC_GSTAT_ERRC 4 /* Error Cause */
|
|
#define BITP_SEC_GSTAT_ERR 1 /* Error */
|
|
|
|
#define BITM_SEC_GSTAT_LWERR (_ADI_MSK(0x80000000,uint32_t)) /* Lock Write Error */
|
|
#define ENUM_SEC_GSTAT_NO_LWERR (_ADI_MSK(0x00000000,uint32_t)) /* LWERR: No Error */
|
|
#define ENUM_SEC_GSTAT_LWERR (_ADI_MSK(0x80000000,uint32_t)) /* LWERR: Error Occurred */
|
|
|
|
#define BITM_SEC_GSTAT_ADRERR (_ADI_MSK(0x40000000,uint32_t)) /* Address Error */
|
|
#define ENUM_SEC_GSTAT_NO_ADRERR (_ADI_MSK(0x00000000,uint32_t)) /* ADRERR: No Error */
|
|
#define ENUM_SEC_GSTAT_ADRERR (_ADI_MSK(0x40000000,uint32_t)) /* ADRERR: Error Occurred */
|
|
#define BITM_SEC_GSTAT_SID (_ADI_MSK(0x00FF0000,uint32_t)) /* Source ID for SSI Error */
|
|
#define BITM_SEC_GSTAT_SCI (_ADI_MSK(0x00000F00,uint32_t)) /* SCI ID for SCI Error */
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|
|
|
#define BITM_SEC_GSTAT_ERRC (_ADI_MSK(0x00000030,uint32_t)) /* Error Cause */
|
|
#define ENUM_SEC_GSTAT_SFIERR (_ADI_MSK(0x00000000,uint32_t)) /* ERRC: SFI Error */
|
|
#define ENUM_SEC_GSTAT_SCIERR (_ADI_MSK(0x00000010,uint32_t)) /* ERRC: SCI Error */
|
|
#define ENUM_SEC_GSTAT_SSIERR (_ADI_MSK(0x00000020,uint32_t)) /* ERRC: SSI Error */
|
|
|
|
#define BITM_SEC_GSTAT_ERR (_ADI_MSK(0x00000002,uint32_t)) /* Error */
|
|
#define ENUM_SEC_GSTAT_NO_ERR (_ADI_MSK(0x00000000,uint32_t)) /* ERR: No Error */
|
|
#define ENUM_SEC_GSTAT_ERR (_ADI_MSK(0x00000002,uint32_t)) /* ERR: Error Occurred */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SEC_RAISE Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SEC_RAISE_SID 0 /* Source ID IRQ Set to Pending */
|
|
#define BITM_SEC_RAISE_SID (_ADI_MSK(0x000000FF,uint32_t)) /* Source ID IRQ Set to Pending */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SEC_END Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SEC_END_SID 0 /* Source ID IRQ to End */
|
|
#define BITM_SEC_END_SID (_ADI_MSK(0x000000FF,uint32_t)) /* Source ID IRQ to End */
|
|
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SEC_SCTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SEC_SCTL_LOCK 31 /* Lock */
|
|
#define BITP_SEC_SCTL_CTG 24 /* Core Target Select */
|
|
#define BITP_SEC_SCTL_GRP 16 /* Group Select */
|
|
#define BITP_SEC_SCTL_PRIO 8 /* Priority Level Select */
|
|
#define BITP_SEC_SCTL_ERREN 4 /* Error Enable */
|
|
#define BITP_SEC_SCTL_ES 3 /* Edge Select */
|
|
#define BITP_SEC_SCTL_SEN 2 /* Source (signal) Enable */
|
|
#define BITP_SEC_SCTL_FEN 1 /* Fault Enable */
|
|
#define BITP_SEC_SCTL_IEN 0 /* Interrupt Enable */
|
|
|
|
#define BITM_SEC_SCTL_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
|
|
#define ENUM_SEC_SCTL_UNLOCK (_ADI_MSK(0x00000000,uint32_t)) /* LOCK: Unlock */
|
|
#define ENUM_SEC_SCTL_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* LOCK: Lock */
|
|
#define BITM_SEC_SCTL_CTG (_ADI_MSK(0x0F000000,uint32_t)) /* Core Target Select */
|
|
#define BITM_SEC_SCTL_GRP (_ADI_MSK(0x000F0000,uint32_t)) /* Group Select */
|
|
#define BITM_SEC_SCTL_PRIO (_ADI_MSK(0x0000FF00,uint32_t)) /* Priority Level Select */
|
|
|
|
#define BITM_SEC_SCTL_ERREN (_ADI_MSK(0x00000010,uint32_t)) /* Error Enable */
|
|
#define ENUM_SEC_SCTL_ERR_DIS (_ADI_MSK(0x00000000,uint32_t)) /* ERREN: Disable */
|
|
#define ENUM_SEC_SCTL_ERR_EN (_ADI_MSK(0x00000010,uint32_t)) /* ERREN: Enable */
|
|
|
|
#define BITM_SEC_SCTL_ES (_ADI_MSK(0x00000008,uint32_t)) /* Edge Select */
|
|
#define ENUM_SEC_SCTL_LEVEL (_ADI_MSK(0x00000000,uint32_t)) /* ES: Level Sensitive */
|
|
#define ENUM_SEC_SCTL_EDGE (_ADI_MSK(0x00000008,uint32_t)) /* ES: Edge Sensitive */
|
|
|
|
#define BITM_SEC_SCTL_SEN (_ADI_MSK(0x00000004,uint32_t)) /* Source (signal) Enable */
|
|
#define ENUM_SEC_SCTL_SRC_DIS (_ADI_MSK(0x00000000,uint32_t)) /* SEN: Disable */
|
|
#define ENUM_SEC_SCTL_SRC_EN (_ADI_MSK(0x00000004,uint32_t)) /* SEN: Enable */
|
|
|
|
#define BITM_SEC_SCTL_FEN (_ADI_MSK(0x00000002,uint32_t)) /* Fault Enable */
|
|
#define ENUM_SEC_SCTL_FAULT_DIS (_ADI_MSK(0x00000000,uint32_t)) /* FEN: Disable */
|
|
#define ENUM_SEC_SCTL_FAULT_EN (_ADI_MSK(0x00000002,uint32_t)) /* FEN: Enable */
|
|
|
|
#define BITM_SEC_SCTL_IEN (_ADI_MSK(0x00000001,uint32_t)) /* Interrupt Enable */
|
|
#define ENUM_SEC_SCTL_INT_DIS (_ADI_MSK(0x00000000,uint32_t)) /* IEN: Disable */
|
|
#define ENUM_SEC_SCTL_INT_EN (_ADI_MSK(0x00000001,uint32_t)) /* IEN: Enable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SEC_SSTAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SEC_SSTAT_CHID 16 /* Channel ID */
|
|
#define BITP_SEC_SSTAT_ACT 9 /* Active Source */
|
|
#define BITP_SEC_SSTAT_PND 8 /* Pending Source */
|
|
#define BITP_SEC_SSTAT_ERRC 4 /* Error Cause */
|
|
#define BITP_SEC_SSTAT_ERR 1 /* Error */
|
|
#define BITM_SEC_SSTAT_CHID (_ADI_MSK(0x00FF0000,uint32_t)) /* Channel ID */
|
|
|
|
#define BITM_SEC_SSTAT_ACT (_ADI_MSK(0x00000200,uint32_t)) /* Active Source */
|
|
#define ENUM_SEC_SSTAT_NO_SRC (_ADI_MSK(0x00000000,uint32_t)) /* ACT: No Source */
|
|
#define ENUM_SEC_SSTAT_ACTIVE_SRC (_ADI_MSK(0x00000200,uint32_t)) /* ACT: Active Source */
|
|
|
|
#define BITM_SEC_SSTAT_PND (_ADI_MSK(0x00000100,uint32_t)) /* Pending Source */
|
|
#define ENUM_SEC_SSTAT_NOTPENDING (_ADI_MSK(0x00000000,uint32_t)) /* PND: Not Pending */
|
|
#define ENUM_SEC_SSTAT_PENDING (_ADI_MSK(0x00000100,uint32_t)) /* PND: Pending */
|
|
|
|
#define BITM_SEC_SSTAT_ERRC (_ADI_MSK(0x00000030,uint32_t)) /* Error Cause */
|
|
#define ENUM_SEC_SSTAT_SOVFERR (_ADI_MSK(0x00000000,uint32_t)) /* ERRC: Source Overflow Error */
|
|
#define ENUM_SEC_SSTAT_ENDERR (_ADI_MSK(0x00000020,uint32_t)) /* ERRC: End Error */
|
|
|
|
#define BITM_SEC_SSTAT_ERR (_ADI_MSK(0x00000002,uint32_t)) /* Error */
|
|
#define ENUM_SEC_SSTAT_NO_ERR (_ADI_MSK(0x00000000,uint32_t)) /* ERR: No Error */
|
|
#define ENUM_SEC_SSTAT_ERR (_ADI_MSK(0x00000002,uint32_t)) /* ERR: Error Occurred */
|
|
|
|
/* ==================================================
|
|
Trigger Routing Unit Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
TRU0
|
|
========================= */
|
|
#define REG_TRU0_SSR0 0xFFCA5000 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR1 0xFFCA5004 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR2 0xFFCA5008 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR3 0xFFCA500C /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR4 0xFFCA5010 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR5 0xFFCA5014 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR6 0xFFCA5018 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR7 0xFFCA501C /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR8 0xFFCA5020 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR9 0xFFCA5024 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR10 0xFFCA5028 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR11 0xFFCA502C /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR12 0xFFCA5030 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR13 0xFFCA5034 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR14 0xFFCA5038 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR15 0xFFCA503C /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR16 0xFFCA5040 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR17 0xFFCA5044 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR18 0xFFCA5048 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR19 0xFFCA504C /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR20 0xFFCA5050 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR21 0xFFCA5054 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR22 0xFFCA5058 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR23 0xFFCA505C /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR24 0xFFCA5060 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR25 0xFFCA5064 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR26 0xFFCA5068 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR27 0xFFCA506C /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR28 0xFFCA5070 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR29 0xFFCA5074 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR30 0xFFCA5078 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR31 0xFFCA507C /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR32 0xFFCA5080 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR33 0xFFCA5084 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR34 0xFFCA5088 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR35 0xFFCA508C /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR36 0xFFCA5090 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR37 0xFFCA5094 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR38 0xFFCA5098 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR39 0xFFCA509C /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR40 0xFFCA50A0 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR41 0xFFCA50A4 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR42 0xFFCA50A8 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR43 0xFFCA50AC /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR44 0xFFCA50B0 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR45 0xFFCA50B4 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR46 0xFFCA50B8 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR47 0xFFCA50BC /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR48 0xFFCA50C0 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR49 0xFFCA50C4 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR50 0xFFCA50C8 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR51 0xFFCA50CC /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR52 0xFFCA50D0 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR53 0xFFCA50D4 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR54 0xFFCA50D8 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR55 0xFFCA50DC /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR56 0xFFCA50E0 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR57 0xFFCA50E4 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR58 0xFFCA50E8 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR59 0xFFCA50EC /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR60 0xFFCA50F0 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR61 0xFFCA50F4 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR62 0xFFCA50F8 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR63 0xFFCA50FC /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR64 0xFFCA5100 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR65 0xFFCA5104 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR66 0xFFCA5108 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR67 0xFFCA510C /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR68 0xFFCA5110 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR69 0xFFCA5114 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR70 0xFFCA5118 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR71 0xFFCA511C /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR72 0xFFCA5120 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR73 0xFFCA5124 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR74 0xFFCA5128 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR75 0xFFCA512C /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR76 0xFFCA5130 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR77 0xFFCA5134 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR78 0xFFCA5138 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR79 0xFFCA513C /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR80 0xFFCA5140 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR81 0xFFCA5144 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR82 0xFFCA5148 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR83 0xFFCA514C /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR84 0xFFCA5150 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR85 0xFFCA5154 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_SSR86 0xFFCA5158 /* TRU0 Slave Select Register */
|
|
#define REG_TRU0_MTR 0xFFCA57E0 /* TRU0 Master Trigger Register */
|
|
#define REG_TRU0_ERRADDR 0xFFCA57E8 /* TRU0 Error Address Register */
|
|
#define REG_TRU0_STAT 0xFFCA57EC /* TRU0 Status Information Register */
|
|
#define REG_TRU0_REVID 0xFFCA57F0 /* TRU0 Revision ID Register */
|
|
#define REG_TRU0_GCTL 0xFFCA57F4 /* TRU0 Global Control Register */
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|
|
|
/* =========================
|
|
TRU
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TRU_SSR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TRU_SSR_LOCK 31 /* SSRn Lock */
|
|
#define BITP_TRU_SSR_SSR 0 /* SSRn Slave Select */
|
|
#define BITM_TRU_SSR_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* SSRn Lock */
|
|
#define BITM_TRU_SSR_SSR (_ADI_MSK(0x000000FF,uint32_t)) /* SSRn Slave Select */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TRU_MTR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TRU_MTR_MTR3 24 /* Master Trigger Register 3 */
|
|
#define BITP_TRU_MTR_MTR2 16 /* Master Trigger Register 2 */
|
|
#define BITP_TRU_MTR_MTR1 8 /* Master Trigger Register 1 */
|
|
#define BITP_TRU_MTR_MTR0 0 /* Master Trigger Register 0 */
|
|
#define BITM_TRU_MTR_MTR3 (_ADI_MSK(0xFF000000,uint32_t)) /* Master Trigger Register 3 */
|
|
#define BITM_TRU_MTR_MTR2 (_ADI_MSK(0x00FF0000,uint32_t)) /* Master Trigger Register 2 */
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|
#define BITM_TRU_MTR_MTR1 (_ADI_MSK(0x0000FF00,uint32_t)) /* Master Trigger Register 1 */
|
|
#define BITM_TRU_MTR_MTR0 (_ADI_MSK(0x000000FF,uint32_t)) /* Master Trigger Register 0 */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TRU_ERRADDR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TRU_ERRADDR_ADDR 0 /* Error Address */
|
|
#define BITM_TRU_ERRADDR_ADDR (_ADI_MSK(0x00000FFF,uint32_t)) /* Error Address */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TRU_STAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TRU_STAT_ADDRERR 1 /* Address Error Status */
|
|
#define BITP_TRU_STAT_LWERR 0 /* Lock Write Error Status */
|
|
#define BITM_TRU_STAT_ADDRERR (_ADI_MSK(0x00000002,uint32_t)) /* Address Error Status */
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|
#define BITM_TRU_STAT_LWERR (_ADI_MSK(0x00000001,uint32_t)) /* Lock Write Error Status */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TRU_REVID Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TRU_REVID_MAJOR 4 /* Major Version ID */
|
|
#define BITP_TRU_REVID_REV 0 /* Incremental Version ID */
|
|
#define BITM_TRU_REVID_MAJOR (_ADI_MSK(0x000000F0,uint32_t)) /* Major Version ID */
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|
#define BITM_TRU_REVID_REV (_ADI_MSK(0x0000000F,uint32_t)) /* Incremental Version ID */
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|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TRU_GCTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TRU_GCTL_LOCK 31 /* GCTL Lock Bit */
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|
#define BITP_TRU_GCTL_MTRL 2 /* MTR Lock Bit */
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|
#define BITP_TRU_GCTL_RESET 1 /* Soft Reset */
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|
#define BITP_TRU_GCTL_EN 0 /* Non-MMR Enable */
|
|
#define BITM_TRU_GCTL_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* GCTL Lock Bit */
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|
#define BITM_TRU_GCTL_MTRL (_ADI_MSK(0x00000004,uint32_t)) /* MTR Lock Bit */
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#define BITM_TRU_GCTL_RESET (_ADI_MSK(0x00000002,uint32_t)) /* Soft Reset */
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|
#define BITM_TRU_GCTL_EN (_ADI_MSK(0x00000001,uint32_t)) /* Non-MMR Enable */
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|
|
|
/* ==================================================
|
|
Reset Control Unit Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
RCU0
|
|
========================= */
|
|
#define REG_RCU0_CTL 0xFFCA6000 /* RCU0 Control Register */
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|
#define REG_RCU0_STAT 0xFFCA6004 /* RCU0 Status Register */
|
|
#define REG_RCU0_CRCTL 0xFFCA6008 /* RCU0 Core Reset Control Register */
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|
#define REG_RCU0_CRSTAT 0xFFCA600C /* RCU0 Core Reset Status Register */
|
|
#define REG_RCU0_SIDIS 0xFFCA6010 /* RCU0 System Interface Disable Register */
|
|
#define REG_RCU0_SISTAT 0xFFCA6014 /* RCU0 System Interface Status Register */
|
|
#define REG_RCU0_SVECT_LCK 0xFFCA6018 /* RCU0 SVECT Lock Register */
|
|
#define REG_RCU0_BCODE 0xFFCA601C /* RCU0 Boot Code Register */
|
|
#define REG_RCU0_SVECT0 0xFFCA6020 /* RCU0 Software Vector Register n */
|
|
#define REG_RCU0_SVECT1 0xFFCA6024 /* RCU0 Software Vector Register n */
|
|
|
|
/* =========================
|
|
RCU
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
RCU_CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RCU_CTL_LOCK 31 /* Lock */
|
|
#define BITP_RCU_CTL_RSTOUTDSRT 2 /* Reset Out Deassert */
|
|
#define BITP_RCU_CTL_RSTOUTASRT 1 /* Reset Out Assert */
|
|
#define BITP_RCU_CTL_SYSRST 0 /* System Reset */
|
|
#define BITM_RCU_CTL_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
|
|
#define BITM_RCU_CTL_RSTOUTDSRT (_ADI_MSK(0x00000004,uint32_t)) /* Reset Out Deassert */
|
|
#define BITM_RCU_CTL_RSTOUTASRT (_ADI_MSK(0x00000002,uint32_t)) /* Reset Out Assert */
|
|
#define BITM_RCU_CTL_SYSRST (_ADI_MSK(0x00000001,uint32_t)) /* System Reset */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
RCU_STAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RCU_STAT_RSTOUTERR 18 /* Reset Out Error */
|
|
#define BITP_RCU_STAT_LWERR 17 /* Lock Write Error */
|
|
#define BITP_RCU_STAT_ADDRERR 16 /* Address Error */
|
|
#define BITP_RCU_STAT_BMODE 8 /* Boot Mode */
|
|
#define BITP_RCU_STAT_RSTOUT 5 /* Reset Out Status */
|
|
#define BITP_RCU_STAT_SWRST 3 /* Software Reset */
|
|
#define BITP_RCU_STAT_SSRST 2 /* System Source Reset */
|
|
#define BITP_RCU_STAT_HBRST 1 /* Hibernate Reset */
|
|
#define BITP_RCU_STAT_HWRST 0 /* Hardware Reset */
|
|
#define BITM_RCU_STAT_RSTOUTERR (_ADI_MSK(0x00040000,uint32_t)) /* Reset Out Error */
|
|
#define BITM_RCU_STAT_LWERR (_ADI_MSK(0x00020000,uint32_t)) /* Lock Write Error */
|
|
#define BITM_RCU_STAT_ADDRERR (_ADI_MSK(0x00010000,uint32_t)) /* Address Error */
|
|
#define BITM_RCU_STAT_BMODE (_ADI_MSK(0x00000F00,uint32_t)) /* Boot Mode */
|
|
#define BITM_RCU_STAT_RSTOUT (_ADI_MSK(0x00000020,uint32_t)) /* Reset Out Status */
|
|
#define BITM_RCU_STAT_SWRST (_ADI_MSK(0x00000008,uint32_t)) /* Software Reset */
|
|
#define BITM_RCU_STAT_SSRST (_ADI_MSK(0x00000004,uint32_t)) /* System Source Reset */
|
|
#define BITM_RCU_STAT_HBRST (_ADI_MSK(0x00000002,uint32_t)) /* Hibernate Reset */
|
|
#define BITM_RCU_STAT_HWRST (_ADI_MSK(0x00000001,uint32_t)) /* Hardware Reset */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
RCU_CRCTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RCU_CRCTL_LOCK 31 /* Lock */
|
|
#define BITP_RCU_CRCTL_CR0 0 /* Core Reset n */
|
|
#define BITP_RCU_CRCTL_CR1 1 /* Core Reset n */
|
|
#define BITM_RCU_CRCTL_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
|
|
#define BITM_RCU_CRCTL_CR0 (_ADI_MSK(0x00000001,uint32_t)) /* Core Reset n */
|
|
#define BITM_RCU_CRCTL_CR1 (_ADI_MSK(0x00000002,uint32_t)) /* Core Reset n */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
RCU_CRSTAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RCU_CRSTAT_CR0 0 /* Core Reset n */
|
|
#define BITP_RCU_CRSTAT_CR1 1 /* Core Reset n */
|
|
#define BITM_RCU_CRSTAT_CR0 (_ADI_MSK(0x00000001,uint32_t)) /* Core Reset n */
|
|
#define BITM_RCU_CRSTAT_CR1 (_ADI_MSK(0x00000002,uint32_t)) /* Core Reset n */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
RCU_SIDIS Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RCU_SIDIS_LOCK 31 /* Lock */
|
|
#define BITP_RCU_SIDIS_SI0 0 /* System Interface n */
|
|
#define BITP_RCU_SIDIS_SI1 1 /* System Interface n */
|
|
#define BITM_RCU_SIDIS_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
|
|
#define BITM_RCU_SIDIS_SI0 (_ADI_MSK(0x00000001,uint32_t)) /* System Interface n */
|
|
#define BITM_RCU_SIDIS_SI1 (_ADI_MSK(0x00000002,uint32_t)) /* System Interface n */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
RCU_SISTAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RCU_SISTAT_SI0 0 /* System Interface n */
|
|
#define BITP_RCU_SISTAT_SI1 1 /* System Interface n */
|
|
#define BITM_RCU_SISTAT_SI0 (_ADI_MSK(0x00000001,uint32_t)) /* System Interface n */
|
|
#define BITM_RCU_SISTAT_SI1 (_ADI_MSK(0x00000002,uint32_t)) /* System Interface n */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
RCU_SVECT_LCK Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RCU_SVECT_LCK_LOCK 31 /* Lock */
|
|
#define BITP_RCU_SVECT_LCK_SVECT0 0 /* Software Vector Register n */
|
|
#define BITP_RCU_SVECT_LCK_SVECT1 1 /* Software Vector Register n */
|
|
#define BITM_RCU_SVECT_LCK_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
|
|
#define BITM_RCU_SVECT_LCK_SVECT0 (_ADI_MSK(0x00000001,uint32_t)) /* Software Vector Register n */
|
|
#define BITM_RCU_SVECT_LCK_SVECT1 (_ADI_MSK(0x00000002,uint32_t)) /* Software Vector Register n */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
RCU_BCODE Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_RCU_BCODE_LOCK 31 /* Lock */
|
|
#define BITP_RCU_BCODE_BCODE 0 /* Boot Code */
|
|
#define BITM_RCU_BCODE_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
|
|
#define BITM_RCU_BCODE_BCODE (_ADI_MSK(0x7FFFFFFF,uint32_t)) /* Boot Code */
|
|
|
|
/* ==================================================
|
|
System Protection Unit Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
SPU0
|
|
========================= */
|
|
#define REG_SPU0_CTL 0xFFCA7000 /* SPU0 Control Register */
|
|
#define REG_SPU0_STAT 0xFFCA7004 /* SPU0 Status Register */
|
|
#define REG_SPU0_WP0 0xFFCA7400 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP1 0xFFCA7404 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP2 0xFFCA7408 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP3 0xFFCA740C /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP4 0xFFCA7410 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP5 0xFFCA7414 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP6 0xFFCA7418 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP7 0xFFCA741C /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP8 0xFFCA7420 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP9 0xFFCA7424 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP10 0xFFCA7428 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP11 0xFFCA742C /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP12 0xFFCA7430 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP13 0xFFCA7434 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP14 0xFFCA7438 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP15 0xFFCA743C /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP16 0xFFCA7440 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP17 0xFFCA7444 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP18 0xFFCA7448 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP19 0xFFCA744C /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP20 0xFFCA7450 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP21 0xFFCA7454 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP22 0xFFCA7458 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP23 0xFFCA745C /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP24 0xFFCA7460 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP25 0xFFCA7464 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP26 0xFFCA7468 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP27 0xFFCA746C /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP28 0xFFCA7470 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP29 0xFFCA7474 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP30 0xFFCA7478 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP31 0xFFCA747C /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP32 0xFFCA7480 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP33 0xFFCA7484 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP34 0xFFCA7488 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP35 0xFFCA748C /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP36 0xFFCA7490 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP37 0xFFCA7494 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP38 0xFFCA7498 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP39 0xFFCA749C /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP40 0xFFCA74A0 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP41 0xFFCA74A4 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP42 0xFFCA74A8 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP43 0xFFCA74AC /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP44 0xFFCA74B0 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP45 0xFFCA74B4 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP46 0xFFCA74B8 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP47 0xFFCA74BC /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP48 0xFFCA74C0 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP49 0xFFCA74C4 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP50 0xFFCA74C8 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP51 0xFFCA74CC /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP52 0xFFCA74D0 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP53 0xFFCA74D4 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP54 0xFFCA74D8 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP55 0xFFCA74DC /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP56 0xFFCA74E0 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP57 0xFFCA74E4 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP58 0xFFCA74E8 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP59 0xFFCA74EC /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP60 0xFFCA74F0 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP61 0xFFCA74F4 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP62 0xFFCA74F8 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP63 0xFFCA74FC /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP64 0xFFCA7500 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP65 0xFFCA7504 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP66 0xFFCA7508 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP67 0xFFCA750C /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP68 0xFFCA7510 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP69 0xFFCA7514 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP70 0xFFCA7518 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP71 0xFFCA751C /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP72 0xFFCA7520 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP73 0xFFCA7524 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP74 0xFFCA7528 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP75 0xFFCA752C /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP76 0xFFCA7530 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP77 0xFFCA7534 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP78 0xFFCA7538 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP79 0xFFCA753C /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP80 0xFFCA7540 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP81 0xFFCA7544 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP82 0xFFCA7548 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP83 0xFFCA754C /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP84 0xFFCA7550 /* SPU0 Write Protect Register n */
|
|
#define REG_SPU0_WP85 0xFFCA7554 /* SPU0 Write Protect Register n */
|
|
|
|
/* =========================
|
|
SPU
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SPU_CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SPU_CTL_WPLCK 16 /* Write Protect Register Lock */
|
|
#define BITP_SPU_CTL_GLCK 0 /* Global Lock Disable */
|
|
#define BITM_SPU_CTL_WPLCK (_ADI_MSK(0x00010000,uint32_t)) /* Write Protect Register Lock */
|
|
#define BITM_SPU_CTL_GLCK (_ADI_MSK(0x000000FF,uint32_t)) /* Global Lock Disable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SPU_STAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SPU_STAT_LWERR 31 /* Lock Write Error */
|
|
#define BITP_SPU_STAT_ADDRERR 30 /* Address Error */
|
|
#define BITP_SPU_STAT_GLCK 0 /* Global Lock Status */
|
|
#define BITM_SPU_STAT_LWERR (_ADI_MSK(0x80000000,uint32_t)) /* Lock Write Error */
|
|
#define BITM_SPU_STAT_ADDRERR (_ADI_MSK(0x40000000,uint32_t)) /* Address Error */
|
|
#define BITM_SPU_STAT_GLCK (_ADI_MSK(0x00000001,uint32_t)) /* Global Lock Status */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SPU_WP Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SPU_WP_SM0 16 /* System Master x Write Protect Enable */
|
|
#define BITP_SPU_WP_SM1 17 /* System Master x Write Protect Enable */
|
|
#define BITP_SPU_WP_CM0 0 /* Core Master x Write Protect Enable */
|
|
#define BITP_SPU_WP_CM1 1 /* Core Master x Write Protect Enable */
|
|
#define BITM_SPU_WP_SM0 (_ADI_MSK(0x00010000,uint32_t)) /* System Master x Write Protect Enable */
|
|
#define BITM_SPU_WP_SM1 (_ADI_MSK(0x00020000,uint32_t)) /* System Master x Write Protect Enable */
|
|
#define BITM_SPU_WP_CM0 (_ADI_MSK(0x00000001,uint32_t)) /* Core Master x Write Protect Enable */
|
|
#define BITM_SPU_WP_CM1 (_ADI_MSK(0x00000002,uint32_t)) /* Core Master x Write Protect Enable */
|
|
|
|
/* ==================================================
|
|
Clock Generation Unit Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
CGU0
|
|
========================= */
|
|
#define REG_CGU0_CTL 0xFFCA8000 /* CGU0 Control Register */
|
|
#define REG_CGU0_STAT 0xFFCA8004 /* CGU0 Status Register */
|
|
#define REG_CGU0_DIV 0xFFCA8008 /* CGU0 Divisor Register */
|
|
#define REG_CGU0_CLKOUTSEL 0xFFCA800C /* CGU0 CLKOUT Select Register */
|
|
|
|
/* =========================
|
|
CGU
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
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CGU_CTL Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_CGU_CTL_LOCK 31 /* Lock */
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#define BITP_CGU_CTL_WFI 30 /* Wait For Idle */
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#define BITP_CGU_CTL_MSEL 8 /* Multiplier Select */
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#define BITP_CGU_CTL_DF 0 /* Divide Frequency */
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#define BITM_CGU_CTL_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
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#define BITM_CGU_CTL_WFI (_ADI_MSK(0x40000000,uint32_t)) /* Wait For Idle */
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#define BITM_CGU_CTL_MSEL (_ADI_MSK(0x00007F00,uint32_t)) /* Multiplier Select */
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#define ENUM_CGU_CTL_MSEL1TO127 (_ADI_MSK(0x00000000,uint32_t)) /* MSEL: MSEL = 1 to 127 */
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#define BITM_CGU_CTL_DF (_ADI_MSK(0x00000001,uint32_t)) /* Divide Frequency */
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/* ------------------------------------------------------------------------------------------------------------------------
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CGU_STAT Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_CGU_STAT_PLOCKERR 21 /* PLL Lock Error */
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#define BITP_CGU_STAT_WDIVERR 20 /* Write to DIV Error */
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#define BITP_CGU_STAT_WDFMSERR 19 /* Write to DF or MSEL Error */
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#define BITP_CGU_STAT_DIVERR 18 /* DIV Error */
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#define BITP_CGU_STAT_LWERR 17 /* Lock Write Error */
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#define BITP_CGU_STAT_ADDRERR 16 /* Address Error */
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#define BITP_CGU_STAT_OCBF 9 /* OUTCLK Buffer Status */
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#define BITP_CGU_STAT_DCBF 8 /* DCLK Buffer Status */
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#define BITP_CGU_STAT_SCBF1 7 /* SCLK1 Buffer Status */
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#define BITP_CGU_STAT_SCBF0 6 /* SCLK0 Buffer Status */
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#define BITP_CGU_STAT_CCBF1 5 /* CCLK1 Buffer Status */
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#define BITP_CGU_STAT_CCBF0 4 /* CCLK0 Buffer Status */
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#define BITP_CGU_STAT_CLKSALGN 3 /* Clock Alignment */
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#define BITP_CGU_STAT_PLOCK 2 /* PLL Lock */
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#define BITP_CGU_STAT_PLLBP 1 /* PLL Bypass */
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#define BITP_CGU_STAT_PLLEN 0 /* PLL Enable */
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#define BITM_CGU_STAT_PLOCKERR (_ADI_MSK(0x00200000,uint32_t)) /* PLL Lock Error */
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#define BITM_CGU_STAT_WDIVERR (_ADI_MSK(0x00100000,uint32_t)) /* Write to DIV Error */
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#define BITM_CGU_STAT_WDFMSERR (_ADI_MSK(0x00080000,uint32_t)) /* Write to DF or MSEL Error */
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#define BITM_CGU_STAT_DIVERR (_ADI_MSK(0x00040000,uint32_t)) /* DIV Error */
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#define BITM_CGU_STAT_LWERR (_ADI_MSK(0x00020000,uint32_t)) /* Lock Write Error */
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#define BITM_CGU_STAT_ADDRERR (_ADI_MSK(0x00010000,uint32_t)) /* Address Error */
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#define BITM_CGU_STAT_OCBF (_ADI_MSK(0x00000200,uint32_t)) /* OUTCLK Buffer Status */
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#define BITM_CGU_STAT_DCBF (_ADI_MSK(0x00000100,uint32_t)) /* DCLK Buffer Status */
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#define BITM_CGU_STAT_SCBF1 (_ADI_MSK(0x00000080,uint32_t)) /* SCLK1 Buffer Status */
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#define BITM_CGU_STAT_SCBF0 (_ADI_MSK(0x00000040,uint32_t)) /* SCLK0 Buffer Status */
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#define BITM_CGU_STAT_CCBF1 (_ADI_MSK(0x00000020,uint32_t)) /* CCLK1 Buffer Status */
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#define BITM_CGU_STAT_CCBF0 (_ADI_MSK(0x00000010,uint32_t)) /* CCLK0 Buffer Status */
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#define BITM_CGU_STAT_CLKSALGN (_ADI_MSK(0x00000008,uint32_t)) /* Clock Alignment */
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#define BITM_CGU_STAT_PLOCK (_ADI_MSK(0x00000004,uint32_t)) /* PLL Lock */
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#define BITM_CGU_STAT_PLLBP (_ADI_MSK(0x00000002,uint32_t)) /* PLL Bypass */
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#define BITM_CGU_STAT_PLLEN (_ADI_MSK(0x00000001,uint32_t)) /* PLL Enable */
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/* ------------------------------------------------------------------------------------------------------------------------
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CGU_DIV Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_CGU_DIV_LOCK 31 /* Lock */
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#define BITP_CGU_DIV_UPDT 30 /* Update Clock Divisors */
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#define BITP_CGU_DIV_ALGN 29 /* Align */
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#define BITP_CGU_DIV_OSEL 22 /* OUTCLK Divisor */
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#define BITP_CGU_DIV_DSEL 16 /* DCLK Divisor */
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#define BITP_CGU_DIV_S1SEL 13 /* SCLK 1 Divisor */
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#define BITP_CGU_DIV_SYSSEL 8 /* SYSCLK Divisor */
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#define BITP_CGU_DIV_S0SEL 5 /* SCLK 0 Divisor */
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#define BITP_CGU_DIV_CSEL 0 /* CCLK Divisor */
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#define BITM_CGU_DIV_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
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#define BITM_CGU_DIV_UPDT (_ADI_MSK(0x40000000,uint32_t)) /* Update Clock Divisors */
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#define BITM_CGU_DIV_ALGN (_ADI_MSK(0x20000000,uint32_t)) /* Align */
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#define BITM_CGU_DIV_OSEL (_ADI_MSK(0x1FC00000,uint32_t)) /* OUTCLK Divisor */
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#define ENUM_CGU_DIV_OSEL1TO127 (_ADI_MSK(0x00000000,uint32_t)) /* OSEL: OSEL = 1 to 127 */
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#define BITM_CGU_DIV_DSEL (_ADI_MSK(0x001F0000,uint32_t)) /* DCLK Divisor */
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#define ENUM_CGU_DIV_DSEL1TO31 (_ADI_MSK(0x00000000,uint32_t)) /* DSEL: DSEL = 1 to 31 */
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#define BITM_CGU_DIV_S1SEL (_ADI_MSK(0x0000E000,uint32_t)) /* SCLK 1 Divisor */
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#define ENUM_CGU_DIV_S1SEL1TO7 (_ADI_MSK(0x00000000,uint32_t)) /* S1SEL: S1SEL = 1 to 7 */
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#define BITM_CGU_DIV_SYSSEL (_ADI_MSK(0x00001F00,uint32_t)) /* SYSCLK Divisor */
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#define ENUM_CGU_DIV_SYSSEL1TO31 (_ADI_MSK(0x00000000,uint32_t)) /* SYSSEL: SYSSEL = 1 to 31 */
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#define BITM_CGU_DIV_S0SEL (_ADI_MSK(0x000000E0,uint32_t)) /* SCLK 0 Divisor */
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#define ENUM_CGU_DIV_S0SEL1TO7 (_ADI_MSK(0x00000000,uint32_t)) /* S0SEL: S0SEL = 1 to 7 */
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#define BITM_CGU_DIV_CSEL (_ADI_MSK(0x0000001F,uint32_t)) /* CCLK Divisor */
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#define ENUM_CGU_DIV_CSEL1TO31 (_ADI_MSK(0x00000000,uint32_t)) /* CSEL: CSEL= 1 to 31 */
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/* ------------------------------------------------------------------------------------------------------------------------
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CGU_CLKOUTSEL Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_CGU_CLKOUTSEL_LOCK 31 /* Lock */
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#define BITP_CGU_CLKOUTSEL_CLKOUTSEL 0 /* CLKOUT Select */
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#define BITM_CGU_CLKOUTSEL_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
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#define ENUM_CGU_CLKOUTSEL_UNLOCK (_ADI_MSK(0x00000000,uint32_t)) /* LOCK: Unlock */
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#define ENUM_CGU_CLKOUTSEL_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* LOCK: Lock */
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#define BITM_CGU_CLKOUTSEL_CLKOUTSEL (_ADI_MSK(0x0000000F,uint32_t)) /* CLKOUT Select */
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#define ENUM_CGU_CLKOUTSEL_CLKIN (_ADI_MSK(0x00000000,uint32_t)) /* CLKOUTSEL: CLKIN */
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#define ENUM_CGU_CLKOUTSEL_CCLKDIV4 (_ADI_MSK(0x00000001,uint32_t)) /* CLKOUTSEL: CCLKn/4 */
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#define ENUM_CGU_CLKOUTSEL_GNDDIS (_ADI_MSK(0x0000000B,uint32_t)) /* CLKOUTSEL: GND (Disable OUTCLK) */
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#define ENUM_CGU_CLKOUTSEL_SYSCLKDIV2 (_ADI_MSK(0x00000002,uint32_t)) /* CLKOUTSEL: SYSCLK/2 */
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#define ENUM_CGU_CLKOUTSEL_SCLK0 (_ADI_MSK(0x00000003,uint32_t)) /* CLKOUTSEL: SCLK0 */
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#define ENUM_CGU_CLKOUTSEL_SCLK1 (_ADI_MSK(0x00000004,uint32_t)) /* CLKOUTSEL: SCLK1 */
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#define ENUM_CGU_CLKOUTSEL_DCLKDIV2 (_ADI_MSK(0x00000005,uint32_t)) /* CLKOUTSEL: DCLK/2 */
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#define ENUM_CGU_CLKOUTSEL_OUTCLK (_ADI_MSK(0x00000007,uint32_t)) /* CLKOUTSEL: OUTCLK */
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/* ==================================================
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Dynamic Power Management Registers
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================================================== */
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/* =========================
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DPM0
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========================= */
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#define REG_DPM0_CTL 0xFFCA9000 /* DPM0 Control Register */
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#define REG_DPM0_STAT 0xFFCA9004 /* DPM0 Status Register */
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#define REG_DPM0_CCBF_DIS 0xFFCA9008 /* DPM0 Core Clock Buffer Disable Register */
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#define REG_DPM0_CCBF_EN 0xFFCA900C /* DPM0 Core Clock Buffer Enable Register */
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#define REG_DPM0_CCBF_STAT 0xFFCA9010 /* DPM0 Core Clock Buffer Status Register */
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#define REG_DPM0_CCBF_STAT_STKY 0xFFCA9014 /* DPM0 Core Clock Buffer Status Sticky Register */
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#define REG_DPM0_SCBF_DIS 0xFFCA9018 /* DPM0 System Clock Buffer Disable Register */
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#define REG_DPM0_WAKE_EN 0xFFCA901C /* DPM0 Wakeup Enable Register */
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#define REG_DPM0_WAKE_POL 0xFFCA9020 /* DPM0 Wakeup Polarity Register */
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#define REG_DPM0_WAKE_STAT 0xFFCA9024 /* DPM0 Wakeup Status Register */
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#define REG_DPM0_HIB_DIS 0xFFCA9028 /* DPM0 Hibernate Disable Register */
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#define REG_DPM0_PGCNTR 0xFFCA902C /* DPM0 Power Good Counter Register */
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#define REG_DPM0_RESTORE0 0xFFCA9030 /* DPM0 Restore n Register */
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#define REG_DPM0_RESTORE1 0xFFCA9034 /* DPM0 Restore n Register */
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#define REG_DPM0_RESTORE2 0xFFCA9038 /* DPM0 Restore n Register */
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#define REG_DPM0_RESTORE3 0xFFCA903C /* DPM0 Restore n Register */
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#define REG_DPM0_RESTORE4 0xFFCA9040 /* DPM0 Restore n Register */
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#define REG_DPM0_RESTORE5 0xFFCA9044 /* DPM0 Restore n Register */
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#define REG_DPM0_RESTORE6 0xFFCA9048 /* DPM0 Restore n Register */
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#define REG_DPM0_RESTORE7 0xFFCA904C /* DPM0 Restore n Register */
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#define REG_DPM0_RESTORE8 0xFFCA9050 /* DPM0 Restore n Register */
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#define REG_DPM0_RESTORE9 0xFFCA9054 /* DPM0 Restore n Register */
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#define REG_DPM0_RESTORE10 0xFFCA9058 /* DPM0 Restore n Register */
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#define REG_DPM0_RESTORE11 0xFFCA905C /* DPM0 Restore n Register */
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#define REG_DPM0_RESTORE12 0xFFCA9060 /* DPM0 Restore n Register */
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#define REG_DPM0_RESTORE13 0xFFCA9064 /* DPM0 Restore n Register */
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#define REG_DPM0_RESTORE14 0xFFCA9068 /* DPM0 Restore n Register */
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#define REG_DPM0_RESTORE15 0xFFCA906C /* DPM0 Restore n Register */
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/* =========================
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DPM
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========================= */
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/* ------------------------------------------------------------------------------------------------------------------------
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DPM_CTL Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_DPM_CTL_LOCK 31 /* Lock */
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#define BITP_DPM_CTL_HIBERNATE 4 /* Hibernate */
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#define BITP_DPM_CTL_DEEPSLEEP 3 /* Deep Sleep */
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#define BITP_DPM_CTL_PLLDIS 2 /* PLL Disable */
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#define BITP_DPM_CTL_PLLBPCL 1 /* PLL Bypass Clear */
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#define BITP_DPM_CTL_PLLBPST 0 /* PLL Bypass Set */
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#define BITM_DPM_CTL_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
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#define BITM_DPM_CTL_HIBERNATE (_ADI_MSK(0x00000010,uint32_t)) /* Hibernate */
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#define BITM_DPM_CTL_DEEPSLEEP (_ADI_MSK(0x00000008,uint32_t)) /* Deep Sleep */
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#define BITM_DPM_CTL_PLLDIS (_ADI_MSK(0x00000004,uint32_t)) /* PLL Disable */
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#define BITM_DPM_CTL_PLLBPCL (_ADI_MSK(0x00000002,uint32_t)) /* PLL Bypass Clear */
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#define BITM_DPM_CTL_PLLBPST (_ADI_MSK(0x00000001,uint32_t)) /* PLL Bypass Set */
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/* ------------------------------------------------------------------------------------------------------------------------
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DPM_STAT Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_DPM_STAT_PLLCFGERR 19 /* PLL Configuration Error */
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#define BITP_DPM_STAT_HVBSYERR 18 /* HV Busy Error */
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#define BITP_DPM_STAT_LWERR 17 /* Lock Write Error */
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#define BITP_DPM_STAT_ADDRERR 16 /* Address Error */
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#define BITP_DPM_STAT_HVBSY 9 /* HV Busy */
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#define BITP_DPM_STAT_CCLKDIS 8 /* Core Clock(s) Disabled */
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#define BITP_DPM_STAT_PRVMODE 4 /* Previous Mode */
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#define BITP_DPM_STAT_CURMODE 0 /* Current Mode */
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#define BITM_DPM_STAT_PLLCFGERR (_ADI_MSK(0x00080000,uint32_t)) /* PLL Configuration Error */
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#define BITM_DPM_STAT_HVBSYERR (_ADI_MSK(0x00040000,uint32_t)) /* HV Busy Error */
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#define BITM_DPM_STAT_LWERR (_ADI_MSK(0x00020000,uint32_t)) /* Lock Write Error */
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#define BITM_DPM_STAT_ADDRERR (_ADI_MSK(0x00010000,uint32_t)) /* Address Error */
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#define BITM_DPM_STAT_HVBSY (_ADI_MSK(0x00000200,uint32_t)) /* HV Busy */
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#define BITM_DPM_STAT_CCLKDIS (_ADI_MSK(0x00000100,uint32_t)) /* Core Clock(s) Disabled */
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#define BITM_DPM_STAT_PRVMODE (_ADI_MSK(0x000000F0,uint32_t)) /* Previous Mode */
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#define BITM_DPM_STAT_CURMODE (_ADI_MSK(0x0000000F,uint32_t)) /* Current Mode */
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/* ------------------------------------------------------------------------------------------------------------------------
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DPM_CCBF_DIS Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_DPM_CCBF_DIS_LOCK 31 /* Lock */
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#define BITP_DPM_CCBF_DIS_CCBF0 0 /* Core Clock Buffer n Disable */
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#define BITP_DPM_CCBF_DIS_CCBF1 1 /* Core Clock Buffer n Disable */
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#define BITM_DPM_CCBF_DIS_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
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#define BITM_DPM_CCBF_DIS_CCBF0 (_ADI_MSK(0x00000001,uint32_t)) /* Core Clock Buffer n Disable */
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#define BITM_DPM_CCBF_DIS_CCBF1 (_ADI_MSK(0x00000002,uint32_t)) /* Core Clock Buffer n Disable */
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/* ------------------------------------------------------------------------------------------------------------------------
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DPM_CCBF_EN Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_DPM_CCBF_EN_LOCK 31 /* Lock */
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#define BITP_DPM_CCBF_EN_CCBF0 0 /* Core Clock Buffer n Enable */
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#define BITP_DPM_CCBF_EN_CCBF1 1 /* Core Clock Buffer n Enable */
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#define BITM_DPM_CCBF_EN_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
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#define BITM_DPM_CCBF_EN_CCBF0 (_ADI_MSK(0x00000001,uint32_t)) /* Core Clock Buffer n Enable */
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#define BITM_DPM_CCBF_EN_CCBF1 (_ADI_MSK(0x00000002,uint32_t)) /* Core Clock Buffer n Enable */
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/* ------------------------------------------------------------------------------------------------------------------------
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DPM_CCBF_STAT Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_DPM_CCBF_STAT_CCBF0 0 /* Core Clock Buffer n Status */
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#define BITP_DPM_CCBF_STAT_CCBF1 1 /* Core Clock Buffer n Status */
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#define BITM_DPM_CCBF_STAT_CCBF0 (_ADI_MSK(0x00000001,uint32_t)) /* Core Clock Buffer n Status */
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#define BITM_DPM_CCBF_STAT_CCBF1 (_ADI_MSK(0x00000002,uint32_t)) /* Core Clock Buffer n Status */
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/* ------------------------------------------------------------------------------------------------------------------------
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DPM_CCBF_STAT_STKY Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_DPM_CCBF_STAT_STKY_CCBF0 0 /* Core Clock Buffer n Status - Sticky */
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#define BITP_DPM_CCBF_STAT_STKY_CCBF1 1 /* Core Clock Buffer n Status - Sticky */
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#define BITM_DPM_CCBF_STAT_STKY_CCBF0 (_ADI_MSK(0x00000001,uint32_t)) /* Core Clock Buffer n Status - Sticky */
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#define BITM_DPM_CCBF_STAT_STKY_CCBF1 (_ADI_MSK(0x00000002,uint32_t)) /* Core Clock Buffer n Status - Sticky */
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/* ------------------------------------------------------------------------------------------------------------------------
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DPM_SCBF_DIS Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_DPM_SCBF_DIS_LOCK 31 /* Lock */
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#define BITP_DPM_SCBF_DIS_SCBF0 0 /* System Clock Buffer n Disable */
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#define BITP_DPM_SCBF_DIS_SCBF1 1 /* System Clock Buffer n Disable */
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#define BITP_DPM_SCBF_DIS_SCBF2 2 /* System Clock Buffer n Disable */
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#define BITP_DPM_SCBF_DIS_SCBF3 3 /* System Clock Buffer n Disable */
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#define BITM_DPM_SCBF_DIS_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
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#define BITM_DPM_SCBF_DIS_SCBF0 (_ADI_MSK(0x00000001,uint32_t)) /* System Clock Buffer n Disable */
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#define BITM_DPM_SCBF_DIS_SCBF1 (_ADI_MSK(0x00000002,uint32_t)) /* System Clock Buffer n Disable */
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#define BITM_DPM_SCBF_DIS_SCBF2 (_ADI_MSK(0x00000004,uint32_t)) /* System Clock Buffer n Disable */
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#define BITM_DPM_SCBF_DIS_SCBF3 (_ADI_MSK(0x00000008,uint32_t)) /* System Clock Buffer n Disable */
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/* ------------------------------------------------------------------------------------------------------------------------
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DPM_WAKE_EN Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_DPM_WAKE_EN_LOCK 31 /* Lock */
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#define BITP_DPM_WAKE_EN_WS0 0 /* Wakeup Source n Enable */
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#define BITP_DPM_WAKE_EN_WS1 1 /* Wakeup Source n Enable */
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#define BITP_DPM_WAKE_EN_WS2 2 /* Wakeup Source n Enable */
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#define BITP_DPM_WAKE_EN_WS3 3 /* Wakeup Source n Enable */
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#define BITP_DPM_WAKE_EN_WS4 4 /* Wakeup Source n Enable */
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#define BITP_DPM_WAKE_EN_WS5 5 /* Wakeup Source n Enable */
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#define BITP_DPM_WAKE_EN_WS6 6 /* Wakeup Source n Enable */
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#define BITP_DPM_WAKE_EN_WS7 7 /* Wakeup Source n Enable */
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#define BITM_DPM_WAKE_EN_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
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#define BITM_DPM_WAKE_EN_WS0 (_ADI_MSK(0x00000001,uint32_t)) /* Wakeup Source n Enable */
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#define BITM_DPM_WAKE_EN_WS1 (_ADI_MSK(0x00000002,uint32_t)) /* Wakeup Source n Enable */
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#define BITM_DPM_WAKE_EN_WS2 (_ADI_MSK(0x00000004,uint32_t)) /* Wakeup Source n Enable */
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#define BITM_DPM_WAKE_EN_WS3 (_ADI_MSK(0x00000008,uint32_t)) /* Wakeup Source n Enable */
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#define BITM_DPM_WAKE_EN_WS4 (_ADI_MSK(0x00000010,uint32_t)) /* Wakeup Source n Enable */
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#define BITM_DPM_WAKE_EN_WS5 (_ADI_MSK(0x00000020,uint32_t)) /* Wakeup Source n Enable */
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#define BITM_DPM_WAKE_EN_WS6 (_ADI_MSK(0x00000040,uint32_t)) /* Wakeup Source n Enable */
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#define BITM_DPM_WAKE_EN_WS7 (_ADI_MSK(0x00000080,uint32_t)) /* Wakeup Source n Enable */
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/* ------------------------------------------------------------------------------------------------------------------------
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DPM_WAKE_POL Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_DPM_WAKE_POL_LOCK 31 /* Lock */
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#define BITP_DPM_WAKE_POL_WS0 0 /* Wakeup Source n Polarity */
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#define BITP_DPM_WAKE_POL_WS1 1 /* Wakeup Source n Polarity */
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#define BITP_DPM_WAKE_POL_WS2 2 /* Wakeup Source n Polarity */
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#define BITP_DPM_WAKE_POL_WS3 3 /* Wakeup Source n Polarity */
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#define BITP_DPM_WAKE_POL_WS4 4 /* Wakeup Source n Polarity */
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#define BITP_DPM_WAKE_POL_WS5 5 /* Wakeup Source n Polarity */
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#define BITP_DPM_WAKE_POL_WS6 6 /* Wakeup Source n Polarity */
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#define BITP_DPM_WAKE_POL_WS7 7 /* Wakeup Source n Polarity */
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#define BITM_DPM_WAKE_POL_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
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#define BITM_DPM_WAKE_POL_WS0 (_ADI_MSK(0x00000001,uint32_t)) /* Wakeup Source n Polarity */
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#define BITM_DPM_WAKE_POL_WS1 (_ADI_MSK(0x00000002,uint32_t)) /* Wakeup Source n Polarity */
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#define BITM_DPM_WAKE_POL_WS2 (_ADI_MSK(0x00000004,uint32_t)) /* Wakeup Source n Polarity */
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#define BITM_DPM_WAKE_POL_WS3 (_ADI_MSK(0x00000008,uint32_t)) /* Wakeup Source n Polarity */
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#define BITM_DPM_WAKE_POL_WS4 (_ADI_MSK(0x00000010,uint32_t)) /* Wakeup Source n Polarity */
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#define BITM_DPM_WAKE_POL_WS5 (_ADI_MSK(0x00000020,uint32_t)) /* Wakeup Source n Polarity */
|
|
#define BITM_DPM_WAKE_POL_WS6 (_ADI_MSK(0x00000040,uint32_t)) /* Wakeup Source n Polarity */
|
|
#define BITM_DPM_WAKE_POL_WS7 (_ADI_MSK(0x00000080,uint32_t)) /* Wakeup Source n Polarity */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DPM_WAKE_STAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DPM_WAKE_STAT_WS0 0 /* Wakeup Source n Status */
|
|
#define BITP_DPM_WAKE_STAT_WS1 1 /* Wakeup Source n Status */
|
|
#define BITP_DPM_WAKE_STAT_WS2 2 /* Wakeup Source n Status */
|
|
#define BITP_DPM_WAKE_STAT_WS3 3 /* Wakeup Source n Status */
|
|
#define BITP_DPM_WAKE_STAT_WS4 4 /* Wakeup Source n Status */
|
|
#define BITP_DPM_WAKE_STAT_WS5 5 /* Wakeup Source n Status */
|
|
#define BITP_DPM_WAKE_STAT_WS6 6 /* Wakeup Source n Status */
|
|
#define BITP_DPM_WAKE_STAT_WS7 7 /* Wakeup Source n Status */
|
|
#define BITM_DPM_WAKE_STAT_WS0 (_ADI_MSK(0x00000001,uint32_t)) /* Wakeup Source n Status */
|
|
#define BITM_DPM_WAKE_STAT_WS1 (_ADI_MSK(0x00000002,uint32_t)) /* Wakeup Source n Status */
|
|
#define BITM_DPM_WAKE_STAT_WS2 (_ADI_MSK(0x00000004,uint32_t)) /* Wakeup Source n Status */
|
|
#define BITM_DPM_WAKE_STAT_WS3 (_ADI_MSK(0x00000008,uint32_t)) /* Wakeup Source n Status */
|
|
#define BITM_DPM_WAKE_STAT_WS4 (_ADI_MSK(0x00000010,uint32_t)) /* Wakeup Source n Status */
|
|
#define BITM_DPM_WAKE_STAT_WS5 (_ADI_MSK(0x00000020,uint32_t)) /* Wakeup Source n Status */
|
|
#define BITM_DPM_WAKE_STAT_WS6 (_ADI_MSK(0x00000040,uint32_t)) /* Wakeup Source n Status */
|
|
#define BITM_DPM_WAKE_STAT_WS7 (_ADI_MSK(0x00000080,uint32_t)) /* Wakeup Source n Status */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DPM_HIB_DIS Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DPM_HIB_DIS_LOCK 31 /* Lock */
|
|
#define BITP_DPM_HIB_DIS_HD0 0 /* Hibernate Disable n */
|
|
#define BITP_DPM_HIB_DIS_HD1 1 /* Hibernate Disable n */
|
|
#define BITP_DPM_HIB_DIS_HD2 2 /* Hibernate Disable n */
|
|
#define BITP_DPM_HIB_DIS_HD3 3 /* Hibernate Disable n */
|
|
#define BITP_DPM_HIB_DIS_HD4 4 /* Hibernate Disable n */
|
|
#define BITP_DPM_HIB_DIS_HD5 5 /* Hibernate Disable n */
|
|
#define BITP_DPM_HIB_DIS_HD6 6 /* Hibernate Disable n */
|
|
#define BITP_DPM_HIB_DIS_HD7 7 /* Hibernate Disable n */
|
|
#define BITM_DPM_HIB_DIS_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
|
|
#define BITM_DPM_HIB_DIS_HD0 (_ADI_MSK(0x00000001,uint32_t)) /* Hibernate Disable n */
|
|
#define BITM_DPM_HIB_DIS_HD1 (_ADI_MSK(0x00000002,uint32_t)) /* Hibernate Disable n */
|
|
#define BITM_DPM_HIB_DIS_HD2 (_ADI_MSK(0x00000004,uint32_t)) /* Hibernate Disable n */
|
|
#define BITM_DPM_HIB_DIS_HD3 (_ADI_MSK(0x00000008,uint32_t)) /* Hibernate Disable n */
|
|
#define BITM_DPM_HIB_DIS_HD4 (_ADI_MSK(0x00000010,uint32_t)) /* Hibernate Disable n */
|
|
#define BITM_DPM_HIB_DIS_HD5 (_ADI_MSK(0x00000020,uint32_t)) /* Hibernate Disable n */
|
|
#define BITM_DPM_HIB_DIS_HD6 (_ADI_MSK(0x00000040,uint32_t)) /* Hibernate Disable n */
|
|
#define BITM_DPM_HIB_DIS_HD7 (_ADI_MSK(0x00000080,uint32_t)) /* Hibernate Disable n */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DPM_PGCNTR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DPM_PGCNTR_LOCK 31 /* Lock */
|
|
#define BITP_DPM_PGCNTR_CNT 0 /* Power Good Count */
|
|
#define BITM_DPM_PGCNTR_LOCK (_ADI_MSK(0x80000000,uint32_t)) /* Lock */
|
|
#define BITM_DPM_PGCNTR_CNT (_ADI_MSK(0x0000FFFF,uint32_t)) /* Power Good Count */
|
|
|
|
/* ==================================================
|
|
eFUSE Controller Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
EFS0
|
|
========================= */
|
|
#define REG_EFS0_CTL 0xFFCC0000 /* EFS0 Control Register */
|
|
#define REG_EFS0_DAT0 0xFFCC0008 /* EFS0 Data Register 0 */
|
|
#define REG_EFS0_DAT1 0xFFCC000C /* EFS0 Data Register 1 */
|
|
#define REG_EFS0_DAT2 0xFFCC0010 /* EFS0 Data Register 2 */
|
|
#define REG_EFS0_DAT3 0xFFCC0014 /* EFS0 Data Register 3 */
|
|
#define REG_EFS0_DAT4 0xFFCC0018 /* EFS0 Data Register 4 */
|
|
#define REG_EFS0_DAT5 0xFFCC001C /* EFS0 Data Register 5 */
|
|
#define REG_EFS0_DAT6 0xFFCC0020 /* EFS0 Data Register 6 */
|
|
#define REG_EFS0_DAT7 0xFFCC0024 /* EFS0 Data Register 7 */
|
|
|
|
/* =========================
|
|
EFS
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
EFS_CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_EFS_CTL_READ 0 /* Read */
|
|
#define BITM_EFS_CTL_READ (_ADI_MSK(0x00000001,uint32_t)) /* Read */
|
|
|
|
/* ==================================================
|
|
Universal Serial Bus Controller Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
USB0
|
|
========================= */
|
|
#define REG_USB0_FADDR 0xFFCC1000 /* USB0 Function Address Register */
|
|
#define REG_USB0_POWER 0xFFCC1001 /* USB0 Power and Device Control Register */
|
|
#define REG_USB0_INTRTX 0xFFCC1002 /* USB0 Transmit Interrupt Register */
|
|
#define REG_USB0_INTRRX 0xFFCC1004 /* USB0 Receive Interrupt Register */
|
|
#define REG_USB0_INTRTXE 0xFFCC1006 /* USB0 Transmit Interrupt Enable Register */
|
|
#define REG_USB0_INTRRXE 0xFFCC1008 /* USB0 Receive Interrupt Enable Register */
|
|
#define REG_USB0_IRQ 0xFFCC100A /* USB0 Common Interrupts Register */
|
|
#define REG_USB0_IEN 0xFFCC100B /* USB0 Common Interrupts Enable Register */
|
|
#define REG_USB0_FRAME 0xFFCC100C /* USB0 Frame Number Register */
|
|
#define REG_USB0_INDEX 0xFFCC100E /* USB0 Index Register */
|
|
#define REG_USB0_TESTMODE 0xFFCC100F /* USB0 Testmode Register */
|
|
#define REG_USB0_EPI_TXMAXP0 0xFFCC1010 /* USB0 EPn Transmit Maximum Packet Length Register */
|
|
#define REG_USB0_EPI_TXCSR_P0 0xFFCC1012 /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
|
|
#define REG_USB0_EPI_TXCSR_H0 0xFFCC1012 /* USB0 EPn Transmit Configuration and Status (Host) Register */
|
|
#define REG_USB0_EP0I_CSR0_P 0xFFCC1012 /* USB0 EP0 Configuration and Status (Peripheral) Register */
|
|
#define REG_USB0_EP0I_CSR0_H 0xFFCC1012 /* USB0 EP0 Configuration and Status (Host) Register */
|
|
#define REG_USB0_EPI_RXMAXP0 0xFFCC1014 /* USB0 EPn Receive Maximum Packet Length Register */
|
|
#define REG_USB0_EPI_RXCSR_H0 0xFFCC1016 /* USB0 EPn Receive Configuration and Status (Host) Register */
|
|
#define REG_USB0_EPI_RXCSR_P0 0xFFCC1016 /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
|
|
#define REG_USB0_EP0I_CNT0 0xFFCC1018 /* USB0 EP0 Number of Received Bytes Register */
|
|
#define REG_USB0_EPI_RXCNT0 0xFFCC1018 /* USB0 EPn Number of Bytes Received Register */
|
|
#define REG_USB0_EPI_TXTYPE0 0xFFCC101A /* USB0 EPn Transmit Type Register */
|
|
#define REG_USB0_EP0I_TYPE0 0xFFCC101A /* USB0 EP0 Connection Type Register */
|
|
#define REG_USB0_EPI_TXINTERVAL0 0xFFCC101B /* USB0 EPn Transmit Polling Interval Register */
|
|
#define REG_USB0_EP0I_NAKLIMIT0 0xFFCC101B /* USB0 EP0 NAK Limit Register */
|
|
#define REG_USB0_EPI_RXTYPE0 0xFFCC101C /* USB0 EPn Receive Type Register */
|
|
#define REG_USB0_EPI_RXINTERVAL0 0xFFCC101D /* USB0 EPn Receive Polling Interval Register */
|
|
#define REG_USB0_EP0I_CFGDATA0 0xFFCC101F /* USB0 EP0 Configuration Information Register */
|
|
#define REG_USB0_FIFOB0 0xFFCC1020 /* USB0 FIFO Byte (8-Bit) Register */
|
|
#define REG_USB0_FIFOB1 0xFFCC1024 /* USB0 FIFO Byte (8-Bit) Register */
|
|
#define REG_USB0_FIFOB2 0xFFCC1028 /* USB0 FIFO Byte (8-Bit) Register */
|
|
#define REG_USB0_FIFOB3 0xFFCC102C /* USB0 FIFO Byte (8-Bit) Register */
|
|
#define REG_USB0_FIFOB4 0xFFCC1030 /* USB0 FIFO Byte (8-Bit) Register */
|
|
#define REG_USB0_FIFOB5 0xFFCC1034 /* USB0 FIFO Byte (8-Bit) Register */
|
|
#define REG_USB0_FIFOB6 0xFFCC1038 /* USB0 FIFO Byte (8-Bit) Register */
|
|
#define REG_USB0_FIFOB7 0xFFCC103C /* USB0 FIFO Byte (8-Bit) Register */
|
|
#define REG_USB0_FIFOB8 0xFFCC1040 /* USB0 FIFO Byte (8-Bit) Register */
|
|
#define REG_USB0_FIFOB9 0xFFCC1044 /* USB0 FIFO Byte (8-Bit) Register */
|
|
#define REG_USB0_FIFOB10 0xFFCC1048 /* USB0 FIFO Byte (8-Bit) Register */
|
|
#define REG_USB0_FIFOB11 0xFFCC104C /* USB0 FIFO Byte (8-Bit) Register */
|
|
#define REG_USB0_FIFOH0 0xFFCC1020 /* USB0 FIFO Half-Word (16-Bit) Register */
|
|
#define REG_USB0_FIFOH1 0xFFCC1024 /* USB0 FIFO Half-Word (16-Bit) Register */
|
|
#define REG_USB0_FIFOH2 0xFFCC1028 /* USB0 FIFO Half-Word (16-Bit) Register */
|
|
#define REG_USB0_FIFOH3 0xFFCC102C /* USB0 FIFO Half-Word (16-Bit) Register */
|
|
#define REG_USB0_FIFOH4 0xFFCC1030 /* USB0 FIFO Half-Word (16-Bit) Register */
|
|
#define REG_USB0_FIFOH5 0xFFCC1034 /* USB0 FIFO Half-Word (16-Bit) Register */
|
|
#define REG_USB0_FIFOH6 0xFFCC1038 /* USB0 FIFO Half-Word (16-Bit) Register */
|
|
#define REG_USB0_FIFOH7 0xFFCC103C /* USB0 FIFO Half-Word (16-Bit) Register */
|
|
#define REG_USB0_FIFOH8 0xFFCC1040 /* USB0 FIFO Half-Word (16-Bit) Register */
|
|
#define REG_USB0_FIFOH9 0xFFCC1044 /* USB0 FIFO Half-Word (16-Bit) Register */
|
|
#define REG_USB0_FIFOH10 0xFFCC1048 /* USB0 FIFO Half-Word (16-Bit) Register */
|
|
#define REG_USB0_FIFOH11 0xFFCC104C /* USB0 FIFO Half-Word (16-Bit) Register */
|
|
#define REG_USB0_FIFO0 0xFFCC1020 /* USB0 FIFO Word (32-Bit) Register */
|
|
#define REG_USB0_FIFO1 0xFFCC1024 /* USB0 FIFO Word (32-Bit) Register */
|
|
#define REG_USB0_FIFO2 0xFFCC1028 /* USB0 FIFO Word (32-Bit) Register */
|
|
#define REG_USB0_FIFO3 0xFFCC102C /* USB0 FIFO Word (32-Bit) Register */
|
|
#define REG_USB0_FIFO4 0xFFCC1030 /* USB0 FIFO Word (32-Bit) Register */
|
|
#define REG_USB0_FIFO5 0xFFCC1034 /* USB0 FIFO Word (32-Bit) Register */
|
|
#define REG_USB0_FIFO6 0xFFCC1038 /* USB0 FIFO Word (32-Bit) Register */
|
|
#define REG_USB0_FIFO7 0xFFCC103C /* USB0 FIFO Word (32-Bit) Register */
|
|
#define REG_USB0_FIFO8 0xFFCC1040 /* USB0 FIFO Word (32-Bit) Register */
|
|
#define REG_USB0_FIFO9 0xFFCC1044 /* USB0 FIFO Word (32-Bit) Register */
|
|
#define REG_USB0_FIFO10 0xFFCC1048 /* USB0 FIFO Word (32-Bit) Register */
|
|
#define REG_USB0_FIFO11 0xFFCC104C /* USB0 FIFO Word (32-Bit) Register */
|
|
#define REG_USB0_DEV_CTL 0xFFCC1060 /* USB0 Device Control Register */
|
|
#define REG_USB0_TXFIFOSZ 0xFFCC1062 /* USB0 Transmit FIFO Size Register */
|
|
#define REG_USB0_RXFIFOSZ 0xFFCC1063 /* USB0 Receive FIFO Size Register */
|
|
#define REG_USB0_TXFIFOADDR 0xFFCC1064 /* USB0 Transmit FIFO Address Register */
|
|
#define REG_USB0_RXFIFOADDR 0xFFCC1066 /* USB0 Receive FIFO Address Register */
|
|
#define REG_USB0_EPINFO 0xFFCC1078 /* USB0 Endpoint Information Register */
|
|
#define REG_USB0_RAMINFO 0xFFCC1079 /* USB0 RAM Information Register */
|
|
#define REG_USB0_LINKINFO 0xFFCC107A /* USB0 Link Information Register */
|
|
#define REG_USB0_VPLEN 0xFFCC107B /* USB0 VBUS Pulse Length Register */
|
|
#define REG_USB0_HS_EOF1 0xFFCC107C /* USB0 High-Speed EOF 1 Register */
|
|
#define REG_USB0_FS_EOF1 0xFFCC107D /* USB0 Full-Speed EOF 1 Register */
|
|
#define REG_USB0_LS_EOF1 0xFFCC107E /* USB0 Low-Speed EOF 1 Register */
|
|
#define REG_USB0_SOFT_RST 0xFFCC107F /* USB0 Software Reset Register */
|
|
#define REG_USB0_MP0_TXFUNCADDR 0xFFCC1080 /* USB0 MPn Transmit Function Address Register */
|
|
#define REG_USB0_MP1_TXFUNCADDR 0xFFCC1088 /* USB0 MPn Transmit Function Address Register */
|
|
#define REG_USB0_MP2_TXFUNCADDR 0xFFCC1090 /* USB0 MPn Transmit Function Address Register */
|
|
#define REG_USB0_MP3_TXFUNCADDR 0xFFCC1098 /* USB0 MPn Transmit Function Address Register */
|
|
#define REG_USB0_MP4_TXFUNCADDR 0xFFCC10A0 /* USB0 MPn Transmit Function Address Register */
|
|
#define REG_USB0_MP5_TXFUNCADDR 0xFFCC10A8 /* USB0 MPn Transmit Function Address Register */
|
|
#define REG_USB0_MP6_TXFUNCADDR 0xFFCC10B0 /* USB0 MPn Transmit Function Address Register */
|
|
#define REG_USB0_MP7_TXFUNCADDR 0xFFCC10B8 /* USB0 MPn Transmit Function Address Register */
|
|
#define REG_USB0_MP8_TXFUNCADDR 0xFFCC10C0 /* USB0 MPn Transmit Function Address Register */
|
|
#define REG_USB0_MP9_TXFUNCADDR 0xFFCC10C8 /* USB0 MPn Transmit Function Address Register */
|
|
#define REG_USB0_MP10_TXFUNCADDR 0xFFCC10D0 /* USB0 MPn Transmit Function Address Register */
|
|
#define REG_USB0_MP11_TXFUNCADDR 0xFFCC10D8 /* USB0 MPn Transmit Function Address Register */
|
|
#define REG_USB0_MP0_TXHUBADDR 0xFFCC1082 /* USB0 MPn Transmit Hub Address Register */
|
|
#define REG_USB0_MP1_TXHUBADDR 0xFFCC108A /* USB0 MPn Transmit Hub Address Register */
|
|
#define REG_USB0_MP2_TXHUBADDR 0xFFCC1092 /* USB0 MPn Transmit Hub Address Register */
|
|
#define REG_USB0_MP3_TXHUBADDR 0xFFCC109A /* USB0 MPn Transmit Hub Address Register */
|
|
#define REG_USB0_MP4_TXHUBADDR 0xFFCC10A2 /* USB0 MPn Transmit Hub Address Register */
|
|
#define REG_USB0_MP5_TXHUBADDR 0xFFCC10AA /* USB0 MPn Transmit Hub Address Register */
|
|
#define REG_USB0_MP6_TXHUBADDR 0xFFCC10B2 /* USB0 MPn Transmit Hub Address Register */
|
|
#define REG_USB0_MP7_TXHUBADDR 0xFFCC10BA /* USB0 MPn Transmit Hub Address Register */
|
|
#define REG_USB0_MP8_TXHUBADDR 0xFFCC10C2 /* USB0 MPn Transmit Hub Address Register */
|
|
#define REG_USB0_MP9_TXHUBADDR 0xFFCC10CA /* USB0 MPn Transmit Hub Address Register */
|
|
#define REG_USB0_MP10_TXHUBADDR 0xFFCC10D2 /* USB0 MPn Transmit Hub Address Register */
|
|
#define REG_USB0_MP11_TXHUBADDR 0xFFCC10DA /* USB0 MPn Transmit Hub Address Register */
|
|
#define REG_USB0_MP0_TXHUBPORT 0xFFCC1083 /* USB0 MPn Transmit Hub Port Register */
|
|
#define REG_USB0_MP1_TXHUBPORT 0xFFCC108B /* USB0 MPn Transmit Hub Port Register */
|
|
#define REG_USB0_MP2_TXHUBPORT 0xFFCC1093 /* USB0 MPn Transmit Hub Port Register */
|
|
#define REG_USB0_MP3_TXHUBPORT 0xFFCC109B /* USB0 MPn Transmit Hub Port Register */
|
|
#define REG_USB0_MP4_TXHUBPORT 0xFFCC10A3 /* USB0 MPn Transmit Hub Port Register */
|
|
#define REG_USB0_MP5_TXHUBPORT 0xFFCC10AB /* USB0 MPn Transmit Hub Port Register */
|
|
#define REG_USB0_MP6_TXHUBPORT 0xFFCC10B3 /* USB0 MPn Transmit Hub Port Register */
|
|
#define REG_USB0_MP7_TXHUBPORT 0xFFCC10BB /* USB0 MPn Transmit Hub Port Register */
|
|
#define REG_USB0_MP8_TXHUBPORT 0xFFCC10C3 /* USB0 MPn Transmit Hub Port Register */
|
|
#define REG_USB0_MP9_TXHUBPORT 0xFFCC10CB /* USB0 MPn Transmit Hub Port Register */
|
|
#define REG_USB0_MP10_TXHUBPORT 0xFFCC10D3 /* USB0 MPn Transmit Hub Port Register */
|
|
#define REG_USB0_MP11_TXHUBPORT 0xFFCC10DB /* USB0 MPn Transmit Hub Port Register */
|
|
#define REG_USB0_MP0_RXFUNCADDR 0xFFCC1084 /* USB0 MPn Receive Function Address Register */
|
|
#define REG_USB0_MP1_RXFUNCADDR 0xFFCC108C /* USB0 MPn Receive Function Address Register */
|
|
#define REG_USB0_MP2_RXFUNCADDR 0xFFCC1094 /* USB0 MPn Receive Function Address Register */
|
|
#define REG_USB0_MP3_RXFUNCADDR 0xFFCC109C /* USB0 MPn Receive Function Address Register */
|
|
#define REG_USB0_MP4_RXFUNCADDR 0xFFCC10A4 /* USB0 MPn Receive Function Address Register */
|
|
#define REG_USB0_MP5_RXFUNCADDR 0xFFCC10AC /* USB0 MPn Receive Function Address Register */
|
|
#define REG_USB0_MP6_RXFUNCADDR 0xFFCC10B4 /* USB0 MPn Receive Function Address Register */
|
|
#define REG_USB0_MP7_RXFUNCADDR 0xFFCC10BC /* USB0 MPn Receive Function Address Register */
|
|
#define REG_USB0_MP8_RXFUNCADDR 0xFFCC10C4 /* USB0 MPn Receive Function Address Register */
|
|
#define REG_USB0_MP9_RXFUNCADDR 0xFFCC10CC /* USB0 MPn Receive Function Address Register */
|
|
#define REG_USB0_MP10_RXFUNCADDR 0xFFCC10D4 /* USB0 MPn Receive Function Address Register */
|
|
#define REG_USB0_MP11_RXFUNCADDR 0xFFCC10DC /* USB0 MPn Receive Function Address Register */
|
|
#define REG_USB0_MP0_RXHUBADDR 0xFFCC1086 /* USB0 MPn Receive Hub Address Register */
|
|
#define REG_USB0_MP1_RXHUBADDR 0xFFCC108E /* USB0 MPn Receive Hub Address Register */
|
|
#define REG_USB0_MP2_RXHUBADDR 0xFFCC1096 /* USB0 MPn Receive Hub Address Register */
|
|
#define REG_USB0_MP3_RXHUBADDR 0xFFCC109E /* USB0 MPn Receive Hub Address Register */
|
|
#define REG_USB0_MP4_RXHUBADDR 0xFFCC10A6 /* USB0 MPn Receive Hub Address Register */
|
|
#define REG_USB0_MP5_RXHUBADDR 0xFFCC10AE /* USB0 MPn Receive Hub Address Register */
|
|
#define REG_USB0_MP6_RXHUBADDR 0xFFCC10B6 /* USB0 MPn Receive Hub Address Register */
|
|
#define REG_USB0_MP7_RXHUBADDR 0xFFCC10BE /* USB0 MPn Receive Hub Address Register */
|
|
#define REG_USB0_MP8_RXHUBADDR 0xFFCC10C6 /* USB0 MPn Receive Hub Address Register */
|
|
#define REG_USB0_MP9_RXHUBADDR 0xFFCC10CE /* USB0 MPn Receive Hub Address Register */
|
|
#define REG_USB0_MP10_RXHUBADDR 0xFFCC10D6 /* USB0 MPn Receive Hub Address Register */
|
|
#define REG_USB0_MP11_RXHUBADDR 0xFFCC10DE /* USB0 MPn Receive Hub Address Register */
|
|
#define REG_USB0_MP0_RXHUBPORT 0xFFCC1087 /* USB0 MPn Receive Hub Port Register */
|
|
#define REG_USB0_MP1_RXHUBPORT 0xFFCC108F /* USB0 MPn Receive Hub Port Register */
|
|
#define REG_USB0_MP2_RXHUBPORT 0xFFCC1097 /* USB0 MPn Receive Hub Port Register */
|
|
#define REG_USB0_MP3_RXHUBPORT 0xFFCC109F /* USB0 MPn Receive Hub Port Register */
|
|
#define REG_USB0_MP4_RXHUBPORT 0xFFCC10A7 /* USB0 MPn Receive Hub Port Register */
|
|
#define REG_USB0_MP5_RXHUBPORT 0xFFCC10AF /* USB0 MPn Receive Hub Port Register */
|
|
#define REG_USB0_MP6_RXHUBPORT 0xFFCC10B7 /* USB0 MPn Receive Hub Port Register */
|
|
#define REG_USB0_MP7_RXHUBPORT 0xFFCC10BF /* USB0 MPn Receive Hub Port Register */
|
|
#define REG_USB0_MP8_RXHUBPORT 0xFFCC10C7 /* USB0 MPn Receive Hub Port Register */
|
|
#define REG_USB0_MP9_RXHUBPORT 0xFFCC10CF /* USB0 MPn Receive Hub Port Register */
|
|
#define REG_USB0_MP10_RXHUBPORT 0xFFCC10D7 /* USB0 MPn Receive Hub Port Register */
|
|
#define REG_USB0_MP11_RXHUBPORT 0xFFCC10DF /* USB0 MPn Receive Hub Port Register */
|
|
#define REG_USB0_EP0_TXMAXP 0xFFCC1100 /* USB0 EPn Transmit Maximum Packet Length Register */
|
|
#define REG_USB0_EP1_TXMAXP 0xFFCC1110 /* USB0 EPn Transmit Maximum Packet Length Register */
|
|
#define REG_USB0_EP2_TXMAXP 0xFFCC1120 /* USB0 EPn Transmit Maximum Packet Length Register */
|
|
#define REG_USB0_EP3_TXMAXP 0xFFCC1130 /* USB0 EPn Transmit Maximum Packet Length Register */
|
|
#define REG_USB0_EP4_TXMAXP 0xFFCC1140 /* USB0 EPn Transmit Maximum Packet Length Register */
|
|
#define REG_USB0_EP5_TXMAXP 0xFFCC1150 /* USB0 EPn Transmit Maximum Packet Length Register */
|
|
#define REG_USB0_EP6_TXMAXP 0xFFCC1160 /* USB0 EPn Transmit Maximum Packet Length Register */
|
|
#define REG_USB0_EP7_TXMAXP 0xFFCC1170 /* USB0 EPn Transmit Maximum Packet Length Register */
|
|
#define REG_USB0_EP8_TXMAXP 0xFFCC1180 /* USB0 EPn Transmit Maximum Packet Length Register */
|
|
#define REG_USB0_EP9_TXMAXP 0xFFCC1190 /* USB0 EPn Transmit Maximum Packet Length Register */
|
|
#define REG_USB0_EP10_TXMAXP 0xFFCC11A0 /* USB0 EPn Transmit Maximum Packet Length Register */
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#define REG_USB0_EP11_TXMAXP 0xFFCC11B0 /* USB0 EPn Transmit Maximum Packet Length Register */
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|
#define REG_USB0_EP0_CSR0_H 0xFFCC1102 /* USB0 EP0 Configuration and Status (Host) Register */
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|
#define REG_USB0_EP0_TXCSR_H 0xFFCC1102 /* USB0 EPn Transmit Configuration and Status (Host) Register */
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|
#define REG_USB0_EP1_TXCSR_H 0xFFCC1112 /* USB0 EPn Transmit Configuration and Status (Host) Register */
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|
#define REG_USB0_EP2_TXCSR_H 0xFFCC1122 /* USB0 EPn Transmit Configuration and Status (Host) Register */
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|
#define REG_USB0_EP3_TXCSR_H 0xFFCC1132 /* USB0 EPn Transmit Configuration and Status (Host) Register */
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|
#define REG_USB0_EP4_TXCSR_H 0xFFCC1142 /* USB0 EPn Transmit Configuration and Status (Host) Register */
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|
#define REG_USB0_EP5_TXCSR_H 0xFFCC1152 /* USB0 EPn Transmit Configuration and Status (Host) Register */
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|
#define REG_USB0_EP6_TXCSR_H 0xFFCC1162 /* USB0 EPn Transmit Configuration and Status (Host) Register */
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|
#define REG_USB0_EP7_TXCSR_H 0xFFCC1172 /* USB0 EPn Transmit Configuration and Status (Host) Register */
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|
#define REG_USB0_EP8_TXCSR_H 0xFFCC1182 /* USB0 EPn Transmit Configuration and Status (Host) Register */
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|
#define REG_USB0_EP9_TXCSR_H 0xFFCC1192 /* USB0 EPn Transmit Configuration and Status (Host) Register */
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|
#define REG_USB0_EP10_TXCSR_H 0xFFCC11A2 /* USB0 EPn Transmit Configuration and Status (Host) Register */
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|
#define REG_USB0_EP11_TXCSR_H 0xFFCC11B2 /* USB0 EPn Transmit Configuration and Status (Host) Register */
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|
#define REG_USB0_EP0_CSR0_P 0xFFCC1102 /* USB0 EP0 Configuration and Status (Peripheral) Register */
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|
#define REG_USB0_EP0_TXCSR_P 0xFFCC1102 /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
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|
#define REG_USB0_EP1_TXCSR_P 0xFFCC1112 /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
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|
#define REG_USB0_EP2_TXCSR_P 0xFFCC1122 /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
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|
#define REG_USB0_EP3_TXCSR_P 0xFFCC1132 /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
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|
#define REG_USB0_EP4_TXCSR_P 0xFFCC1142 /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
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|
#define REG_USB0_EP5_TXCSR_P 0xFFCC1152 /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
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|
#define REG_USB0_EP6_TXCSR_P 0xFFCC1162 /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
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|
#define REG_USB0_EP7_TXCSR_P 0xFFCC1172 /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
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|
#define REG_USB0_EP8_TXCSR_P 0xFFCC1182 /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
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|
#define REG_USB0_EP9_TXCSR_P 0xFFCC1192 /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
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|
#define REG_USB0_EP10_TXCSR_P 0xFFCC11A2 /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
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|
#define REG_USB0_EP11_TXCSR_P 0xFFCC11B2 /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
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#define REG_USB0_EP0_RXMAXP 0xFFCC1104 /* USB0 EPn Receive Maximum Packet Length Register */
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|
#define REG_USB0_EP1_RXMAXP 0xFFCC1114 /* USB0 EPn Receive Maximum Packet Length Register */
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|
#define REG_USB0_EP2_RXMAXP 0xFFCC1124 /* USB0 EPn Receive Maximum Packet Length Register */
|
|
#define REG_USB0_EP3_RXMAXP 0xFFCC1134 /* USB0 EPn Receive Maximum Packet Length Register */
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|
#define REG_USB0_EP4_RXMAXP 0xFFCC1144 /* USB0 EPn Receive Maximum Packet Length Register */
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|
#define REG_USB0_EP5_RXMAXP 0xFFCC1154 /* USB0 EPn Receive Maximum Packet Length Register */
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|
#define REG_USB0_EP6_RXMAXP 0xFFCC1164 /* USB0 EPn Receive Maximum Packet Length Register */
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|
#define REG_USB0_EP7_RXMAXP 0xFFCC1174 /* USB0 EPn Receive Maximum Packet Length Register */
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|
#define REG_USB0_EP8_RXMAXP 0xFFCC1184 /* USB0 EPn Receive Maximum Packet Length Register */
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|
#define REG_USB0_EP9_RXMAXP 0xFFCC1194 /* USB0 EPn Receive Maximum Packet Length Register */
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|
#define REG_USB0_EP10_RXMAXP 0xFFCC11A4 /* USB0 EPn Receive Maximum Packet Length Register */
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|
#define REG_USB0_EP11_RXMAXP 0xFFCC11B4 /* USB0 EPn Receive Maximum Packet Length Register */
|
|
#define REG_USB0_EP0_RXCSR_H 0xFFCC1106 /* USB0 EPn Receive Configuration and Status (Host) Register */
|
|
#define REG_USB0_EP1_RXCSR_H 0xFFCC1116 /* USB0 EPn Receive Configuration and Status (Host) Register */
|
|
#define REG_USB0_EP2_RXCSR_H 0xFFCC1126 /* USB0 EPn Receive Configuration and Status (Host) Register */
|
|
#define REG_USB0_EP3_RXCSR_H 0xFFCC1136 /* USB0 EPn Receive Configuration and Status (Host) Register */
|
|
#define REG_USB0_EP4_RXCSR_H 0xFFCC1146 /* USB0 EPn Receive Configuration and Status (Host) Register */
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|
#define REG_USB0_EP5_RXCSR_H 0xFFCC1156 /* USB0 EPn Receive Configuration and Status (Host) Register */
|
|
#define REG_USB0_EP6_RXCSR_H 0xFFCC1166 /* USB0 EPn Receive Configuration and Status (Host) Register */
|
|
#define REG_USB0_EP7_RXCSR_H 0xFFCC1176 /* USB0 EPn Receive Configuration and Status (Host) Register */
|
|
#define REG_USB0_EP8_RXCSR_H 0xFFCC1186 /* USB0 EPn Receive Configuration and Status (Host) Register */
|
|
#define REG_USB0_EP9_RXCSR_H 0xFFCC1196 /* USB0 EPn Receive Configuration and Status (Host) Register */
|
|
#define REG_USB0_EP10_RXCSR_H 0xFFCC11A6 /* USB0 EPn Receive Configuration and Status (Host) Register */
|
|
#define REG_USB0_EP11_RXCSR_H 0xFFCC11B6 /* USB0 EPn Receive Configuration and Status (Host) Register */
|
|
#define REG_USB0_EP0_RXCSR_P 0xFFCC1106 /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
|
|
#define REG_USB0_EP1_RXCSR_P 0xFFCC1116 /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
|
|
#define REG_USB0_EP2_RXCSR_P 0xFFCC1126 /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
|
|
#define REG_USB0_EP3_RXCSR_P 0xFFCC1136 /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
|
|
#define REG_USB0_EP4_RXCSR_P 0xFFCC1146 /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
|
|
#define REG_USB0_EP5_RXCSR_P 0xFFCC1156 /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
|
|
#define REG_USB0_EP6_RXCSR_P 0xFFCC1166 /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
|
|
#define REG_USB0_EP7_RXCSR_P 0xFFCC1176 /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
|
|
#define REG_USB0_EP8_RXCSR_P 0xFFCC1186 /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
|
|
#define REG_USB0_EP9_RXCSR_P 0xFFCC1196 /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
|
|
#define REG_USB0_EP10_RXCSR_P 0xFFCC11A6 /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
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|
#define REG_USB0_EP11_RXCSR_P 0xFFCC11B6 /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
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#define REG_USB0_EP0_CNT0 0xFFCC1108 /* USB0 EP0 Number of Received Bytes Register */
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|
#define REG_USB0_EP0_RXCNT 0xFFCC1108 /* USB0 EPn Number of Bytes Received Register */
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|
#define REG_USB0_EP1_RXCNT 0xFFCC1118 /* USB0 EPn Number of Bytes Received Register */
|
|
#define REG_USB0_EP2_RXCNT 0xFFCC1128 /* USB0 EPn Number of Bytes Received Register */
|
|
#define REG_USB0_EP3_RXCNT 0xFFCC1138 /* USB0 EPn Number of Bytes Received Register */
|
|
#define REG_USB0_EP4_RXCNT 0xFFCC1148 /* USB0 EPn Number of Bytes Received Register */
|
|
#define REG_USB0_EP5_RXCNT 0xFFCC1158 /* USB0 EPn Number of Bytes Received Register */
|
|
#define REG_USB0_EP6_RXCNT 0xFFCC1168 /* USB0 EPn Number of Bytes Received Register */
|
|
#define REG_USB0_EP7_RXCNT 0xFFCC1178 /* USB0 EPn Number of Bytes Received Register */
|
|
#define REG_USB0_EP8_RXCNT 0xFFCC1188 /* USB0 EPn Number of Bytes Received Register */
|
|
#define REG_USB0_EP9_RXCNT 0xFFCC1198 /* USB0 EPn Number of Bytes Received Register */
|
|
#define REG_USB0_EP10_RXCNT 0xFFCC11A8 /* USB0 EPn Number of Bytes Received Register */
|
|
#define REG_USB0_EP11_RXCNT 0xFFCC11B8 /* USB0 EPn Number of Bytes Received Register */
|
|
#define REG_USB0_EP0_TYPE0 0xFFCC110A /* USB0 EP0 Connection Type Register */
|
|
#define REG_USB0_EP0_TXTYPE 0xFFCC110A /* USB0 EPn Transmit Type Register */
|
|
#define REG_USB0_EP1_TXTYPE 0xFFCC111A /* USB0 EPn Transmit Type Register */
|
|
#define REG_USB0_EP2_TXTYPE 0xFFCC112A /* USB0 EPn Transmit Type Register */
|
|
#define REG_USB0_EP3_TXTYPE 0xFFCC113A /* USB0 EPn Transmit Type Register */
|
|
#define REG_USB0_EP4_TXTYPE 0xFFCC114A /* USB0 EPn Transmit Type Register */
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|
#define REG_USB0_EP5_TXTYPE 0xFFCC115A /* USB0 EPn Transmit Type Register */
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|
#define REG_USB0_EP6_TXTYPE 0xFFCC116A /* USB0 EPn Transmit Type Register */
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|
#define REG_USB0_EP7_TXTYPE 0xFFCC117A /* USB0 EPn Transmit Type Register */
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|
#define REG_USB0_EP8_TXTYPE 0xFFCC118A /* USB0 EPn Transmit Type Register */
|
|
#define REG_USB0_EP9_TXTYPE 0xFFCC119A /* USB0 EPn Transmit Type Register */
|
|
#define REG_USB0_EP10_TXTYPE 0xFFCC11AA /* USB0 EPn Transmit Type Register */
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|
#define REG_USB0_EP11_TXTYPE 0xFFCC11BA /* USB0 EPn Transmit Type Register */
|
|
#define REG_USB0_EP0_NAKLIMIT0 0xFFCC110B /* USB0 EP0 NAK Limit Register */
|
|
#define REG_USB0_EP0_TXINTERVAL 0xFFCC110B /* USB0 EPn Transmit Polling Interval Register */
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|
#define REG_USB0_EP1_TXINTERVAL 0xFFCC111B /* USB0 EPn Transmit Polling Interval Register */
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|
#define REG_USB0_EP2_TXINTERVAL 0xFFCC112B /* USB0 EPn Transmit Polling Interval Register */
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#define REG_USB0_EP3_TXINTERVAL 0xFFCC113B /* USB0 EPn Transmit Polling Interval Register */
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#define REG_USB0_EP4_TXINTERVAL 0xFFCC114B /* USB0 EPn Transmit Polling Interval Register */
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#define REG_USB0_EP5_TXINTERVAL 0xFFCC115B /* USB0 EPn Transmit Polling Interval Register */
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#define REG_USB0_EP6_TXINTERVAL 0xFFCC116B /* USB0 EPn Transmit Polling Interval Register */
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#define REG_USB0_EP7_TXINTERVAL 0xFFCC117B /* USB0 EPn Transmit Polling Interval Register */
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#define REG_USB0_EP8_TXINTERVAL 0xFFCC118B /* USB0 EPn Transmit Polling Interval Register */
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#define REG_USB0_EP9_TXINTERVAL 0xFFCC119B /* USB0 EPn Transmit Polling Interval Register */
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#define REG_USB0_EP10_TXINTERVAL 0xFFCC11AB /* USB0 EPn Transmit Polling Interval Register */
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#define REG_USB0_EP11_TXINTERVAL 0xFFCC11BB /* USB0 EPn Transmit Polling Interval Register */
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#define REG_USB0_EP0_RXTYPE 0xFFCC110C /* USB0 EPn Receive Type Register */
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#define REG_USB0_EP1_RXTYPE 0xFFCC111C /* USB0 EPn Receive Type Register */
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#define REG_USB0_EP2_RXTYPE 0xFFCC112C /* USB0 EPn Receive Type Register */
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#define REG_USB0_EP3_RXTYPE 0xFFCC113C /* USB0 EPn Receive Type Register */
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#define REG_USB0_EP4_RXTYPE 0xFFCC114C /* USB0 EPn Receive Type Register */
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#define REG_USB0_EP5_RXTYPE 0xFFCC115C /* USB0 EPn Receive Type Register */
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#define REG_USB0_EP6_RXTYPE 0xFFCC116C /* USB0 EPn Receive Type Register */
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|
#define REG_USB0_EP7_RXTYPE 0xFFCC117C /* USB0 EPn Receive Type Register */
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#define REG_USB0_EP8_RXTYPE 0xFFCC118C /* USB0 EPn Receive Type Register */
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#define REG_USB0_EP9_RXTYPE 0xFFCC119C /* USB0 EPn Receive Type Register */
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#define REG_USB0_EP10_RXTYPE 0xFFCC11AC /* USB0 EPn Receive Type Register */
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#define REG_USB0_EP11_RXTYPE 0xFFCC11BC /* USB0 EPn Receive Type Register */
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#define REG_USB0_EP0_RXINTERVAL 0xFFCC110D /* USB0 EPn Receive Polling Interval Register */
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#define REG_USB0_EP1_RXINTERVAL 0xFFCC111D /* USB0 EPn Receive Polling Interval Register */
|
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#define REG_USB0_EP2_RXINTERVAL 0xFFCC112D /* USB0 EPn Receive Polling Interval Register */
|
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#define REG_USB0_EP3_RXINTERVAL 0xFFCC113D /* USB0 EPn Receive Polling Interval Register */
|
|
#define REG_USB0_EP4_RXINTERVAL 0xFFCC114D /* USB0 EPn Receive Polling Interval Register */
|
|
#define REG_USB0_EP5_RXINTERVAL 0xFFCC115D /* USB0 EPn Receive Polling Interval Register */
|
|
#define REG_USB0_EP6_RXINTERVAL 0xFFCC116D /* USB0 EPn Receive Polling Interval Register */
|
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#define REG_USB0_EP7_RXINTERVAL 0xFFCC117D /* USB0 EPn Receive Polling Interval Register */
|
|
#define REG_USB0_EP8_RXINTERVAL 0xFFCC118D /* USB0 EPn Receive Polling Interval Register */
|
|
#define REG_USB0_EP9_RXINTERVAL 0xFFCC119D /* USB0 EPn Receive Polling Interval Register */
|
|
#define REG_USB0_EP10_RXINTERVAL 0xFFCC11AD /* USB0 EPn Receive Polling Interval Register */
|
|
#define REG_USB0_EP11_RXINTERVAL 0xFFCC11BD /* USB0 EPn Receive Polling Interval Register */
|
|
#define REG_USB0_EP0_CFGDATA0 0xFFCC110F /* USB0 EP0 Configuration Information Register */
|
|
#define REG_USB0_DMA_IRQ 0xFFCC1200 /* USB0 DMA Interrupt Register */
|
|
#define REG_USB0_DMA0_CTL 0xFFCC1204 /* USB0 DMA Channel n Control Register */
|
|
#define REG_USB0_DMA1_CTL 0xFFCC1214 /* USB0 DMA Channel n Control Register */
|
|
#define REG_USB0_DMA2_CTL 0xFFCC1224 /* USB0 DMA Channel n Control Register */
|
|
#define REG_USB0_DMA3_CTL 0xFFCC1234 /* USB0 DMA Channel n Control Register */
|
|
#define REG_USB0_DMA4_CTL 0xFFCC1244 /* USB0 DMA Channel n Control Register */
|
|
#define REG_USB0_DMA5_CTL 0xFFCC1254 /* USB0 DMA Channel n Control Register */
|
|
#define REG_USB0_DMA6_CTL 0xFFCC1264 /* USB0 DMA Channel n Control Register */
|
|
#define REG_USB0_DMA7_CTL 0xFFCC1274 /* USB0 DMA Channel n Control Register */
|
|
#define REG_USB0_DMA0_ADDR 0xFFCC1208 /* USB0 DMA Channel n Address Register */
|
|
#define REG_USB0_DMA1_ADDR 0xFFCC1218 /* USB0 DMA Channel n Address Register */
|
|
#define REG_USB0_DMA2_ADDR 0xFFCC1228 /* USB0 DMA Channel n Address Register */
|
|
#define REG_USB0_DMA3_ADDR 0xFFCC1238 /* USB0 DMA Channel n Address Register */
|
|
#define REG_USB0_DMA4_ADDR 0xFFCC1248 /* USB0 DMA Channel n Address Register */
|
|
#define REG_USB0_DMA5_ADDR 0xFFCC1258 /* USB0 DMA Channel n Address Register */
|
|
#define REG_USB0_DMA6_ADDR 0xFFCC1268 /* USB0 DMA Channel n Address Register */
|
|
#define REG_USB0_DMA7_ADDR 0xFFCC1278 /* USB0 DMA Channel n Address Register */
|
|
#define REG_USB0_DMA0_CNT 0xFFCC120C /* USB0 DMA Channel n Count Register */
|
|
#define REG_USB0_DMA1_CNT 0xFFCC121C /* USB0 DMA Channel n Count Register */
|
|
#define REG_USB0_DMA2_CNT 0xFFCC122C /* USB0 DMA Channel n Count Register */
|
|
#define REG_USB0_DMA3_CNT 0xFFCC123C /* USB0 DMA Channel n Count Register */
|
|
#define REG_USB0_DMA4_CNT 0xFFCC124C /* USB0 DMA Channel n Count Register */
|
|
#define REG_USB0_DMA5_CNT 0xFFCC125C /* USB0 DMA Channel n Count Register */
|
|
#define REG_USB0_DMA6_CNT 0xFFCC126C /* USB0 DMA Channel n Count Register */
|
|
#define REG_USB0_DMA7_CNT 0xFFCC127C /* USB0 DMA Channel n Count Register */
|
|
#define REG_USB0_RQPKTCNT0 0xFFCC1300 /* USB0 EPn Request Packet Count Register */
|
|
#define REG_USB0_RQPKTCNT1 0xFFCC1304 /* USB0 EPn Request Packet Count Register */
|
|
#define REG_USB0_RQPKTCNT2 0xFFCC1308 /* USB0 EPn Request Packet Count Register */
|
|
#define REG_USB0_RQPKTCNT3 0xFFCC130C /* USB0 EPn Request Packet Count Register */
|
|
#define REG_USB0_RQPKTCNT4 0xFFCC1310 /* USB0 EPn Request Packet Count Register */
|
|
#define REG_USB0_RQPKTCNT5 0xFFCC1314 /* USB0 EPn Request Packet Count Register */
|
|
#define REG_USB0_RQPKTCNT6 0xFFCC1318 /* USB0 EPn Request Packet Count Register */
|
|
#define REG_USB0_RQPKTCNT7 0xFFCC131C /* USB0 EPn Request Packet Count Register */
|
|
#define REG_USB0_RQPKTCNT8 0xFFCC1320 /* USB0 EPn Request Packet Count Register */
|
|
#define REG_USB0_RQPKTCNT9 0xFFCC1324 /* USB0 EPn Request Packet Count Register */
|
|
#define REG_USB0_RQPKTCNT10 0xFFCC1328 /* USB0 EPn Request Packet Count Register */
|
|
#define REG_USB0_CT_UCH 0xFFCC1344 /* USB0 Chirp Timeout Register */
|
|
#define REG_USB0_CT_HHSRTN 0xFFCC1346 /* USB0 Host High Speed Return to Normal Register */
|
|
#define REG_USB0_CT_HSBT 0xFFCC1348 /* USB0 High Speed Timeout Register */
|
|
#define REG_USB0_LPM_ATTR 0xFFCC1360 /* USB0 LPM Attribute Register */
|
|
#define REG_USB0_LPM_CTL 0xFFCC1362 /* USB0 LPM Control Register */
|
|
#define REG_USB0_LPM_IEN 0xFFCC1363 /* USB0 LPM Interrupt Enable Register */
|
|
#define REG_USB0_LPM_IRQ 0xFFCC1364 /* USB0 LPM Interrupt Status Register */
|
|
#define REG_USB0_LPM_FADDR 0xFFCC1365 /* USB0 LPM Function Address Register */
|
|
#define REG_USB0_VBUS_CTL 0xFFCC1380 /* USB0 VBUS Control Register */
|
|
#define REG_USB0_BAT_CHG 0xFFCC1381 /* USB0 Battery Charging Control Register */
|
|
#define REG_USB0_PHY_CTL 0xFFCC1394 /* USB0 PHY Control Register */
|
|
#define REG_USB0_PLL_OSC 0xFFCC1398 /* USB0 PLL and Oscillator Control Register */
|
|
|
|
/* =========================
|
|
USB
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_FADDR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_FADDR_VALUE 0 /* Function Address Value */
|
|
#define BITM_USB_FADDR_VALUE (_ADI_MSK(0x0000007F,uint8_t)) /* Function Address Value */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_POWER Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_POWER_ISOUPDT 7 /* ISO Update Enable */
|
|
#define BITP_USB_POWER_SOFTCONN 6 /* Soft Connect/Disconnect Enable */
|
|
#define BITP_USB_POWER_HSEN 5 /* High Speed Mode Enable */
|
|
#define BITP_USB_POWER_HSMODE 4 /* High Speed Mode */
|
|
#define BITP_USB_POWER_RESET 3 /* Reset USB */
|
|
#define BITP_USB_POWER_RESUME 2 /* Resume Mode */
|
|
#define BITP_USB_POWER_SUSPEND 1 /* Suspend Mode */
|
|
#define BITP_USB_POWER_SUSEN 0 /* SUSPENDM Output Enable */
|
|
|
|
#define BITM_USB_POWER_ISOUPDT (_ADI_MSK(0x00000080,uint8_t)) /* ISO Update Enable */
|
|
#define ENUM_USB_POWER_NO_ISOUPDT (_ADI_MSK(0x00000000,uint8_t)) /* ISOUPDT: Disable ISO Update */
|
|
#define ENUM_USB_POWER_ISOUPDT (_ADI_MSK(0x00000080,uint8_t)) /* ISOUPDT: Enable ISO Update */
|
|
|
|
#define BITM_USB_POWER_SOFTCONN (_ADI_MSK(0x00000040,uint8_t)) /* Soft Connect/Disconnect Enable */
|
|
#define ENUM_USB_POWER_NO_SOFTCONN (_ADI_MSK(0x00000000,uint8_t)) /* SOFTCONN: Disable Soft Connect/Disconnect */
|
|
#define ENUM_USB_POWER_SOFTCONN (_ADI_MSK(0x00000040,uint8_t)) /* SOFTCONN: Enable Soft Connect/Disconnect */
|
|
|
|
#define BITM_USB_POWER_HSEN (_ADI_MSK(0x00000020,uint8_t)) /* High Speed Mode Enable */
|
|
#define ENUM_USB_POWER_HSDIS (_ADI_MSK(0x00000000,uint8_t)) /* HSEN: Disable Negotiation for HS Mode */
|
|
#define ENUM_USB_POWER_HSEN (_ADI_MSK(0x00000020,uint8_t)) /* HSEN: Enable Negotiation for HS Mode */
|
|
|
|
#define BITM_USB_POWER_HSMODE (_ADI_MSK(0x00000010,uint8_t)) /* High Speed Mode */
|
|
#define ENUM_USB_POWER_NO_HSMODE (_ADI_MSK(0x00000000,uint8_t)) /* HSMODE: Full Speed Mode (HS fail during reset) */
|
|
#define ENUM_USB_POWER_HSMODE (_ADI_MSK(0x00000010,uint8_t)) /* HSMODE: High Speed Mode (HS success during reset) */
|
|
|
|
#define BITM_USB_POWER_RESET (_ADI_MSK(0x00000008,uint8_t)) /* Reset USB */
|
|
#define ENUM_USB_POWER_NO_RESET (_ADI_MSK(0x00000000,uint8_t)) /* RESET: No Reset */
|
|
#define ENUM_USB_POWER_RESET (_ADI_MSK(0x00000008,uint8_t)) /* RESET: Reset USB */
|
|
|
|
#define BITM_USB_POWER_RESUME (_ADI_MSK(0x00000004,uint8_t)) /* Resume Mode */
|
|
#define ENUM_USB_POWER_NO_RESUME (_ADI_MSK(0x00000000,uint8_t)) /* RESUME: Disable Resume Signaling */
|
|
#define ENUM_USB_POWER_RESUME (_ADI_MSK(0x00000004,uint8_t)) /* RESUME: Enable Resume Signaling */
|
|
|
|
#define BITM_USB_POWER_SUSPEND (_ADI_MSK(0x00000002,uint8_t)) /* Suspend Mode */
|
|
#define ENUM_USB_POWER_NO_SUSPEND (_ADI_MSK(0x00000000,uint8_t)) /* SUSPEND: Disable Suspend Mode (Host) */
|
|
#define ENUM_USB_POWER_SUSPEND (_ADI_MSK(0x00000002,uint8_t)) /* SUSPEND: Enable Suspend Mode (Host) */
|
|
|
|
#define BITM_USB_POWER_SUSEN (_ADI_MSK(0x00000001,uint8_t)) /* SUSPENDM Output Enable */
|
|
#define ENUM_USB_POWER_SUSDIS (_ADI_MSK(0x00000000,uint8_t)) /* SUSEN: Disable SUSPENDM Output */
|
|
#define ENUM_USB_POWER_SUSEN (_ADI_MSK(0x00000001,uint8_t)) /* SUSEN: Enable SUSPENDM Output */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_INTRTX Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_INTRTX_EP11 11 /* End Point 11 Tx Interrupt */
|
|
#define BITP_USB_INTRTX_EP10 10 /* End Point 10 Tx Interrupt */
|
|
#define BITP_USB_INTRTX_EP9 9 /* End Point 9 Tx Interrupt */
|
|
#define BITP_USB_INTRTX_EP8 8 /* End Point 8 Tx Interrupt */
|
|
#define BITP_USB_INTRTX_EP7 7 /* End Point 7 Tx Interrupt */
|
|
#define BITP_USB_INTRTX_EP6 6 /* End Point 6 Tx Interrupt */
|
|
#define BITP_USB_INTRTX_EP5 5 /* End Point 5 Tx Interrupt */
|
|
#define BITP_USB_INTRTX_EP4 4 /* End Point 4 Tx Interrupt */
|
|
#define BITP_USB_INTRTX_EP3 3 /* End Point 3 Tx Interrupt */
|
|
#define BITP_USB_INTRTX_EP2 2 /* End Point 2 Tx Interrupt */
|
|
#define BITP_USB_INTRTX_EP1 1 /* End Point 1 Tx Interrupt */
|
|
#define BITP_USB_INTRTX_EP0 0 /* End Point 0 Tx Interrupt */
|
|
#define BITM_USB_INTRTX_EP11 (_ADI_MSK(0x00000800,uint16_t)) /* End Point 11 Tx Interrupt */
|
|
#define BITM_USB_INTRTX_EP10 (_ADI_MSK(0x00000400,uint16_t)) /* End Point 10 Tx Interrupt */
|
|
#define BITM_USB_INTRTX_EP9 (_ADI_MSK(0x00000200,uint16_t)) /* End Point 9 Tx Interrupt */
|
|
#define BITM_USB_INTRTX_EP8 (_ADI_MSK(0x00000100,uint16_t)) /* End Point 8 Tx Interrupt */
|
|
#define BITM_USB_INTRTX_EP7 (_ADI_MSK(0x00000080,uint16_t)) /* End Point 7 Tx Interrupt */
|
|
#define BITM_USB_INTRTX_EP6 (_ADI_MSK(0x00000040,uint16_t)) /* End Point 6 Tx Interrupt */
|
|
#define BITM_USB_INTRTX_EP5 (_ADI_MSK(0x00000020,uint16_t)) /* End Point 5 Tx Interrupt */
|
|
#define BITM_USB_INTRTX_EP4 (_ADI_MSK(0x00000010,uint16_t)) /* End Point 4 Tx Interrupt */
|
|
#define BITM_USB_INTRTX_EP3 (_ADI_MSK(0x00000008,uint16_t)) /* End Point 3 Tx Interrupt */
|
|
#define BITM_USB_INTRTX_EP2 (_ADI_MSK(0x00000004,uint16_t)) /* End Point 2 Tx Interrupt */
|
|
#define BITM_USB_INTRTX_EP1 (_ADI_MSK(0x00000002,uint16_t)) /* End Point 1 Tx Interrupt */
|
|
#define BITM_USB_INTRTX_EP0 (_ADI_MSK(0x00000001,uint16_t)) /* End Point 0 Tx Interrupt */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_INTRRX Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_INTRRX_EP11 11 /* End Point 11 Rx Interrupt. */
|
|
#define BITP_USB_INTRRX_EP10 10 /* End Point 10 Rx Interrupt. */
|
|
#define BITP_USB_INTRRX_EP9 9 /* End Point 9 Rx Interrupt. */
|
|
#define BITP_USB_INTRRX_EP8 8 /* End Point 8 Rx Interrupt. */
|
|
#define BITP_USB_INTRRX_EP7 7 /* End Point 7 Rx Interrupt. */
|
|
#define BITP_USB_INTRRX_EP6 6 /* End Point 6 Rx Interrupt. */
|
|
#define BITP_USB_INTRRX_EP5 5 /* End Point 5 Rx Interrupt. */
|
|
#define BITP_USB_INTRRX_EP4 4 /* End Point 4 Rx Interrupt. */
|
|
#define BITP_USB_INTRRX_EP3 3 /* End Point 3 Rx Interrupt. */
|
|
#define BITP_USB_INTRRX_EP2 2 /* End Point 2 Rx Interrupt. */
|
|
#define BITP_USB_INTRRX_EP1 1 /* End Point 1 Rx Interrupt. */
|
|
#define BITM_USB_INTRRX_EP11 (_ADI_MSK(0x00000800,uint16_t)) /* End Point 11 Rx Interrupt. */
|
|
#define BITM_USB_INTRRX_EP10 (_ADI_MSK(0x00000400,uint16_t)) /* End Point 10 Rx Interrupt. */
|
|
#define BITM_USB_INTRRX_EP9 (_ADI_MSK(0x00000200,uint16_t)) /* End Point 9 Rx Interrupt. */
|
|
#define BITM_USB_INTRRX_EP8 (_ADI_MSK(0x00000100,uint16_t)) /* End Point 8 Rx Interrupt. */
|
|
#define BITM_USB_INTRRX_EP7 (_ADI_MSK(0x00000080,uint16_t)) /* End Point 7 Rx Interrupt. */
|
|
#define BITM_USB_INTRRX_EP6 (_ADI_MSK(0x00000040,uint16_t)) /* End Point 6 Rx Interrupt. */
|
|
#define BITM_USB_INTRRX_EP5 (_ADI_MSK(0x00000020,uint16_t)) /* End Point 5 Rx Interrupt. */
|
|
#define BITM_USB_INTRRX_EP4 (_ADI_MSK(0x00000010,uint16_t)) /* End Point 4 Rx Interrupt. */
|
|
#define BITM_USB_INTRRX_EP3 (_ADI_MSK(0x00000008,uint16_t)) /* End Point 3 Rx Interrupt. */
|
|
#define BITM_USB_INTRRX_EP2 (_ADI_MSK(0x00000004,uint16_t)) /* End Point 2 Rx Interrupt. */
|
|
#define BITM_USB_INTRRX_EP1 (_ADI_MSK(0x00000002,uint16_t)) /* End Point 1 Rx Interrupt. */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_INTRTXE Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_INTRTXE_EP11 11 /* End Point 11 Tx Interrupt Enable */
|
|
#define BITP_USB_INTRTXE_EP10 10 /* End Point 10 Tx Interrupt Enable */
|
|
#define BITP_USB_INTRTXE_EP9 9 /* End Point 9 Tx Interrupt Enable */
|
|
#define BITP_USB_INTRTXE_EP8 8 /* End Point 8 Tx Interrupt Enable */
|
|
#define BITP_USB_INTRTXE_EP7 7 /* End Point 7 Tx Interrupt Enable */
|
|
#define BITP_USB_INTRTXE_EP6 6 /* End Point 6 Tx Interrupt Enable */
|
|
#define BITP_USB_INTRTXE_EP5 5 /* End Point 5 Tx Interrupt Enable */
|
|
#define BITP_USB_INTRTXE_EP4 4 /* End Point 4 Tx Interrupt Enable */
|
|
#define BITP_USB_INTRTXE_EP3 3 /* End Point 3 Tx Interrupt Enable */
|
|
#define BITP_USB_INTRTXE_EP2 2 /* End Point 2 Tx Interrupt Enable */
|
|
#define BITP_USB_INTRTXE_EP1 1 /* End Point 1 Tx Interrupt Enable */
|
|
#define BITP_USB_INTRTXE_EP0 0 /* End Point 0 Tx Interrupt Enable */
|
|
#define BITM_USB_INTRTXE_EP11 (_ADI_MSK(0x00000800,uint16_t)) /* End Point 11 Tx Interrupt Enable */
|
|
#define BITM_USB_INTRTXE_EP10 (_ADI_MSK(0x00000400,uint16_t)) /* End Point 10 Tx Interrupt Enable */
|
|
#define BITM_USB_INTRTXE_EP9 (_ADI_MSK(0x00000200,uint16_t)) /* End Point 9 Tx Interrupt Enable */
|
|
#define BITM_USB_INTRTXE_EP8 (_ADI_MSK(0x00000100,uint16_t)) /* End Point 8 Tx Interrupt Enable */
|
|
#define BITM_USB_INTRTXE_EP7 (_ADI_MSK(0x00000080,uint16_t)) /* End Point 7 Tx Interrupt Enable */
|
|
#define BITM_USB_INTRTXE_EP6 (_ADI_MSK(0x00000040,uint16_t)) /* End Point 6 Tx Interrupt Enable */
|
|
#define BITM_USB_INTRTXE_EP5 (_ADI_MSK(0x00000020,uint16_t)) /* End Point 5 Tx Interrupt Enable */
|
|
#define BITM_USB_INTRTXE_EP4 (_ADI_MSK(0x00000010,uint16_t)) /* End Point 4 Tx Interrupt Enable */
|
|
#define BITM_USB_INTRTXE_EP3 (_ADI_MSK(0x00000008,uint16_t)) /* End Point 3 Tx Interrupt Enable */
|
|
#define BITM_USB_INTRTXE_EP2 (_ADI_MSK(0x00000004,uint16_t)) /* End Point 2 Tx Interrupt Enable */
|
|
#define BITM_USB_INTRTXE_EP1 (_ADI_MSK(0x00000002,uint16_t)) /* End Point 1 Tx Interrupt Enable */
|
|
#define BITM_USB_INTRTXE_EP0 (_ADI_MSK(0x00000001,uint16_t)) /* End Point 0 Tx Interrupt Enable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_INTRRXE Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_INTRRXE_EP11 11 /* End Point 11 Rx Interrupt Enable */
|
|
#define BITP_USB_INTRRXE_EP10 10 /* End Point 10 Rx Interrupt Enable */
|
|
#define BITP_USB_INTRRXE_EP9 9 /* End Point 9 Rx Interrupt Enable */
|
|
#define BITP_USB_INTRRXE_EP8 8 /* End Point 8 Rx Interrupt Enable */
|
|
#define BITP_USB_INTRRXE_EP7 7 /* End Point 7 Rx Interrupt Enable */
|
|
#define BITP_USB_INTRRXE_EP6 6 /* End Point 6 Rx Interrupt Enable */
|
|
#define BITP_USB_INTRRXE_EP5 5 /* End Point 5 Rx Interrupt Enable */
|
|
#define BITP_USB_INTRRXE_EP4 4 /* End Point 4 Rx Interrupt Enable */
|
|
#define BITP_USB_INTRRXE_EP3 3 /* End Point 3 Rx Interrupt Enable */
|
|
#define BITP_USB_INTRRXE_EP2 2 /* End Point 2 Rx Interrupt Enable */
|
|
#define BITP_USB_INTRRXE_EP1 1 /* End Point 1 Rx Interrupt Enable */
|
|
#define BITM_USB_INTRRXE_EP11 (_ADI_MSK(0x00000800,uint16_t)) /* End Point 11 Rx Interrupt Enable */
|
|
#define BITM_USB_INTRRXE_EP10 (_ADI_MSK(0x00000400,uint16_t)) /* End Point 10 Rx Interrupt Enable */
|
|
#define BITM_USB_INTRRXE_EP9 (_ADI_MSK(0x00000200,uint16_t)) /* End Point 9 Rx Interrupt Enable */
|
|
#define BITM_USB_INTRRXE_EP8 (_ADI_MSK(0x00000100,uint16_t)) /* End Point 8 Rx Interrupt Enable */
|
|
#define BITM_USB_INTRRXE_EP7 (_ADI_MSK(0x00000080,uint16_t)) /* End Point 7 Rx Interrupt Enable */
|
|
#define BITM_USB_INTRRXE_EP6 (_ADI_MSK(0x00000040,uint16_t)) /* End Point 6 Rx Interrupt Enable */
|
|
#define BITM_USB_INTRRXE_EP5 (_ADI_MSK(0x00000020,uint16_t)) /* End Point 5 Rx Interrupt Enable */
|
|
#define BITM_USB_INTRRXE_EP4 (_ADI_MSK(0x00000010,uint16_t)) /* End Point 4 Rx Interrupt Enable */
|
|
#define BITM_USB_INTRRXE_EP3 (_ADI_MSK(0x00000008,uint16_t)) /* End Point 3 Rx Interrupt Enable */
|
|
#define BITM_USB_INTRRXE_EP2 (_ADI_MSK(0x00000004,uint16_t)) /* End Point 2 Rx Interrupt Enable */
|
|
#define BITM_USB_INTRRXE_EP1 (_ADI_MSK(0x00000002,uint16_t)) /* End Point 1 Rx Interrupt Enable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_IRQ Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_IRQ_VBUSERR 7 /* VBUS Threshold Indicator */
|
|
#define BITP_USB_IRQ_SESSREQ 6 /* Session Request Indicator */
|
|
#define BITP_USB_IRQ_DISCON 5 /* Disconnect Indicator */
|
|
#define BITP_USB_IRQ_CON 4 /* Connection Indicator */
|
|
#define BITP_USB_IRQ_SOF 3 /* Start-of-frame Indicator */
|
|
#define BITP_USB_IRQ_RSTBABBLE 2 /* Reset/Babble Indicator */
|
|
#define BITP_USB_IRQ_RESUME 1 /* Resume Indicator */
|
|
#define BITP_USB_IRQ_SUSPEND 0 /* Suspend Indicator */
|
|
|
|
#define BITM_USB_IRQ_VBUSERR (_ADI_MSK(0x00000080,uint8_t)) /* VBUS Threshold Indicator */
|
|
#define ENUM_USB_IRQ_NO_VBUSERR (_ADI_MSK(0x00000000,uint8_t)) /* VBUSERR: No Interrupt */
|
|
#define ENUM_USB_IRQ_VBUSERR (_ADI_MSK(0x00000080,uint8_t)) /* VBUSERR: Interrupt Pending */
|
|
|
|
#define BITM_USB_IRQ_SESSREQ (_ADI_MSK(0x00000040,uint8_t)) /* Session Request Indicator */
|
|
#define ENUM_USB_IRQ_NO_SESSREQ (_ADI_MSK(0x00000000,uint8_t)) /* SESSREQ: No Interrupt */
|
|
#define ENUM_USB_IRQ_SESSREQ (_ADI_MSK(0x00000040,uint8_t)) /* SESSREQ: Interrupt Pending */
|
|
|
|
#define BITM_USB_IRQ_DISCON (_ADI_MSK(0x00000020,uint8_t)) /* Disconnect Indicator */
|
|
#define ENUM_USB_IRQ_NO_DISCON (_ADI_MSK(0x00000000,uint8_t)) /* DISCON: No Interrupt */
|
|
#define ENUM_USB_IRQ_DISCON (_ADI_MSK(0x00000020,uint8_t)) /* DISCON: Interrupt Pending */
|
|
|
|
#define BITM_USB_IRQ_CON (_ADI_MSK(0x00000010,uint8_t)) /* Connection Indicator */
|
|
#define ENUM_USB_IRQ_NO_CON (_ADI_MSK(0x00000000,uint8_t)) /* CON: No Interrupt */
|
|
#define ENUM_USB_IRQ_CON (_ADI_MSK(0x00000010,uint8_t)) /* CON: Interrupt Pending */
|
|
|
|
#define BITM_USB_IRQ_SOF (_ADI_MSK(0x00000008,uint8_t)) /* Start-of-frame Indicator */
|
|
#define ENUM_USB_IRQ_NO_SOF (_ADI_MSK(0x00000000,uint8_t)) /* SOF: No Interrupt */
|
|
#define ENUM_USB_IRQ_SOF (_ADI_MSK(0x00000008,uint8_t)) /* SOF: Interrupt Pending */
|
|
|
|
#define BITM_USB_IRQ_RSTBABBLE (_ADI_MSK(0x00000004,uint8_t)) /* Reset/Babble Indicator */
|
|
#define ENUM_USB_IRQ_NO_RSTBABBLE (_ADI_MSK(0x00000000,uint8_t)) /* RSTBABBLE: No Interrupt */
|
|
#define ENUM_USB_IRQ_RSTBABBLE (_ADI_MSK(0x00000004,uint8_t)) /* RSTBABBLE: Interrupt Pending */
|
|
|
|
#define BITM_USB_IRQ_RESUME (_ADI_MSK(0x00000002,uint8_t)) /* Resume Indicator */
|
|
#define ENUM_USB_IRQ_NO_RESUME (_ADI_MSK(0x00000000,uint8_t)) /* RESUME: No Interrupt */
|
|
#define ENUM_USB_IRQ_RESUME (_ADI_MSK(0x00000002,uint8_t)) /* RESUME: Interrupt Pending */
|
|
|
|
#define BITM_USB_IRQ_SUSPEND (_ADI_MSK(0x00000001,uint8_t)) /* Suspend Indicator */
|
|
#define ENUM_USB_IRQ_NO_SUSPEND (_ADI_MSK(0x00000000,uint8_t)) /* SUSPEND: No Interrupt */
|
|
#define ENUM_USB_IRQ_SUSPEND (_ADI_MSK(0x00000001,uint8_t)) /* SUSPEND: Interrupt Pending */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_IEN Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_IEN_VBUSERR 7 /* VBUS Threshold Indicator Interrupt Enable */
|
|
#define BITP_USB_IEN_SESSREQ 6 /* Session Request Indicator Interrupt Enable */
|
|
#define BITP_USB_IEN_DISCON 5 /* Disconnect Indicator Interrupt Enable */
|
|
#define BITP_USB_IEN_CON 4 /* Connection Indicator Interrupt Enable */
|
|
#define BITP_USB_IEN_SOF 3 /* Start-of-frame Indicator Interrupt Enable */
|
|
#define BITP_USB_IEN_RSTBABBLE 2 /* Reset/Babble Indicator Interrupt Enable */
|
|
#define BITP_USB_IEN_RESUME 1 /* Resume Indicator Interrupt Enable */
|
|
#define BITP_USB_IEN_SUSPEND 0 /* Suspend Indicator Interrupt Enable */
|
|
|
|
#define BITM_USB_IEN_VBUSERR (_ADI_MSK(0x00000080,uint8_t)) /* VBUS Threshold Indicator Interrupt Enable */
|
|
#define ENUM_USB_IEN_VBUSERRDIS (_ADI_MSK(0x00000000,uint8_t)) /* VBUSERR: Disable Interrupt */
|
|
#define ENUM_USB_IEN_VBUSERREN (_ADI_MSK(0x00000080,uint8_t)) /* VBUSERR: Enable Interrupt */
|
|
|
|
#define BITM_USB_IEN_SESSREQ (_ADI_MSK(0x00000040,uint8_t)) /* Session Request Indicator Interrupt Enable */
|
|
#define ENUM_USB_IEN_SESSREQDIS (_ADI_MSK(0x00000000,uint8_t)) /* SESSREQ: Disable Interrupt */
|
|
#define ENUM_USB_IEN_SESSREQEN (_ADI_MSK(0x00000040,uint8_t)) /* SESSREQ: Enable Interrupt */
|
|
|
|
#define BITM_USB_IEN_DISCON (_ADI_MSK(0x00000020,uint8_t)) /* Disconnect Indicator Interrupt Enable */
|
|
#define ENUM_USB_IEN_DISCONDIS (_ADI_MSK(0x00000000,uint8_t)) /* DISCON: Disable Interrupt */
|
|
#define ENUM_USB_IEN_DISCONEN (_ADI_MSK(0x00000020,uint8_t)) /* DISCON: Enable Interrupt */
|
|
|
|
#define BITM_USB_IEN_CON (_ADI_MSK(0x00000010,uint8_t)) /* Connection Indicator Interrupt Enable */
|
|
#define ENUM_USB_IEN_CONDIS (_ADI_MSK(0x00000000,uint8_t)) /* CON: Disable Interrupt */
|
|
#define ENUM_USB_IEN_CONEN (_ADI_MSK(0x00000010,uint8_t)) /* CON: Enable Interrupt */
|
|
|
|
#define BITM_USB_IEN_SOF (_ADI_MSK(0x00000008,uint8_t)) /* Start-of-frame Indicator Interrupt Enable */
|
|
#define ENUM_USB_IEN_SOFDIS (_ADI_MSK(0x00000000,uint8_t)) /* SOF: Disable Interrupt */
|
|
#define ENUM_USB_IEN_SOFEN (_ADI_MSK(0x00000008,uint8_t)) /* SOF: Enable Interrupt */
|
|
|
|
#define BITM_USB_IEN_RSTBABBLE (_ADI_MSK(0x00000004,uint8_t)) /* Reset/Babble Indicator Interrupt Enable */
|
|
#define ENUM_USB_IEN_RSTBABBLEDIS (_ADI_MSK(0x00000000,uint8_t)) /* RSTBABBLE: Disable Interrupt */
|
|
#define ENUM_USB_IEN_RSTBABBLEEN (_ADI_MSK(0x00000004,uint8_t)) /* RSTBABBLE: Enable Interrupt */
|
|
|
|
#define BITM_USB_IEN_RESUME (_ADI_MSK(0x00000002,uint8_t)) /* Resume Indicator Interrupt Enable */
|
|
#define ENUM_USB_IEN_RESUMEDIS (_ADI_MSK(0x00000000,uint8_t)) /* RESUME: Disable Interrupt */
|
|
#define ENUM_USB_IEN_RESUMEEN (_ADI_MSK(0x00000002,uint8_t)) /* RESUME: Enable Interrupt */
|
|
|
|
#define BITM_USB_IEN_SUSPEND (_ADI_MSK(0x00000001,uint8_t)) /* Suspend Indicator Interrupt Enable */
|
|
#define ENUM_USB_IEN_SUSPENDDIS (_ADI_MSK(0x00000000,uint8_t)) /* SUSPEND: Disable Interrupt */
|
|
#define ENUM_USB_IEN_SUSPENDEN (_ADI_MSK(0x00000001,uint8_t)) /* SUSPEND: Enable Interrupt */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_FRAME Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_FRAME_VALUE 0 /* Frame Number Value */
|
|
#define BITM_USB_FRAME_VALUE (_ADI_MSK(0x000007FF,uint16_t)) /* Frame Number Value */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_INDEX Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_INDEX_EP 0 /* Endpoint Index */
|
|
#define BITM_USB_INDEX_EP (_ADI_MSK(0x0000000F,uint8_t)) /* Endpoint Index */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_TESTMODE Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_TESTMODE_FIFOACCESS 6 /* FIFO Access */
|
|
#define BITP_USB_TESTMODE_TESTPACKET 3 /* Test_Packet Mode */
|
|
#define BITP_USB_TESTMODE_TESTK 2 /* Test_K Mode */
|
|
#define BITP_USB_TESTMODE_TESTJ 1 /* Test_J Mode */
|
|
#define BITP_USB_TESTMODE_TESTSE0NAK 0 /* Test SE0 NAK */
|
|
#define BITM_USB_TESTMODE_FIFOACCESS (_ADI_MSK(0x00000040,uint8_t)) /* FIFO Access */
|
|
#define BITM_USB_TESTMODE_TESTPACKET (_ADI_MSK(0x00000008,uint8_t)) /* Test_Packet Mode */
|
|
#define BITM_USB_TESTMODE_TESTK (_ADI_MSK(0x00000004,uint8_t)) /* Test_K Mode */
|
|
#define BITM_USB_TESTMODE_TESTJ (_ADI_MSK(0x00000002,uint8_t)) /* Test_J Mode */
|
|
#define BITM_USB_TESTMODE_TESTSE0NAK (_ADI_MSK(0x00000001,uint8_t)) /* Test SE0 NAK */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_EPI_TXMAXP Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_EPI_TXMAXP_MULTM1 11 /* Multi-Packets per Micro-frame */
|
|
#define BITP_USB_EPI_TXMAXP_MAXPAY 0 /* Maximum Payload */
|
|
#define BITM_USB_EPI_TXMAXP_MULTM1 (_ADI_MSK(0x00001800,uint16_t)) /* Multi-Packets per Micro-frame */
|
|
#define BITM_USB_EPI_TXMAXP_MAXPAY (_ADI_MSK(0x000007FF,uint16_t)) /* Maximum Payload */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_EPI_TXCSR_P Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_EPI_TXCSR_P_AUTOSET 15 /* TxPkRdy Autoset Enable */
|
|
#define BITP_USB_EPI_TXCSR_P_ISO 14 /* Isochronous Transfers Enable */
|
|
#define BITP_USB_EPI_TXCSR_P_DMAREQEN 12 /* DMA Request Enable Tx EP */
|
|
#define BITP_USB_EPI_TXCSR_P_FRCDATATGL 11 /* Force Data Toggle */
|
|
#define BITP_USB_EPI_TXCSR_P_DMAREQMODE 10 /* DMA Mode Select */
|
|
#define BITP_USB_EPI_TXCSR_P_INCOMPTX 7 /* Incomplete Tx */
|
|
#define BITP_USB_EPI_TXCSR_P_CLRDATATGL 6 /* Clear Endpoint Data Toggle */
|
|
#define BITP_USB_EPI_TXCSR_P_SENTSTALL 5 /* Sent STALL */
|
|
#define BITP_USB_EPI_TXCSR_P_SENDSTALL 4 /* Send STALL */
|
|
#define BITP_USB_EPI_TXCSR_P_FLUSHFIFO 3 /* Flush Endpoint FIFO */
|
|
#define BITP_USB_EPI_TXCSR_P_URUNERR 2 /* Underrun Error */
|
|
#define BITP_USB_EPI_TXCSR_P_NEFIFO 1 /* Not Empty FIFO */
|
|
#define BITP_USB_EPI_TXCSR_P_TXPKTRDY 0 /* Tx Packet Ready */
|
|
|
|
#define BITM_USB_EPI_TXCSR_P_AUTOSET (_ADI_MSK(0x00008000,uint16_t)) /* TxPkRdy Autoset Enable */
|
|
#define ENUM_USB_EPI_TXCSR_P_NO_AUTOSET (_ADI_MSK(0x00000000,uint16_t)) /* AUTOSET: Disable Autoset */
|
|
#define ENUM_USB_EPI_TXCSR_P_AUTOSET (_ADI_MSK(0x00008000,uint16_t)) /* AUTOSET: Enable Autoset */
|
|
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#define BITM_USB_EPI_TXCSR_P_ISO (_ADI_MSK(0x00004000,uint16_t)) /* Isochronous Transfers Enable */
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#define ENUM_USB_EPI_TXCSR_P_ISODIS (_ADI_MSK(0x00000000,uint16_t)) /* ISO: Disable Tx EP Isochronous Transfers */
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#define ENUM_USB_EPI_TXCSR_P_ISOEN (_ADI_MSK(0x00004000,uint16_t)) /* ISO: Enable Tx EP Isochronous Transfers */
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#define BITM_USB_EPI_TXCSR_P_DMAREQEN (_ADI_MSK(0x00001000,uint16_t)) /* DMA Request Enable Tx EP */
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#define ENUM_USB_EPI_TXCSR_P_DMAREQDIS (_ADI_MSK(0x00000000,uint16_t)) /* DMAREQEN: Disable DMA Request */
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#define ENUM_USB_EPI_TXCSR_P_DMAREQEN (_ADI_MSK(0x00001000,uint16_t)) /* DMAREQEN: Enable DMA Request */
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#define BITM_USB_EPI_TXCSR_P_FRCDATATGL (_ADI_MSK(0x00000800,uint16_t)) /* Force Data Toggle */
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#define ENUM_USB_EPI_TXCSR_P_NO_FRCTGL (_ADI_MSK(0x00000000,uint16_t)) /* FRCDATATGL: No Action */
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#define ENUM_USB_EPI_TXCSR_P_FRCTGL (_ADI_MSK(0x00000800,uint16_t)) /* FRCDATATGL: Toggle Endpoint Data */
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#define BITM_USB_EPI_TXCSR_P_DMAREQMODE (_ADI_MSK(0x00000400,uint16_t)) /* DMA Mode Select */
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#define ENUM_USB_EPI_TXCSR_P_DMARQMODE0 (_ADI_MSK(0x00000000,uint16_t)) /* DMAREQMODE: DMA Request Mode 0 */
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#define ENUM_USB_EPI_TXCSR_P_DMARQMODE1 (_ADI_MSK(0x00000400,uint16_t)) /* DMAREQMODE: DMA Request Mode 1 */
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#define BITM_USB_EPI_TXCSR_P_INCOMPTX (_ADI_MSK(0x00000080,uint16_t)) /* Incomplete Tx */
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#define ENUM_USB_EPI_TXCSR_P_NO_INCOMP (_ADI_MSK(0x00000000,uint16_t)) /* INCOMPTX: No Status */
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#define ENUM_USB_EPI_TXCSR_P_INCOMP (_ADI_MSK(0x00000080,uint16_t)) /* INCOMPTX: Incomplete Tx (Insufficient IN Tokens) */
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#define BITM_USB_EPI_TXCSR_P_CLRDATATGL (_ADI_MSK(0x00000040,uint16_t)) /* Clear Endpoint Data Toggle */
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#define ENUM_USB_EPI_TXCSR_P_NO_CLRTGL (_ADI_MSK(0x00000000,uint16_t)) /* CLRDATATGL: No Action */
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#define ENUM_USB_EPI_TXCSR_P_CLRTGL (_ADI_MSK(0x00000040,uint16_t)) /* CLRDATATGL: Reset EP Data Toggle to 0 */
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#define BITM_USB_EPI_TXCSR_P_SENTSTALL (_ADI_MSK(0x00000020,uint16_t)) /* Sent STALL */
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#define ENUM_USB_EPI_TXCSR_P_NO_STALSNT (_ADI_MSK(0x00000000,uint16_t)) /* SENTSTALL: No Status */
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#define ENUM_USB_EPI_TXCSR_P_STALSNT (_ADI_MSK(0x00000020,uint16_t)) /* SENTSTALL: STALL Handshake Transmitted */
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#define BITM_USB_EPI_TXCSR_P_SENDSTALL (_ADI_MSK(0x00000010,uint16_t)) /* Send STALL */
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#define ENUM_USB_EPI_TXCSR_P_NO_STALL (_ADI_MSK(0x00000000,uint16_t)) /* SENDSTALL: No Request */
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#define ENUM_USB_EPI_TXCSR_P_STALL (_ADI_MSK(0x00000010,uint16_t)) /* SENDSTALL: Request STALL Handshake Transmission */
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#define BITM_USB_EPI_TXCSR_P_FLUSHFIFO (_ADI_MSK(0x00000008,uint16_t)) /* Flush Endpoint FIFO */
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#define ENUM_USB_EPI_TXCSR_P_NO_FLUSH (_ADI_MSK(0x00000000,uint16_t)) /* FLUSHFIFO: No Flush */
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#define ENUM_USB_EPI_TXCSR_P_FLUSH (_ADI_MSK(0x00000008,uint16_t)) /* FLUSHFIFO: Flush endpoint FIFO */
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#define BITM_USB_EPI_TXCSR_P_URUNERR (_ADI_MSK(0x00000004,uint16_t)) /* Underrun Error */
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#define ENUM_USB_EPI_TXCSR_P_NO_URUNERR (_ADI_MSK(0x00000000,uint16_t)) /* URUNERR: No Status */
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#define ENUM_USB_EPI_TXCSR_P_URUNERR (_ADI_MSK(0x00000004,uint16_t)) /* URUNERR: Underrun Error */
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#define BITM_USB_EPI_TXCSR_P_NEFIFO (_ADI_MSK(0x00000002,uint16_t)) /* Not Empty FIFO */
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#define ENUM_USB_EPI_TXCSR_P_NO_FIFONE (_ADI_MSK(0x00000000,uint16_t)) /* NEFIFO: FIFO Empty */
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#define ENUM_USB_EPI_TXCSR_P_FIFONE (_ADI_MSK(0x00000002,uint16_t)) /* NEFIFO: FIFO Not Empty */
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#define BITM_USB_EPI_TXCSR_P_TXPKTRDY (_ADI_MSK(0x00000001,uint16_t)) /* Tx Packet Ready */
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#define ENUM_USB_EPI_TXCSR_P_NO_PKTRDY (_ADI_MSK(0x00000000,uint16_t)) /* TXPKTRDY: No Tx Packet */
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#define ENUM_USB_EPI_TXCSR_P_PKTRDY (_ADI_MSK(0x00000001,uint16_t)) /* TXPKTRDY: Tx Packet in Endpoint FIFO */
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/* ------------------------------------------------------------------------------------------------------------------------
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USB_EPI_TXCSR_H Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_USB_EPI_TXCSR_H_AUTOSET 15 /* TxPkRdy Autoset Enable */
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#define BITP_USB_EPI_TXCSR_H_DMAREQEN 12 /* DMA Request Enable Tx EP */
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#define BITP_USB_EPI_TXCSR_H_FRCDATATGL 11 /* Force Data Toggle */
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#define BITP_USB_EPI_TXCSR_H_DMAREQMODE 10 /* DMA Mode Select */
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#define BITP_USB_EPI_TXCSR_H_DATGLEN 9 /* Data Toggle Write Enable */
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#define BITP_USB_EPI_TXCSR_H_DATGL 8 /* Data Toggle */
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#define BITP_USB_EPI_TXCSR_H_NAKTOINCMP 7 /* NAK Timeout Incomplete */
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#define BITP_USB_EPI_TXCSR_H_CLRDATATGL 6 /* Clear Endpoint Data Toggle */
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#define BITP_USB_EPI_TXCSR_H_RXSTALL 5 /* Rx STALL */
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#define BITP_USB_EPI_TXCSR_H_SETUPPKT 4 /* Setup Packet */
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#define BITP_USB_EPI_TXCSR_H_FLUSHFIFO 3 /* Flush Endpoint FIFO */
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#define BITP_USB_EPI_TXCSR_H_TXTOERR 2 /* Tx Timeout Error */
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#define BITP_USB_EPI_TXCSR_H_NEFIFO 1 /* Not Empty FIFO */
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#define BITP_USB_EPI_TXCSR_H_TXPKTRDY 0 /* Tx Packet Ready */
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#define BITM_USB_EPI_TXCSR_H_AUTOSET (_ADI_MSK(0x00008000,uint16_t)) /* TxPkRdy Autoset Enable */
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#define ENUM_USB_EPI_TXCSR_H_NO_AUTOSET (_ADI_MSK(0x00000000,uint16_t)) /* AUTOSET: Disable Autoset */
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#define ENUM_USB_EPI_TXCSR_H_AUTOSET (_ADI_MSK(0x00008000,uint16_t)) /* AUTOSET: Enable Autoset */
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#define BITM_USB_EPI_TXCSR_H_DMAREQEN (_ADI_MSK(0x00001000,uint16_t)) /* DMA Request Enable Tx EP */
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#define ENUM_USB_EPI_TXCSR_H_DMAREQDIS (_ADI_MSK(0x00000000,uint16_t)) /* DMAREQEN: Disable DMA Request */
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#define ENUM_USB_EPI_TXCSR_H_DMAREQEN (_ADI_MSK(0x00001000,uint16_t)) /* DMAREQEN: Enable DMA Request */
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#define BITM_USB_EPI_TXCSR_H_FRCDATATGL (_ADI_MSK(0x00000800,uint16_t)) /* Force Data Toggle */
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#define ENUM_USB_EPI_TXCSR_H_NO_FRCTGL (_ADI_MSK(0x00000000,uint16_t)) /* FRCDATATGL: No Action */
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#define ENUM_USB_EPI_TXCSR_H_FRCTGL (_ADI_MSK(0x00000800,uint16_t)) /* FRCDATATGL: Toggle Endpoint Data */
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#define BITM_USB_EPI_TXCSR_H_DMAREQMODE (_ADI_MSK(0x00000400,uint16_t)) /* DMA Mode Select */
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#define ENUM_USB_EPI_TXCSR_H_DMARQMODE0 (_ADI_MSK(0x00000000,uint16_t)) /* DMAREQMODE: DMA Request Mode 0 */
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#define ENUM_USB_EPI_TXCSR_H_DMARQMODE1 (_ADI_MSK(0x00000400,uint16_t)) /* DMAREQMODE: DMA Request Mode 1 */
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#define BITM_USB_EPI_TXCSR_H_DATGLEN (_ADI_MSK(0x00000200,uint16_t)) /* Data Toggle Write Enable */
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#define ENUM_USB_EPI_TXCSR_H_NO_DATGLEN (_ADI_MSK(0x00000000,uint16_t)) /* DATGLEN: Disable Write to DATGL */
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#define ENUM_USB_EPI_TXCSR_H_DATGLEN (_ADI_MSK(0x00000200,uint16_t)) /* DATGLEN: Enable Write to DATGL */
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#define BITM_USB_EPI_TXCSR_H_DATGL (_ADI_MSK(0x00000100,uint16_t)) /* Data Toggle */
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#define ENUM_USB_EPI_TXCSR_H_NO_DATGL (_ADI_MSK(0x00000000,uint16_t)) /* DATGL: DATA0 is set */
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#define ENUM_USB_EPI_TXCSR_H_DATGL (_ADI_MSK(0x00000100,uint16_t)) /* DATGL: DATA1 is set */
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#define BITM_USB_EPI_TXCSR_H_NAKTOINCMP (_ADI_MSK(0x00000080,uint16_t)) /* NAK Timeout Incomplete */
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#define ENUM_USB_EPI_TXCSR_H_NO_NAKTO (_ADI_MSK(0x00000000,uint16_t)) /* NAKTOINCMP: No Status */
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#define ENUM_USB_EPI_TXCSR_H_NAKTO (_ADI_MSK(0x00000080,uint16_t)) /* NAKTOINCMP: NAK Timeout Over Maximum */
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#define BITM_USB_EPI_TXCSR_H_CLRDATATGL (_ADI_MSK(0x00000040,uint16_t)) /* Clear Endpoint Data Toggle */
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#define ENUM_USB_EPI_TXCSR_H_NO_CLRTGL (_ADI_MSK(0x00000000,uint16_t)) /* CLRDATATGL: No Action */
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#define ENUM_USB_EPI_TXCSR_H_CLRTGL (_ADI_MSK(0x00000040,uint16_t)) /* CLRDATATGL: Reset EP Data Toggle to 0 */
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#define BITM_USB_EPI_TXCSR_H_RXSTALL (_ADI_MSK(0x00000020,uint16_t)) /* Rx STALL */
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#define ENUM_USB_EPI_TXCSR_H_NO_RXSTALL (_ADI_MSK(0x00000000,uint16_t)) /* RXSTALL: No Status */
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#define ENUM_USB_EPI_TXCSR_H_RXSTALL (_ADI_MSK(0x00000020,uint16_t)) /* RXSTALL: Stall Received from Device */
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#define BITM_USB_EPI_TXCSR_H_SETUPPKT (_ADI_MSK(0x00000010,uint16_t)) /* Setup Packet */
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#define ENUM_USB_EPI_TXCSR_H_NO_SETUPPK (_ADI_MSK(0x00000000,uint16_t)) /* SETUPPKT: No Request */
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#define ENUM_USB_EPI_TXCSR_H_SETUPPKT (_ADI_MSK(0x00000010,uint16_t)) /* SETUPPKT: Send SETUP Token */
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#define BITM_USB_EPI_TXCSR_H_FLUSHFIFO (_ADI_MSK(0x00000008,uint16_t)) /* Flush Endpoint FIFO */
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#define ENUM_USB_EPI_TXCSR_H_NO_FLUSH (_ADI_MSK(0x00000000,uint16_t)) /* FLUSHFIFO: No Flush */
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#define ENUM_USB_EPI_TXCSR_H_FLUSH (_ADI_MSK(0x00000008,uint16_t)) /* FLUSHFIFO: Flush endpoint FIFO */
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#define BITM_USB_EPI_TXCSR_H_TXTOERR (_ADI_MSK(0x00000004,uint16_t)) /* Tx Timeout Error */
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#define ENUM_USB_EPI_TXCSR_H_NO_TXTOERR (_ADI_MSK(0x00000000,uint16_t)) /* TXTOERR: No Status */
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#define ENUM_USB_EPI_TXCSR_H_TXTOERR (_ADI_MSK(0x00000004,uint16_t)) /* TXTOERR: Tx Timeout Error */
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#define BITM_USB_EPI_TXCSR_H_NEFIFO (_ADI_MSK(0x00000002,uint16_t)) /* Not Empty FIFO */
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#define ENUM_USB_EPI_TXCSR_H_NO_NEFIFO (_ADI_MSK(0x00000000,uint16_t)) /* NEFIFO: FIFO Empty */
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#define ENUM_USB_EPI_TXCSR_H_NEFIFO (_ADI_MSK(0x00000002,uint16_t)) /* NEFIFO: FIFO Not Empty */
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#define BITM_USB_EPI_TXCSR_H_TXPKTRDY (_ADI_MSK(0x00000001,uint16_t)) /* Tx Packet Ready */
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#define ENUM_USB_EPI_TXCSR_H_NO_PKTRDY (_ADI_MSK(0x00000000,uint16_t)) /* TXPKTRDY: No Tx Packet */
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#define ENUM_USB_EPI_TXCSR_H_PKTRDY (_ADI_MSK(0x00000001,uint16_t)) /* TXPKTRDY: Tx Packet in Endpoint FIFO */
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/* ------------------------------------------------------------------------------------------------------------------------
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USB_EP0I_CSR_P Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_USB_EP0I_CSR_P_FLUSHFIFO 8 /* Flush Endpoint FIFO */
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#define BITP_USB_EP0I_CSR_P_SSETUPEND 7 /* Service Setup End */
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#define BITP_USB_EP0I_CSR_P_SPKTRDY 6 /* Service Rx Packet Ready */
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#define BITP_USB_EP0I_CSR_P_SENDSTALL 5 /* Send Stall */
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#define BITP_USB_EP0I_CSR_P_SETUPEND 4 /* Setup End */
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#define BITP_USB_EP0I_CSR_P_DATAEND 3 /* Data End */
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#define BITP_USB_EP0I_CSR_P_SENTSTALL 2 /* Sent Stall */
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#define BITP_USB_EP0I_CSR_P_TXPKTRDY 1 /* Tx Packet Ready */
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#define BITP_USB_EP0I_CSR_P_RXPKTRDY 0 /* Rx Packet Ready */
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#define BITM_USB_EP0I_CSR_P_FLUSHFIFO (_ADI_MSK(0x00000100,uint16_t)) /* Flush Endpoint FIFO */
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#define ENUM_USB_EP0I_CSR_P_NO_FLUSH (_ADI_MSK(0x00000000,uint16_t)) /* FLUSHFIFO: No Flush */
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#define ENUM_USB_EP0I_CSR_P_FLUSH (_ADI_MSK(0x00000100,uint16_t)) /* FLUSHFIFO: Flush Endpoint FIFO */
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#define BITM_USB_EP0I_CSR_P_SSETUPEND (_ADI_MSK(0x00000080,uint16_t)) /* Service Setup End */
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#define ENUM_USB_EP0I_CSR_P_NOSSETUPEND (_ADI_MSK(0x00000000,uint16_t)) /* SSETUPEND: No Action */
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#define ENUM_USB_EP0I_CSR_P_SSETUPEND (_ADI_MSK(0x00000080,uint16_t)) /* SSETUPEND: Clear SETUPEND Bit */
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#define BITM_USB_EP0I_CSR_P_SPKTRDY (_ADI_MSK(0x00000040,uint16_t)) /* Service Rx Packet Ready */
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#define ENUM_USB_EP0I_CSR_P_NO_SPKTRDY (_ADI_MSK(0x00000000,uint16_t)) /* SPKTRDY: No Action */
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#define ENUM_USB_EP0I_CSR_P_SPKTRDY (_ADI_MSK(0x00000040,uint16_t)) /* SPKTRDY: Clear RXPKTRDY Bit */
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#define BITM_USB_EP0I_CSR_P_SENDSTALL (_ADI_MSK(0x00000020,uint16_t)) /* Send Stall */
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#define ENUM_USB_EP0I_CSR_P_NO_STALL (_ADI_MSK(0x00000000,uint16_t)) /* SENDSTALL: No Action */
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#define ENUM_USB_EP0I_CSR_P_STALL (_ADI_MSK(0x00000020,uint16_t)) /* SENDSTALL: Terminate Current Transaction */
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#define BITM_USB_EP0I_CSR_P_SETUPEND (_ADI_MSK(0x00000010,uint16_t)) /* Setup End */
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#define ENUM_USB_EP0I_CSR_P_NO_SETUPEND (_ADI_MSK(0x00000000,uint16_t)) /* SETUPEND: No Status */
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#define ENUM_USB_EP0I_CSR_P_SETUPEND (_ADI_MSK(0x00000010,uint16_t)) /* SETUPEND: Setup Ended before DATAEND */
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#define BITM_USB_EP0I_CSR_P_DATAEND (_ADI_MSK(0x00000008,uint16_t)) /* Data End */
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#define ENUM_USB_EP0I_CSR_P_NO_DATAEND (_ADI_MSK(0x00000000,uint16_t)) /* DATAEND: No Status */
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#define ENUM_USB_EP0I_CSR_P_DATAEND (_ADI_MSK(0x00000008,uint16_t)) /* DATAEND: Data End Condition */
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#define BITM_USB_EP0I_CSR_P_SENTSTALL (_ADI_MSK(0x00000004,uint16_t)) /* Sent Stall */
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#define ENUM_USB_EP0I_CSR_P_NO_STALSNT (_ADI_MSK(0x00000000,uint16_t)) /* SENTSTALL: No Status */
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#define ENUM_USB_EP0I_CSR_P_STALSNT (_ADI_MSK(0x00000004,uint16_t)) /* SENTSTALL: Transmitted STALL Handshake */
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#define BITM_USB_EP0I_CSR_P_TXPKTRDY (_ADI_MSK(0x00000002,uint16_t)) /* Tx Packet Ready */
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#define ENUM_USB_EP0I_CSR_P_NO_TXPKTRDY (_ADI_MSK(0x00000000,uint16_t)) /* TXPKTRDY: */
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#define ENUM_USB_EP0I_CSR_P_TXPKTRDY (_ADI_MSK(0x00000002,uint16_t)) /* TXPKTRDY: Set this bit after loading a data packet into the FIFO */
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#define BITM_USB_EP0I_CSR_P_RXPKTRDY (_ADI_MSK(0x00000001,uint16_t)) /* Rx Packet Ready */
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#define ENUM_USB_EP0I_CSR_P_NO_PKTRDY (_ADI_MSK(0x00000000,uint16_t)) /* RXPKTRDY: No Rx Packet */
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#define ENUM_USB_EP0I_CSR_P_PKTRDY (_ADI_MSK(0x00000001,uint16_t)) /* RXPKTRDY: Rx Packet in Endpoint FIFO */
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/* ------------------------------------------------------------------------------------------------------------------------
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USB_EP0I_CSR_H Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_USB_EP0I_CSR_H_DISPING 11 /* Disable Ping */
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#define BITP_USB_EP0I_CSR_H_DATGLEN 10 /* Data Toggle Write Enable */
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#define BITP_USB_EP0I_CSR_H_DATGL 9 /* Data Toggle */
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#define BITP_USB_EP0I_CSR_H_FLUSHFIFO 8 /* Flush Endpoint FIFO */
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#define BITP_USB_EP0I_CSR_H_NAKTO 7 /* NAK Timeout */
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#define BITP_USB_EP0I_CSR_H_STATUSPKT 6 /* Status Packet */
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#define BITP_USB_EP0I_CSR_H_REQPKT 5 /* Request Packet */
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#define BITP_USB_EP0I_CSR_H_TOERR 4 /* Timeout Error */
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#define BITP_USB_EP0I_CSR_H_SETUPPKT 3 /* Setup Packet */
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#define BITP_USB_EP0I_CSR_H_RXSTALL 2 /* Rx Stall */
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#define BITP_USB_EP0I_CSR_H_TXPKTRDY 1 /* Tx Packet Ready */
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#define BITP_USB_EP0I_CSR_H_RXPKTRDY 0 /* Rx Packet Ready */
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#define BITM_USB_EP0I_CSR_H_DISPING (_ADI_MSK(0x00000800,uint16_t)) /* Disable Ping */
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#define ENUM_USB_EP0I_CSR_H_NO_DISPING (_ADI_MSK(0x00000000,uint16_t)) /* DISPING: Issue PING tokens */
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#define ENUM_USB_EP0I_CSR_H_DISPING (_ADI_MSK(0x00000800,uint16_t)) /* DISPING: Do not issue PING */
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#define BITM_USB_EP0I_CSR_H_DATGLEN (_ADI_MSK(0x00000400,uint16_t)) /* Data Toggle Write Enable */
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#define ENUM_USB_EP0I_CSR_H_NO_DATGLEN (_ADI_MSK(0x00000000,uint16_t)) /* DATGLEN: Disable Write to DATGL */
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#define ENUM_USB_EP0I_CSR_H_DATGLEN (_ADI_MSK(0x00000400,uint16_t)) /* DATGLEN: Enable Write to DATGL */
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#define BITM_USB_EP0I_CSR_H_DATGL (_ADI_MSK(0x00000200,uint16_t)) /* Data Toggle */
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#define ENUM_USB_EP0I_CSR_H_NO_DATATGL (_ADI_MSK(0x00000000,uint16_t)) /* DATGL: DATA0 is Set */
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#define ENUM_USB_EP0I_CSR_H_DATATGL (_ADI_MSK(0x00000200,uint16_t)) /* DATGL: DATA1 is Set */
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#define BITM_USB_EP0I_CSR_H_FLUSHFIFO (_ADI_MSK(0x00000100,uint16_t)) /* Flush Endpoint FIFO */
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#define ENUM_USB_EP0I_CSR_H_NO_FLUSH (_ADI_MSK(0x00000000,uint16_t)) /* FLUSHFIFO: No Flush */
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#define ENUM_USB_EP0I_CSR_H_FLUSH (_ADI_MSK(0x00000100,uint16_t)) /* FLUSHFIFO: Flush Endpoint FIFO */
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#define BITM_USB_EP0I_CSR_H_NAKTO (_ADI_MSK(0x00000080,uint16_t)) /* NAK Timeout */
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#define ENUM_USB_EP0I_CSR_H_NO_NAKTO (_ADI_MSK(0x00000000,uint16_t)) /* NAKTO: No Status */
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#define ENUM_USB_EP0I_CSR_H_NAKTO (_ADI_MSK(0x00000080,uint16_t)) /* NAKTO: Endpoint Halted (NAK Timeout) */
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#define BITM_USB_EP0I_CSR_H_STATUSPKT (_ADI_MSK(0x00000040,uint16_t)) /* Status Packet */
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#define ENUM_USB_EP0I_CSR_H_NO_STATPKT (_ADI_MSK(0x00000000,uint16_t)) /* STATUSPKT: No Request */
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#define ENUM_USB_EP0I_CSR_H_STATPKT (_ADI_MSK(0x00000040,uint16_t)) /* STATUSPKT: Request Status Transaction */
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#define BITM_USB_EP0I_CSR_H_REQPKT (_ADI_MSK(0x00000020,uint16_t)) /* Request Packet */
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#define ENUM_USB_EP0I_CSR_H_NO_REQPKT (_ADI_MSK(0x00000000,uint16_t)) /* REQPKT: No Request */
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#define ENUM_USB_EP0I_CSR_H_REQPKT (_ADI_MSK(0x00000020,uint16_t)) /* REQPKT: Send IN Tokens to Device */
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#define BITM_USB_EP0I_CSR_H_TOERR (_ADI_MSK(0x00000010,uint16_t)) /* Timeout Error */
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#define ENUM_USB_EP0I_CSR_H_NO_TOERR (_ADI_MSK(0x00000000,uint16_t)) /* TOERR: No Status */
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#define ENUM_USB_EP0I_CSR_H_TOERR (_ADI_MSK(0x00000010,uint16_t)) /* TOERR: Timeout Error */
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#define BITM_USB_EP0I_CSR_H_SETUPPKT (_ADI_MSK(0x00000008,uint16_t)) /* Setup Packet */
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#define ENUM_USB_EP0I_CSR_H_NO_SETUPPKT (_ADI_MSK(0x00000000,uint16_t)) /* SETUPPKT: No Request */
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#define ENUM_USB_EP0I_CSR_H_SETUPPKT (_ADI_MSK(0x00000008,uint16_t)) /* SETUPPKT: Send SETUP token */
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#define BITM_USB_EP0I_CSR_H_RXSTALL (_ADI_MSK(0x00000004,uint16_t)) /* Rx Stall */
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#define ENUM_USB_EP0I_CSR_H_NO_RXSTALL (_ADI_MSK(0x00000000,uint16_t)) /* RXSTALL: No Status */
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#define ENUM_USB_EP0I_CSR_H_RXSTALL (_ADI_MSK(0x00000004,uint16_t)) /* RXSTALL: Stall Received from Device */
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#define BITM_USB_EP0I_CSR_H_TXPKTRDY (_ADI_MSK(0x00000002,uint16_t)) /* Tx Packet Ready */
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#define ENUM_USB_EP0I_CSR_H_NO_TXPKTRDY (_ADI_MSK(0x00000000,uint16_t)) /* TXPKTRDY: No Tx Packet */
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#define ENUM_USB_EP0I_CSR_H_TXPKTRDY (_ADI_MSK(0x00000002,uint16_t)) /* TXPKTRDY: Tx Packet in Endpoint FIFO */
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#define BITM_USB_EP0I_CSR_H_RXPKTRDY (_ADI_MSK(0x00000001,uint16_t)) /* Rx Packet Ready */
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#define ENUM_USB_EP0I_CSR_H_NO_RXPKTRDY (_ADI_MSK(0x00000000,uint16_t)) /* RXPKTRDY: No Rx Packet */
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#define ENUM_USB_EP0I_CSR_H_RXPKTRDY (_ADI_MSK(0x00000001,uint16_t)) /* RXPKTRDY: Rx Packet in Endpoint FIFO */
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/* ------------------------------------------------------------------------------------------------------------------------
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USB_EPI_RXMAXP Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_USB_EPI_RXMAXP_MULTM1 11 /* Multi-Packets per Micro-frame */
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#define BITP_USB_EPI_RXMAXP_MAXPAY 0 /* Maximum Payload */
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#define BITM_USB_EPI_RXMAXP_MULTM1 (_ADI_MSK(0x00001800,uint16_t)) /* Multi-Packets per Micro-frame */
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#define BITM_USB_EPI_RXMAXP_MAXPAY (_ADI_MSK(0x000007FF,uint16_t)) /* Maximum Payload */
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/* ------------------------------------------------------------------------------------------------------------------------
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USB_EPI_RXCSR_H Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_USB_EPI_RXCSR_H_AUTOCLR 15 /* Auto Clear Enable */
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#define BITP_USB_EPI_RXCSR_H_AUTOREQ 14 /* Auto Request Clear Enable */
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#define BITP_USB_EPI_RXCSR_H_DMAREQEN 13 /* DMA Request Enable Rx EP */
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#define BITP_USB_EPI_RXCSR_H_PIDERR 12 /* Packet ID Error */
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#define BITP_USB_EPI_RXCSR_H_DMAREQMODE 11 /* DMA Mode Select */
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#define BITP_USB_EPI_RXCSR_H_DATGLEN 10 /* Data Toggle Write Enable */
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#define BITP_USB_EPI_RXCSR_H_DATGL 9 /* Data Toggle */
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#define BITP_USB_EPI_RXCSR_H_INCOMPRX 8 /* Incomplete Rx */
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#define BITP_USB_EPI_RXCSR_H_CLRDATATGL 7 /* Clear Endpoint Data Toggle */
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#define BITP_USB_EPI_RXCSR_H_RXSTALL 6 /* Rx STALL */
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#define BITP_USB_EPI_RXCSR_H_REQPKT 5 /* Request Packet */
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#define BITP_USB_EPI_RXCSR_H_FLUSHFIFO 4 /* Flush Endpoint FIFO */
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#define BITP_USB_EPI_RXCSR_H_NAKTODERR 3 /* NAK Timeout Data Error */
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#define BITP_USB_EPI_RXCSR_H_RXTOERR 2 /* Rx Timeout Error */
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#define BITP_USB_EPI_RXCSR_H_FIFOFULL 1 /* FIFO Full */
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#define BITP_USB_EPI_RXCSR_H_RXPKTRDY 0 /* Rx Packet Ready */
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#define BITM_USB_EPI_RXCSR_H_AUTOCLR (_ADI_MSK(0x00008000,uint16_t)) /* Auto Clear Enable */
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#define ENUM_USB_EPI_RXCSR_H_NO_AUTOCLR (_ADI_MSK(0x00000000,uint16_t)) /* AUTOCLR: Disable Auto Clear */
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#define ENUM_USB_EPI_RXCSR_H_AUTOCLR (_ADI_MSK(0x00008000,uint16_t)) /* AUTOCLR: Enable Auto Clear */
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#define BITM_USB_EPI_RXCSR_H_AUTOREQ (_ADI_MSK(0x00004000,uint16_t)) /* Auto Request Clear Enable */
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#define ENUM_USB_EPI_RXCSR_H_NO_AUTOREQ (_ADI_MSK(0x00000000,uint16_t)) /* AUTOREQ: Disable Auto Request Clear */
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#define ENUM_USB_EPI_RXCSR_H_AUTOREQ (_ADI_MSK(0x00004000,uint16_t)) /* AUTOREQ: Enable Auto Request Clear */
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#define BITM_USB_EPI_RXCSR_H_DMAREQEN (_ADI_MSK(0x00002000,uint16_t)) /* DMA Request Enable Rx EP */
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#define ENUM_USB_EPI_RXCSR_H_DMAREQDIS (_ADI_MSK(0x00000000,uint16_t)) /* DMAREQEN: Disable DMA Request */
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#define ENUM_USB_EPI_RXCSR_H_DMAREQEN (_ADI_MSK(0x00002000,uint16_t)) /* DMAREQEN: Enable DMA Request */
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#define BITM_USB_EPI_RXCSR_H_PIDERR (_ADI_MSK(0x00001000,uint16_t)) /* Packet ID Error */
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#define ENUM_USB_EPI_RXCSR_H_NO_PIDERR (_ADI_MSK(0x00000000,uint16_t)) /* PIDERR: No Status */
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#define ENUM_USB_EPI_RXCSR_H_PIDERR (_ADI_MSK(0x00001000,uint16_t)) /* PIDERR: PID Error */
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#define BITM_USB_EPI_RXCSR_H_DMAREQMODE (_ADI_MSK(0x00000800,uint16_t)) /* DMA Mode Select */
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#define ENUM_USB_EPI_RXCSR_H_DMARQMODE0 (_ADI_MSK(0x00000000,uint16_t)) /* DMAREQMODE: DMA Request Mode 0 */
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#define ENUM_USB_EPI_RXCSR_H_DMARQMODE1 (_ADI_MSK(0x00000800,uint16_t)) /* DMAREQMODE: DMA Request Mode 1 */
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#define BITM_USB_EPI_RXCSR_H_DATGLEN (_ADI_MSK(0x00000400,uint16_t)) /* Data Toggle Write Enable */
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#define ENUM_USB_EPI_RXCSR_H_DATGLDIS (_ADI_MSK(0x00000000,uint16_t)) /* DATGLEN: Disable Write to DATGL */
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#define ENUM_USB_EPI_RXCSR_H_DATGLEN (_ADI_MSK(0x00000400,uint16_t)) /* DATGLEN: Enable Write to DATGL */
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#define BITM_USB_EPI_RXCSR_H_DATGL (_ADI_MSK(0x00000200,uint16_t)) /* Data Toggle */
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#define ENUM_USB_EPI_RXCSR_H_NO_DATGL (_ADI_MSK(0x00000000,uint16_t)) /* DATGL: DATA0 is Set */
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#define ENUM_USB_EPI_RXCSR_H_DATGL (_ADI_MSK(0x00000200,uint16_t)) /* DATGL: DATA1 is Set */
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#define BITM_USB_EPI_RXCSR_H_INCOMPRX (_ADI_MSK(0x00000100,uint16_t)) /* Incomplete Rx */
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#define ENUM_USB_EPI_RXCSR_H_NO_INCOMP (_ADI_MSK(0x00000000,uint16_t)) /* INCOMPRX: No Status */
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#define ENUM_USB_EPI_RXCSR_H_INCOMP (_ADI_MSK(0x00000100,uint16_t)) /* INCOMPRX: Incomplete Rx */
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#define BITM_USB_EPI_RXCSR_H_CLRDATATGL (_ADI_MSK(0x00000080,uint16_t)) /* Clear Endpoint Data Toggle */
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#define ENUM_USB_EPI_RXCSR_H_NO_CLRTGL (_ADI_MSK(0x00000000,uint16_t)) /* CLRDATATGL: No Action */
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#define ENUM_USB_EPI_RXCSR_H_CLRTGL (_ADI_MSK(0x00000080,uint16_t)) /* CLRDATATGL: Reset EP Data Toggle to 0 */
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#define BITM_USB_EPI_RXCSR_H_RXSTALL (_ADI_MSK(0x00000040,uint16_t)) /* Rx STALL */
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#define ENUM_USB_EPI_RXCSR_H_NO_RXSTALL (_ADI_MSK(0x00000000,uint16_t)) /* RXSTALL: No Status */
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#define ENUM_USB_EPI_RXCSR_H_RXSTALL (_ADI_MSK(0x00000040,uint16_t)) /* RXSTALL: Stall Received from Device */
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#define BITM_USB_EPI_RXCSR_H_REQPKT (_ADI_MSK(0x00000020,uint16_t)) /* Request Packet */
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#define ENUM_USB_EPI_RXCSR_H_NO_REQPKT (_ADI_MSK(0x00000000,uint16_t)) /* REQPKT: No Request */
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#define ENUM_USB_EPI_RXCSR_H_REQPKT (_ADI_MSK(0x00000020,uint16_t)) /* REQPKT: Send IN Tokens to Device */
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#define BITM_USB_EPI_RXCSR_H_FLUSHFIFO (_ADI_MSK(0x00000010,uint16_t)) /* Flush Endpoint FIFO */
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#define ENUM_USB_EPI_RXCSR_H_NO_FLUSH (_ADI_MSK(0x00000000,uint16_t)) /* FLUSHFIFO: No Flush */
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#define ENUM_USB_EPI_RXCSR_H_FLUSH (_ADI_MSK(0x00000010,uint16_t)) /* FLUSHFIFO: Flush Endpoint FIFO */
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#define BITM_USB_EPI_RXCSR_H_NAKTODERR (_ADI_MSK(0x00000008,uint16_t)) /* NAK Timeout Data Error */
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#define ENUM_USB_EPI_RXCSR_H_NO_NAKTO (_ADI_MSK(0x00000000,uint16_t)) /* NAKTODERR: No Status */
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#define ENUM_USB_EPI_RXCSR_H_NAKTO (_ADI_MSK(0x00000008,uint16_t)) /* NAKTODERR: NAK Timeout Data Error */
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#define BITM_USB_EPI_RXCSR_H_RXTOERR (_ADI_MSK(0x00000004,uint16_t)) /* Rx Timeout Error */
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#define ENUM_USB_EPI_RXCSR_H_NO_RXTOERR (_ADI_MSK(0x00000000,uint16_t)) /* RXTOERR: No Status */
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#define ENUM_USB_EPI_RXCSR_H_RXTOERR (_ADI_MSK(0x00000004,uint16_t)) /* RXTOERR: Rx Timeout Error */
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#define BITM_USB_EPI_RXCSR_H_FIFOFULL (_ADI_MSK(0x00000002,uint16_t)) /* FIFO Full */
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#define ENUM_USB_EPI_RXCSR_H_NO_FIFOFUL (_ADI_MSK(0x00000000,uint16_t)) /* FIFOFULL: No Status */
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#define ENUM_USB_EPI_RXCSR_H_FIFOFUL (_ADI_MSK(0x00000002,uint16_t)) /* FIFOFULL: FIFO Full */
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#define BITM_USB_EPI_RXCSR_H_RXPKTRDY (_ADI_MSK(0x00000001,uint16_t)) /* Rx Packet Ready */
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#define ENUM_USB_EPI_RXCSR_H_NO_PKTRDY (_ADI_MSK(0x00000000,uint16_t)) /* RXPKTRDY: No Rx Packet */
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#define ENUM_USB_EPI_RXCSR_H_PKTRDY (_ADI_MSK(0x00000001,uint16_t)) /* RXPKTRDY: Rx Packet in Endpoint FIFO */
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/* ------------------------------------------------------------------------------------------------------------------------
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USB_EPI_RXCSR_P Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_USB_EPI_RXCSR_P_AUTOCLR 15 /* Auto Clear Enable */
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#define BITP_USB_EPI_RXCSR_P_ISO 14 /* Isochronous Transfers */
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#define BITP_USB_EPI_RXCSR_P_DMAREQEN 13 /* DMA Request Enable Rx EP */
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#define BITP_USB_EPI_RXCSR_P_DNYETPERR 12 /* Disable NYET Handshake */
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#define BITP_USB_EPI_RXCSR_P_DMAREQMODE 11 /* DMA Mode Select */
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#define BITP_USB_EPI_RXCSR_P_INCOMPRX 8 /* Incomplete Rx */
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#define BITP_USB_EPI_RXCSR_P_CLRDATATGL 7 /* Clear Endpoint Data Toggle */
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#define BITP_USB_EPI_RXCSR_P_SENTSTALL 6 /* Sent STALL */
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#define BITP_USB_EPI_RXCSR_P_SENDSTALL 5 /* Send STALL */
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#define BITP_USB_EPI_RXCSR_P_FLUSHFIFO 4 /* Flush Endpoint FIFO */
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#define BITP_USB_EPI_RXCSR_P_DATAERR 3 /* Data Error */
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#define BITP_USB_EPI_RXCSR_P_ORUNERR 2 /* OUT Run Error */
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#define BITP_USB_EPI_RXCSR_P_FIFOFULL 1 /* FIFO Full */
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#define BITP_USB_EPI_RXCSR_P_RXPKTRDY 0 /* Rx Packet Ready */
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#define BITM_USB_EPI_RXCSR_P_AUTOCLR (_ADI_MSK(0x00008000,uint16_t)) /* Auto Clear Enable */
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#define ENUM_USB_EPI_RXCSR_P_NO_AUTOCLR (_ADI_MSK(0x00000000,uint16_t)) /* AUTOCLR: Disable Auto Clear */
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#define ENUM_USB_EPI_RXCSR_P_AUTOCLR (_ADI_MSK(0x00008000,uint16_t)) /* AUTOCLR: Enable Auto Clear */
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#define BITM_USB_EPI_RXCSR_P_ISO (_ADI_MSK(0x00004000,uint16_t)) /* Isochronous Transfers */
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#define ENUM_USB_EPI_RXCSR_P_ISODIS (_ADI_MSK(0x00000000,uint16_t)) /* ISO: This bit should be cleared for bulk or interrupt transfers. */
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#define ENUM_USB_EPI_RXCSR_P_ISOEN (_ADI_MSK(0x00004000,uint16_t)) /* ISO: This bit should be set for isochronous transfers. */
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#define BITM_USB_EPI_RXCSR_P_DMAREQEN (_ADI_MSK(0x00002000,uint16_t)) /* DMA Request Enable Rx EP */
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#define ENUM_USB_EPI_RXCSR_P_DMAREQDIS (_ADI_MSK(0x00000000,uint16_t)) /* DMAREQEN: Disable DMA Request */
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#define ENUM_USB_EPI_RXCSR_P_DMAREQEN (_ADI_MSK(0x00002000,uint16_t)) /* DMAREQEN: Enable DMA Request */
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#define BITM_USB_EPI_RXCSR_P_DNYETPERR (_ADI_MSK(0x00001000,uint16_t)) /* Disable NYET Handshake */
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#define ENUM_USB_EPI_RXCSR_P_DNYTERREN (_ADI_MSK(0x00000000,uint16_t)) /* DNYETPERR: Enable NYET Handshake */
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#define ENUM_USB_EPI_RXCSR_P_DNYTERRDIS (_ADI_MSK(0x00001000,uint16_t)) /* DNYETPERR: Disable NYET Handshake */
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#define BITM_USB_EPI_RXCSR_P_DMAREQMODE (_ADI_MSK(0x00000800,uint16_t)) /* DMA Mode Select */
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#define ENUM_USB_EPI_RXCSR_P_DMARQMODE0 (_ADI_MSK(0x00000000,uint16_t)) /* DMAREQMODE: DMA Request Mode 0 */
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#define ENUM_USB_EPI_RXCSR_P_DMARQMODE1 (_ADI_MSK(0x00000800,uint16_t)) /* DMAREQMODE: DMA Request Mode 1 */
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#define BITM_USB_EPI_RXCSR_P_INCOMPRX (_ADI_MSK(0x00000100,uint16_t)) /* Incomplete Rx */
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#define ENUM_USB_EPI_RXCSR_P_NO_INCOMP (_ADI_MSK(0x00000000,uint16_t)) /* INCOMPRX: No Status */
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#define ENUM_USB_EPI_RXCSR_P_INCOMP (_ADI_MSK(0x00000100,uint16_t)) /* INCOMPRX: Incomplete Rx */
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#define BITM_USB_EPI_RXCSR_P_CLRDATATGL (_ADI_MSK(0x00000080,uint16_t)) /* Clear Endpoint Data Toggle */
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#define ENUM_USB_EPI_RXCSR_P_NO_CLRTGL (_ADI_MSK(0x00000000,uint16_t)) /* CLRDATATGL: No Action */
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#define ENUM_USB_EPI_RXCSR_P_CLRTGL (_ADI_MSK(0x00000080,uint16_t)) /* CLRDATATGL: Reset EP Data Toggle to 0 */
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#define BITM_USB_EPI_RXCSR_P_SENTSTALL (_ADI_MSK(0x00000040,uint16_t)) /* Sent STALL */
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#define ENUM_USB_EPI_RXCSR_P_NO_STALSNT (_ADI_MSK(0x00000000,uint16_t)) /* SENTSTALL: No Status */
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#define ENUM_USB_EPI_RXCSR_P_STALSNT (_ADI_MSK(0x00000040,uint16_t)) /* SENTSTALL: STALL Handshake Transmitted */
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#define BITM_USB_EPI_RXCSR_P_SENDSTALL (_ADI_MSK(0x00000020,uint16_t)) /* Send STALL */
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#define ENUM_USB_EPI_RXCSR_P_NO_STALL (_ADI_MSK(0x00000000,uint16_t)) /* SENDSTALL: No Action */
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#define ENUM_USB_EPI_RXCSR_P_STALL (_ADI_MSK(0x00000020,uint16_t)) /* SENDSTALL: Request STALL Handshake */
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#define BITM_USB_EPI_RXCSR_P_FLUSHFIFO (_ADI_MSK(0x00000010,uint16_t)) /* Flush Endpoint FIFO */
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#define ENUM_USB_EPI_RXCSR_P_NO_FLUSH (_ADI_MSK(0x00000000,uint16_t)) /* FLUSHFIFO: No Flush */
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#define ENUM_USB_EPI_RXCSR_P_FLUSH (_ADI_MSK(0x00000010,uint16_t)) /* FLUSHFIFO: Flush Endpoint FIFO */
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#define BITM_USB_EPI_RXCSR_P_DATAERR (_ADI_MSK(0x00000008,uint16_t)) /* Data Error */
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#define ENUM_USB_EPI_RXCSR_P_NO_DATAERR (_ADI_MSK(0x00000000,uint16_t)) /* DATAERR: No Status */
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#define ENUM_USB_EPI_RXCSR_P_DATAERR (_ADI_MSK(0x00000008,uint16_t)) /* DATAERR: Data Error */
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#define BITM_USB_EPI_RXCSR_P_ORUNERR (_ADI_MSK(0x00000004,uint16_t)) /* OUT Run Error */
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#define ENUM_USB_EPI_RXCSR_P_NO_ORUNERR (_ADI_MSK(0x00000000,uint16_t)) /* ORUNERR: No Status */
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#define ENUM_USB_EPI_RXCSR_P_ORUNERR (_ADI_MSK(0x00000004,uint16_t)) /* ORUNERR: OUT Run Error */
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#define BITM_USB_EPI_RXCSR_P_FIFOFULL (_ADI_MSK(0x00000002,uint16_t)) /* FIFO Full */
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#define ENUM_USB_EPI_RXCSR_P_NO_FIFOFUL (_ADI_MSK(0x00000000,uint16_t)) /* FIFOFULL: No Status */
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#define ENUM_USB_EPI_RXCSR_P_FIFOFUL (_ADI_MSK(0x00000002,uint16_t)) /* FIFOFULL: FIFO Full */
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#define BITM_USB_EPI_RXCSR_P_RXPKTRDY (_ADI_MSK(0x00000001,uint16_t)) /* Rx Packet Ready */
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#define ENUM_USB_EPI_RXCSR_P_NO_PKTRDY (_ADI_MSK(0x00000000,uint16_t)) /* RXPKTRDY: No Rx Packet */
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#define ENUM_USB_EPI_RXCSR_P_PKTRDY (_ADI_MSK(0x00000001,uint16_t)) /* RXPKTRDY: Rx Packet in Endpoint FIFO */
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_EP0I_CNT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
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#define BITP_USB_EP0I_CNT_RXCNT 0 /* Rx Byte Count Value */
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#define BITM_USB_EP0I_CNT_RXCNT (_ADI_MSK(0x0000007F,uint16_t)) /* Rx Byte Count Value */
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/* ------------------------------------------------------------------------------------------------------------------------
|
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USB_EPI_RXCNT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_USB_EPI_RXCNT_EPRXCNT 0 /* EP Rx Count */
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#define BITM_USB_EPI_RXCNT_EPRXCNT (_ADI_MSK(0x00003FFF,uint16_t)) /* EP Rx Count */
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_EPI_TXTYPE Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_USB_EPI_TXTYPE_SPEED 6 /* Speed of Operation Value */
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#define BITP_USB_EPI_TXTYPE_PROTOCOL 4 /* Protocol for Transfer */
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#define BITP_USB_EPI_TXTYPE_TGTEP 0 /* Target Endpoint Number */
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#define BITM_USB_EPI_TXTYPE_SPEED (_ADI_MSK(0x000000C0,uint8_t)) /* Speed of Operation Value */
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#define ENUM_USB_EPI_TXTYPE_UNUSED (_ADI_MSK(0x00000000,uint8_t)) /* SPEED: Same Speed as the Core */
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#define ENUM_USB_EPI_TXTYPE_HIGHSPEED (_ADI_MSK(0x00000040,uint8_t)) /* SPEED: High Speed */
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#define ENUM_USB_EPI_TXTYPE_FULLSPEED (_ADI_MSK(0x00000080,uint8_t)) /* SPEED: Full Speed */
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#define ENUM_USB_EPI_TXTYPE_LOWSPEED (_ADI_MSK(0x000000C0,uint8_t)) /* SPEED: Low Speed */
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#define BITM_USB_EPI_TXTYPE_PROTOCOL (_ADI_MSK(0x00000030,uint8_t)) /* Protocol for Transfer */
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#define ENUM_USB_EPI_TXTYPE_CONTROL (_ADI_MSK(0x00000000,uint8_t)) /* PROTOCOL: Control */
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#define ENUM_USB_EPI_TXTYPE_ISO (_ADI_MSK(0x00000010,uint8_t)) /* PROTOCOL: Isochronous */
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#define ENUM_USB_EPI_TXTYPE_BULK (_ADI_MSK(0x00000020,uint8_t)) /* PROTOCOL: Bulk */
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#define ENUM_USB_EPI_TXTYPE_INT (_ADI_MSK(0x00000030,uint8_t)) /* PROTOCOL: Interrupt */
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#define BITM_USB_EPI_TXTYPE_TGTEP (_ADI_MSK(0x0000000F,uint8_t)) /* Target Endpoint Number */
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#define ENUM_USB_EPI_TXTYPE_TGTEP0 (_ADI_MSK(0x00000000,uint8_t)) /* TGTEP: Endpoint 0 */
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#define ENUM_USB_EPI_TXTYPE_TGTEP1 (_ADI_MSK(0x00000001,uint8_t)) /* TGTEP: Endpoint 1 */
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#define ENUM_USB_EPI_TXTYPE_TGTEP10 (_ADI_MSK(0x0000000A,uint8_t)) /* TGTEP: Endpoint 10 */
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#define ENUM_USB_EPI_TXTYPE_TGTEP11 (_ADI_MSK(0x0000000B,uint8_t)) /* TGTEP: Endpoint 11 */
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#define ENUM_USB_EPI_TXTYPE_TGTEP12 (_ADI_MSK(0x0000000C,uint8_t)) /* TGTEP: Endpoint 12 */
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#define ENUM_USB_EPI_TXTYPE_TGTEP13 (_ADI_MSK(0x0000000D,uint8_t)) /* TGTEP: Endpoint 13 */
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#define ENUM_USB_EPI_TXTYPE_TGTEP14 (_ADI_MSK(0x0000000E,uint8_t)) /* TGTEP: Endpoint 14 */
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#define ENUM_USB_EPI_TXTYPE_TGTEP15 (_ADI_MSK(0x0000000F,uint8_t)) /* TGTEP: Endpoint 15 */
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#define ENUM_USB_EPI_TXTYPE_TGTEP2 (_ADI_MSK(0x00000002,uint8_t)) /* TGTEP: Endpoint 2 */
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#define ENUM_USB_EPI_TXTYPE_TGTEP3 (_ADI_MSK(0x00000003,uint8_t)) /* TGTEP: Endpoint 3 */
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#define ENUM_USB_EPI_TXTYPE_TGTEP4 (_ADI_MSK(0x00000004,uint8_t)) /* TGTEP: Endpoint 4 */
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#define ENUM_USB_EPI_TXTYPE_TGTEP5 (_ADI_MSK(0x00000005,uint8_t)) /* TGTEP: Endpoint 5 */
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#define ENUM_USB_EPI_TXTYPE_TGTEP6 (_ADI_MSK(0x00000006,uint8_t)) /* TGTEP: Endpoint 6 */
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#define ENUM_USB_EPI_TXTYPE_TGTEP7 (_ADI_MSK(0x00000007,uint8_t)) /* TGTEP: Endpoint 7 */
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#define ENUM_USB_EPI_TXTYPE_TGTEP8 (_ADI_MSK(0x00000008,uint8_t)) /* TGTEP: Endpoint 8 */
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#define ENUM_USB_EPI_TXTYPE_TGTEP9 (_ADI_MSK(0x00000009,uint8_t)) /* TGTEP: Endpoint 9 */
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/* ------------------------------------------------------------------------------------------------------------------------
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USB_EP0I_TYPE Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_USB_EP0I_TYPE_SPEED 0 /* Speed of Operation Value */
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#define BITM_USB_EP0I_TYPE_SPEED (_ADI_MSK(0x00000003,uint8_t)) /* Speed of Operation Value */
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/* ------------------------------------------------------------------------------------------------------------------------
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USB_EP0I_NAKLIMIT Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_USB_EP0I_NAKLIMIT_VALUE 0 /* Endpoint 0 Timeout Value (in Frames) */
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#define BITM_USB_EP0I_NAKLIMIT_VALUE (_ADI_MSK(0x0000001F,uint8_t)) /* Endpoint 0 Timeout Value (in Frames) */
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/* ------------------------------------------------------------------------------------------------------------------------
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USB_EPI_RXTYPE Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_USB_EPI_RXTYPE_SPEED 6 /* Speed of Operation Value */
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#define BITP_USB_EPI_RXTYPE_PROTOCOL 4 /* Protocol for Transfer */
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#define BITP_USB_EPI_RXTYPE_TGTEP 0 /* Target Endpoint Number */
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#define BITM_USB_EPI_RXTYPE_SPEED (_ADI_MSK(0x000000C0,uint8_t)) /* Speed of Operation Value */
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#define ENUM_USB_EPI_RXTYPE_UNUSED (_ADI_MSK(0x00000000,uint8_t)) /* SPEED: Same Speed as the Core */
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#define ENUM_USB_EPI_RXTYPE_HIGHSPEED (_ADI_MSK(0x00000040,uint8_t)) /* SPEED: High Speed */
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#define ENUM_USB_EPI_RXTYPE_FULLSPEED (_ADI_MSK(0x00000080,uint8_t)) /* SPEED: Full Speed */
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#define ENUM_USB_EPI_RXTYPE_LOWSPEED (_ADI_MSK(0x000000C0,uint8_t)) /* SPEED: Low Speed */
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#define BITM_USB_EPI_RXTYPE_PROTOCOL (_ADI_MSK(0x00000030,uint8_t)) /* Protocol for Transfer */
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#define ENUM_USB_EPI_RXTYPE_CONTROL (_ADI_MSK(0x00000000,uint8_t)) /* PROTOCOL: Control */
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#define ENUM_USB_EPI_RXTYPE_ISO (_ADI_MSK(0x00000010,uint8_t)) /* PROTOCOL: Isochronous */
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#define ENUM_USB_EPI_RXTYPE_BULK (_ADI_MSK(0x00000020,uint8_t)) /* PROTOCOL: Bulk */
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#define ENUM_USB_EPI_RXTYPE_INT (_ADI_MSK(0x00000030,uint8_t)) /* PROTOCOL: Interrupt */
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#define BITM_USB_EPI_RXTYPE_TGTEP (_ADI_MSK(0x0000000F,uint8_t)) /* Target Endpoint Number */
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#define ENUM_USB_EPI_RXTYPE_TGTEP0 (_ADI_MSK(0x00000000,uint8_t)) /* TGTEP: Endpoint 0 */
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#define ENUM_USB_EPI_RXTYPE_TGTEP1 (_ADI_MSK(0x00000001,uint8_t)) /* TGTEP: Endpoint 1 */
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#define ENUM_USB_EPI_RXTYPE_TGTEP10 (_ADI_MSK(0x0000000A,uint8_t)) /* TGTEP: Endpoint 10 */
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#define ENUM_USB_EPI_RXTYPE_TGTEP11 (_ADI_MSK(0x0000000B,uint8_t)) /* TGTEP: Endpoint 11 */
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#define ENUM_USB_EPI_RXTYPE_TGTEP12 (_ADI_MSK(0x0000000C,uint8_t)) /* TGTEP: Endpoint 12 */
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#define ENUM_USB_EPI_RXTYPE_TGTEP13 (_ADI_MSK(0x0000000D,uint8_t)) /* TGTEP: Endpoint 13 */
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#define ENUM_USB_EPI_RXTYPE_TGTEP14 (_ADI_MSK(0x0000000E,uint8_t)) /* TGTEP: Endpoint 14 */
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#define ENUM_USB_EPI_RXTYPE_TGTEP15 (_ADI_MSK(0x0000000F,uint8_t)) /* TGTEP: Endpoint 15 */
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#define ENUM_USB_EPI_RXTYPE_TGTEP2 (_ADI_MSK(0x00000002,uint8_t)) /* TGTEP: Endpoint 2 */
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#define ENUM_USB_EPI_RXTYPE_TGTEP3 (_ADI_MSK(0x00000003,uint8_t)) /* TGTEP: Endpoint 3 */
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#define ENUM_USB_EPI_RXTYPE_TGTEP4 (_ADI_MSK(0x00000004,uint8_t)) /* TGTEP: Endpoint 4 */
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#define ENUM_USB_EPI_RXTYPE_TGTEP5 (_ADI_MSK(0x00000005,uint8_t)) /* TGTEP: Endpoint 5 */
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#define ENUM_USB_EPI_RXTYPE_TGTEP6 (_ADI_MSK(0x00000006,uint8_t)) /* TGTEP: Endpoint 6 */
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#define ENUM_USB_EPI_RXTYPE_TGTEP7 (_ADI_MSK(0x00000007,uint8_t)) /* TGTEP: Endpoint 7 */
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#define ENUM_USB_EPI_RXTYPE_TGTEP8 (_ADI_MSK(0x00000008,uint8_t)) /* TGTEP: Endpoint 8 */
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#define ENUM_USB_EPI_RXTYPE_TGTEP9 (_ADI_MSK(0x00000009,uint8_t)) /* TGTEP: Endpoint 9 */
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_EP0I_CFGDATA Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_USB_EP0I_CFGDATA_MPRX 7 /* Multi-Packet Aggregate for Rx Enable */
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#define BITP_USB_EP0I_CFGDATA_MPTX 6 /* Multi-Packet Split for Tx Enable */
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#define BITP_USB_EP0I_CFGDATA_BIGEND 5 /* Big Endian Data */
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#define BITP_USB_EP0I_CFGDATA_HBRX 4 /* High Bandwidth Rx Enable */
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#define BITP_USB_EP0I_CFGDATA_HBTX 3 /* High Bandwidth Tx Enable */
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#define BITP_USB_EP0I_CFGDATA_DYNFIFO 2 /* Dynamic FIFO Size Enable */
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#define BITP_USB_EP0I_CFGDATA_SOFTCON 1 /* Soft Connect Enable */
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#define BITP_USB_EP0I_CFGDATA_UTMIWID 0 /* UTMI Data Width */
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#define BITM_USB_EP0I_CFGDATA_MPRX (_ADI_MSK(0x00000080,uint8_t)) /* Multi-Packet Aggregate for Rx Enable */
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#define ENUM_USB_EP0I_CFGDATA_MPRXDIS (_ADI_MSK(0x00000000,uint8_t)) /* MPRX: No Aggregate Rx Bulk Packets */
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#define ENUM_USB_EP0I_CFGDATA_MPRXEN (_ADI_MSK(0x00000080,uint8_t)) /* MPRX: Aggregate Rx Bulk Packets */
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#define BITM_USB_EP0I_CFGDATA_MPTX (_ADI_MSK(0x00000040,uint8_t)) /* Multi-Packet Split for Tx Enable */
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#define ENUM_USB_EP0I_CFGDATA_MPTXDIS (_ADI_MSK(0x00000000,uint8_t)) /* MPTX: No Split Tx Bulk Packets */
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#define ENUM_USB_EP0I_CFGDATA_MPTXEN (_ADI_MSK(0x00000040,uint8_t)) /* MPTX: Split Tx Bulk Packets */
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#define BITM_USB_EP0I_CFGDATA_BIGEND (_ADI_MSK(0x00000020,uint8_t)) /* Big Endian Data */
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#define ENUM_USB_EP0I_CFGDATA_BIGENDDIS (_ADI_MSK(0x00000000,uint8_t)) /* BIGEND: Little Endian Configuration */
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#define ENUM_USB_EP0I_CFGDATA_BIGENDEN (_ADI_MSK(0x00000020,uint8_t)) /* BIGEND: Big Endian Configuration */
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#define BITM_USB_EP0I_CFGDATA_HBRX (_ADI_MSK(0x00000010,uint8_t)) /* High Bandwidth Rx Enable */
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#define ENUM_USB_EP0I_CFGDATA_HBRXDIS (_ADI_MSK(0x00000000,uint8_t)) /* HBRX: No High Bandwidth Rx */
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#define ENUM_USB_EP0I_CFGDATA_HBRXEN (_ADI_MSK(0x00000010,uint8_t)) /* HBRX: High Bandwidth Rx */
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#define BITM_USB_EP0I_CFGDATA_HBTX (_ADI_MSK(0x00000008,uint8_t)) /* High Bandwidth Tx Enable */
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#define ENUM_USB_EP0I_CFGDATA_HBTXDIS (_ADI_MSK(0x00000000,uint8_t)) /* HBTX: No High Bandwidth Tx */
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#define ENUM_USB_EP0I_CFGDATA_HBTXEN (_ADI_MSK(0x00000008,uint8_t)) /* HBTX: High Bandwidth Tx */
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#define BITM_USB_EP0I_CFGDATA_DYNFIFO (_ADI_MSK(0x00000004,uint8_t)) /* Dynamic FIFO Size Enable */
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#define ENUM_USB_EP0I_CFGDATA_DYNSZDIS (_ADI_MSK(0x00000000,uint8_t)) /* DYNFIFO: No Dynamic FIFO Size */
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#define ENUM_USB_EP0I_CFGDATA_DYNSZEN (_ADI_MSK(0x00000004,uint8_t)) /* DYNFIFO: Dynamic FIFO Size */
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#define BITM_USB_EP0I_CFGDATA_SOFTCON (_ADI_MSK(0x00000002,uint8_t)) /* Soft Connect Enable */
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#define ENUM_USB_EP0I_CFGDATA_SFTCONDIS (_ADI_MSK(0x00000000,uint8_t)) /* SOFTCON: No Soft Connect */
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#define ENUM_USB_EP0I_CFGDATA_SFTCONEN (_ADI_MSK(0x00000002,uint8_t)) /* SOFTCON: Soft Connect */
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#define BITM_USB_EP0I_CFGDATA_UTMIWID (_ADI_MSK(0x00000001,uint8_t)) /* UTMI Data Width */
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#define ENUM_USB_EP0I_CFGDATA_UTMIWID8 (_ADI_MSK(0x00000000,uint8_t)) /* UTMIWID: 8-bit UTMI Data Width */
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#define ENUM_USB_EP0I_CFGDATA_UTMIWID16 (_ADI_MSK(0x00000001,uint8_t)) /* UTMIWID: 16-bit UTMI Data Width */
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/* ------------------------------------------------------------------------------------------------------------------------
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USB_DEV_CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_USB_DEV_CTL_BDEVICE 7 /* A or B Devices Indicator */
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#define BITP_USB_DEV_CTL_FSDEV 6 /* Full or High-Speed Indicator */
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#define BITP_USB_DEV_CTL_LSDEV 5 /* Low-Speed Indicator */
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#define BITP_USB_DEV_CTL_VBUS 3 /* VBUS Level Indicator */
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#define BITP_USB_DEV_CTL_HOSTMODE 2 /* Host Mode Indicator */
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#define BITP_USB_DEV_CTL_HOSTREQ 1 /* Host Negotiation Request */
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#define BITP_USB_DEV_CTL_SESSION 0 /* Session Indicator */
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#define BITM_USB_DEV_CTL_BDEVICE (_ADI_MSK(0x00000080,uint8_t)) /* A or B Devices Indicator */
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#define ENUM_USB_DEV_CTL_ADEVICE (_ADI_MSK(0x00000000,uint8_t)) /* BDEVICE: A Device Detected */
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#define ENUM_USB_DEV_CTL_BDEVICE (_ADI_MSK(0x00000080,uint8_t)) /* BDEVICE: B Device Detected */
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#define BITM_USB_DEV_CTL_FSDEV (_ADI_MSK(0x00000040,uint8_t)) /* Full or High-Speed Indicator */
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#define ENUM_USB_DEV_CTL_NO_FSDEV (_ADI_MSK(0x00000000,uint8_t)) /* FSDEV: Not Detected */
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#define ENUM_USB_DEV_CTL_FSDEV (_ADI_MSK(0x00000040,uint8_t)) /* FSDEV: Full or High Speed Detected */
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#define BITM_USB_DEV_CTL_LSDEV (_ADI_MSK(0x00000020,uint8_t)) /* Low-Speed Indicator */
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#define ENUM_USB_DEV_CTL_NO_LSDEV (_ADI_MSK(0x00000000,uint8_t)) /* LSDEV: Not Detected */
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#define ENUM_USB_DEV_CTL_LSDEV (_ADI_MSK(0x00000020,uint8_t)) /* LSDEV: Low Speed Detected */
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#define BITM_USB_DEV_CTL_VBUS (_ADI_MSK(0x00000018,uint8_t)) /* VBUS Level Indicator */
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#define ENUM_USB_DEV_CTL_VBUS_BS (_ADI_MSK(0x00000000,uint8_t)) /* VBUS: Below SessionEnd */
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#define ENUM_USB_DEV_CTL_VBUS_ASBA (_ADI_MSK(0x00000008,uint8_t)) /* VBUS: Above SessionEnd, below AValid */
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#define ENUM_USB_DEV_CTL_VBUS_AABV (_ADI_MSK(0x00000010,uint8_t)) /* VBUS: Above AValid, below VBUSValid */
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#define ENUM_USB_DEV_CTL_VBUS_AV (_ADI_MSK(0x00000018,uint8_t)) /* VBUS: Above VBUSValid */
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#define BITM_USB_DEV_CTL_HOSTMODE (_ADI_MSK(0x00000004,uint8_t)) /* Host Mode Indicator */
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#define ENUM_USB_DEV_CTL_NO_HOSTMODE (_ADI_MSK(0x00000000,uint8_t)) /* HOSTMODE: Peripheral Mode */
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#define ENUM_USB_DEV_CTL_HOSTMODE (_ADI_MSK(0x00000004,uint8_t)) /* HOSTMODE: Host Mode */
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#define BITM_USB_DEV_CTL_HOSTREQ (_ADI_MSK(0x00000002,uint8_t)) /* Host Negotiation Request */
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#define ENUM_USB_DEV_CTL_NO_HOSTREQ (_ADI_MSK(0x00000000,uint8_t)) /* HOSTREQ: No Request */
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#define ENUM_USB_DEV_CTL_HOSTREQ (_ADI_MSK(0x00000002,uint8_t)) /* HOSTREQ: Place Request */
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#define BITM_USB_DEV_CTL_SESSION (_ADI_MSK(0x00000001,uint8_t)) /* Session Indicator */
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#define ENUM_USB_DEV_CTL_NO_SESSION (_ADI_MSK(0x00000000,uint8_t)) /* SESSION: Not Detected */
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#define ENUM_USB_DEV_CTL_SESSION (_ADI_MSK(0x00000001,uint8_t)) /* SESSION: Detected Session */
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_TXFIFOSZ Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_USB_TXFIFOSZ_DPB 4 /* Double Packet Buffering Enable */
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#define BITP_USB_TXFIFOSZ_SZ 0 /* Maximum Packet Size */
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#define BITM_USB_TXFIFOSZ_DPB (_ADI_MSK(0x00000010,uint8_t)) /* Double Packet Buffering Enable */
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#define ENUM_USB_TXFIFOSZ_DPNDIS (_ADI_MSK(0x00000000,uint8_t)) /* DPB: Single Packet Buffering */
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#define ENUM_USB_TXFIFOSZ_DPBEN (_ADI_MSK(0x00000010,uint8_t)) /* DPB: Double Packet Buffering */
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#define BITM_USB_TXFIFOSZ_SZ (_ADI_MSK(0x0000000F,uint8_t)) /* Maximum Packet Size */
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#define ENUM_USB_TXFIFOSZ_SZ8 (_ADI_MSK(0x00000000,uint8_t)) /* SZ: PktSz=8, DPB0=8, DPB1=16 */
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#define ENUM_USB_TXFIFOSZ_SZ16 (_ADI_MSK(0x00000001,uint8_t)) /* SZ: PktSz=16, DPB0=16, DPB1=32 */
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#define ENUM_USB_TXFIFOSZ_SZ32 (_ADI_MSK(0x00000002,uint8_t)) /* SZ: PktSz=32, DPB0=32, DPB1=64 */
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#define ENUM_USB_TXFIFOSZ_SZ64 (_ADI_MSK(0x00000003,uint8_t)) /* SZ: PktSz=64, DPB0=64, DPB1=128 */
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#define ENUM_USB_TXFIFOSZ_SZ128 (_ADI_MSK(0x00000004,uint8_t)) /* SZ: PktSz=128, DPB0=128, DPB1=256 */
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#define ENUM_USB_TXFIFOSZ_SZ256 (_ADI_MSK(0x00000005,uint8_t)) /* SZ: PktSz=256, DPB0=256, DPB1=512 */
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#define ENUM_USB_TXFIFOSZ_SZ512 (_ADI_MSK(0x00000006,uint8_t)) /* SZ: PktSz=512, DPB0=512, DPB1=1024 */
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#define ENUM_USB_TXFIFOSZ_SZ1024 (_ADI_MSK(0x00000007,uint8_t)) /* SZ: PktSz=1024, DPB0=1024, DPB1=2048 */
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#define ENUM_USB_TXFIFOSZ_SZ2048 (_ADI_MSK(0x00000008,uint8_t)) /* SZ: PktSz=2048, DPB0=2048, DPB1=4096 */
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#define ENUM_USB_TXFIFOSZ_SZ4096 (_ADI_MSK(0x00000009,uint8_t)) /* SZ: PktSz=4096, DPB0=4096, DPB1=8192 */
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_RXFIFOSZ Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_RXFIFOSZ_DPB 4 /* Double Packet Buffering Enable */
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|
#define BITP_USB_RXFIFOSZ_SZ 0 /* Maximum Packet Size */
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|
|
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#define BITM_USB_RXFIFOSZ_DPB (_ADI_MSK(0x00000010,uint8_t)) /* Double Packet Buffering Enable */
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|
#define ENUM_USB_RXFIFOSZ_DPBDIS (_ADI_MSK(0x00000000,uint8_t)) /* DPB: Single Packet Buffering */
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#define ENUM_USB_RXFIFOSZ_DPBEN (_ADI_MSK(0x00000010,uint8_t)) /* DPB: Double Packet Buffering */
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|
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#define BITM_USB_RXFIFOSZ_SZ (_ADI_MSK(0x0000000F,uint8_t)) /* Maximum Packet Size */
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|
#define ENUM_USB_RXFIFOSZ_SZ8 (_ADI_MSK(0x00000000,uint8_t)) /* SZ: PktSz=8, DPB0=8, DPB1=16 */
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#define ENUM_USB_RXFIFOSZ_SZ16 (_ADI_MSK(0x00000001,uint8_t)) /* SZ: PktSz=16, DPB0=16, DPB1=32 */
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|
#define ENUM_USB_RXFIFOSZ_SZ32 (_ADI_MSK(0x00000002,uint8_t)) /* SZ: PktSz=32, DPB0=32, DPB1=64 */
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|
#define ENUM_USB_RXFIFOSZ_SZ64 (_ADI_MSK(0x00000003,uint8_t)) /* SZ: PktSz=64, DPB0=64, DPB1=128 */
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|
#define ENUM_USB_RXFIFOSZ_SZ128 (_ADI_MSK(0x00000004,uint8_t)) /* SZ: PktSz=128, DPB0=128, DPB1=256 */
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|
#define ENUM_USB_RXFIFOSZ_SZ256 (_ADI_MSK(0x00000005,uint8_t)) /* SZ: PktSz=256, DPB0=256, DPB1=512 */
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|
#define ENUM_USB_RXFIFOSZ_SZ512 (_ADI_MSK(0x00000006,uint8_t)) /* SZ: PktSz=512, DPB0=512, DPB1=1024 */
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|
#define ENUM_USB_RXFIFOSZ_SZ1024 (_ADI_MSK(0x00000007,uint8_t)) /* SZ: PktSz=1024, DPB0=1024, DPB1=2048 */
|
|
#define ENUM_USB_RXFIFOSZ_SZ2048 (_ADI_MSK(0x00000008,uint8_t)) /* SZ: PktSz=2048, DPB0=2048, DPB1=4096 */
|
|
#define ENUM_USB_RXFIFOSZ_SZ4096 (_ADI_MSK(0x00000009,uint8_t)) /* SZ: PktSz=4096, DPB0=4096, DPB1=8192 */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_TXFIFOADDR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_TXFIFOADDR_VALUE 0 /* Tx FIFO Start Address */
|
|
#define BITM_USB_TXFIFOADDR_VALUE (_ADI_MSK(0x00001FFF,uint16_t)) /* Tx FIFO Start Address */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_RXFIFOADDR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_RXFIFOADDR_VALUE 0 /* Rx FIFO Start Address */
|
|
#define BITM_USB_RXFIFOADDR_VALUE (_ADI_MSK(0x00000FFF,uint16_t)) /* Rx FIFO Start Address */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_EPINFO Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_EPINFO_RXEP 4 /* Rx Endpoints */
|
|
#define BITP_USB_EPINFO_TXEP 0 /* Tx Endpoints */
|
|
#define BITM_USB_EPINFO_RXEP (_ADI_MSK(0x000000F0,uint8_t)) /* Rx Endpoints */
|
|
#define BITM_USB_EPINFO_TXEP (_ADI_MSK(0x0000000F,uint8_t)) /* Tx Endpoints */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_RAMINFO Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_RAMINFO_DMACHANS 4 /* DMA Channels */
|
|
#define BITP_USB_RAMINFO_RAMBITS 0 /* RAM Address Bits */
|
|
#define BITM_USB_RAMINFO_DMACHANS (_ADI_MSK(0x000000F0,uint8_t)) /* DMA Channels */
|
|
#define BITM_USB_RAMINFO_RAMBITS (_ADI_MSK(0x0000000F,uint8_t)) /* RAM Address Bits */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_LINKINFO Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_LINKINFO_WTCON 4 /* Wait for Connect/Disconnect */
|
|
#define BITP_USB_LINKINFO_WTID 0 /* Wait from ID Pull-up */
|
|
#define BITM_USB_LINKINFO_WTCON (_ADI_MSK(0x000000F0,uint8_t)) /* Wait for Connect/Disconnect */
|
|
#define BITM_USB_LINKINFO_WTID (_ADI_MSK(0x0000000F,uint8_t)) /* Wait from ID Pull-up */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_SOFT_RST Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_SOFT_RST_RSTX 1 /* Reset USB XCLK Domain */
|
|
#define BITP_USB_SOFT_RST_RST 0 /* Reset USB CLK Domain */
|
|
|
|
#define BITM_USB_SOFT_RST_RSTX (_ADI_MSK(0x00000002,uint8_t)) /* Reset USB XCLK Domain */
|
|
#define ENUM_USB_SOFT_RST_NO_RSTX (_ADI_MSK(0x00000000,uint8_t)) /* RSTX: No Reset */
|
|
#define ENUM_USB_SOFT_RST_RSTX (_ADI_MSK(0x00000002,uint8_t)) /* RSTX: Reset USB XCLK Domain */
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|
|
|
#define BITM_USB_SOFT_RST_RST (_ADI_MSK(0x00000001,uint8_t)) /* Reset USB CLK Domain */
|
|
#define ENUM_USB_SOFT_RST_NO_RST (_ADI_MSK(0x00000000,uint8_t)) /* RST: No Reset */
|
|
#define ENUM_USB_SOFT_RST_RST (_ADI_MSK(0x00000001,uint8_t)) /* RST: Reset USB CLK Domain */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_MP_TXFUNCADDR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_MP_TXFUNCADDR_VALUE 0 /* Tx Function Address Value */
|
|
#define BITM_USB_MP_TXFUNCADDR_VALUE (_ADI_MSK(0x0000007F,uint8_t)) /* Tx Function Address Value */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_MP_TXHUBADDR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_MP_TXHUBADDR_MULTTRANS 7 /* Multiple Transaction Translators */
|
|
#define BITP_USB_MP_TXHUBADDR_ADDR 0 /* Hub Address Value */
|
|
#define BITM_USB_MP_TXHUBADDR_MULTTRANS (_ADI_MSK(0x00000080,uint8_t)) /* Multiple Transaction Translators */
|
|
#define BITM_USB_MP_TXHUBADDR_ADDR (_ADI_MSK(0x0000007F,uint8_t)) /* Hub Address Value */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_MP_TXHUBPORT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_MP_TXHUBPORT_VALUE 0 /* Hub Port Value */
|
|
#define BITM_USB_MP_TXHUBPORT_VALUE (_ADI_MSK(0x0000007F,uint8_t)) /* Hub Port Value */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_MP_RXFUNCADDR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_MP_RXFUNCADDR_VALUE 0 /* Rx Function Address Value */
|
|
#define BITM_USB_MP_RXFUNCADDR_VALUE (_ADI_MSK(0x0000007F,uint8_t)) /* Rx Function Address Value */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_MP_RXHUBADDR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_MP_RXHUBADDR_MULTTRANS 7 /* Multiple Transaction Translators */
|
|
#define BITP_USB_MP_RXHUBADDR_ADDR 0 /* Hub Address Value */
|
|
#define BITM_USB_MP_RXHUBADDR_MULTTRANS (_ADI_MSK(0x00000080,uint8_t)) /* Multiple Transaction Translators */
|
|
#define BITM_USB_MP_RXHUBADDR_ADDR (_ADI_MSK(0x0000007F,uint8_t)) /* Hub Address Value */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_MP_RXHUBPORT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_MP_RXHUBPORT_VALUE 0 /* Hub Port Value */
|
|
#define BITM_USB_MP_RXHUBPORT_VALUE (_ADI_MSK(0x0000007F,uint8_t)) /* Hub Port Value */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_EP_TXMAXP Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_EP_TXMAXP_MULTM1 11 /* Multi-Packets per Micro-frame */
|
|
#define BITP_USB_EP_TXMAXP_MAXPAY 0 /* Maximum Payload */
|
|
#define BITM_USB_EP_TXMAXP_MULTM1 (_ADI_MSK(0x00001800,uint16_t)) /* Multi-Packets per Micro-frame */
|
|
#define BITM_USB_EP_TXMAXP_MAXPAY (_ADI_MSK(0x000007FF,uint16_t)) /* Maximum Payload */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_EP0_CSR_H Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_EP0_CSR_H_DISPING 11 /* Disable Ping */
|
|
#define BITP_USB_EP0_CSR_H_DATGLEN 10 /* Data Toggle Write Enable */
|
|
#define BITP_USB_EP0_CSR_H_DATGL 9 /* Data Toggle */
|
|
#define BITP_USB_EP0_CSR_H_FLUSHFIFO 8 /* Flush Endpoint FIFO */
|
|
#define BITP_USB_EP0_CSR_H_NAKTO 7 /* NAK Timeout */
|
|
#define BITP_USB_EP0_CSR_H_STATUSPKT 6 /* Status Packet */
|
|
#define BITP_USB_EP0_CSR_H_REQPKT 5 /* Request Packet */
|
|
#define BITP_USB_EP0_CSR_H_TOERR 4 /* Timeout Error */
|
|
#define BITP_USB_EP0_CSR_H_SETUPPKT 3 /* Setup Packet */
|
|
#define BITP_USB_EP0_CSR_H_RXSTALL 2 /* Rx Stall */
|
|
#define BITP_USB_EP0_CSR_H_TXPKTRDY 1 /* Tx Packet Ready */
|
|
#define BITP_USB_EP0_CSR_H_RXPKTRDY 0 /* Rx Packet Ready */
|
|
|
|
#define BITM_USB_EP0_CSR_H_DISPING (_ADI_MSK(0x00000800,uint16_t)) /* Disable Ping */
|
|
#define ENUM_USB_EP0_CSR_H_NO_DISPING (_ADI_MSK(0x00000000,uint16_t)) /* DISPING: Issue PING tokens */
|
|
#define ENUM_USB_EP0_CSR_H_DISPING (_ADI_MSK(0x00000800,uint16_t)) /* DISPING: Do not issue PING */
|
|
|
|
#define BITM_USB_EP0_CSR_H_DATGLEN (_ADI_MSK(0x00000400,uint16_t)) /* Data Toggle Write Enable */
|
|
#define ENUM_USB_EP0_CSR_H_NO_DATGLEN (_ADI_MSK(0x00000000,uint16_t)) /* DATGLEN: Disable Write to DATGL */
|
|
#define ENUM_USB_EP0_CSR_H_DATGLEN (_ADI_MSK(0x00000400,uint16_t)) /* DATGLEN: Enable Write to DATGL */
|
|
|
|
#define BITM_USB_EP0_CSR_H_DATGL (_ADI_MSK(0x00000200,uint16_t)) /* Data Toggle */
|
|
#define ENUM_USB_EP0_CSR_H_NO_DATATGL (_ADI_MSK(0x00000000,uint16_t)) /* DATGL: DATA0 is Set */
|
|
#define ENUM_USB_EP0_CSR_H_DATATGL (_ADI_MSK(0x00000200,uint16_t)) /* DATGL: DATA1 is Set */
|
|
|
|
#define BITM_USB_EP0_CSR_H_FLUSHFIFO (_ADI_MSK(0x00000100,uint16_t)) /* Flush Endpoint FIFO */
|
|
#define ENUM_USB_EP0_CSR_H_NO_FLUSH (_ADI_MSK(0x00000000,uint16_t)) /* FLUSHFIFO: No Flush */
|
|
#define ENUM_USB_EP0_CSR_H_FLUSH (_ADI_MSK(0x00000100,uint16_t)) /* FLUSHFIFO: Flush Endpoint FIFO */
|
|
|
|
#define BITM_USB_EP0_CSR_H_NAKTO (_ADI_MSK(0x00000080,uint16_t)) /* NAK Timeout */
|
|
#define ENUM_USB_EP0_CSR_H_NO_NAKTO (_ADI_MSK(0x00000000,uint16_t)) /* NAKTO: No Status */
|
|
#define ENUM_USB_EP0_CSR_H_NAKTO (_ADI_MSK(0x00000080,uint16_t)) /* NAKTO: Endpoint Halted (NAK Timeout) */
|
|
|
|
#define BITM_USB_EP0_CSR_H_STATUSPKT (_ADI_MSK(0x00000040,uint16_t)) /* Status Packet */
|
|
#define ENUM_USB_EP0_CSR_H_NO_STATPKT (_ADI_MSK(0x00000000,uint16_t)) /* STATUSPKT: No Request */
|
|
#define ENUM_USB_EP0_CSR_H_STATPKT (_ADI_MSK(0x00000040,uint16_t)) /* STATUSPKT: Request Status Transaction */
|
|
|
|
#define BITM_USB_EP0_CSR_H_REQPKT (_ADI_MSK(0x00000020,uint16_t)) /* Request Packet */
|
|
#define ENUM_USB_EP0_CSR_H_NO_REQPKT (_ADI_MSK(0x00000000,uint16_t)) /* REQPKT: No Request */
|
|
#define ENUM_USB_EP0_CSR_H_REQPKT (_ADI_MSK(0x00000020,uint16_t)) /* REQPKT: Send IN Tokens to Device */
|
|
|
|
#define BITM_USB_EP0_CSR_H_TOERR (_ADI_MSK(0x00000010,uint16_t)) /* Timeout Error */
|
|
#define ENUM_USB_EP0_CSR_H_NO_TOERR (_ADI_MSK(0x00000000,uint16_t)) /* TOERR: No Status */
|
|
#define ENUM_USB_EP0_CSR_H_TOERR (_ADI_MSK(0x00000010,uint16_t)) /* TOERR: Timeout Error */
|
|
|
|
#define BITM_USB_EP0_CSR_H_SETUPPKT (_ADI_MSK(0x00000008,uint16_t)) /* Setup Packet */
|
|
#define ENUM_USB_EP0_CSR_H_NO_SETUPPKT (_ADI_MSK(0x00000000,uint16_t)) /* SETUPPKT: No Request */
|
|
#define ENUM_USB_EP0_CSR_H_SETUPPKT (_ADI_MSK(0x00000008,uint16_t)) /* SETUPPKT: Send SETUP token */
|
|
|
|
#define BITM_USB_EP0_CSR_H_RXSTALL (_ADI_MSK(0x00000004,uint16_t)) /* Rx Stall */
|
|
#define ENUM_USB_EP0_CSR_H_NO_RXSTALL (_ADI_MSK(0x00000000,uint16_t)) /* RXSTALL: No Status */
|
|
#define ENUM_USB_EP0_CSR_H_RXSTALL (_ADI_MSK(0x00000004,uint16_t)) /* RXSTALL: Stall Received from Device */
|
|
|
|
#define BITM_USB_EP0_CSR_H_TXPKTRDY (_ADI_MSK(0x00000002,uint16_t)) /* Tx Packet Ready */
|
|
#define ENUM_USB_EP0_CSR_H_NO_TXPKTRDY (_ADI_MSK(0x00000000,uint16_t)) /* TXPKTRDY: No Tx Packet */
|
|
#define ENUM_USB_EP0_CSR_H_TXPKTRDY (_ADI_MSK(0x00000002,uint16_t)) /* TXPKTRDY: Tx Packet in Endpoint FIFO */
|
|
|
|
#define BITM_USB_EP0_CSR_H_RXPKTRDY (_ADI_MSK(0x00000001,uint16_t)) /* Rx Packet Ready */
|
|
#define ENUM_USB_EP0_CSR_H_NO_RXPKTRDY (_ADI_MSK(0x00000000,uint16_t)) /* RXPKTRDY: No Rx Packet */
|
|
#define ENUM_USB_EP0_CSR_H_RXPKTRDY (_ADI_MSK(0x00000001,uint16_t)) /* RXPKTRDY: Rx Packet in Endpoint FIFO */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_EP_TXCSR_H Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_EP_TXCSR_H_AUTOSET 15 /* TxPkRdy Autoset Enable */
|
|
#define BITP_USB_EP_TXCSR_H_DMAREQEN 12 /* DMA Request Enable Tx EP */
|
|
#define BITP_USB_EP_TXCSR_H_FRCDATATGL 11 /* Force Data Toggle */
|
|
#define BITP_USB_EP_TXCSR_H_DMAREQMODE 10 /* DMA Mode Select */
|
|
#define BITP_USB_EP_TXCSR_H_DATGLEN 9 /* Data Toggle Write Enable */
|
|
#define BITP_USB_EP_TXCSR_H_DATGL 8 /* Data Toggle */
|
|
#define BITP_USB_EP_TXCSR_H_NAKTOINCMP 7 /* NAK Timeout Incomplete */
|
|
#define BITP_USB_EP_TXCSR_H_CLRDATATGL 6 /* Clear Endpoint Data Toggle */
|
|
#define BITP_USB_EP_TXCSR_H_RXSTALL 5 /* Rx STALL */
|
|
#define BITP_USB_EP_TXCSR_H_SETUPPKT 4 /* Setup Packet */
|
|
#define BITP_USB_EP_TXCSR_H_FLUSHFIFO 3 /* Flush Endpoint FIFO */
|
|
#define BITP_USB_EP_TXCSR_H_TXTOERR 2 /* Tx Timeout Error */
|
|
#define BITP_USB_EP_TXCSR_H_NEFIFO 1 /* Not Empty FIFO */
|
|
#define BITP_USB_EP_TXCSR_H_TXPKTRDY 0 /* Tx Packet Ready */
|
|
|
|
#define BITM_USB_EP_TXCSR_H_AUTOSET (_ADI_MSK(0x00008000,uint16_t)) /* TxPkRdy Autoset Enable */
|
|
#define ENUM_USB_EP_TXCSR_H_NO_AUTOSET (_ADI_MSK(0x00000000,uint16_t)) /* AUTOSET: Disable Autoset */
|
|
#define ENUM_USB_EP_TXCSR_H_AUTOSET (_ADI_MSK(0x00008000,uint16_t)) /* AUTOSET: Enable Autoset */
|
|
|
|
#define BITM_USB_EP_TXCSR_H_DMAREQEN (_ADI_MSK(0x00001000,uint16_t)) /* DMA Request Enable Tx EP */
|
|
#define ENUM_USB_EP_TXCSR_H_DMAREQDIS (_ADI_MSK(0x00000000,uint16_t)) /* DMAREQEN: Disable DMA Request */
|
|
#define ENUM_USB_EP_TXCSR_H_DMAREQEN (_ADI_MSK(0x00001000,uint16_t)) /* DMAREQEN: Enable DMA Request */
|
|
|
|
#define BITM_USB_EP_TXCSR_H_FRCDATATGL (_ADI_MSK(0x00000800,uint16_t)) /* Force Data Toggle */
|
|
#define ENUM_USB_EP_TXCSR_H_NO_FRCTGL (_ADI_MSK(0x00000000,uint16_t)) /* FRCDATATGL: No Action */
|
|
#define ENUM_USB_EP_TXCSR_H_FRCTGL (_ADI_MSK(0x00000800,uint16_t)) /* FRCDATATGL: Toggle Endpoint Data */
|
|
|
|
#define BITM_USB_EP_TXCSR_H_DMAREQMODE (_ADI_MSK(0x00000400,uint16_t)) /* DMA Mode Select */
|
|
#define ENUM_USB_EP_TXCSR_H_DMARQMODE0 (_ADI_MSK(0x00000000,uint16_t)) /* DMAREQMODE: DMA Request Mode 0 */
|
|
#define ENUM_USB_EP_TXCSR_H_DMARQMODE1 (_ADI_MSK(0x00000400,uint16_t)) /* DMAREQMODE: DMA Request Mode 1 */
|
|
|
|
#define BITM_USB_EP_TXCSR_H_DATGLEN (_ADI_MSK(0x00000200,uint16_t)) /* Data Toggle Write Enable */
|
|
#define ENUM_USB_EP_TXCSR_H_NO_DATGLEN (_ADI_MSK(0x00000000,uint16_t)) /* DATGLEN: Disable Write to DATGL */
|
|
#define ENUM_USB_EP_TXCSR_H_DATGLEN (_ADI_MSK(0x00000200,uint16_t)) /* DATGLEN: Enable Write to DATGL */
|
|
|
|
#define BITM_USB_EP_TXCSR_H_DATGL (_ADI_MSK(0x00000100,uint16_t)) /* Data Toggle */
|
|
#define ENUM_USB_EP_TXCSR_H_NO_DATGL (_ADI_MSK(0x00000000,uint16_t)) /* DATGL: DATA0 is set */
|
|
#define ENUM_USB_EP_TXCSR_H_DATGL (_ADI_MSK(0x00000100,uint16_t)) /* DATGL: DATA1 is set */
|
|
|
|
#define BITM_USB_EP_TXCSR_H_NAKTOINCMP (_ADI_MSK(0x00000080,uint16_t)) /* NAK Timeout Incomplete */
|
|
#define ENUM_USB_EP_TXCSR_H_NO_NAKTO (_ADI_MSK(0x00000000,uint16_t)) /* NAKTOINCMP: No Status */
|
|
#define ENUM_USB_EP_TXCSR_H_NAKTO (_ADI_MSK(0x00000080,uint16_t)) /* NAKTOINCMP: NAK Timeout Over Maximum */
|
|
|
|
#define BITM_USB_EP_TXCSR_H_CLRDATATGL (_ADI_MSK(0x00000040,uint16_t)) /* Clear Endpoint Data Toggle */
|
|
#define ENUM_USB_EP_TXCSR_H_NO_CLRTGL (_ADI_MSK(0x00000000,uint16_t)) /* CLRDATATGL: No Action */
|
|
#define ENUM_USB_EP_TXCSR_H_CLRTGL (_ADI_MSK(0x00000040,uint16_t)) /* CLRDATATGL: Reset EP Data Toggle to 0 */
|
|
|
|
#define BITM_USB_EP_TXCSR_H_RXSTALL (_ADI_MSK(0x00000020,uint16_t)) /* Rx STALL */
|
|
#define ENUM_USB_EP_TXCSR_H_NO_RXSTALL (_ADI_MSK(0x00000000,uint16_t)) /* RXSTALL: No Status */
|
|
#define ENUM_USB_EP_TXCSR_H_RXSTALL (_ADI_MSK(0x00000020,uint16_t)) /* RXSTALL: Stall Received from Device */
|
|
|
|
#define BITM_USB_EP_TXCSR_H_SETUPPKT (_ADI_MSK(0x00000010,uint16_t)) /* Setup Packet */
|
|
#define ENUM_USB_EP_TXCSR_H_NO_SETUPPK (_ADI_MSK(0x00000000,uint16_t)) /* SETUPPKT: No Request */
|
|
#define ENUM_USB_EP_TXCSR_H_SETUPPKT (_ADI_MSK(0x00000010,uint16_t)) /* SETUPPKT: Send SETUP Token */
|
|
|
|
#define BITM_USB_EP_TXCSR_H_FLUSHFIFO (_ADI_MSK(0x00000008,uint16_t)) /* Flush Endpoint FIFO */
|
|
#define ENUM_USB_EP_TXCSR_H_NO_FLUSH (_ADI_MSK(0x00000000,uint16_t)) /* FLUSHFIFO: No Flush */
|
|
#define ENUM_USB_EP_TXCSR_H_FLUSH (_ADI_MSK(0x00000008,uint16_t)) /* FLUSHFIFO: Flush endpoint FIFO */
|
|
|
|
#define BITM_USB_EP_TXCSR_H_TXTOERR (_ADI_MSK(0x00000004,uint16_t)) /* Tx Timeout Error */
|
|
#define ENUM_USB_EP_TXCSR_H_NO_TXTOERR (_ADI_MSK(0x00000000,uint16_t)) /* TXTOERR: No Status */
|
|
#define ENUM_USB_EP_TXCSR_H_TXTOERR (_ADI_MSK(0x00000004,uint16_t)) /* TXTOERR: Tx Timeout Error */
|
|
|
|
#define BITM_USB_EP_TXCSR_H_NEFIFO (_ADI_MSK(0x00000002,uint16_t)) /* Not Empty FIFO */
|
|
#define ENUM_USB_EP_TXCSR_H_NO_NEFIFO (_ADI_MSK(0x00000000,uint16_t)) /* NEFIFO: FIFO Empty */
|
|
#define ENUM_USB_EP_TXCSR_H_NEFIFO (_ADI_MSK(0x00000002,uint16_t)) /* NEFIFO: FIFO Not Empty */
|
|
|
|
#define BITM_USB_EP_TXCSR_H_TXPKTRDY (_ADI_MSK(0x00000001,uint16_t)) /* Tx Packet Ready */
|
|
#define ENUM_USB_EP_TXCSR_H_NO_PKTRDY (_ADI_MSK(0x00000000,uint16_t)) /* TXPKTRDY: No Tx Packet */
|
|
#define ENUM_USB_EP_TXCSR_H_PKTRDY (_ADI_MSK(0x00000001,uint16_t)) /* TXPKTRDY: Tx Packet in Endpoint FIFO */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_EP0_CSR_P Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_EP0_CSR_P_FLUSHFIFO 8 /* Flush Endpoint FIFO */
|
|
#define BITP_USB_EP0_CSR_P_SSETUPEND 7 /* Service Setup End */
|
|
#define BITP_USB_EP0_CSR_P_SPKTRDY 6 /* Service Rx Packet Ready */
|
|
#define BITP_USB_EP0_CSR_P_SENDSTALL 5 /* Send Stall */
|
|
#define BITP_USB_EP0_CSR_P_SETUPEND 4 /* Setup End */
|
|
#define BITP_USB_EP0_CSR_P_DATAEND 3 /* Data End */
|
|
#define BITP_USB_EP0_CSR_P_SENTSTALL 2 /* Sent Stall */
|
|
#define BITP_USB_EP0_CSR_P_TXPKTRDY 1 /* Tx Packet Ready */
|
|
#define BITP_USB_EP0_CSR_P_RXPKTRDY 0 /* Rx Packet Ready */
|
|
|
|
#define BITM_USB_EP0_CSR_P_FLUSHFIFO (_ADI_MSK(0x00000100,uint16_t)) /* Flush Endpoint FIFO */
|
|
#define ENUM_USB_EP0_CSR_P_NO_FLUSH (_ADI_MSK(0x00000000,uint16_t)) /* FLUSHFIFO: No Flush */
|
|
#define ENUM_USB_EP0_CSR_P_FLUSH (_ADI_MSK(0x00000100,uint16_t)) /* FLUSHFIFO: Flush Endpoint FIFO */
|
|
|
|
#define BITM_USB_EP0_CSR_P_SSETUPEND (_ADI_MSK(0x00000080,uint16_t)) /* Service Setup End */
|
|
#define ENUM_USB_EP0_CSR_P_NOSSETUPEND (_ADI_MSK(0x00000000,uint16_t)) /* SSETUPEND: No Action */
|
|
#define ENUM_USB_EP0_CSR_P_SSETUPEND (_ADI_MSK(0x00000080,uint16_t)) /* SSETUPEND: Clear SETUPEND Bit */
|
|
|
|
#define BITM_USB_EP0_CSR_P_SPKTRDY (_ADI_MSK(0x00000040,uint16_t)) /* Service Rx Packet Ready */
|
|
#define ENUM_USB_EP0_CSR_P_NO_SPKTRDY (_ADI_MSK(0x00000000,uint16_t)) /* SPKTRDY: No Action */
|
|
#define ENUM_USB_EP0_CSR_P_SPKTRDY (_ADI_MSK(0x00000040,uint16_t)) /* SPKTRDY: Clear RXPKTRDY Bit */
|
|
|
|
#define BITM_USB_EP0_CSR_P_SENDSTALL (_ADI_MSK(0x00000020,uint16_t)) /* Send Stall */
|
|
#define ENUM_USB_EP0_CSR_P_NO_STALL (_ADI_MSK(0x00000000,uint16_t)) /* SENDSTALL: No Action */
|
|
#define ENUM_USB_EP0_CSR_P_STALL (_ADI_MSK(0x00000020,uint16_t)) /* SENDSTALL: Terminate Current Transaction */
|
|
|
|
#define BITM_USB_EP0_CSR_P_SETUPEND (_ADI_MSK(0x00000010,uint16_t)) /* Setup End */
|
|
#define ENUM_USB_EP0_CSR_P_NO_SETUPEND (_ADI_MSK(0x00000000,uint16_t)) /* SETUPEND: No Status */
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#define ENUM_USB_EP0_CSR_P_SETUPEND (_ADI_MSK(0x00000010,uint16_t)) /* SETUPEND: Setup Ended before DATAEND */
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#define BITM_USB_EP0_CSR_P_DATAEND (_ADI_MSK(0x00000008,uint16_t)) /* Data End */
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#define ENUM_USB_EP0_CSR_P_NO_DATAEND (_ADI_MSK(0x00000000,uint16_t)) /* DATAEND: No Status */
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#define ENUM_USB_EP0_CSR_P_DATAEND (_ADI_MSK(0x00000008,uint16_t)) /* DATAEND: Data End Condition */
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#define BITM_USB_EP0_CSR_P_SENTSTALL (_ADI_MSK(0x00000004,uint16_t)) /* Sent Stall */
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#define ENUM_USB_EP0_CSR_P_NO_STALSNT (_ADI_MSK(0x00000000,uint16_t)) /* SENTSTALL: No Status */
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#define ENUM_USB_EP0_CSR_P_STALSNT (_ADI_MSK(0x00000004,uint16_t)) /* SENTSTALL: Transmitted STALL Handshake */
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#define BITM_USB_EP0_CSR_P_TXPKTRDY (_ADI_MSK(0x00000002,uint16_t)) /* Tx Packet Ready */
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#define ENUM_USB_EP0_CSR_P_NO_TXPKTRDY (_ADI_MSK(0x00000000,uint16_t)) /* TXPKTRDY: */
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#define ENUM_USB_EP0_CSR_P_TXPKTRDY (_ADI_MSK(0x00000002,uint16_t)) /* TXPKTRDY: Set this bit after loading a data packet into the FIFO */
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#define BITM_USB_EP0_CSR_P_RXPKTRDY (_ADI_MSK(0x00000001,uint16_t)) /* Rx Packet Ready */
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#define ENUM_USB_EP0_CSR_P_NO_PKTRDY (_ADI_MSK(0x00000000,uint16_t)) /* RXPKTRDY: No Rx Packet */
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#define ENUM_USB_EP0_CSR_P_PKTRDY (_ADI_MSK(0x00000001,uint16_t)) /* RXPKTRDY: Rx Packet in Endpoint FIFO */
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/* ------------------------------------------------------------------------------------------------------------------------
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USB_EP_TXCSR_P Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_USB_EP_TXCSR_P_AUTOSET 15 /* TxPkRdy Autoset Enable */
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#define BITP_USB_EP_TXCSR_P_ISO 14 /* Isochronous Transfers Enable */
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#define BITP_USB_EP_TXCSR_P_DMAREQEN 12 /* DMA Request Enable Tx EP */
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#define BITP_USB_EP_TXCSR_P_FRCDATATGL 11 /* Force Data Toggle */
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#define BITP_USB_EP_TXCSR_P_DMAREQMODE 10 /* DMA Mode Select */
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#define BITP_USB_EP_TXCSR_P_INCOMPTX 7 /* Incomplete Tx */
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#define BITP_USB_EP_TXCSR_P_CLRDATATGL 6 /* Clear Endpoint Data Toggle */
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#define BITP_USB_EP_TXCSR_P_SENTSTALL 5 /* Sent STALL */
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#define BITP_USB_EP_TXCSR_P_SENDSTALL 4 /* Send STALL */
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#define BITP_USB_EP_TXCSR_P_FLUSHFIFO 3 /* Flush Endpoint FIFO */
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#define BITP_USB_EP_TXCSR_P_URUNERR 2 /* Underrun Error */
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#define BITP_USB_EP_TXCSR_P_NEFIFO 1 /* Not Empty FIFO */
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#define BITP_USB_EP_TXCSR_P_TXPKTRDY 0 /* Tx Packet Ready */
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#define BITM_USB_EP_TXCSR_P_AUTOSET (_ADI_MSK(0x00008000,uint16_t)) /* TxPkRdy Autoset Enable */
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#define ENUM_USB_EP_TXCSR_P_NO_AUTOSET (_ADI_MSK(0x00000000,uint16_t)) /* AUTOSET: Disable Autoset */
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#define ENUM_USB_EP_TXCSR_P_AUTOSET (_ADI_MSK(0x00008000,uint16_t)) /* AUTOSET: Enable Autoset */
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#define BITM_USB_EP_TXCSR_P_ISO (_ADI_MSK(0x00004000,uint16_t)) /* Isochronous Transfers Enable */
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#define ENUM_USB_EP_TXCSR_P_ISODIS (_ADI_MSK(0x00000000,uint16_t)) /* ISO: Disable Tx EP Isochronous Transfers */
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#define ENUM_USB_EP_TXCSR_P_ISOEN (_ADI_MSK(0x00004000,uint16_t)) /* ISO: Enable Tx EP Isochronous Transfers */
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#define BITM_USB_EP_TXCSR_P_DMAREQEN (_ADI_MSK(0x00001000,uint16_t)) /* DMA Request Enable Tx EP */
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#define ENUM_USB_EP_TXCSR_P_DMAREQDIS (_ADI_MSK(0x00000000,uint16_t)) /* DMAREQEN: Disable DMA Request */
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#define ENUM_USB_EP_TXCSR_P_DMAREQEN (_ADI_MSK(0x00001000,uint16_t)) /* DMAREQEN: Enable DMA Request */
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#define BITM_USB_EP_TXCSR_P_FRCDATATGL (_ADI_MSK(0x00000800,uint16_t)) /* Force Data Toggle */
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#define ENUM_USB_EP_TXCSR_P_NO_FRCTGL (_ADI_MSK(0x00000000,uint16_t)) /* FRCDATATGL: No Action */
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#define ENUM_USB_EP_TXCSR_P_FRCTGL (_ADI_MSK(0x00000800,uint16_t)) /* FRCDATATGL: Toggle Endpoint Data */
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#define BITM_USB_EP_TXCSR_P_DMAREQMODE (_ADI_MSK(0x00000400,uint16_t)) /* DMA Mode Select */
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#define ENUM_USB_EP_TXCSR_P_DMARQMODE0 (_ADI_MSK(0x00000000,uint16_t)) /* DMAREQMODE: DMA Request Mode 0 */
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#define ENUM_USB_EP_TXCSR_P_DMARQMODE1 (_ADI_MSK(0x00000400,uint16_t)) /* DMAREQMODE: DMA Request Mode 1 */
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#define BITM_USB_EP_TXCSR_P_INCOMPTX (_ADI_MSK(0x00000080,uint16_t)) /* Incomplete Tx */
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#define ENUM_USB_EP_TXCSR_P_NO_INCOMP (_ADI_MSK(0x00000000,uint16_t)) /* INCOMPTX: No Status */
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#define ENUM_USB_EP_TXCSR_P_INCOMP (_ADI_MSK(0x00000080,uint16_t)) /* INCOMPTX: Incomplete Tx (Insufficient IN Tokens) */
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#define BITM_USB_EP_TXCSR_P_CLRDATATGL (_ADI_MSK(0x00000040,uint16_t)) /* Clear Endpoint Data Toggle */
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#define ENUM_USB_EP_TXCSR_P_NO_CLRTGL (_ADI_MSK(0x00000000,uint16_t)) /* CLRDATATGL: No Action */
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#define ENUM_USB_EP_TXCSR_P_CLRTGL (_ADI_MSK(0x00000040,uint16_t)) /* CLRDATATGL: Reset EP Data Toggle to 0 */
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#define BITM_USB_EP_TXCSR_P_SENTSTALL (_ADI_MSK(0x00000020,uint16_t)) /* Sent STALL */
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#define ENUM_USB_EP_TXCSR_P_NO_STALSNT (_ADI_MSK(0x00000000,uint16_t)) /* SENTSTALL: No Status */
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#define ENUM_USB_EP_TXCSR_P_STALSNT (_ADI_MSK(0x00000020,uint16_t)) /* SENTSTALL: STALL Handshake Transmitted */
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#define BITM_USB_EP_TXCSR_P_SENDSTALL (_ADI_MSK(0x00000010,uint16_t)) /* Send STALL */
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#define ENUM_USB_EP_TXCSR_P_NO_STALL (_ADI_MSK(0x00000000,uint16_t)) /* SENDSTALL: No Request */
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#define ENUM_USB_EP_TXCSR_P_STALL (_ADI_MSK(0x00000010,uint16_t)) /* SENDSTALL: Request STALL Handshake Transmission */
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#define BITM_USB_EP_TXCSR_P_FLUSHFIFO (_ADI_MSK(0x00000008,uint16_t)) /* Flush Endpoint FIFO */
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#define ENUM_USB_EP_TXCSR_P_NO_FLUSH (_ADI_MSK(0x00000000,uint16_t)) /* FLUSHFIFO: No Flush */
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#define ENUM_USB_EP_TXCSR_P_FLUSH (_ADI_MSK(0x00000008,uint16_t)) /* FLUSHFIFO: Flush endpoint FIFO */
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#define BITM_USB_EP_TXCSR_P_URUNERR (_ADI_MSK(0x00000004,uint16_t)) /* Underrun Error */
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#define ENUM_USB_EP_TXCSR_P_NO_URUNERR (_ADI_MSK(0x00000000,uint16_t)) /* URUNERR: No Status */
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#define ENUM_USB_EP_TXCSR_P_URUNERR (_ADI_MSK(0x00000004,uint16_t)) /* URUNERR: Underrun Error */
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#define BITM_USB_EP_TXCSR_P_NEFIFO (_ADI_MSK(0x00000002,uint16_t)) /* Not Empty FIFO */
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#define ENUM_USB_EP_TXCSR_P_NO_FIFONE (_ADI_MSK(0x00000000,uint16_t)) /* NEFIFO: FIFO Empty */
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#define ENUM_USB_EP_TXCSR_P_FIFONE (_ADI_MSK(0x00000002,uint16_t)) /* NEFIFO: FIFO Not Empty */
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#define BITM_USB_EP_TXCSR_P_TXPKTRDY (_ADI_MSK(0x00000001,uint16_t)) /* Tx Packet Ready */
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#define ENUM_USB_EP_TXCSR_P_NO_PKTRDY (_ADI_MSK(0x00000000,uint16_t)) /* TXPKTRDY: No Tx Packet */
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#define ENUM_USB_EP_TXCSR_P_PKTRDY (_ADI_MSK(0x00000001,uint16_t)) /* TXPKTRDY: Tx Packet in Endpoint FIFO */
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/* ------------------------------------------------------------------------------------------------------------------------
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USB_EP_RXMAXP Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_USB_EP_RXMAXP_MULTM1 11 /* Multi-Packets per Micro-frame */
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#define BITP_USB_EP_RXMAXP_MAXPAY 0 /* Maximum Payload */
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#define BITM_USB_EP_RXMAXP_MULTM1 (_ADI_MSK(0x00001800,uint16_t)) /* Multi-Packets per Micro-frame */
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#define BITM_USB_EP_RXMAXP_MAXPAY (_ADI_MSK(0x000007FF,uint16_t)) /* Maximum Payload */
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/* ------------------------------------------------------------------------------------------------------------------------
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USB_EP_RXCSR_H Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_USB_EP_RXCSR_H_AUTOCLR 15 /* Auto Clear Enable */
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#define BITP_USB_EP_RXCSR_H_AUTOREQ 14 /* Auto Request Clear Enable */
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#define BITP_USB_EP_RXCSR_H_DMAREQEN 13 /* DMA Request Enable Rx EP */
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#define BITP_USB_EP_RXCSR_H_PIDERR 12 /* Packet ID Error */
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#define BITP_USB_EP_RXCSR_H_DMAREQMODE 11 /* DMA Mode Select */
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#define BITP_USB_EP_RXCSR_H_DATGLEN 10 /* Data Toggle Write Enable */
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#define BITP_USB_EP_RXCSR_H_DATGL 9 /* Data Toggle */
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#define BITP_USB_EP_RXCSR_H_INCOMPRX 8 /* Incomplete Rx */
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#define BITP_USB_EP_RXCSR_H_CLRDATATGL 7 /* Clear Endpoint Data Toggle */
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#define BITP_USB_EP_RXCSR_H_RXSTALL 6 /* Rx STALL */
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#define BITP_USB_EP_RXCSR_H_REQPKT 5 /* Request Packet */
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#define BITP_USB_EP_RXCSR_H_FLUSHFIFO 4 /* Flush Endpoint FIFO */
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#define BITP_USB_EP_RXCSR_H_NAKTODERR 3 /* NAK Timeout Data Error */
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#define BITP_USB_EP_RXCSR_H_RXTOERR 2 /* Rx Timeout Error */
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#define BITP_USB_EP_RXCSR_H_FIFOFULL 1 /* FIFO Full */
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#define BITP_USB_EP_RXCSR_H_RXPKTRDY 0 /* Rx Packet Ready */
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#define BITM_USB_EP_RXCSR_H_AUTOCLR (_ADI_MSK(0x00008000,uint16_t)) /* Auto Clear Enable */
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#define ENUM_USB_EP_RXCSR_H_NO_AUTOCLR (_ADI_MSK(0x00000000,uint16_t)) /* AUTOCLR: Disable Auto Clear */
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#define ENUM_USB_EP_RXCSR_H_AUTOCLR (_ADI_MSK(0x00008000,uint16_t)) /* AUTOCLR: Enable Auto Clear */
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#define BITM_USB_EP_RXCSR_H_AUTOREQ (_ADI_MSK(0x00004000,uint16_t)) /* Auto Request Clear Enable */
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#define ENUM_USB_EP_RXCSR_H_NO_AUTOREQ (_ADI_MSK(0x00000000,uint16_t)) /* AUTOREQ: Disable Auto Request Clear */
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#define ENUM_USB_EP_RXCSR_H_AUTOREQ (_ADI_MSK(0x00004000,uint16_t)) /* AUTOREQ: Enable Auto Request Clear */
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#define BITM_USB_EP_RXCSR_H_DMAREQEN (_ADI_MSK(0x00002000,uint16_t)) /* DMA Request Enable Rx EP */
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#define ENUM_USB_EP_RXCSR_H_DMAREQDIS (_ADI_MSK(0x00000000,uint16_t)) /* DMAREQEN: Disable DMA Request */
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#define ENUM_USB_EP_RXCSR_H_DMAREQEN (_ADI_MSK(0x00002000,uint16_t)) /* DMAREQEN: Enable DMA Request */
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#define BITM_USB_EP_RXCSR_H_PIDERR (_ADI_MSK(0x00001000,uint16_t)) /* Packet ID Error */
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#define ENUM_USB_EP_RXCSR_H_NO_PIDERR (_ADI_MSK(0x00000000,uint16_t)) /* PIDERR: No Status */
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#define ENUM_USB_EP_RXCSR_H_PIDERR (_ADI_MSK(0x00001000,uint16_t)) /* PIDERR: PID Error */
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#define BITM_USB_EP_RXCSR_H_DMAREQMODE (_ADI_MSK(0x00000800,uint16_t)) /* DMA Mode Select */
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#define ENUM_USB_EP_RXCSR_H_DMARQMODE0 (_ADI_MSK(0x00000000,uint16_t)) /* DMAREQMODE: DMA Request Mode 0 */
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#define ENUM_USB_EP_RXCSR_H_DMARQMODE1 (_ADI_MSK(0x00000800,uint16_t)) /* DMAREQMODE: DMA Request Mode 1 */
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#define BITM_USB_EP_RXCSR_H_DATGLEN (_ADI_MSK(0x00000400,uint16_t)) /* Data Toggle Write Enable */
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#define ENUM_USB_EP_RXCSR_H_DATGLDIS (_ADI_MSK(0x00000000,uint16_t)) /* DATGLEN: Disable Write to DATGL */
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#define ENUM_USB_EP_RXCSR_H_DATGLEN (_ADI_MSK(0x00000400,uint16_t)) /* DATGLEN: Enable Write to DATGL */
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#define BITM_USB_EP_RXCSR_H_DATGL (_ADI_MSK(0x00000200,uint16_t)) /* Data Toggle */
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#define ENUM_USB_EP_RXCSR_H_NO_DATGL (_ADI_MSK(0x00000000,uint16_t)) /* DATGL: DATA0 is Set */
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#define ENUM_USB_EP_RXCSR_H_DATGL (_ADI_MSK(0x00000200,uint16_t)) /* DATGL: DATA1 is Set */
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#define BITM_USB_EP_RXCSR_H_INCOMPRX (_ADI_MSK(0x00000100,uint16_t)) /* Incomplete Rx */
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#define ENUM_USB_EP_RXCSR_H_NO_INCOMP (_ADI_MSK(0x00000000,uint16_t)) /* INCOMPRX: No Status */
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#define ENUM_USB_EP_RXCSR_H_INCOMP (_ADI_MSK(0x00000100,uint16_t)) /* INCOMPRX: Incomplete Rx */
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#define BITM_USB_EP_RXCSR_H_CLRDATATGL (_ADI_MSK(0x00000080,uint16_t)) /* Clear Endpoint Data Toggle */
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#define ENUM_USB_EP_RXCSR_H_NO_CLRTGL (_ADI_MSK(0x00000000,uint16_t)) /* CLRDATATGL: No Action */
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#define ENUM_USB_EP_RXCSR_H_CLRTGL (_ADI_MSK(0x00000080,uint16_t)) /* CLRDATATGL: Reset EP Data Toggle to 0 */
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#define BITM_USB_EP_RXCSR_H_RXSTALL (_ADI_MSK(0x00000040,uint16_t)) /* Rx STALL */
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#define ENUM_USB_EP_RXCSR_H_NO_RXSTALL (_ADI_MSK(0x00000000,uint16_t)) /* RXSTALL: No Status */
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#define ENUM_USB_EP_RXCSR_H_RXSTALL (_ADI_MSK(0x00000040,uint16_t)) /* RXSTALL: Stall Received from Device */
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#define BITM_USB_EP_RXCSR_H_REQPKT (_ADI_MSK(0x00000020,uint16_t)) /* Request Packet */
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#define ENUM_USB_EP_RXCSR_H_NO_REQPKT (_ADI_MSK(0x00000000,uint16_t)) /* REQPKT: No Request */
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#define ENUM_USB_EP_RXCSR_H_REQPKT (_ADI_MSK(0x00000020,uint16_t)) /* REQPKT: Send IN Tokens to Device */
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#define BITM_USB_EP_RXCSR_H_FLUSHFIFO (_ADI_MSK(0x00000010,uint16_t)) /* Flush Endpoint FIFO */
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#define ENUM_USB_EP_RXCSR_H_NO_FLUSH (_ADI_MSK(0x00000000,uint16_t)) /* FLUSHFIFO: No Flush */
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#define ENUM_USB_EP_RXCSR_H_FLUSH (_ADI_MSK(0x00000010,uint16_t)) /* FLUSHFIFO: Flush Endpoint FIFO */
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#define BITM_USB_EP_RXCSR_H_NAKTODERR (_ADI_MSK(0x00000008,uint16_t)) /* NAK Timeout Data Error */
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#define ENUM_USB_EP_RXCSR_H_NO_NAKTO (_ADI_MSK(0x00000000,uint16_t)) /* NAKTODERR: No Status */
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#define ENUM_USB_EP_RXCSR_H_NAKTO (_ADI_MSK(0x00000008,uint16_t)) /* NAKTODERR: NAK Timeout Data Error */
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#define BITM_USB_EP_RXCSR_H_RXTOERR (_ADI_MSK(0x00000004,uint16_t)) /* Rx Timeout Error */
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#define ENUM_USB_EP_RXCSR_H_NO_RXTOERR (_ADI_MSK(0x00000000,uint16_t)) /* RXTOERR: No Status */
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#define ENUM_USB_EP_RXCSR_H_RXTOERR (_ADI_MSK(0x00000004,uint16_t)) /* RXTOERR: Rx Timeout Error */
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#define BITM_USB_EP_RXCSR_H_FIFOFULL (_ADI_MSK(0x00000002,uint16_t)) /* FIFO Full */
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#define ENUM_USB_EP_RXCSR_H_NO_FIFOFUL (_ADI_MSK(0x00000000,uint16_t)) /* FIFOFULL: No Status */
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#define ENUM_USB_EP_RXCSR_H_FIFOFUL (_ADI_MSK(0x00000002,uint16_t)) /* FIFOFULL: FIFO Full */
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#define BITM_USB_EP_RXCSR_H_RXPKTRDY (_ADI_MSK(0x00000001,uint16_t)) /* Rx Packet Ready */
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#define ENUM_USB_EP_RXCSR_H_NO_PKTRDY (_ADI_MSK(0x00000000,uint16_t)) /* RXPKTRDY: No Rx Packet */
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#define ENUM_USB_EP_RXCSR_H_PKTRDY (_ADI_MSK(0x00000001,uint16_t)) /* RXPKTRDY: Rx Packet in Endpoint FIFO */
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/* ------------------------------------------------------------------------------------------------------------------------
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USB_EP_RXCSR_P Pos/Masks Description
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------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_USB_EP_RXCSR_P_AUTOCLR 15 /* Auto Clear Enable */
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#define BITP_USB_EP_RXCSR_P_ISO 14 /* Isochronous Transfers */
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#define BITP_USB_EP_RXCSR_P_DMAREQEN 13 /* DMA Request Enable Rx EP */
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#define BITP_USB_EP_RXCSR_P_DNYETPERR 12 /* Disable NYET Handshake */
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#define BITP_USB_EP_RXCSR_P_DMAREQMODE 11 /* DMA Mode Select */
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#define BITP_USB_EP_RXCSR_P_INCOMPRX 8 /* Incomplete Rx */
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#define BITP_USB_EP_RXCSR_P_CLRDATATGL 7 /* Clear Endpoint Data Toggle */
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#define BITP_USB_EP_RXCSR_P_SENTSTALL 6 /* Sent STALL */
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#define BITP_USB_EP_RXCSR_P_SENDSTALL 5 /* Send STALL */
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#define BITP_USB_EP_RXCSR_P_FLUSHFIFO 4 /* Flush Endpoint FIFO */
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#define BITP_USB_EP_RXCSR_P_DATAERR 3 /* Data Error */
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#define BITP_USB_EP_RXCSR_P_ORUNERR 2 /* OUT Run Error */
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#define BITP_USB_EP_RXCSR_P_FIFOFULL 1 /* FIFO Full */
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#define BITP_USB_EP_RXCSR_P_RXPKTRDY 0 /* Rx Packet Ready */
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#define BITM_USB_EP_RXCSR_P_AUTOCLR (_ADI_MSK(0x00008000,uint16_t)) /* Auto Clear Enable */
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#define ENUM_USB_EP_RXCSR_P_NO_AUTOCLR (_ADI_MSK(0x00000000,uint16_t)) /* AUTOCLR: Disable Auto Clear */
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#define ENUM_USB_EP_RXCSR_P_AUTOCLR (_ADI_MSK(0x00008000,uint16_t)) /* AUTOCLR: Enable Auto Clear */
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#define BITM_USB_EP_RXCSR_P_ISO (_ADI_MSK(0x00004000,uint16_t)) /* Isochronous Transfers */
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#define ENUM_USB_EP_RXCSR_P_ISODIS (_ADI_MSK(0x00000000,uint16_t)) /* ISO: This bit should be cleared for bulk or interrupt transfers. */
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#define ENUM_USB_EP_RXCSR_P_ISOEN (_ADI_MSK(0x00004000,uint16_t)) /* ISO: This bit should be set for isochronous transfers. */
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#define BITM_USB_EP_RXCSR_P_DMAREQEN (_ADI_MSK(0x00002000,uint16_t)) /* DMA Request Enable Rx EP */
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#define ENUM_USB_EP_RXCSR_P_DMAREQDIS (_ADI_MSK(0x00000000,uint16_t)) /* DMAREQEN: Disable DMA Request */
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#define ENUM_USB_EP_RXCSR_P_DMAREQEN (_ADI_MSK(0x00002000,uint16_t)) /* DMAREQEN: Enable DMA Request */
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#define BITM_USB_EP_RXCSR_P_DNYETPERR (_ADI_MSK(0x00001000,uint16_t)) /* Disable NYET Handshake */
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#define ENUM_USB_EP_RXCSR_P_DNYTERREN (_ADI_MSK(0x00000000,uint16_t)) /* DNYETPERR: Enable NYET Handshake */
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#define ENUM_USB_EP_RXCSR_P_DNYTERRDIS (_ADI_MSK(0x00001000,uint16_t)) /* DNYETPERR: Disable NYET Handshake */
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#define BITM_USB_EP_RXCSR_P_DMAREQMODE (_ADI_MSK(0x00000800,uint16_t)) /* DMA Mode Select */
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#define ENUM_USB_EP_RXCSR_P_DMARQMODE0 (_ADI_MSK(0x00000000,uint16_t)) /* DMAREQMODE: DMA Request Mode 0 */
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#define ENUM_USB_EP_RXCSR_P_DMARQMODE1 (_ADI_MSK(0x00000800,uint16_t)) /* DMAREQMODE: DMA Request Mode 1 */
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#define BITM_USB_EP_RXCSR_P_INCOMPRX (_ADI_MSK(0x00000100,uint16_t)) /* Incomplete Rx */
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#define ENUM_USB_EP_RXCSR_P_NO_INCOMP (_ADI_MSK(0x00000000,uint16_t)) /* INCOMPRX: No Status */
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#define ENUM_USB_EP_RXCSR_P_INCOMP (_ADI_MSK(0x00000100,uint16_t)) /* INCOMPRX: Incomplete Rx */
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#define BITM_USB_EP_RXCSR_P_CLRDATATGL (_ADI_MSK(0x00000080,uint16_t)) /* Clear Endpoint Data Toggle */
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#define ENUM_USB_EP_RXCSR_P_NO_CLRTGL (_ADI_MSK(0x00000000,uint16_t)) /* CLRDATATGL: No Action */
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#define ENUM_USB_EP_RXCSR_P_CLRTGL (_ADI_MSK(0x00000080,uint16_t)) /* CLRDATATGL: Reset EP Data Toggle to 0 */
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#define BITM_USB_EP_RXCSR_P_SENTSTALL (_ADI_MSK(0x00000040,uint16_t)) /* Sent STALL */
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#define ENUM_USB_EP_RXCSR_P_NO_STALSNT (_ADI_MSK(0x00000000,uint16_t)) /* SENTSTALL: No Status */
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#define ENUM_USB_EP_RXCSR_P_STALSNT (_ADI_MSK(0x00000040,uint16_t)) /* SENTSTALL: STALL Handshake Transmitted */
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#define BITM_USB_EP_RXCSR_P_SENDSTALL (_ADI_MSK(0x00000020,uint16_t)) /* Send STALL */
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#define ENUM_USB_EP_RXCSR_P_NO_STALL (_ADI_MSK(0x00000000,uint16_t)) /* SENDSTALL: No Action */
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#define ENUM_USB_EP_RXCSR_P_STALL (_ADI_MSK(0x00000020,uint16_t)) /* SENDSTALL: Request STALL Handshake */
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#define BITM_USB_EP_RXCSR_P_FLUSHFIFO (_ADI_MSK(0x00000010,uint16_t)) /* Flush Endpoint FIFO */
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#define ENUM_USB_EP_RXCSR_P_NO_FLUSH (_ADI_MSK(0x00000000,uint16_t)) /* FLUSHFIFO: No Flush */
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#define ENUM_USB_EP_RXCSR_P_FLUSH (_ADI_MSK(0x00000010,uint16_t)) /* FLUSHFIFO: Flush Endpoint FIFO */
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#define BITM_USB_EP_RXCSR_P_DATAERR (_ADI_MSK(0x00000008,uint16_t)) /* Data Error */
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#define ENUM_USB_EP_RXCSR_P_NO_DATAERR (_ADI_MSK(0x00000000,uint16_t)) /* DATAERR: No Status */
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#define ENUM_USB_EP_RXCSR_P_DATAERR (_ADI_MSK(0x00000008,uint16_t)) /* DATAERR: Data Error */
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#define BITM_USB_EP_RXCSR_P_ORUNERR (_ADI_MSK(0x00000004,uint16_t)) /* OUT Run Error */
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#define ENUM_USB_EP_RXCSR_P_NO_ORUNERR (_ADI_MSK(0x00000000,uint16_t)) /* ORUNERR: No Status */
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#define ENUM_USB_EP_RXCSR_P_ORUNERR (_ADI_MSK(0x00000004,uint16_t)) /* ORUNERR: OUT Run Error */
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#define BITM_USB_EP_RXCSR_P_FIFOFULL (_ADI_MSK(0x00000002,uint16_t)) /* FIFO Full */
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#define ENUM_USB_EP_RXCSR_P_NO_FIFOFUL (_ADI_MSK(0x00000000,uint16_t)) /* FIFOFULL: No Status */
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#define ENUM_USB_EP_RXCSR_P_FIFOFUL (_ADI_MSK(0x00000002,uint16_t)) /* FIFOFULL: FIFO Full */
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#define BITM_USB_EP_RXCSR_P_RXPKTRDY (_ADI_MSK(0x00000001,uint16_t)) /* Rx Packet Ready */
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#define ENUM_USB_EP_RXCSR_P_NO_PKTRDY (_ADI_MSK(0x00000000,uint16_t)) /* RXPKTRDY: No Rx Packet */
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#define ENUM_USB_EP_RXCSR_P_PKTRDY (_ADI_MSK(0x00000001,uint16_t)) /* RXPKTRDY: Rx Packet in Endpoint FIFO */
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/* ------------------------------------------------------------------------------------------------------------------------
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|
USB_EP0_CNT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_USB_EP0_CNT_RXCNT 0 /* Rx Byte Count Value */
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#define BITM_USB_EP0_CNT_RXCNT (_ADI_MSK(0x0000007F,uint16_t)) /* Rx Byte Count Value */
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/* ------------------------------------------------------------------------------------------------------------------------
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USB_EP_RXCNT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_USB_EP_RXCNT_EPRXCNT 0 /* EP Rx Count */
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#define BITM_USB_EP_RXCNT_EPRXCNT (_ADI_MSK(0x00003FFF,uint16_t)) /* EP Rx Count */
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_EP0_TYPE Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_USB_EP0_TYPE_SPEED 0 /* Speed of Operation Value */
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#define BITM_USB_EP0_TYPE_SPEED (_ADI_MSK(0x00000003,uint8_t)) /* Speed of Operation Value */
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_EP_TXTYPE Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
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#define BITP_USB_EP_TXTYPE_SPEED 6 /* Speed of Operation Value */
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#define BITP_USB_EP_TXTYPE_PROTOCOL 4 /* Protocol for Transfer */
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#define BITP_USB_EP_TXTYPE_TGTEP 0 /* Target Endpoint Number */
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#define BITM_USB_EP_TXTYPE_SPEED (_ADI_MSK(0x000000C0,uint8_t)) /* Speed of Operation Value */
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#define ENUM_USB_EP_TXTYPE_UNUSED (_ADI_MSK(0x00000000,uint8_t)) /* SPEED: Same Speed as the Core */
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#define ENUM_USB_EP_TXTYPE_HIGHSPEED (_ADI_MSK(0x00000040,uint8_t)) /* SPEED: High Speed */
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#define ENUM_USB_EP_TXTYPE_FULLSPEED (_ADI_MSK(0x00000080,uint8_t)) /* SPEED: Full Speed */
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#define ENUM_USB_EP_TXTYPE_LOWSPEED (_ADI_MSK(0x000000C0,uint8_t)) /* SPEED: Low Speed */
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#define BITM_USB_EP_TXTYPE_PROTOCOL (_ADI_MSK(0x00000030,uint8_t)) /* Protocol for Transfer */
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#define ENUM_USB_EP_TXTYPE_CONTROL (_ADI_MSK(0x00000000,uint8_t)) /* PROTOCOL: Control */
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#define ENUM_USB_EP_TXTYPE_ISO (_ADI_MSK(0x00000010,uint8_t)) /* PROTOCOL: Isochronous */
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#define ENUM_USB_EP_TXTYPE_BULK (_ADI_MSK(0x00000020,uint8_t)) /* PROTOCOL: Bulk */
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#define ENUM_USB_EP_TXTYPE_INT (_ADI_MSK(0x00000030,uint8_t)) /* PROTOCOL: Interrupt */
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#define BITM_USB_EP_TXTYPE_TGTEP (_ADI_MSK(0x0000000F,uint8_t)) /* Target Endpoint Number */
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#define ENUM_USB_EP_TXTYPE_TGTEP0 (_ADI_MSK(0x00000000,uint8_t)) /* TGTEP: Endpoint 0 */
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#define ENUM_USB_EP_TXTYPE_TGTEP1 (_ADI_MSK(0x00000001,uint8_t)) /* TGTEP: Endpoint 1 */
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#define ENUM_USB_EP_TXTYPE_TGTEP10 (_ADI_MSK(0x0000000A,uint8_t)) /* TGTEP: Endpoint 10 */
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#define ENUM_USB_EP_TXTYPE_TGTEP11 (_ADI_MSK(0x0000000B,uint8_t)) /* TGTEP: Endpoint 11 */
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#define ENUM_USB_EP_TXTYPE_TGTEP12 (_ADI_MSK(0x0000000C,uint8_t)) /* TGTEP: Endpoint 12 */
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#define ENUM_USB_EP_TXTYPE_TGTEP13 (_ADI_MSK(0x0000000D,uint8_t)) /* TGTEP: Endpoint 13 */
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#define ENUM_USB_EP_TXTYPE_TGTEP14 (_ADI_MSK(0x0000000E,uint8_t)) /* TGTEP: Endpoint 14 */
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#define ENUM_USB_EP_TXTYPE_TGTEP15 (_ADI_MSK(0x0000000F,uint8_t)) /* TGTEP: Endpoint 15 */
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#define ENUM_USB_EP_TXTYPE_TGTEP2 (_ADI_MSK(0x00000002,uint8_t)) /* TGTEP: Endpoint 2 */
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#define ENUM_USB_EP_TXTYPE_TGTEP3 (_ADI_MSK(0x00000003,uint8_t)) /* TGTEP: Endpoint 3 */
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#define ENUM_USB_EP_TXTYPE_TGTEP4 (_ADI_MSK(0x00000004,uint8_t)) /* TGTEP: Endpoint 4 */
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#define ENUM_USB_EP_TXTYPE_TGTEP5 (_ADI_MSK(0x00000005,uint8_t)) /* TGTEP: Endpoint 5 */
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|
#define ENUM_USB_EP_TXTYPE_TGTEP6 (_ADI_MSK(0x00000006,uint8_t)) /* TGTEP: Endpoint 6 */
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|
#define ENUM_USB_EP_TXTYPE_TGTEP7 (_ADI_MSK(0x00000007,uint8_t)) /* TGTEP: Endpoint 7 */
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#define ENUM_USB_EP_TXTYPE_TGTEP8 (_ADI_MSK(0x00000008,uint8_t)) /* TGTEP: Endpoint 8 */
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|
#define ENUM_USB_EP_TXTYPE_TGTEP9 (_ADI_MSK(0x00000009,uint8_t)) /* TGTEP: Endpoint 9 */
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|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_EP0_NAKLIMIT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_EP0_NAKLIMIT_VALUE 0 /* Endpoint 0 Timeout Value (in Frames) */
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|
#define BITM_USB_EP0_NAKLIMIT_VALUE (_ADI_MSK(0x0000001F,uint8_t)) /* Endpoint 0 Timeout Value (in Frames) */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_EP_RXTYPE Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_EP_RXTYPE_SPEED 6 /* Speed of Operation Value */
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|
#define BITP_USB_EP_RXTYPE_PROTOCOL 4 /* Protocol for Transfer */
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|
#define BITP_USB_EP_RXTYPE_TGTEP 0 /* Target Endpoint Number */
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|
|
#define BITM_USB_EP_RXTYPE_SPEED (_ADI_MSK(0x000000C0,uint8_t)) /* Speed of Operation Value */
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|
#define ENUM_USB_EP_RXTYPE_UNUSED (_ADI_MSK(0x00000000,uint8_t)) /* SPEED: Same Speed as the Core */
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|
#define ENUM_USB_EP_RXTYPE_HIGHSPEED (_ADI_MSK(0x00000040,uint8_t)) /* SPEED: High Speed */
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|
#define ENUM_USB_EP_RXTYPE_FULLSPEED (_ADI_MSK(0x00000080,uint8_t)) /* SPEED: Full Speed */
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#define ENUM_USB_EP_RXTYPE_LOWSPEED (_ADI_MSK(0x000000C0,uint8_t)) /* SPEED: Low Speed */
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#define BITM_USB_EP_RXTYPE_PROTOCOL (_ADI_MSK(0x00000030,uint8_t)) /* Protocol for Transfer */
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#define ENUM_USB_EP_RXTYPE_CONTROL (_ADI_MSK(0x00000000,uint8_t)) /* PROTOCOL: Control */
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#define ENUM_USB_EP_RXTYPE_ISO (_ADI_MSK(0x00000010,uint8_t)) /* PROTOCOL: Isochronous */
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#define ENUM_USB_EP_RXTYPE_BULK (_ADI_MSK(0x00000020,uint8_t)) /* PROTOCOL: Bulk */
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#define ENUM_USB_EP_RXTYPE_INT (_ADI_MSK(0x00000030,uint8_t)) /* PROTOCOL: Interrupt */
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#define BITM_USB_EP_RXTYPE_TGTEP (_ADI_MSK(0x0000000F,uint8_t)) /* Target Endpoint Number */
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#define ENUM_USB_EP_RXTYPE_TGTEP0 (_ADI_MSK(0x00000000,uint8_t)) /* TGTEP: Endpoint 0 */
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#define ENUM_USB_EP_RXTYPE_TGTEP1 (_ADI_MSK(0x00000001,uint8_t)) /* TGTEP: Endpoint 1 */
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#define ENUM_USB_EP_RXTYPE_TGTEP10 (_ADI_MSK(0x0000000A,uint8_t)) /* TGTEP: Endpoint 10 */
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#define ENUM_USB_EP_RXTYPE_TGTEP11 (_ADI_MSK(0x0000000B,uint8_t)) /* TGTEP: Endpoint 11 */
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#define ENUM_USB_EP_RXTYPE_TGTEP12 (_ADI_MSK(0x0000000C,uint8_t)) /* TGTEP: Endpoint 12 */
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#define ENUM_USB_EP_RXTYPE_TGTEP13 (_ADI_MSK(0x0000000D,uint8_t)) /* TGTEP: Endpoint 13 */
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#define ENUM_USB_EP_RXTYPE_TGTEP14 (_ADI_MSK(0x0000000E,uint8_t)) /* TGTEP: Endpoint 14 */
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#define ENUM_USB_EP_RXTYPE_TGTEP15 (_ADI_MSK(0x0000000F,uint8_t)) /* TGTEP: Endpoint 15 */
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#define ENUM_USB_EP_RXTYPE_TGTEP2 (_ADI_MSK(0x00000002,uint8_t)) /* TGTEP: Endpoint 2 */
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#define ENUM_USB_EP_RXTYPE_TGTEP3 (_ADI_MSK(0x00000003,uint8_t)) /* TGTEP: Endpoint 3 */
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#define ENUM_USB_EP_RXTYPE_TGTEP4 (_ADI_MSK(0x00000004,uint8_t)) /* TGTEP: Endpoint 4 */
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#define ENUM_USB_EP_RXTYPE_TGTEP5 (_ADI_MSK(0x00000005,uint8_t)) /* TGTEP: Endpoint 5 */
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#define ENUM_USB_EP_RXTYPE_TGTEP6 (_ADI_MSK(0x00000006,uint8_t)) /* TGTEP: Endpoint 6 */
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#define ENUM_USB_EP_RXTYPE_TGTEP7 (_ADI_MSK(0x00000007,uint8_t)) /* TGTEP: Endpoint 7 */
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#define ENUM_USB_EP_RXTYPE_TGTEP8 (_ADI_MSK(0x00000008,uint8_t)) /* TGTEP: Endpoint 8 */
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#define ENUM_USB_EP_RXTYPE_TGTEP9 (_ADI_MSK(0x00000009,uint8_t)) /* TGTEP: Endpoint 9 */
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/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_EP0_CFGDATA Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_EP0_CFGDATA_MPRX 7 /* Multi-Packet Aggregate for Rx Enable */
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|
#define BITP_USB_EP0_CFGDATA_MPTX 6 /* Multi-Packet Split for Tx Enable */
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#define BITP_USB_EP0_CFGDATA_BIGEND 5 /* Big Endian Data */
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#define BITP_USB_EP0_CFGDATA_HBRX 4 /* High Bandwidth Rx Enable */
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|
#define BITP_USB_EP0_CFGDATA_HBTX 3 /* High Bandwidth Tx Enable */
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|
#define BITP_USB_EP0_CFGDATA_DYNFIFO 2 /* Dynamic FIFO Size Enable */
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#define BITP_USB_EP0_CFGDATA_SOFTCON 1 /* Soft Connect Enable */
|
|
#define BITP_USB_EP0_CFGDATA_UTMIWID 0 /* UTMI Data Width */
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|
|
|
#define BITM_USB_EP0_CFGDATA_MPRX (_ADI_MSK(0x00000080,uint8_t)) /* Multi-Packet Aggregate for Rx Enable */
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#define ENUM_USB_EP0_CFGDATA_MPRXDIS (_ADI_MSK(0x00000000,uint8_t)) /* MPRX: No Aggregate Rx Bulk Packets */
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#define ENUM_USB_EP0_CFGDATA_MPRXEN (_ADI_MSK(0x00000080,uint8_t)) /* MPRX: Aggregate Rx Bulk Packets */
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#define BITM_USB_EP0_CFGDATA_MPTX (_ADI_MSK(0x00000040,uint8_t)) /* Multi-Packet Split for Tx Enable */
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#define ENUM_USB_EP0_CFGDATA_MPTXDIS (_ADI_MSK(0x00000000,uint8_t)) /* MPTX: No Split Tx Bulk Packets */
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|
#define ENUM_USB_EP0_CFGDATA_MPTXEN (_ADI_MSK(0x00000040,uint8_t)) /* MPTX: Split Tx Bulk Packets */
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|
|
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#define BITM_USB_EP0_CFGDATA_BIGEND (_ADI_MSK(0x00000020,uint8_t)) /* Big Endian Data */
|
|
#define ENUM_USB_EP0_CFGDATA_BIGENDDIS (_ADI_MSK(0x00000000,uint8_t)) /* BIGEND: Little Endian Configuration */
|
|
#define ENUM_USB_EP0_CFGDATA_BIGENDEN (_ADI_MSK(0x00000020,uint8_t)) /* BIGEND: Big Endian Configuration */
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|
|
|
#define BITM_USB_EP0_CFGDATA_HBRX (_ADI_MSK(0x00000010,uint8_t)) /* High Bandwidth Rx Enable */
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|
#define ENUM_USB_EP0_CFGDATA_HBRXDIS (_ADI_MSK(0x00000000,uint8_t)) /* HBRX: No High Bandwidth Rx */
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#define ENUM_USB_EP0_CFGDATA_HBRXEN (_ADI_MSK(0x00000010,uint8_t)) /* HBRX: High Bandwidth Rx */
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|
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#define BITM_USB_EP0_CFGDATA_HBTX (_ADI_MSK(0x00000008,uint8_t)) /* High Bandwidth Tx Enable */
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#define ENUM_USB_EP0_CFGDATA_HBTXDIS (_ADI_MSK(0x00000000,uint8_t)) /* HBTX: No High Bandwidth Tx */
|
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#define ENUM_USB_EP0_CFGDATA_HBTXEN (_ADI_MSK(0x00000008,uint8_t)) /* HBTX: High Bandwidth Tx */
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|
|
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#define BITM_USB_EP0_CFGDATA_DYNFIFO (_ADI_MSK(0x00000004,uint8_t)) /* Dynamic FIFO Size Enable */
|
|
#define ENUM_USB_EP0_CFGDATA_DYNSZDIS (_ADI_MSK(0x00000000,uint8_t)) /* DYNFIFO: No Dynamic FIFO Size */
|
|
#define ENUM_USB_EP0_CFGDATA_DYNSZEN (_ADI_MSK(0x00000004,uint8_t)) /* DYNFIFO: Dynamic FIFO Size */
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|
|
|
#define BITM_USB_EP0_CFGDATA_SOFTCON (_ADI_MSK(0x00000002,uint8_t)) /* Soft Connect Enable */
|
|
#define ENUM_USB_EP0_CFGDATA_SFTCONDIS (_ADI_MSK(0x00000000,uint8_t)) /* SOFTCON: No Soft Connect */
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#define ENUM_USB_EP0_CFGDATA_SFTCONEN (_ADI_MSK(0x00000002,uint8_t)) /* SOFTCON: Soft Connect */
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|
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|
#define BITM_USB_EP0_CFGDATA_UTMIWID (_ADI_MSK(0x00000001,uint8_t)) /* UTMI Data Width */
|
|
#define ENUM_USB_EP0_CFGDATA_UTMIWID8 (_ADI_MSK(0x00000000,uint8_t)) /* UTMIWID: 8-bit UTMI Data Width */
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#define ENUM_USB_EP0_CFGDATA_UTMIWID16 (_ADI_MSK(0x00000001,uint8_t)) /* UTMIWID: 16-bit UTMI Data Width */
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|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_DMA_IRQ Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_DMA_IRQ_D7 7 /* DMA 7 Interrupt Pending Status */
|
|
#define BITP_USB_DMA_IRQ_D6 6 /* DMA 6 Interrupt Pending Status */
|
|
#define BITP_USB_DMA_IRQ_D5 5 /* DMA 5 Interrupt Pending Status */
|
|
#define BITP_USB_DMA_IRQ_D4 4 /* DMA 4 Interrupt Pending Status */
|
|
#define BITP_USB_DMA_IRQ_D3 3 /* DMA 3 Interrupt Pending Status */
|
|
#define BITP_USB_DMA_IRQ_D2 2 /* DMA 2 Interrupt Pending Status */
|
|
#define BITP_USB_DMA_IRQ_D1 1 /* DMA 1 Interrupt Pending Status */
|
|
#define BITP_USB_DMA_IRQ_D0 0 /* DMA 0 Interrupt Pending Status */
|
|
#define BITM_USB_DMA_IRQ_D7 (_ADI_MSK(0x00000080,uint8_t)) /* DMA 7 Interrupt Pending Status */
|
|
#define BITM_USB_DMA_IRQ_D6 (_ADI_MSK(0x00000040,uint8_t)) /* DMA 6 Interrupt Pending Status */
|
|
#define BITM_USB_DMA_IRQ_D5 (_ADI_MSK(0x00000020,uint8_t)) /* DMA 5 Interrupt Pending Status */
|
|
#define BITM_USB_DMA_IRQ_D4 (_ADI_MSK(0x00000010,uint8_t)) /* DMA 4 Interrupt Pending Status */
|
|
#define BITM_USB_DMA_IRQ_D3 (_ADI_MSK(0x00000008,uint8_t)) /* DMA 3 Interrupt Pending Status */
|
|
#define BITM_USB_DMA_IRQ_D2 (_ADI_MSK(0x00000004,uint8_t)) /* DMA 2 Interrupt Pending Status */
|
|
#define BITM_USB_DMA_IRQ_D1 (_ADI_MSK(0x00000002,uint8_t)) /* DMA 1 Interrupt Pending Status */
|
|
#define BITM_USB_DMA_IRQ_D0 (_ADI_MSK(0x00000001,uint8_t)) /* DMA 0 Interrupt Pending Status */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_DMA_CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_DMA_CTL_BRSTM 9 /* Burst Mode */
|
|
#define BITP_USB_DMA_CTL_ERR 8 /* Bus Error */
|
|
#define BITP_USB_DMA_CTL_EP 4 /* DMA Channel Endpoint Assignment */
|
|
#define BITP_USB_DMA_CTL_IE 3 /* DMA Interrupt Enable */
|
|
#define BITP_USB_DMA_CTL_MODE 2 /* DMA Mode */
|
|
#define BITP_USB_DMA_CTL_DIR 1 /* DMA Transfer Direction */
|
|
#define BITP_USB_DMA_CTL_EN 0 /* DMA Enable */
|
|
|
|
#define BITM_USB_DMA_CTL_BRSTM (_ADI_MSK(0x00000600,uint16_t)) /* Burst Mode */
|
|
#define ENUM_USB_DMA_CTL_BRSTM00 (_ADI_MSK(0x00000000,uint16_t)) /* BRSTM: Unspecified Length */
|
|
#define ENUM_USB_DMA_CTL_BRSTM01 (_ADI_MSK(0x00000200,uint16_t)) /* BRSTM: INCR4 or Unspecified Length */
|
|
#define ENUM_USB_DMA_CTL_BRSTM10 (_ADI_MSK(0x00000400,uint16_t)) /* BRSTM: INCR8, INCR4, or Unspecified Length */
|
|
#define ENUM_USB_DMA_CTL_BRSTM11 (_ADI_MSK(0x00000600,uint16_t)) /* BRSTM: INCR16, INCR8, INCR4, or Unspecified Length */
|
|
|
|
#define BITM_USB_DMA_CTL_ERR (_ADI_MSK(0x00000100,uint16_t)) /* Bus Error */
|
|
#define ENUM_USB_DMA_CTL_NO_DMAERR (_ADI_MSK(0x00000000,uint16_t)) /* ERR: No Status */
|
|
#define ENUM_USB_DMA_CTL_DMAERR (_ADI_MSK(0x00000100,uint16_t)) /* ERR: Bus Error */
|
|
|
|
#define BITM_USB_DMA_CTL_EP (_ADI_MSK(0x000000F0,uint16_t)) /* DMA Channel Endpoint Assignment */
|
|
#define ENUM_USB_DMA_CTL_DMAEP0 (_ADI_MSK(0x00000000,uint16_t)) /* EP: Endpoint 0 */
|
|
#define ENUM_USB_DMA_CTL_DMAEP1 (_ADI_MSK(0x00000010,uint16_t)) /* EP: Endpoint 1 */
|
|
#define ENUM_USB_DMA_CTL_DMAEP10 (_ADI_MSK(0x000000A0,uint16_t)) /* EP: Endpoint 10 */
|
|
#define ENUM_USB_DMA_CTL_DMAEP11 (_ADI_MSK(0x000000B0,uint16_t)) /* EP: Endpoint 11 */
|
|
#define ENUM_USB_DMA_CTL_DMAEP12 (_ADI_MSK(0x000000C0,uint16_t)) /* EP: Endpoint 12 */
|
|
#define ENUM_USB_DMA_CTL_DMAEP13 (_ADI_MSK(0x000000D0,uint16_t)) /* EP: Endpoint 13 */
|
|
#define ENUM_USB_DMA_CTL_DMAEP14 (_ADI_MSK(0x000000E0,uint16_t)) /* EP: Endpoint 14 */
|
|
#define ENUM_USB_DMA_CTL_DMAEP15 (_ADI_MSK(0x000000F0,uint16_t)) /* EP: Endpoint 15 */
|
|
#define ENUM_USB_DMA_CTL_DMAEP2 (_ADI_MSK(0x00000020,uint16_t)) /* EP: Endpoint 2 */
|
|
#define ENUM_USB_DMA_CTL_DMAEP3 (_ADI_MSK(0x00000030,uint16_t)) /* EP: Endpoint 3 */
|
|
#define ENUM_USB_DMA_CTL_DMAEP4 (_ADI_MSK(0x00000040,uint16_t)) /* EP: Endpoint 4 */
|
|
#define ENUM_USB_DMA_CTL_DMAEP5 (_ADI_MSK(0x00000050,uint16_t)) /* EP: Endpoint 5 */
|
|
#define ENUM_USB_DMA_CTL_DMAEP6 (_ADI_MSK(0x00000060,uint16_t)) /* EP: Endpoint 6 */
|
|
#define ENUM_USB_DMA_CTL_DMAEP7 (_ADI_MSK(0x00000070,uint16_t)) /* EP: Endpoint 7 */
|
|
#define ENUM_USB_DMA_CTL_DMAEP8 (_ADI_MSK(0x00000080,uint16_t)) /* EP: Endpoint 8 */
|
|
#define ENUM_USB_DMA_CTL_DMAEP9 (_ADI_MSK(0x00000090,uint16_t)) /* EP: Endpoint 9 */
|
|
|
|
#define BITM_USB_DMA_CTL_IE (_ADI_MSK(0x00000008,uint16_t)) /* DMA Interrupt Enable */
|
|
#define ENUM_USB_DMA_CTL_DMAINTDIS (_ADI_MSK(0x00000000,uint16_t)) /* IE: Disable Interrupt */
|
|
#define ENUM_USB_DMA_CTL_DMAINTEN (_ADI_MSK(0x00000008,uint16_t)) /* IE: Enable Interrupt */
|
|
|
|
#define BITM_USB_DMA_CTL_MODE (_ADI_MSK(0x00000004,uint16_t)) /* DMA Mode */
|
|
#define ENUM_USB_DMA_CTL_DMAMODE0 (_ADI_MSK(0x00000000,uint16_t)) /* MODE: DMA Mode 0 */
|
|
#define ENUM_USB_DMA_CTL_DMAMODE1 (_ADI_MSK(0x00000004,uint16_t)) /* MODE: DMA Mode 1 */
|
|
|
|
#define BITM_USB_DMA_CTL_DIR (_ADI_MSK(0x00000002,uint16_t)) /* DMA Transfer Direction */
|
|
#define ENUM_USB_DMA_CTL_DMADIR_RX (_ADI_MSK(0x00000000,uint16_t)) /* DIR: DMA Write (for Rx Endpoint) */
|
|
#define ENUM_USB_DMA_CTL_DMADIR_TX (_ADI_MSK(0x00000002,uint16_t)) /* DIR: DMA Read (for Tx Endpoint) */
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|
|
|
#define BITM_USB_DMA_CTL_EN (_ADI_MSK(0x00000001,uint16_t)) /* DMA Enable */
|
|
#define ENUM_USB_DMA_CTL_DMADIS (_ADI_MSK(0x00000000,uint16_t)) /* EN: Disable DMA */
|
|
#define ENUM_USB_DMA_CTL_DMAEN (_ADI_MSK(0x00000001,uint16_t)) /* EN: Enable DMA (Start Transfer) */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_CT_UCH Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_CT_UCH_VALUE 0 /* Chirp Timeout Value */
|
|
#define BITM_USB_CT_UCH_VALUE (_ADI_MSK(0x00007FFF,uint16_t)) /* Chirp Timeout Value */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_CT_HHSRTN Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_CT_HHSRTN_VALUE 0 /* Host High Speed Return to Normal Value */
|
|
#define BITM_USB_CT_HHSRTN_VALUE (_ADI_MSK(0x00007FFF,uint16_t)) /* Host High Speed Return to Normal Value */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_CT_HSBT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_CT_HSBT_VALUE 0 /* HS Timeout Adder */
|
|
#define BITM_USB_CT_HSBT_VALUE (_ADI_MSK(0x0000000F,uint16_t)) /* HS Timeout Adder */
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|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_LPM_ATTR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_LPM_ATTR_EP 12 /* Endpoint */
|
|
#define BITP_USB_LPM_ATTR_RMTWAK 8 /* Remote Wakeup Enable */
|
|
#define BITP_USB_LPM_ATTR_HIRD 4 /* Host Initiated Resume Duration */
|
|
#define BITP_USB_LPM_ATTR_LINKSTATE 0 /* Link State */
|
|
#define BITM_USB_LPM_ATTR_EP (_ADI_MSK(0x0000F000,uint16_t)) /* Endpoint */
|
|
|
|
#define BITM_USB_LPM_ATTR_RMTWAK (_ADI_MSK(0x00000100,uint16_t)) /* Remote Wakeup Enable */
|
|
#define ENUM_USB_LPM_ATTR_RMTWAKDIS (_ADI_MSK(0x00000000,uint16_t)) /* RMTWAK: Disable Remote Wakeup */
|
|
#define ENUM_USB_LPM_ATTR_RMTWAKEN (_ADI_MSK(0x00000100,uint16_t)) /* RMTWAK: Enable Remote Wakeup */
|
|
#define BITM_USB_LPM_ATTR_HIRD (_ADI_MSK(0x000000F0,uint16_t)) /* Host Initiated Resume Duration */
|
|
|
|
#define BITM_USB_LPM_ATTR_LINKSTATE (_ADI_MSK(0x0000000F,uint16_t)) /* Link State */
|
|
#define ENUM_USB_LPM_ATTR_LNKSTATE_SSL1 (_ADI_MSK(0x00000001,uint16_t)) /* LINKSTATE: Sleep State (L1) */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_LPM_CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_LPM_CTL_NAK 4 /* LPM NAK Enable */
|
|
#define BITP_USB_LPM_CTL_EN 2 /* LPM Enable */
|
|
#define BITP_USB_LPM_CTL_RESUME 1 /* LPM Resume (Remote Wakeup) */
|
|
#define BITP_USB_LPM_CTL_TX 0 /* LPM Transmit */
|
|
#define BITM_USB_LPM_CTL_NAK (_ADI_MSK(0x00000010,uint8_t)) /* LPM NAK Enable */
|
|
#define BITM_USB_LPM_CTL_EN (_ADI_MSK(0x0000000C,uint8_t)) /* LPM Enable */
|
|
#define BITM_USB_LPM_CTL_RESUME (_ADI_MSK(0x00000002,uint8_t)) /* LPM Resume (Remote Wakeup) */
|
|
#define BITM_USB_LPM_CTL_TX (_ADI_MSK(0x00000001,uint8_t)) /* LPM Transmit */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_LPM_IEN Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_LPM_IEN_LPMERR 5 /* LPM Error Interrupt Enable */
|
|
#define BITP_USB_LPM_IEN_LPMRES 4 /* LPM Resume Interrupt Enable */
|
|
#define BITP_USB_LPM_IEN_LPMNC 3 /* LPM NYET Control Interrupt Enable */
|
|
#define BITP_USB_LPM_IEN_LPMACK 2 /* LPM ACK Interrupt Enable */
|
|
#define BITP_USB_LPM_IEN_LPMNY 1 /* LPM NYET Interrupt Enable */
|
|
#define BITP_USB_LPM_IEN_LPMST 0 /* LPM STALL Interrupt Enable */
|
|
#define BITM_USB_LPM_IEN_LPMERR (_ADI_MSK(0x00000020,uint8_t)) /* LPM Error Interrupt Enable */
|
|
#define BITM_USB_LPM_IEN_LPMRES (_ADI_MSK(0x00000010,uint8_t)) /* LPM Resume Interrupt Enable */
|
|
#define BITM_USB_LPM_IEN_LPMNC (_ADI_MSK(0x00000008,uint8_t)) /* LPM NYET Control Interrupt Enable */
|
|
#define BITM_USB_LPM_IEN_LPMACK (_ADI_MSK(0x00000004,uint8_t)) /* LPM ACK Interrupt Enable */
|
|
#define BITM_USB_LPM_IEN_LPMNY (_ADI_MSK(0x00000002,uint8_t)) /* LPM NYET Interrupt Enable */
|
|
#define BITM_USB_LPM_IEN_LPMST (_ADI_MSK(0x00000001,uint8_t)) /* LPM STALL Interrupt Enable */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_LPM_IRQ Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_LPM_IRQ_LPMERR 5 /* LPM Error Interrupt */
|
|
#define BITP_USB_LPM_IRQ_LPMRES 4 /* LPM Resume Interrupt */
|
|
#define BITP_USB_LPM_IRQ_LPMNC 3 /* LPM NYET Control Interrupt */
|
|
#define BITP_USB_LPM_IRQ_LPMACK 2 /* LPM ACK Interrupt */
|
|
#define BITP_USB_LPM_IRQ_LPMNY 1 /* LPM NYET Interrupt */
|
|
#define BITP_USB_LPM_IRQ_LPMST 0
|
|
#define BITM_USB_LPM_IRQ_LPMERR (_ADI_MSK(0x00000020,uint8_t)) /* LPM Error Interrupt */
|
|
#define BITM_USB_LPM_IRQ_LPMRES (_ADI_MSK(0x00000010,uint8_t)) /* LPM Resume Interrupt */
|
|
#define BITM_USB_LPM_IRQ_LPMNC (_ADI_MSK(0x00000008,uint8_t)) /* LPM NYET Control Interrupt */
|
|
#define BITM_USB_LPM_IRQ_LPMACK (_ADI_MSK(0x00000004,uint8_t)) /* LPM ACK Interrupt */
|
|
#define BITM_USB_LPM_IRQ_LPMNY (_ADI_MSK(0x00000002,uint8_t)) /* LPM NYET Interrupt */
|
|
#define BITM_USB_LPM_IRQ_LPMST (_ADI_MSK(0x00000001,uint8_t))
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_LPM_FADDR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_LPM_FADDR_VALUE 0 /* Function Address Value */
|
|
#define BITM_USB_LPM_FADDR_VALUE (_ADI_MSK(0x0000007F,uint8_t)) /* Function Address Value */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_VBUS_CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_VBUS_CTL_DRV 4 /* VBUS Drive */
|
|
#define BITP_USB_VBUS_CTL_DRVINT 3 /* VBUS Drive Interrupt */
|
|
#define BITP_USB_VBUS_CTL_DRVIEN 2 /* VBUS Drive Interrupt Enable */
|
|
#define BITP_USB_VBUS_CTL_DRVOD 1 /* VBUS Drive Open Drain */
|
|
#define BITP_USB_VBUS_CTL_INVDRV 0 /* VBUS Invert Drive */
|
|
#define BITM_USB_VBUS_CTL_DRV (_ADI_MSK(0x00000010,uint8_t)) /* VBUS Drive */
|
|
#define BITM_USB_VBUS_CTL_DRVINT (_ADI_MSK(0x00000008,uint8_t)) /* VBUS Drive Interrupt */
|
|
#define BITM_USB_VBUS_CTL_DRVIEN (_ADI_MSK(0x00000004,uint8_t)) /* VBUS Drive Interrupt Enable */
|
|
#define BITM_USB_VBUS_CTL_DRVOD (_ADI_MSK(0x00000002,uint8_t)) /* VBUS Drive Open Drain */
|
|
#define BITM_USB_VBUS_CTL_INVDRV (_ADI_MSK(0x00000001,uint8_t)) /* VBUS Invert Drive */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_BAT_CHG Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_BAT_CHG_DEDCHG 4 /* Dedicated Charging Port */
|
|
#define BITP_USB_BAT_CHG_CHGDET 3 /* Charging Port Detected */
|
|
#define BITP_USB_BAT_CHG_SNSCHGDET 2 /* Sense Charger Detection */
|
|
#define BITP_USB_BAT_CHG_CONDET 1 /* Connected Detected */
|
|
#define BITP_USB_BAT_CHG_SNSCONDET 0 /* Sense Connection Detection */
|
|
#define BITM_USB_BAT_CHG_DEDCHG (_ADI_MSK(0x00000010,uint8_t)) /* Dedicated Charging Port */
|
|
#define BITM_USB_BAT_CHG_CHGDET (_ADI_MSK(0x00000008,uint8_t)) /* Charging Port Detected */
|
|
#define BITM_USB_BAT_CHG_SNSCHGDET (_ADI_MSK(0x00000004,uint8_t)) /* Sense Charger Detection */
|
|
#define BITM_USB_BAT_CHG_CONDET (_ADI_MSK(0x00000002,uint8_t)) /* Connected Detected */
|
|
#define BITM_USB_BAT_CHG_SNSCONDET (_ADI_MSK(0x00000001,uint8_t)) /* Sense Connection Detection */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_PHY_CTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_PHY_CTL_EN 7 /* PHY Enable */
|
|
#define BITP_USB_PHY_CTL_RESTORE 1 /* Restore from Hibernate */
|
|
#define BITP_USB_PHY_CTL_HIBER 0 /* Hibernate */
|
|
#define BITM_USB_PHY_CTL_EN (_ADI_MSK(0x00000080,uint8_t)) /* PHY Enable */
|
|
#define BITM_USB_PHY_CTL_RESTORE (_ADI_MSK(0x00000002,uint8_t)) /* Restore from Hibernate */
|
|
#define BITM_USB_PHY_CTL_HIBER (_ADI_MSK(0x00000001,uint8_t)) /* Hibernate */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
USB_PLL_OSC Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_USB_PLL_OSC_PLLMSEL 7 /* PLL Multiplier Select */
|
|
#define BITP_USB_PLL_OSC_PLLM 1 /* PLL Multiplier Value */
|
|
#define BITP_USB_PLL_OSC_DIVCLKIN 0 /* Divide CLKIN */
|
|
#define BITM_USB_PLL_OSC_PLLMSEL (_ADI_MSK(0x00000080,uint16_t)) /* PLL Multiplier Select */
|
|
#define BITM_USB_PLL_OSC_PLLM (_ADI_MSK(0x0000007E,uint16_t)) /* PLL Multiplier Value */
|
|
#define BITM_USB_PLL_OSC_DIVCLKIN (_ADI_MSK(0x00000001,uint16_t)) /* Divide CLKIN */
|
|
|
|
/* ==================================================
|
|
Data Memory Unit Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
L1DM0
|
|
========================= */
|
|
#define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address */
|
|
#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
|
|
#define DCPLB_STATUS 0xFFE00008 /* Data Cacheability Protection Lookaside Buffer Status */
|
|
#define DCPLB_FAULT_STATUS 0xFFE00008 /* Older definition or alias of above */
|
|
#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cacheability Protection Lookaside Buffer Fault Address */
|
|
#define DCPLB_ADDR0 0xFFE00100 /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define DCPLB_ADDR1 0xFFE00104 /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define DCPLB_ADDR2 0xFFE00108 /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define DCPLB_ADDR3 0xFFE0010C /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define DCPLB_ADDR4 0xFFE00110 /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define DCPLB_ADDR5 0xFFE00114 /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define DCPLB_ADDR6 0xFFE00118 /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define DCPLB_ADDR7 0xFFE0011C /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define DCPLB_ADDR8 0xFFE00120 /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define DCPLB_ADDR9 0xFFE00124 /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define DCPLB_ADDR10 0xFFE00128 /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define DCPLB_ADDR11 0xFFE0012C /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define DCPLB_ADDR12 0xFFE00130 /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define DCPLB_ADDR13 0xFFE00134 /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define DCPLB_ADDR14 0xFFE00138 /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define DCPLB_ADDR15 0xFFE0013C /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define DCPLB_DATA0 0xFFE00200 /* Cacheability Protection Lookaside Buffer Descriptor Data */
|
|
#define DCPLB_DATA1 0xFFE00204 /* Cacheability Protection Lookaside Buffer Descriptor Data */
|
|
#define DCPLB_DATA2 0xFFE00208 /* Cacheability Protection Lookaside Buffer Descriptor Data */
|
|
#define DCPLB_DATA3 0xFFE0020C /* Cacheability Protection Lookaside Buffer Descriptor Data */
|
|
#define DCPLB_DATA4 0xFFE00210 /* Cacheability Protection Lookaside Buffer Descriptor Data */
|
|
#define DCPLB_DATA5 0xFFE00214 /* Cacheability Protection Lookaside Buffer Descriptor Data */
|
|
#define DCPLB_DATA6 0xFFE00218 /* Cacheability Protection Lookaside Buffer Descriptor Data */
|
|
#define DCPLB_DATA7 0xFFE0021C /* Cacheability Protection Lookaside Buffer Descriptor Data */
|
|
#define DCPLB_DATA8 0xFFE00220 /* Cacheability Protection Lookaside Buffer Descriptor Data */
|
|
#define DCPLB_DATA9 0xFFE00224 /* Cacheability Protection Lookaside Buffer Descriptor Data */
|
|
#define DCPLB_DATA10 0xFFE00228 /* Cacheability Protection Lookaside Buffer Descriptor Data */
|
|
#define DCPLB_DATA11 0xFFE0022C /* Cacheability Protection Lookaside Buffer Descriptor Data */
|
|
#define DCPLB_DATA12 0xFFE00230 /* Cacheability Protection Lookaside Buffer Descriptor Data */
|
|
#define DCPLB_DATA13 0xFFE00234 /* Cacheability Protection Lookaside Buffer Descriptor Data */
|
|
#define DCPLB_DATA14 0xFFE00238 /* Cacheability Protection Lookaside Buffer Descriptor Data */
|
|
#define DCPLB_DATA15 0xFFE0023C /* Cacheability Protection Lookaside Buffer Descriptor Data */
|
|
#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
|
|
#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
|
|
#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
|
|
#define L1DBNKA_PELOC 0xFFE00408 /* Data Bank A Parity Error Location */
|
|
#define L1DBNKB_PELOC 0xFFE0040C /* Data Bank B Parity Error Location */
|
|
|
|
/* =========================
|
|
L1DM
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
SRAM_BASE_ADDRESS Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_SRAM_BASE_ADDRESS_ADDR 22 /* SRAM Base Address */
|
|
#define BITM_SRAM_BASE_ADDRESS_ADDR (_ADI_MSK(0xFFC00000,uint32_t)) /* SRAM Base Address */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DMEM_CONTROL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DMEM_CONTROL_PARCTL 15 /* L1 Scratch Parity Control */
|
|
#define BITP_DMEM_CONTROL_PARSEL 14 /* L1 Scratch Parity Select */
|
|
#define BITP_DMEM_CONTROL_PPREF1 13 /* DAG1 Port Preference */
|
|
#define BITP_DMEM_CONTROL_PPREF0 12 /* DAG0 Port Preference */
|
|
#define BITP_DMEM_CONTROL_RDCHK 9 /* Read Parity Checking */
|
|
#define BITP_DMEM_CONTROL_CBYPASS 8 /* Cache Bypass */
|
|
#define BITP_DMEM_CONTROL_DCBS 4 /* L1 Data Cache Bank Select */
|
|
#define BITP_DMEM_CONTROL_CFG 2 /* Data Memory Configuration */
|
|
#define BITP_DMEM_CONTROL_ENCPLB 1 /* Enable DCPLB */
|
|
|
|
#define BITM_DMEM_CONTROL_PARCTL (_ADI_MSK(0x00008000,uint32_t)) /* L1 Scratch Parity Control */
|
|
#define ENUM_DMEM_CONTROL_NO_PARCTL (_ADI_MSK(0x00000000,uint32_t)) /* PARCTL: No Parity Control (Normal Behavior for L1 RD / L1 WT) */
|
|
#define ENUM_DMEM_CONTROL_PARCTL (_ADI_MSK(0x00008000,uint32_t)) /* PARCTL: Parity Control Enabled */
|
|
#define BITM_DMEM_CONTROL_PARSEL (_ADI_MSK(0x00004000,uint32_t)) /* L1 Scratch Parity Select */
|
|
|
|
#define BITM_DMEM_CONTROL_PPREF1 (_ADI_MSK(0x00002000,uint32_t)) /* DAG1 Port Preference */
|
|
#define ENUM_DMEM_CONTROL_PPREF1A (_ADI_MSK(0x00000000,uint32_t)) /* PPREF1: DAG1 Non-cacheable Fetches Use Port A */
|
|
#define ENUM_DMEM_CONTROL_PPREF1B (_ADI_MSK(0x00002000,uint32_t)) /* PPREF1: DAG1 Non-cacheable Fetches Use Port B */
|
|
|
|
#define BITM_DMEM_CONTROL_PPREF0 (_ADI_MSK(0x00001000,uint32_t)) /* DAG0 Port Preference */
|
|
#define ENUM_DMEM_CONTROL_PPREF0A (_ADI_MSK(0x00000000,uint32_t)) /* PPREF0: DAG0 Non-cacheable Fetches Use Port A */
|
|
#define ENUM_DMEM_CONTROL_PPREF0B (_ADI_MSK(0x00001000,uint32_t)) /* PPREF0: DAG0 Non-cacheable Fetches Use Port B */
|
|
|
|
#define BITM_DMEM_CONTROL_RDCHK (_ADI_MSK(0x00000200,uint32_t)) /* Read Parity Checking */
|
|
#define ENUM_DMEM_CONTROL_RDCHK_DIS (_ADI_MSK(0x00000000,uint32_t)) /* RDCHK: Read Parity Checking Disabled */
|
|
#define ENUM_DMEM_CONTROL_RDCHK_EN (_ADI_MSK(0x00000200,uint32_t)) /* RDCHK: Read Parity Checking Enabled */
|
|
|
|
#define BITM_DMEM_CONTROL_CBYPASS (_ADI_MSK(0x00000100,uint32_t)) /* Cache Bypass */
|
|
#define ENUM_DMEM_CONTROL_NO_CBYPASS (_ADI_MSK(0x00000000,uint32_t)) /* CBYPASS: Normal Cache Behavior */
|
|
#define ENUM_DMEM_CONTROL_CBYPASS (_ADI_MSK(0x00000100,uint32_t)) /* CBYPASS: Cache Bypassed */
|
|
|
|
#define BITM_DMEM_CONTROL_DCBS (_ADI_MSK(0x00000010,uint32_t)) /* L1 Data Cache Bank Select */
|
|
#define ENUM_DMEM_CONTROL_DCBS14 (_ADI_MSK(0x00000000,uint32_t)) /* DCBS: Address bit 14 used to select Bank A or B for cache access */
|
|
#define ENUM_DMEM_CONTROL_DCBS23 (_ADI_MSK(0x00000010,uint32_t)) /* DCBS: Address bit 23 used to select Bank A or B for cache access */
|
|
|
|
#define BITM_DMEM_CONTROL_CFG (_ADI_MSK(0x0000000C,uint32_t)) /* Data Memory Configuration */
|
|
#define ENUM_DMEM_CONTROL_ASRAM_BSRAM (_ADI_MSK(0x00000000,uint32_t)) /* CFG: A SRAM, B SRAM */
|
|
#define ENUM_DMEM_CONTROL_ACACHE_BSRAM (_ADI_MSK(0x00000008,uint32_t)) /* CFG: A Cache, B SRAM */
|
|
#define ENUM_DMEM_CONTROL_ACACHE_BCACHE (_ADI_MSK(0x0000000C,uint32_t)) /* CFG: A Cache, B Cache */
|
|
|
|
#define BITM_DMEM_CONTROL_ENCPLB (_ADI_MSK(0x00000002,uint32_t)) /* Enable DCPLB */
|
|
#define ENUM_DMEM_CONTROL_CPLB_DIS (_ADI_MSK(0x00000000,uint32_t)) /* ENCPLB: CPLBs Disabled */
|
|
#define ENUM_DMEM_CONTROL_CPLB_EN (_ADI_MSK(0x00000002,uint32_t)) /* ENCPLB: CPLBs Enabled */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DCPLB_STATUS Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DCPLB_STATUS_ILLADDR 19 /* Illegal Address */
|
|
#define BITP_DCPLB_STATUS_DAG 18 /* Access DAG */
|
|
#define BITP_DCPLB_STATUS_MODE 17 /* Access Mode */
|
|
#define BITP_DCPLB_STATUS_RW 16 /* Access Read/Write */
|
|
#define BITP_DCPLB_STATUS_FAULT 0 /* Fault Status */
|
|
#define BITM_DCPLB_STATUS_ILLADDR (_ADI_MSK(0x00080000,uint32_t)) /* Illegal Address */
|
|
#define BITM_DCPLB_STATUS_DAG (_ADI_MSK(0x00040000,uint32_t)) /* Access DAG */
|
|
#define BITM_DCPLB_STATUS_MODE (_ADI_MSK(0x00020000,uint32_t)) /* Access Mode */
|
|
#define BITM_DCPLB_STATUS_RW (_ADI_MSK(0x00010000,uint32_t)) /* Access Read/Write */
|
|
#define BITM_DCPLB_STATUS_FAULT (_ADI_MSK(0x0000FFFF,uint32_t)) /* Fault Status */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DCPLB_ADDR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DCPLB_ADDR_ADDR 10 /* Address for match */
|
|
#define BITM_DCPLB_ADDR_ADDR (_ADI_MSK(0xFFFFFC00,uint32_t)) /* Address for match */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DCPLB_DATA Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DCPLB_DATA_PSIZE 16 /* Page Size */
|
|
#define BITP_DCPLB_DATA_WT 14 /* CPLB Write Through */
|
|
#define BITP_DCPLB_DATA_L2_CHBL 13 /* CPLB L2 Cacheable */
|
|
#define BITP_DCPLB_DATA_L1_CHBL 12 /* CPLB L1 Cacheable */
|
|
#define BITP_DCPLB_DATA_DIRTY 7 /* CPLB DIRTY */
|
|
#define BITP_DCPLB_DATA_L1SRAM 5 /* CPLB L1SRAM */
|
|
#define BITP_DCPLB_DATA_SWRITE 4 /* CPLB Supervisor Write */
|
|
#define BITP_DCPLB_DATA_UWRITE 3 /* CPLB User Write */
|
|
#define BITP_DCPLB_DATA_UREAD 2 /* CPLB User Read */
|
|
#define BITP_DCPLB_DATA_LOCK 1 /* CPLB Lock */
|
|
#define BITP_DCPLB_DATA_VALID 0 /* CPLB Valid */
|
|
|
|
#define BITM_DCPLB_DATA_PSIZE (_ADI_MSK(0x00070000,uint32_t)) /* Page Size */
|
|
#define ENUM_DCPLB_DATA_1KB (_ADI_MSK(0x00000000,uint32_t)) /* PSIZE: 1 KB Page Size */
|
|
#define ENUM_DCPLB_DATA_4KB (_ADI_MSK(0x00010000,uint32_t)) /* PSIZE: 4 KB Page Size */
|
|
#define ENUM_DCPLB_DATA_1MB (_ADI_MSK(0x00020000,uint32_t)) /* PSIZE: 1 MB Page Size */
|
|
#define ENUM_DCPLB_DATA_4MB (_ADI_MSK(0x00030000,uint32_t)) /* PSIZE: 4 MB Page Size */
|
|
#define ENUM_DCPLB_DATA_16KB (_ADI_MSK(0x00040000,uint32_t)) /* PSIZE: 16 KB Page Size */
|
|
#define ENUM_DCPLB_DATA_64KB (_ADI_MSK(0x00050000,uint32_t)) /* PSIZE: 64 KB Page Size */
|
|
#define ENUM_DCPLB_DATA_16MB (_ADI_MSK(0x00060000,uint32_t)) /* PSIZE: 16 MB Page Size */
|
|
#define ENUM_DCPLB_DATA_64MB (_ADI_MSK(0x00070000,uint32_t)) /* PSIZE: 64 MB Page Size */
|
|
|
|
#define BITM_DCPLB_DATA_WT (_ADI_MSK(0x00004000,uint32_t)) /* CPLB Write Through */
|
|
#define ENUM_DCPLB_DATA_WB (_ADI_MSK(0x00000000,uint32_t)) /* WT: Write-back */
|
|
#define ENUM_DCPLB_DATA_WT (_ADI_MSK(0x00004000,uint32_t)) /* WT: Write-through */
|
|
|
|
#define BITM_DCPLB_DATA_L2_CHBL (_ADI_MSK(0x00002000,uint32_t)) /* CPLB L2 Cacheable */
|
|
#define ENUM_DCPLB_DATA_L2CHBL_DIS (_ADI_MSK(0x00000000,uint32_t)) /* L2CHBL: Non-cacheable in L2 */
|
|
#define ENUM_DCPLB_DATA_L2CHBL_EN (_ADI_MSK(0x00002000,uint32_t)) /* L2CHBL: Cacheable in L2 */
|
|
|
|
#define BITM_DCPLB_DATA_L1_CHBL (_ADI_MSK(0x00001000,uint32_t)) /* CPLB L1 Cacheable */
|
|
#define ENUM_DCPLB_DATA_L1CHBL_DIS (_ADI_MSK(0x00000000,uint32_t)) /* L1CHBL: Non-cacheable in L1 */
|
|
#define ENUM_DCPLB_DATA_L1CHBL_EN (_ADI_MSK(0x00001000,uint32_t)) /* L1CHBL: Cacheable in L1 */
|
|
|
|
#define BITM_DCPLB_DATA_DIRTY (_ADI_MSK(0x00000080,uint32_t)) /* CPLB DIRTY */
|
|
#define ENUM_DCPLB_DATA_CLEAN (_ADI_MSK(0x00000000,uint32_t)) /* DIRTY: Clean */
|
|
#define ENUM_DCPLB_DATA_DIRTY (_ADI_MSK(0x00000080,uint32_t)) /* DIRTY: Dirty */
|
|
#define BITM_DCPLB_DATA_L1SRAM (_ADI_MSK(0x00000020,uint32_t)) /* CPLB L1SRAM */
|
|
|
|
#define BITM_DCPLB_DATA_SWRITE (_ADI_MSK(0x00000010,uint32_t)) /* CPLB Supervisor Write */
|
|
#define ENUM_DCPLB_DATA_NO_SWRITE (_ADI_MSK(0x00000000,uint32_t)) /* SWRITE: No Write Access */
|
|
#define ENUM_DCPLB_DATA_SWRITE (_ADI_MSK(0x00000010,uint32_t)) /* SWRITE: Write Access Allowed (Supervisor Mode) */
|
|
|
|
#define BITM_DCPLB_DATA_UWRITE (_ADI_MSK(0x00000008,uint32_t)) /* CPLB User Write */
|
|
#define ENUM_DCPLB_DATA_NO_UWRITE (_ADI_MSK(0x00000000,uint32_t)) /* UWRITE: No Write Access */
|
|
#define ENUM_DCPLB_DATA_UWRITE (_ADI_MSK(0x00000008,uint32_t)) /* UWRITE: Write Access Allowed (User Mode) */
|
|
|
|
#define BITM_DCPLB_DATA_UREAD (_ADI_MSK(0x00000004,uint32_t)) /* CPLB User Read */
|
|
#define ENUM_DCPLB_DATA_NO_UREAD (_ADI_MSK(0x00000000,uint32_t)) /* UREAD: No Read Access */
|
|
#define ENUM_DCPLB_DATA_UREAD (_ADI_MSK(0x00000004,uint32_t)) /* UREAD: Read Access Allowed (User Mode) */
|
|
|
|
#define BITM_DCPLB_DATA_LOCK (_ADI_MSK(0x00000002,uint32_t)) /* CPLB Lock */
|
|
#define ENUM_DCPLB_DATA_REPLACEABLE (_ADI_MSK(0x00000000,uint32_t)) /* LOCK: Entry May Be Replaced */
|
|
#define ENUM_DCPLB_DATA_LOCKED (_ADI_MSK(0x00000002,uint32_t)) /* LOCK: Entry Locked */
|
|
|
|
#define BITM_DCPLB_DATA_VALID (_ADI_MSK(0x00000001,uint32_t)) /* CPLB Valid */
|
|
#define ENUM_DCPLB_DATA_INVALID (_ADI_MSK(0x00000000,uint32_t)) /* VALID: Invalid Entry */
|
|
#define ENUM_DCPLB_DATA_VALID (_ADI_MSK(0x00000001,uint32_t)) /* VALID: Valid Entry */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DTEST_COMMAND Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DTEST_COMMAND_PARCTL 30 /* Parity Control */
|
|
#define BITP_DTEST_COMMAND_PARSEL 29 /* Parity Select */
|
|
#define BITP_DTEST_COMMAND_WAYSEL 26 /* Access Way/Instruction Address Bit 11 */
|
|
#define BITP_DTEST_COMMAND_IDSEL 24 /* Instruction/Data Access */
|
|
#define BITP_DTEST_COMMAND_BNKSEL 23 /* Data Bank Access */
|
|
#define BITP_DTEST_COMMAND_SBNK 16 /* Subbank Access */
|
|
#define BITP_DTEST_COMMAND_SEL16K 14 /* Address bit 14 */
|
|
#define BITP_DTEST_COMMAND_SET 5 /* Set Index */
|
|
#define BITP_DTEST_COMMAND_DW 3 /* Double Word Index */
|
|
#define BITP_DTEST_COMMAND_TAGSELB 2 /* Array Access */
|
|
#define BITP_DTEST_COMMAND_RW 1 /* Read/Write Access */
|
|
#define BITM_DTEST_COMMAND_PARCTL (_ADI_MSK(0x40000000,uint32_t)) /* Parity Control */
|
|
#define BITM_DTEST_COMMAND_PARSEL (_ADI_MSK(0x20000000,uint32_t)) /* Parity Select */
|
|
#define BITM_DTEST_COMMAND_WAYSEL (_ADI_MSK(0x04000000,uint32_t)) /* Access Way/Instruction Address Bit 11 */
|
|
#define BITM_DTEST_COMMAND_IDSEL (_ADI_MSK(0x01000000,uint32_t)) /* Instruction/Data Access */
|
|
#define BITM_DTEST_COMMAND_BNKSEL (_ADI_MSK(0x00800000,uint32_t)) /* Data Bank Access */
|
|
#define BITM_DTEST_COMMAND_SBNK (_ADI_MSK(0x00030000,uint32_t)) /* Subbank Access */
|
|
#define BITM_DTEST_COMMAND_SEL16K (_ADI_MSK(0x00004000,uint32_t)) /* Address bit 14 */
|
|
#define BITM_DTEST_COMMAND_SET (_ADI_MSK(0x000007E0,uint32_t)) /* Set Index */
|
|
#define BITM_DTEST_COMMAND_DW (_ADI_MSK(0x00000018,uint32_t)) /* Double Word Index */
|
|
#define BITM_DTEST_COMMAND_TAGSELB (_ADI_MSK(0x00000004,uint32_t)) /* Array Access */
|
|
#define BITM_DTEST_COMMAND_RW (_ADI_MSK(0x00000002,uint32_t)) /* Read/Write Access */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
L1DBNKA_PELOC Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_L1DBNKA_PELOC_SCRATCH_MEM 12 /* Scratch Memory Parity Status */
|
|
#define BITP_L1DBNKA_PELOC_TAGPAIR 8 /* Tag Parity Status */
|
|
#define BITP_L1DBNKA_PELOC_MEMBLK 0 /* Memory Parity Status */
|
|
#define BITM_L1DBNKA_PELOC_SCRATCH_MEM (_ADI_MSK(0x00001000,uint32_t)) /* Scratch Memory Parity Status */
|
|
#define BITM_L1DBNKA_PELOC_TAGPAIR (_ADI_MSK(0x00000300,uint32_t)) /* Tag Parity Status */
|
|
#define BITM_L1DBNKA_PELOC_MEMBLK (_ADI_MSK(0x000000FF,uint32_t)) /* Memory Parity Status */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
L1DBNKB_PELOC Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_L1DBNKB_PELOC_TAGPAIR 8 /* Tag Parity Status */
|
|
#define BITP_L1DBNKB_PELOC_MEMBLK 0 /* Memory Parity Status */
|
|
#define BITM_L1DBNKB_PELOC_TAGPAIR (_ADI_MSK(0x00000300,uint32_t)) /* Tag Parity Status */
|
|
#define BITM_L1DBNKB_PELOC_MEMBLK (_ADI_MSK(0x000000FF,uint32_t)) /* Memory Parity Status */
|
|
|
|
/* ==================================================
|
|
Instruction Memory Unit Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
L1IM0
|
|
========================= */
|
|
#define IMEM_CONTROL 0xFFE01004 /* Instruction memory control */
|
|
#define ICPLB_STATUS 0xFFE01008 /* Cacheability Protection Lookaside Buffer Status */
|
|
#define CODE_FAULT_STATUS 0xFFE01008 /* Older definition or alias of above */
|
|
#define ICPLB_FAULT_ADDR 0xFFE0100C /* Cacheability Protection Lookaside Buffer Fault Address */
|
|
#define CODE_FAULT_ADDR 0xFFE0100C /* Older definition or alias of above */
|
|
#define ICPLB_ADDR0 0xFFE01100 /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define ICPLB_ADDR1 0xFFE01104 /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define ICPLB_ADDR2 0xFFE01108 /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define ICPLB_ADDR3 0xFFE0110C /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define ICPLB_ADDR4 0xFFE01110 /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define ICPLB_ADDR5 0xFFE01114 /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define ICPLB_ADDR6 0xFFE01118 /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define ICPLB_ADDR7 0xFFE0111C /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define ICPLB_ADDR8 0xFFE01120 /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define ICPLB_ADDR9 0xFFE01124 /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define ICPLB_ADDR10 0xFFE01128 /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define ICPLB_ADDR11 0xFFE0112C /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define ICPLB_ADDR12 0xFFE01130 /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define ICPLB_ADDR13 0xFFE01134 /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define ICPLB_ADDR14 0xFFE01138 /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define ICPLB_ADDR15 0xFFE0113C /* Cacheability Protection Lookaside Buffer Descriptor Address */
|
|
#define ICPLB_DATA0 0xFFE01200 /* Cacheability Protection Lookaside Buffer Descriptor Status */
|
|
#define ICPLB_DATA1 0xFFE01204 /* Cacheability Protection Lookaside Buffer Descriptor Status */
|
|
#define ICPLB_DATA2 0xFFE01208 /* Cacheability Protection Lookaside Buffer Descriptor Status */
|
|
#define ICPLB_DATA3 0xFFE0120C /* Cacheability Protection Lookaside Buffer Descriptor Status */
|
|
#define ICPLB_DATA4 0xFFE01210 /* Cacheability Protection Lookaside Buffer Descriptor Status */
|
|
#define ICPLB_DATA5 0xFFE01214 /* Cacheability Protection Lookaside Buffer Descriptor Status */
|
|
#define ICPLB_DATA6 0xFFE01218 /* Cacheability Protection Lookaside Buffer Descriptor Status */
|
|
#define ICPLB_DATA7 0xFFE0121C /* Cacheability Protection Lookaside Buffer Descriptor Status */
|
|
#define ICPLB_DATA8 0xFFE01220 /* Cacheability Protection Lookaside Buffer Descriptor Status */
|
|
#define ICPLB_DATA9 0xFFE01224 /* Cacheability Protection Lookaside Buffer Descriptor Status */
|
|
#define ICPLB_DATA10 0xFFE01228 /* Cacheability Protection Lookaside Buffer Descriptor Status */
|
|
#define ICPLB_DATA11 0xFFE0122C /* Cacheability Protection Lookaside Buffer Descriptor Status */
|
|
#define ICPLB_DATA12 0xFFE01230 /* Cacheability Protection Lookaside Buffer Descriptor Status */
|
|
#define ICPLB_DATA13 0xFFE01234 /* Cacheability Protection Lookaside Buffer Descriptor Status */
|
|
#define ICPLB_DATA14 0xFFE01238 /* Cacheability Protection Lookaside Buffer Descriptor Status */
|
|
#define ICPLB_DATA15 0xFFE0123C /* Cacheability Protection Lookaside Buffer Descriptor Status */
|
|
#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
|
|
#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
|
|
#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
|
|
#define L1IBNKA_PELOC 0xFFE01408 /* Instruction Bank A Parity Error Location */
|
|
#define L1IBNKB_PELOC 0xFFE0140C /* Instruction Bank B Parity Error Location */
|
|
#define L1IBNKC_PELOC 0xFFE01410 /* Instruction Bank C Parity Error Location */
|
|
|
|
/* =========================
|
|
L1IM
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
IMEM_CONTROL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_IMEM_CONTROL_LRUPRIORST 13 /* LRU Priority Reset */
|
|
#define BITP_IMEM_CONTROL_RDCHK 9 /* Read Parity Checking */
|
|
#define BITP_IMEM_CONTROL_CBYPASS 8 /* Cache Bypass */
|
|
#define BITP_IMEM_CONTROL_LOC 3 /* Cache Way Lock */
|
|
#define BITP_IMEM_CONTROL_CFG 2 /* Configure L1 code memory as cache */
|
|
#define BITP_IMEM_CONTROL_ENCPLB 1 /* Enable ICPLB */
|
|
|
|
#define BITM_IMEM_CONTROL_LRUPRIORST (_ADI_MSK(0x00002000,uint32_t)) /* LRU Priority Reset */
|
|
#define ENUM_IMEM_CONTROL_LRUPRIO_EN (_ADI_MSK(0x00000000,uint32_t)) /* LRUPRIORST: LRU Priority functionality is enabled */
|
|
#define ENUM_IMEM_CONTROL_LRUPRIO_CLR (_ADI_MSK(0x00002000,uint32_t)) /* LRUPRIORST: All cached LRU priority bits are cleared */
|
|
|
|
#define BITM_IMEM_CONTROL_RDCHK (_ADI_MSK(0x00000200,uint32_t)) /* Read Parity Checking */
|
|
#define ENUM_IMEM_CONTROL_RDCHK_DIS (_ADI_MSK(0x00000000,uint32_t)) /* RDCHK: Read Parity Checking Disabled */
|
|
#define ENUM_IMEM_CONTROL_RDCHK_EN (_ADI_MSK(0x00000200,uint32_t)) /* RDCHK: Read Parity Checking Enabled */
|
|
|
|
#define BITM_IMEM_CONTROL_CBYPASS (_ADI_MSK(0x00000100,uint32_t)) /* Cache Bypass */
|
|
#define ENUM_IMEM_CONTROL_NO_CBYPASS (_ADI_MSK(0x00000000,uint32_t)) /* CBYPASS: Normal Cache Behavior */
|
|
#define ENUM_IMEM_CONTROL_CBYPASS (_ADI_MSK(0x00000100,uint32_t)) /* CBYPASS: Cache Bypassed */
|
|
|
|
#define BITM_IMEM_CONTROL_LOC (_ADI_MSK(0x00000078,uint32_t)) /* Cache Way Lock */
|
|
#define ENUM_IMEM_CONTROL_WAYLOCK_NONE (_ADI_MSK(0x00000000,uint32_t)) /* LOC: All Ways Not Locked */
|
|
#define ENUM_IMEM_CONTROL_WAYLOCK_0 (_ADI_MSK(0x00000008,uint32_t)) /* LOC: Way3, Way2, Way1 Not Locked, Way0 Locked */
|
|
#define ENUM_IMEM_CONTROL_WAYLOCK_ALL (_ADI_MSK(0x00000078,uint32_t)) /* LOC: All Ways Locked */
|
|
|
|
#define BITM_IMEM_CONTROL_CFG (_ADI_MSK(0x00000004,uint32_t)) /* Configure L1 code memory as cache */
|
|
#define ENUM_IMEM_CONTROL_CFG_SRAM (_ADI_MSK(0x00000000,uint32_t)) /* CFG: L1 Instruction Memory Configured as SRAM */
|
|
#define ENUM_IMEM_CONTROL_CFG_CACHE (_ADI_MSK(0x00000004,uint32_t)) /* CFG: L1 Instruction Memory Configures as Cache */
|
|
|
|
#define BITM_IMEM_CONTROL_ENCPLB (_ADI_MSK(0x00000002,uint32_t)) /* Enable ICPLB */
|
|
#define ENUM_IMEM_CONTROL_CPLB_DIS (_ADI_MSK(0x00000000,uint32_t)) /* ENCPLB: CPLBs disabled */
|
|
#define ENUM_IMEM_CONTROL_CPLB_EN (_ADI_MSK(0x00000002,uint32_t)) /* ENCPLB: CPLBs enabled */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
ICPLB_STATUS Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_ICPLB_STATUS_ILLADDR 19 /* Illegal Address */
|
|
#define BITP_ICPLB_STATUS_MODE 17 /* Access Mode */
|
|
#define BITP_ICPLB_STATUS_FAULT 0 /* Fault Status */
|
|
#define BITM_ICPLB_STATUS_ILLADDR (_ADI_MSK(0x00080000,uint32_t)) /* Illegal Address */
|
|
#define BITM_ICPLB_STATUS_MODE (_ADI_MSK(0x00020000,uint32_t)) /* Access Mode */
|
|
#define BITM_ICPLB_STATUS_FAULT (_ADI_MSK(0x0000FFFF,uint32_t)) /* Fault Status */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
ICPLB_ADDR Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_ICPLB_ADDR_ADDR 10 /* Address for match */
|
|
#define BITM_ICPLB_ADDR_ADDR (_ADI_MSK(0xFFFFFC00,uint32_t)) /* Address for match */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
ICPLB_DATA Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_ICPLB_DATA_PSIZE 16 /* Page Size */
|
|
#define BITP_ICPLB_DATA_L1_CHBL 12 /* L1 Cacheable */
|
|
#define BITP_ICPLB_DATA_LRUPRIO 8 /* Least Recently Used Priority */
|
|
#define BITP_ICPLB_DATA_L1SRAM 5 /* CPLB L1SRAM */
|
|
#define BITP_ICPLB_DATA_UREAD 2 /* Allow User Read */
|
|
#define BITP_ICPLB_DATA_LOCK 1 /* CPLB Lock */
|
|
#define BITP_ICPLB_DATA_VALID 0 /* CPLB Valid */
|
|
|
|
#define BITM_ICPLB_DATA_PSIZE (_ADI_MSK(0x00070000,uint32_t)) /* Page Size */
|
|
#define ENUM_ICPLB_DATA_1KB (_ADI_MSK(0x00000000,uint32_t)) /* PSIZE: 1 KB Page Size */
|
|
#define ENUM_ICPLB_DATA_4KB (_ADI_MSK(0x00010000,uint32_t)) /* PSIZE: 4 KB Page Size */
|
|
#define ENUM_ICPLB_DATA_1MB (_ADI_MSK(0x00020000,uint32_t)) /* PSIZE: 1 MB Page Size */
|
|
#define ENUM_ICPLB_DATA_4MB (_ADI_MSK(0x00030000,uint32_t)) /* PSIZE: 4 MB Page Size */
|
|
#define ENUM_ICPLB_DATA_16KB (_ADI_MSK(0x00040000,uint32_t)) /* PSIZE: 16 KB Page Size */
|
|
#define ENUM_ICPLB_DATA_64KB (_ADI_MSK(0x00050000,uint32_t)) /* PSIZE: 64 KB Page Size */
|
|
#define ENUM_ICPLB_DATA_16MB (_ADI_MSK(0x00060000,uint32_t)) /* PSIZE: 16 MB Page Size */
|
|
#define ENUM_ICPLB_DATA_64MB (_ADI_MSK(0x00070000,uint32_t)) /* PSIZE: 64 MB Page Size */
|
|
|
|
#define BITM_ICPLB_DATA_L1_CHBL (_ADI_MSK(0x00001000,uint32_t)) /* L1 Cacheable */
|
|
#define ENUM_ICPLB_DATA_L1CHBL_DIS (_ADI_MSK(0x00000000,uint32_t)) /* L1CHBL: Non-cacheable in L1 */
|
|
#define ENUM_ICPLB_DATA_L1CHBL_EN (_ADI_MSK(0x00001000,uint32_t)) /* L1CHBL: Cacheable in L1 */
|
|
|
|
#define BITM_ICPLB_DATA_LRUPRIO (_ADI_MSK(0x00000100,uint32_t)) /* Least Recently Used Priority */
|
|
#define ENUM_ICPLB_DATA_LRUPRIO_LO (_ADI_MSK(0x00000000,uint32_t)) /* LRUPRIO: Low Importance */
|
|
#define ENUM_ICPLB_DATA_LRUPRIO_HI (_ADI_MSK(0x00000100,uint32_t)) /* LRUPRIO: High Importance */
|
|
#define BITM_ICPLB_DATA_L1SRAM (_ADI_MSK(0x00000020,uint32_t)) /* CPLB L1SRAM */
|
|
|
|
#define BITM_ICPLB_DATA_UREAD (_ADI_MSK(0x00000004,uint32_t)) /* Allow User Read */
|
|
#define ENUM_ICPLB_DATA_NO_UREAD (_ADI_MSK(0x00000000,uint32_t)) /* UREAD: No Read Access */
|
|
#define ENUM_ICPLB_DATA_UREAD (_ADI_MSK(0x00000004,uint32_t)) /* UREAD: Read Access Allowed (User Mode) */
|
|
|
|
#define BITM_ICPLB_DATA_LOCK (_ADI_MSK(0x00000002,uint32_t)) /* CPLB Lock */
|
|
#define ENUM_ICPLB_DATA_REPLACEABLE (_ADI_MSK(0x00000000,uint32_t)) /* LOCK: Entry May Be Replaced */
|
|
#define ENUM_ICPLB_DATA_LOCKED (_ADI_MSK(0x00000002,uint32_t)) /* LOCK: Entry Locked */
|
|
|
|
#define BITM_ICPLB_DATA_VALID (_ADI_MSK(0x00000001,uint32_t)) /* CPLB Valid */
|
|
#define ENUM_ICPLB_DATA_INVALID (_ADI_MSK(0x00000000,uint32_t)) /* VALID: Invalid (disabled) CPLB Entry */
|
|
#define ENUM_ICPLB_DATA_VALID (_ADI_MSK(0x00000001,uint32_t)) /* VALID: Valid (enabled) CPLB Entry */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
ITEST_COMMAND Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_ITEST_COMMAND_PARCTL 30 /* Parity Control */
|
|
#define BITP_ITEST_COMMAND_PARSEL 29 /* Parity Select */
|
|
#define BITP_ITEST_COMMAND_WAYSEL 26 /* Access Way/Instruction Address Bits 11:10 */
|
|
#define BITP_ITEST_COMMAND_SBNK 16 /* Subbank Access */
|
|
#define BITP_ITEST_COMMAND_SET 5 /* Set Index */
|
|
#define BITP_ITEST_COMMAND_DW 3 /* Double Word Index */
|
|
#define BITP_ITEST_COMMAND_TAGSELB 2 /* Array Access */
|
|
#define BITP_ITEST_COMMAND_RW 1 /* Read/Write Access */
|
|
#define BITM_ITEST_COMMAND_PARCTL (_ADI_MSK(0x40000000,uint32_t)) /* Parity Control */
|
|
#define BITM_ITEST_COMMAND_PARSEL (_ADI_MSK(0x20000000,uint32_t)) /* Parity Select */
|
|
#define BITM_ITEST_COMMAND_WAYSEL (_ADI_MSK(0x0C000000,uint32_t)) /* Access Way/Instruction Address Bits 11:10 */
|
|
#define BITM_ITEST_COMMAND_SBNK (_ADI_MSK(0x00030000,uint32_t)) /* Subbank Access */
|
|
#define BITM_ITEST_COMMAND_SET (_ADI_MSK(0x000003E0,uint32_t)) /* Set Index */
|
|
#define BITM_ITEST_COMMAND_DW (_ADI_MSK(0x00000018,uint32_t)) /* Double Word Index */
|
|
#define BITM_ITEST_COMMAND_TAGSELB (_ADI_MSK(0x00000004,uint32_t)) /* Array Access */
|
|
#define BITM_ITEST_COMMAND_RW (_ADI_MSK(0x00000002,uint32_t)) /* Read/Write Access */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
L1IBNKA_PELOC Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_L1IBNKA_PELOC_MEMBLK 0 /* Memory Parity Status */
|
|
#define BITM_L1IBNKA_PELOC_MEMBLK (_ADI_MSK(0x000000FF,uint32_t)) /* Memory Parity Status */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
L1IBNKB_PELOC Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_L1IBNKB_PELOC_MEMBLK 0 /* Memory Parity Status */
|
|
#define BITM_L1IBNKB_PELOC_MEMBLK (_ADI_MSK(0x000000FF,uint32_t)) /* Memory Parity Status */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
L1IBNKC_PELOC Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_L1IBNKC_PELOC_TAGPAIR 4 /* Tag Parity Status */
|
|
#define BITP_L1IBNKC_PELOC_MEMBLK 0 /* Memory Parity Status */
|
|
#define BITM_L1IBNKC_PELOC_TAGPAIR (_ADI_MSK(0x00000030,uint32_t)) /* Tag Parity Status */
|
|
#define BITM_L1IBNKC_PELOC_MEMBLK (_ADI_MSK(0x0000000F,uint32_t)) /* Memory Parity Status */
|
|
|
|
/* ==================================================
|
|
Interrupt Controller Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
ICU0
|
|
========================= */
|
|
#define EVT0 0xFFE02000 /* Event Vector */
|
|
#define EVT1 0xFFE02004 /* Event Vector */
|
|
#define EVT2 0xFFE02008 /* Event Vector */
|
|
#define EVT3 0xFFE0200C /* Event Vector */
|
|
#define EVT4 0xFFE02010 /* Event Vector */
|
|
#define EVT5 0xFFE02014 /* Event Vector */
|
|
#define EVT6 0xFFE02018 /* Event Vector */
|
|
#define EVT7 0xFFE0201C /* Event Vector */
|
|
#define EVT8 0xFFE02020 /* Event Vector */
|
|
#define EVT9 0xFFE02024 /* Event Vector */
|
|
#define EVT10 0xFFE02028 /* Event Vector */
|
|
#define EVT11 0xFFE0202C /* Event Vector */
|
|
#define EVT12 0xFFE02030 /* Event Vector */
|
|
#define EVT13 0xFFE02034 /* Event Vector */
|
|
#define EVT14 0xFFE02038 /* Event Vector */
|
|
#define EVT15 0xFFE0203C /* Event Vector */
|
|
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
|
|
#define IPEND 0xFFE02108 /* Interrupts Pending Register */
|
|
#define ILAT 0xFFE0210C /* Interrupt Latch Register */
|
|
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
|
|
#define CEC_SID 0xFFE02118 /* Core System Interrupt ID */
|
|
|
|
/* =========================
|
|
ICU
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
IMASK Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_IMASK_IVG15 15 /* IVG15 interrupt bit position */
|
|
#define BITP_IMASK_IVG14 14 /* IVG14 interrupt bit position */
|
|
#define BITP_IMASK_IVG13 13 /* IVG13 interrupt bit position */
|
|
#define BITP_IMASK_IVG12 12 /* IVG12 interrupt bit position */
|
|
#define BITP_IMASK_IVG11 11 /* IVG11 interrupt bit position */
|
|
#define BITP_IMASK_IVG10 10 /* IVG10 interrupt bit position */
|
|
#define BITP_IMASK_IVG9 9 /* IVG9 interrupt bit position */
|
|
#define BITP_IMASK_IVG8 8 /* IVG8 interrupt bit position */
|
|
#define BITP_IMASK_IVG7 7 /* IVG7 interrupt bit position */
|
|
#define BITP_IMASK_IVTMR 6 /* Timer interrupt bit position */
|
|
#define BITP_IMASK_IVHW 5 /* Hardware Error interrupt bit position */
|
|
#define BITP_IMASK_UNMASKABLE 0 /* Unmaskable interrupts */
|
|
#define BITM_IMASK_IVG15 (_ADI_MSK(0x00008000,uint32_t)) /* IVG15 interrupt bit position */
|
|
#define BITM_IMASK_IVG14 (_ADI_MSK(0x00004000,uint32_t)) /* IVG14 interrupt bit position */
|
|
#define BITM_IMASK_IVG13 (_ADI_MSK(0x00002000,uint32_t)) /* IVG13 interrupt bit position */
|
|
#define BITM_IMASK_IVG12 (_ADI_MSK(0x00001000,uint32_t)) /* IVG12 interrupt bit position */
|
|
#define BITM_IMASK_IVG11 (_ADI_MSK(0x00000800,uint32_t)) /* IVG11 interrupt bit position */
|
|
#define BITM_IMASK_IVG10 (_ADI_MSK(0x00000400,uint32_t)) /* IVG10 interrupt bit position */
|
|
#define BITM_IMASK_IVG9 (_ADI_MSK(0x00000200,uint32_t)) /* IVG9 interrupt bit position */
|
|
#define BITM_IMASK_IVG8 (_ADI_MSK(0x00000100,uint32_t)) /* IVG8 interrupt bit position */
|
|
#define BITM_IMASK_IVG7 (_ADI_MSK(0x00000080,uint32_t)) /* IVG7 interrupt bit position */
|
|
#define BITM_IMASK_IVTMR (_ADI_MSK(0x00000040,uint32_t)) /* Timer interrupt bit position */
|
|
#define BITM_IMASK_IVHW (_ADI_MSK(0x00000020,uint32_t)) /* Hardware Error interrupt bit position */
|
|
#define BITM_IMASK_UNMASKABLE (_ADI_MSK(0x0000001F,uint32_t)) /* Unmaskable interrupts */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
IPEND Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_IPEND_IVG15 15 /* IVG15 interrupt bit position */
|
|
#define BITP_IPEND_IVG14 14 /* IVG14 interrupt bit position */
|
|
#define BITP_IPEND_IVG13 13 /* IVG13 interrupt bit position */
|
|
#define BITP_IPEND_IVG12 12 /* IVG12 interrupt bit position */
|
|
#define BITP_IPEND_IVG11 11 /* IVG11 interrupt bit position */
|
|
#define BITP_IPEND_IVG10 10 /* IVG10 interrupt bit position */
|
|
#define BITP_IPEND_IVG9 9 /* IVG9 interrupt bit position */
|
|
#define BITP_IPEND_IVG8 8 /* IVG8 interrupt bit position */
|
|
#define BITP_IPEND_IVG7 7 /* IVG7 interrupt bit position */
|
|
#define BITP_IPEND_IVTMR 6 /* Timer interrupt bit position */
|
|
#define BITP_IPEND_IVHW 5 /* Hardware Error interrupt bit position */
|
|
#define BITP_IPEND_IRPTEN 4 /* Global interrupt enable bit position */
|
|
#define BITP_IPEND_EVX 3 /* Exception bit position */
|
|
#define BITP_IPEND_NMI 2 /* Non Maskable interrupt bit position */
|
|
#define BITP_IPEND_RST 1 /* Reset interrupt bit position */
|
|
#define BITP_IPEND_EMU 0 /* Emulator interrupt bit position */
|
|
#define BITM_IPEND_IVG15 (_ADI_MSK(0x00008000,uint32_t)) /* IVG15 interrupt bit position */
|
|
#define BITM_IPEND_IVG14 (_ADI_MSK(0x00004000,uint32_t)) /* IVG14 interrupt bit position */
|
|
#define BITM_IPEND_IVG13 (_ADI_MSK(0x00002000,uint32_t)) /* IVG13 interrupt bit position */
|
|
#define BITM_IPEND_IVG12 (_ADI_MSK(0x00001000,uint32_t)) /* IVG12 interrupt bit position */
|
|
#define BITM_IPEND_IVG11 (_ADI_MSK(0x00000800,uint32_t)) /* IVG11 interrupt bit position */
|
|
#define BITM_IPEND_IVG10 (_ADI_MSK(0x00000400,uint32_t)) /* IVG10 interrupt bit position */
|
|
#define BITM_IPEND_IVG9 (_ADI_MSK(0x00000200,uint32_t)) /* IVG9 interrupt bit position */
|
|
#define BITM_IPEND_IVG8 (_ADI_MSK(0x00000100,uint32_t)) /* IVG8 interrupt bit position */
|
|
#define BITM_IPEND_IVG7 (_ADI_MSK(0x00000080,uint32_t)) /* IVG7 interrupt bit position */
|
|
#define BITM_IPEND_IVTMR (_ADI_MSK(0x00000040,uint32_t)) /* Timer interrupt bit position */
|
|
#define BITM_IPEND_IVHW (_ADI_MSK(0x00000020,uint32_t)) /* Hardware Error interrupt bit position */
|
|
#define BITM_IPEND_IRPTEN (_ADI_MSK(0x00000010,uint32_t)) /* Global interrupt enable bit position */
|
|
#define BITM_IPEND_EVX (_ADI_MSK(0x00000008,uint32_t)) /* Exception bit position */
|
|
#define BITM_IPEND_NMI (_ADI_MSK(0x00000004,uint32_t)) /* Non Maskable interrupt bit position */
|
|
#define BITM_IPEND_RST (_ADI_MSK(0x00000002,uint32_t)) /* Reset interrupt bit position */
|
|
#define BITM_IPEND_EMU (_ADI_MSK(0x00000001,uint32_t)) /* Emulator interrupt bit position */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
ILAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_ILAT_IVG15 15 /* IVG15 interrupt bit position */
|
|
#define BITP_ILAT_IVG14 14 /* IVG14 interrupt bit position */
|
|
#define BITP_ILAT_IVG13 13 /* IVG13 interrupt bit position */
|
|
#define BITP_ILAT_IVG12 12 /* IVG12 interrupt bit position */
|
|
#define BITP_ILAT_IVG11 11 /* IVG11 interrupt bit position */
|
|
#define BITP_ILAT_IVG10 10 /* IVG10 interrupt bit position */
|
|
#define BITP_ILAT_IVG9 9 /* IVG9 interrupt bit position */
|
|
#define BITP_ILAT_IVG8 8 /* IVG8 interrupt bit position */
|
|
#define BITP_ILAT_IVG7 7 /* IVG7 interrupt bit position */
|
|
#define BITP_ILAT_IVTMR 6 /* Timer interrupt bit position */
|
|
#define BITP_ILAT_IVHW 5 /* Hardware Error interrupt bit position */
|
|
#define BITP_ILAT_EVX 3 /* Exception bit position */
|
|
#define BITP_ILAT_NMI 2 /* Non Maskable interrupt bit position */
|
|
#define BITP_ILAT_RST 1 /* Reset interrupt bit position */
|
|
#define BITP_ILAT_EMU 0 /* Emulator interrupt bit position */
|
|
#define BITM_ILAT_IVG15 (_ADI_MSK(0x00008000,uint32_t)) /* IVG15 interrupt bit position */
|
|
#define BITM_ILAT_IVG14 (_ADI_MSK(0x00004000,uint32_t)) /* IVG14 interrupt bit position */
|
|
#define BITM_ILAT_IVG13 (_ADI_MSK(0x00002000,uint32_t)) /* IVG13 interrupt bit position */
|
|
#define BITM_ILAT_IVG12 (_ADI_MSK(0x00001000,uint32_t)) /* IVG12 interrupt bit position */
|
|
#define BITM_ILAT_IVG11 (_ADI_MSK(0x00000800,uint32_t)) /* IVG11 interrupt bit position */
|
|
#define BITM_ILAT_IVG10 (_ADI_MSK(0x00000400,uint32_t)) /* IVG10 interrupt bit position */
|
|
#define BITM_ILAT_IVG9 (_ADI_MSK(0x00000200,uint32_t)) /* IVG9 interrupt bit position */
|
|
#define BITM_ILAT_IVG8 (_ADI_MSK(0x00000100,uint32_t)) /* IVG8 interrupt bit position */
|
|
#define BITM_ILAT_IVG7 (_ADI_MSK(0x00000080,uint32_t)) /* IVG7 interrupt bit position */
|
|
#define BITM_ILAT_IVTMR (_ADI_MSK(0x00000040,uint32_t)) /* Timer interrupt bit position */
|
|
#define BITM_ILAT_IVHW (_ADI_MSK(0x00000020,uint32_t)) /* Hardware Error interrupt bit position */
|
|
#define BITM_ILAT_EVX (_ADI_MSK(0x00000008,uint32_t)) /* Exception bit position */
|
|
#define BITM_ILAT_NMI (_ADI_MSK(0x00000004,uint32_t)) /* Non Maskable interrupt bit position */
|
|
#define BITM_ILAT_RST (_ADI_MSK(0x00000002,uint32_t)) /* Reset interrupt bit position */
|
|
#define BITM_ILAT_EMU (_ADI_MSK(0x00000001,uint32_t)) /* Emulator interrupt bit position */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
IPRIO Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_IPRIO_IPRIO_MARK 0 /* Priority Watermark */
|
|
#define BITM_IPRIO_IPRIO_MARK (_ADI_MSK(0x0000000F,uint32_t)) /* Priority Watermark */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
CEC_SID Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_CEC_SID_SID 0 /* System Interrupt ID */
|
|
#define BITM_CEC_SID_SID (_ADI_MSK(0x000000FF,uint32_t)) /* System Interrupt ID */
|
|
|
|
/* ==================================================
|
|
Core Timer Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
TMR0
|
|
========================= */
|
|
#define TCNTL 0xFFE03000 /* Timer Control Register */
|
|
#define TPERIOD 0xFFE03004 /* Timer Period Register */
|
|
#define TSCALE 0xFFE03008 /* Timer Scale Register */
|
|
#define TCOUNT 0xFFE0300C /* Timer Count Register */
|
|
|
|
/* =========================
|
|
TMR
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TCNTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TCNTL_INT 3 /* Interrupt Status (sticky) */
|
|
#define BITP_TCNTL_AUTORLD 2 /* Auto Reload Enable */
|
|
#define BITP_TCNTL_EN 1 /* Timer Enable */
|
|
#define BITP_TCNTL_PWR 0 /* Low Power Mode Select */
|
|
#define BITM_TCNTL_INT (_ADI_MSK(0x00000008,uint32_t)) /* Interrupt Status (sticky) */
|
|
#define BITM_TCNTL_AUTORLD (_ADI_MSK(0x00000004,uint32_t)) /* Auto Reload Enable */
|
|
#define BITM_TCNTL_EN (_ADI_MSK(0x00000002,uint32_t)) /* Timer Enable */
|
|
#define BITM_TCNTL_PWR (_ADI_MSK(0x00000001,uint32_t)) /* Low Power Mode Select */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TSCALE Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TSCALE_SCALE 0 /* Timer Scaling Value */
|
|
#define BITM_TSCALE_SCALE (_ADI_MSK(0x000000FF,uint32_t)) /* Timer Scaling Value */
|
|
|
|
/* ==================================================
|
|
Debug Unit Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
DBG0
|
|
========================= */
|
|
#define DSPID 0xFFE05000 /* DSP Identification Register */
|
|
|
|
/* =========================
|
|
DBG
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
DSPID Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_DSPID_COMPANY 24 /* Analog Devices, Inc. */
|
|
#define BITP_DSPID_MAJOR 16 /* Major Architectural Change */
|
|
#define BITP_DSPID_COREID 0 /* Core ID */
|
|
#define BITM_DSPID_COMPANY (_ADI_MSK(0xFF000000,uint32_t)) /* Analog Devices, Inc. */
|
|
|
|
#define BITM_DSPID_MAJOR (_ADI_MSK(0x00FF0000,uint32_t)) /* Major Architectural Change */
|
|
#define ENUM_DSPID_BF533 (_ADI_MSK(0x00040000,uint32_t)) /* MAJOR: ADSP-BF533 Core Compatible */
|
|
#define BITM_DSPID_COREID (_ADI_MSK(0x000000FF,uint32_t)) /* Core ID */
|
|
|
|
/* ==================================================
|
|
Trace Unit Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
TB0
|
|
========================= */
|
|
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
|
|
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
|
|
#define TBUF 0xFFE06100 /* Trace Buffer */
|
|
|
|
/* =========================
|
|
TB
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TBUFCTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TBUFCTL_COMPRESS 3 /* Trace Buffer Compression */
|
|
#define BITP_TBUFCTL_OVF 2 /* Trace Buffer Overflow */
|
|
#define BITP_TBUFCTL_EN 1 /* Trace Buffer Enable */
|
|
#define BITP_TBUFCTL_PWR 0 /* Trace Buffer Power */
|
|
#define BITM_TBUFCTL_COMPRESS (_ADI_MSK(0x00000018,uint32_t)) /* Trace Buffer Compression */
|
|
#define BITM_TBUFCTL_OVF (_ADI_MSK(0x00000004,uint32_t)) /* Trace Buffer Overflow */
|
|
#define BITM_TBUFCTL_EN (_ADI_MSK(0x00000002,uint32_t)) /* Trace Buffer Enable */
|
|
#define BITM_TBUFCTL_PWR (_ADI_MSK(0x00000001,uint32_t)) /* Trace Buffer Power */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
TBUFSTAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_TBUFSTAT_CNT 0 /* Trace Buffer Count */
|
|
#define BITM_TBUFSTAT_CNT (_ADI_MSK(0x0000001F,uint32_t)) /* Trace Buffer Count */
|
|
|
|
/* ==================================================
|
|
Watchpoint Unit Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
WP0
|
|
========================= */
|
|
#define WPIACTL 0xFFE07000 /* Watchpoint Instruction Address Control Register 01 */
|
|
#define WPIA0 0xFFE07040 /* Watchpoint Instruction Address Register */
|
|
#define WPIA1 0xFFE07044 /* Watchpoint Instruction Address Register */
|
|
#define WPIA2 0xFFE07048 /* Watchpoint Instruction Address Register */
|
|
#define WPIA3 0xFFE0704C /* Watchpoint Instruction Address Register */
|
|
#define WPIA4 0xFFE07050 /* Watchpoint Instruction Address Register */
|
|
#define WPIA5 0xFFE07054 /* Watchpoint Instruction Address Register */
|
|
#define WPIACNT0 0xFFE07080 /* Watchpoint Instruction Address Count Register */
|
|
#define WPIACNT1 0xFFE07084 /* Watchpoint Instruction Address Count Register */
|
|
#define WPIACNT2 0xFFE07088 /* Watchpoint Instruction Address Count Register */
|
|
#define WPIACNT3 0xFFE0708C /* Watchpoint Instruction Address Count Register */
|
|
#define WPIACNT4 0xFFE07090 /* Watchpoint Instruction Address Count Register */
|
|
#define WPIACNT5 0xFFE07094 /* Watchpoint Instruction Address Count Register */
|
|
#define WPDACTL 0xFFE07100 /* Watchpoint Data Address Control Register */
|
|
#define WPDA0 0xFFE07140 /* Watchpoint Data Address Register */
|
|
#define WPDA1 0xFFE07144 /* Watchpoint Data Address Register */
|
|
#define WPDACNT0 0xFFE07180 /* Watchpoint Data Address Count Value Register */
|
|
#define WPDACNT1 0xFFE07184 /* Watchpoint Data Address Count Value Register */
|
|
#define WPSTAT 0xFFE07200 /* Watchpoint Status Register */
|
|
|
|
/* =========================
|
|
WP
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
WPIACTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_WPIACTL_WPAND 25 /* And Triggers */
|
|
#define BITP_WPIACTL_ACT5 24 /* Action field for WPIA5 */
|
|
#define BITP_WPIACTL_ACT4 23 /* Action field for WPIA4 */
|
|
#define BITP_WPIACTL_ENCNT5 22 /* Enable Counter for WPIA5 */
|
|
#define BITP_WPIACTL_ENCNT4 21 /* Enable Counter for WPIA4 */
|
|
#define BITP_WPIACTL_ENIA5 20 /* Enable WPIA5 */
|
|
#define BITP_WPIACTL_ENIA4 19 /* Enable WPIA4 */
|
|
#define BITP_WPIACTL_INVIR45 18 /* Invert Instruction Range 45 */
|
|
#define BITP_WPIACTL_ENIR45 17 /* Enable Instruction Range 45 */
|
|
#define BITP_WPIACTL_ACT3 16 /* Action field for WPIA3 */
|
|
#define BITP_WPIACTL_ACT2 15 /* Action field for WPIA2 */
|
|
#define BITP_WPIACTL_ENCNT3 14 /* Enable Counter for WPIA3 */
|
|
#define BITP_WPIACTL_ENCNT2 13 /* Enable Counter for WPIA2 */
|
|
#define BITP_WPIACTL_ENIA3 12 /* Enable WPIA3 */
|
|
#define BITP_WPIACTL_ENIA2 11 /* Enable WPIA2 */
|
|
#define BITP_WPIACTL_INVIR23 10 /* Invert Instruction Range 23 */
|
|
#define BITP_WPIACTL_ENIR23 9 /* Enable Instruction Range 23 */
|
|
#define BITP_WPIACTL_ACT1 8 /* Action field for WPIA1 */
|
|
#define BITP_WPIACTL_ACT0 7 /* Action field for WPIA0 */
|
|
#define BITP_WPIACTL_ENCNT1 6 /* Enable Counter for WPIA1 */
|
|
#define BITP_WPIACTL_ENCNT0 5 /* Enable Counter for WPIA0 */
|
|
#define BITP_WPIACTL_ENIA1 4 /* Enable WPIA1 */
|
|
#define BITP_WPIACTL_ENIA0 3 /* Enable WPIA0 */
|
|
#define BITP_WPIACTL_INVIR01 2 /* Invert Instruction Range 01 */
|
|
#define BITP_WPIACTL_ENIR01 1 /* Enable Instruction Range 01 */
|
|
#define BITP_WPIACTL_PWR 0 /* Power */
|
|
#define BITM_WPIACTL_WPAND (_ADI_MSK(0x02000000,uint32_t)) /* And Triggers */
|
|
#define BITM_WPIACTL_ACT5 (_ADI_MSK(0x01000000,uint32_t)) /* Action field for WPIA5 */
|
|
#define BITM_WPIACTL_ACT4 (_ADI_MSK(0x00800000,uint32_t)) /* Action field for WPIA4 */
|
|
#define BITM_WPIACTL_ENCNT5 (_ADI_MSK(0x00400000,uint32_t)) /* Enable Counter for WPIA5 */
|
|
#define BITM_WPIACTL_ENCNT4 (_ADI_MSK(0x00200000,uint32_t)) /* Enable Counter for WPIA4 */
|
|
#define BITM_WPIACTL_ENIA5 (_ADI_MSK(0x00100000,uint32_t)) /* Enable WPIA5 */
|
|
#define BITM_WPIACTL_ENIA4 (_ADI_MSK(0x00080000,uint32_t)) /* Enable WPIA4 */
|
|
#define BITM_WPIACTL_INVIR45 (_ADI_MSK(0x00040000,uint32_t)) /* Invert Instruction Range 45 */
|
|
#define BITM_WPIACTL_ENIR45 (_ADI_MSK(0x00020000,uint32_t)) /* Enable Instruction Range 45 */
|
|
#define BITM_WPIACTL_ACT3 (_ADI_MSK(0x00010000,uint32_t)) /* Action field for WPIA3 */
|
|
#define BITM_WPIACTL_ACT2 (_ADI_MSK(0x00008000,uint32_t)) /* Action field for WPIA2 */
|
|
#define BITM_WPIACTL_ENCNT3 (_ADI_MSK(0x00004000,uint32_t)) /* Enable Counter for WPIA3 */
|
|
#define BITM_WPIACTL_ENCNT2 (_ADI_MSK(0x00002000,uint32_t)) /* Enable Counter for WPIA2 */
|
|
#define BITM_WPIACTL_ENIA3 (_ADI_MSK(0x00001000,uint32_t)) /* Enable WPIA3 */
|
|
#define BITM_WPIACTL_ENIA2 (_ADI_MSK(0x00000800,uint32_t)) /* Enable WPIA2 */
|
|
#define BITM_WPIACTL_INVIR23 (_ADI_MSK(0x00000400,uint32_t)) /* Invert Instruction Range 23 */
|
|
#define BITM_WPIACTL_ENIR23 (_ADI_MSK(0x00000200,uint32_t)) /* Enable Instruction Range 23 */
|
|
#define BITM_WPIACTL_ACT1 (_ADI_MSK(0x00000100,uint32_t)) /* Action field for WPIA1 */
|
|
#define BITM_WPIACTL_ACT0 (_ADI_MSK(0x00000080,uint32_t)) /* Action field for WPIA0 */
|
|
#define BITM_WPIACTL_ENCNT1 (_ADI_MSK(0x00000040,uint32_t)) /* Enable Counter for WPIA1 */
|
|
#define BITM_WPIACTL_ENCNT0 (_ADI_MSK(0x00000020,uint32_t)) /* Enable Counter for WPIA0 */
|
|
#define BITM_WPIACTL_ENIA1 (_ADI_MSK(0x00000010,uint32_t)) /* Enable WPIA1 */
|
|
#define BITM_WPIACTL_ENIA0 (_ADI_MSK(0x00000008,uint32_t)) /* Enable WPIA0 */
|
|
#define BITM_WPIACTL_INVIR01 (_ADI_MSK(0x00000004,uint32_t)) /* Invert Instruction Range 01 */
|
|
#define BITM_WPIACTL_ENIR01 (_ADI_MSK(0x00000002,uint32_t)) /* Enable Instruction Range 01 */
|
|
#define BITM_WPIACTL_PWR (_ADI_MSK(0x00000001,uint32_t)) /* Power */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
WPIACNT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_WPIACNT_CNT 0 /* Count Value */
|
|
#define BITM_WPIACNT_CNT (_ADI_MSK(0x0000FFFF,uint32_t)) /* Count Value */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
WPDACTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_WPDACTL_ACC1 12 /* Access type for WPDA1 */
|
|
#define BITP_WPDACTL_SRC1 10 /* DAG Source for WPDA1 */
|
|
#define BITP_WPDACTL_ACC0 8 /* Access type for WPDA0 */
|
|
#define BITP_WPDACTL_SRC0 6 /* DAG Source for WPDA0 */
|
|
#define BITP_WPDACTL_ENCNT1 5 /* Enable WPDA1 Counter */
|
|
#define BITP_WPDACTL_ENCNT0 4 /* Enable WPDA0 Counter */
|
|
#define BITP_WPDACTL_ENDA1 3 /* Enable WPDA1 */
|
|
#define BITP_WPDACTL_ENDA0 2 /* Enable WPDA0 */
|
|
#define BITP_WPDACTL_INVR 1 /* Invert Range Comparision */
|
|
#define BITP_WPDACTL_ENR 0 /* Enable Range Comparison */
|
|
#define BITM_WPDACTL_ACC1 (_ADI_MSK(0x00003000,uint32_t)) /* Access type for WPDA1 */
|
|
#define BITM_WPDACTL_SRC1 (_ADI_MSK(0x00000C00,uint32_t)) /* DAG Source for WPDA1 */
|
|
#define BITM_WPDACTL_ACC0 (_ADI_MSK(0x00000300,uint32_t)) /* Access type for WPDA0 */
|
|
#define BITM_WPDACTL_SRC0 (_ADI_MSK(0x000000C0,uint32_t)) /* DAG Source for WPDA0 */
|
|
#define BITM_WPDACTL_ENCNT1 (_ADI_MSK(0x00000020,uint32_t)) /* Enable WPDA1 Counter */
|
|
#define BITM_WPDACTL_ENCNT0 (_ADI_MSK(0x00000010,uint32_t)) /* Enable WPDA0 Counter */
|
|
#define BITM_WPDACTL_ENDA1 (_ADI_MSK(0x00000008,uint32_t)) /* Enable WPDA1 */
|
|
#define BITM_WPDACTL_ENDA0 (_ADI_MSK(0x00000004,uint32_t)) /* Enable WPDA0 */
|
|
#define BITM_WPDACTL_INVR (_ADI_MSK(0x00000002,uint32_t)) /* Invert Range Comparision */
|
|
#define BITM_WPDACTL_ENR (_ADI_MSK(0x00000001,uint32_t)) /* Enable Range Comparison */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
WPDACNT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_WPDACNT_CNT 0 /* Count Value */
|
|
#define BITM_WPDACNT_CNT (_ADI_MSK(0x0000FFFF,uint32_t)) /* Count Value */
|
|
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
WPSTAT Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_WPSTAT_DA1 7 /* WPDA1 match */
|
|
#define BITP_WPSTAT_DA0 6 /* WPDA0 or WPDA0:1 range match */
|
|
#define BITP_WPSTAT_IA5 5 /* WPIA5 match */
|
|
#define BITP_WPSTAT_IA4 4 /* WPIA4 or WPIA4:5 range match */
|
|
#define BITP_WPSTAT_IA3 3 /* WPIA3 match */
|
|
#define BITP_WPSTAT_IA2 2 /* WPIA2 or WPIA2:3 range match */
|
|
#define BITP_WPSTAT_IA1 1 /* WPIA1 match */
|
|
#define BITP_WPSTAT_IA0 0 /* WPIA0 or WPIA0:1 range match */
|
|
#define BITM_WPSTAT_DA1 (_ADI_MSK(0x00000080,uint32_t)) /* WPDA1 match */
|
|
#define BITM_WPSTAT_DA0 (_ADI_MSK(0x00000040,uint32_t)) /* WPDA0 or WPDA0:1 range match */
|
|
#define BITM_WPSTAT_IA5 (_ADI_MSK(0x00000020,uint32_t)) /* WPIA5 match */
|
|
#define BITM_WPSTAT_IA4 (_ADI_MSK(0x00000010,uint32_t)) /* WPIA4 or WPIA4:5 range match */
|
|
#define BITM_WPSTAT_IA3 (_ADI_MSK(0x00000008,uint32_t)) /* WPIA3 match */
|
|
#define BITM_WPSTAT_IA2 (_ADI_MSK(0x00000004,uint32_t)) /* WPIA2 or WPIA2:3 range match */
|
|
#define BITM_WPSTAT_IA1 (_ADI_MSK(0x00000002,uint32_t)) /* WPIA1 match */
|
|
#define BITM_WPSTAT_IA0 (_ADI_MSK(0x00000001,uint32_t)) /* WPIA0 or WPIA0:1 range match */
|
|
|
|
/* ==================================================
|
|
Performance Monitor Registers
|
|
================================================== */
|
|
|
|
/* =========================
|
|
PF0
|
|
========================= */
|
|
#define PFCTL 0xFFE08000 /* Performance Monitor Control Register */
|
|
#define PFCNTR0 0xFFE08100 /* Performance Monitor Counter 0 */
|
|
#define PFCNTR1 0xFFE08104 /* Performance Monitor Counter 1 */
|
|
|
|
/* =========================
|
|
PF
|
|
========================= */
|
|
/* ------------------------------------------------------------------------------------------------------------------------
|
|
PFCTL Pos/Masks Description
|
|
------------------------------------------------------------------------------------------------------------------------ */
|
|
#define BITP_PFCTL_CNT1 25 /* Count Cycles or Edges 1 */
|
|
#define BITP_PFCTL_CNT0 24 /* Count Cycles or Edges 0 */
|
|
#define BITP_PFCTL_MON1 16 /* Monitor 1 Events */
|
|
#define BITP_PFCTL_ENA1 14 /* Enable Monitor 1 */
|
|
#define BITP_PFCTL_EVENT1 13 /* Emulator or Exception Event 1 */
|
|
#define BITP_PFCTL_MON0 5 /* Monitor 0 Events */
|
|
#define BITP_PFCTL_ENA0 3 /* Enable Monitor 0 */
|
|
#define BITP_PFCTL_EVENT0 2 /* Emulator or Exception Event 0 */
|
|
#define BITP_PFCTL_PWR 0 /* Power */
|
|
#define BITM_PFCTL_CNT1 (_ADI_MSK(0x02000000,uint32_t)) /* Count Cycles or Edges 1 */
|
|
#define BITM_PFCTL_CNT0 (_ADI_MSK(0x01000000,uint32_t)) /* Count Cycles or Edges 0 */
|
|
#define BITM_PFCTL_MON1 (_ADI_MSK(0x00FF0000,uint32_t)) /* Monitor 1 Events */
|
|
#define BITM_PFCTL_ENA1 (_ADI_MSK(0x0000C000,uint32_t)) /* Enable Monitor 1 */
|
|
#define BITM_PFCTL_EVENT1 (_ADI_MSK(0x00002000,uint32_t)) /* Emulator or Exception Event 1 */
|
|
#define BITM_PFCTL_MON0 (_ADI_MSK(0x00001FE0,uint32_t)) /* Monitor 0 Events */
|
|
#define BITM_PFCTL_ENA0 (_ADI_MSK(0x00000018,uint32_t)) /* Enable Monitor 0 */
|
|
#define BITM_PFCTL_EVENT0 (_ADI_MSK(0x00000004,uint32_t)) /* Emulator or Exception Event 0 */
|
|
#define BITM_PFCTL_PWR (_ADI_MSK(0x00000001,uint32_t)) /* Power */
|
|
|
|
/* ==================================
|
|
DMA Alias Definitions
|
|
================================== */
|
|
#define SPORT0_A_DMA_DSCPTR_NXT (REG_DMA0_DSCPTR_NXT)
|
|
#define SPORT0_A_DMA_ADDRSTART (REG_DMA0_ADDRSTART)
|
|
#define SPORT0_A_DMA_CFG (REG_DMA0_CFG)
|
|
#define SPORT0_A_DMA_XCNT (REG_DMA0_XCNT)
|
|
#define SPORT0_A_DMA_XMOD (REG_DMA0_XMOD)
|
|
#define SPORT0_A_DMA_YCNT (REG_DMA0_YCNT)
|
|
#define SPORT0_A_DMA_YMOD (REG_DMA0_YMOD)
|
|
#define SPORT0_A_DMA_DSCPTR_CUR (REG_DMA0_DSCPTR_CUR)
|
|
#define SPORT0_A_DMA_DSCPTR_PRV (REG_DMA0_DSCPTR_PRV)
|
|
#define SPORT0_A_DMA_ADDR_CUR (REG_DMA0_ADDR_CUR)
|
|
#define SPORT0_A_DMA_STAT (REG_DMA0_STAT)
|
|
#define SPORT0_A_DMA_XCNT_CUR (REG_DMA0_XCNT_CUR)
|
|
#define SPORT0_A_DMA_YCNT_CUR (REG_DMA0_YCNT_CUR)
|
|
#define SPORT0_A_DMA_BWLCNT (REG_DMA0_BWLCNT)
|
|
#define SPORT0_A_DMA_BWLCNT_CUR (REG_DMA0_BWLCNT_CUR)
|
|
#define SPORT0_A_DMA_BWMCNT (REG_DMA0_BWMCNT)
|
|
#define SPORT0_A_DMA_BWMCNT_CUR (REG_DMA0_BWMCNT_CUR)
|
|
#define SPORT0_B_DMA_DSCPTR_NXT (REG_DMA1_DSCPTR_NXT)
|
|
#define SPORT0_B_DMA_ADDRSTART (REG_DMA1_ADDRSTART)
|
|
#define SPORT0_B_DMA_CFG (REG_DMA1_CFG)
|
|
#define SPORT0_B_DMA_XCNT (REG_DMA1_XCNT)
|
|
#define SPORT0_B_DMA_XMOD (REG_DMA1_XMOD)
|
|
#define SPORT0_B_DMA_YCNT (REG_DMA1_YCNT)
|
|
#define SPORT0_B_DMA_YMOD (REG_DMA1_YMOD)
|
|
#define SPORT0_B_DMA_DSCPTR_CUR (REG_DMA1_DSCPTR_CUR)
|
|
#define SPORT0_B_DMA_DSCPTR_PRV (REG_DMA1_DSCPTR_PRV)
|
|
#define SPORT0_B_DMA_ADDR_CUR (REG_DMA1_ADDR_CUR)
|
|
#define SPORT0_B_DMA_STAT (REG_DMA1_STAT)
|
|
#define SPORT0_B_DMA_XCNT_CUR (REG_DMA1_XCNT_CUR)
|
|
#define SPORT0_B_DMA_YCNT_CUR (REG_DMA1_YCNT_CUR)
|
|
#define SPORT0_B_DMA_BWLCNT (REG_DMA1_BWLCNT)
|
|
#define SPORT0_B_DMA_BWLCNT_CUR (REG_DMA1_BWLCNT_CUR)
|
|
#define SPORT0_B_DMA_BWMCNT (REG_DMA1_BWMCNT)
|
|
#define SPORT0_B_DMA_BWMCNT_CUR (REG_DMA1_BWMCNT_CUR)
|
|
#define SPORT1_A_DMA_DSCPTR_NXT (REG_DMA2_DSCPTR_NXT)
|
|
#define SPORT1_A_DMA_ADDRSTART (REG_DMA2_ADDRSTART)
|
|
#define SPORT1_A_DMA_CFG (REG_DMA2_CFG)
|
|
#define SPORT1_A_DMA_XCNT (REG_DMA2_XCNT)
|
|
#define SPORT1_A_DMA_XMOD (REG_DMA2_XMOD)
|
|
#define SPORT1_A_DMA_YCNT (REG_DMA2_YCNT)
|
|
#define SPORT1_A_DMA_YMOD (REG_DMA2_YMOD)
|
|
#define SPORT1_A_DMA_DSCPTR_CUR (REG_DMA2_DSCPTR_CUR)
|
|
#define SPORT1_A_DMA_DSCPTR_PRV (REG_DMA2_DSCPTR_PRV)
|
|
#define SPORT1_A_DMA_ADDR_CUR (REG_DMA2_ADDR_CUR)
|
|
#define SPORT1_A_DMA_STAT (REG_DMA2_STAT)
|
|
#define SPORT1_A_DMA_XCNT_CUR (REG_DMA2_XCNT_CUR)
|
|
#define SPORT1_A_DMA_YCNT_CUR (REG_DMA2_YCNT_CUR)
|
|
#define SPORT1_A_DMA_BWLCNT (REG_DMA2_BWLCNT)
|
|
#define SPORT1_A_DMA_BWLCNT_CUR (REG_DMA2_BWLCNT_CUR)
|
|
#define SPORT1_A_DMA_BWMCNT (REG_DMA2_BWMCNT)
|
|
#define SPORT1_A_DMA_BWMCNT_CUR (REG_DMA2_BWMCNT_CUR)
|
|
#define SPORT1_B_DMA_DSCPTR_NXT (REG_DMA3_DSCPTR_NXT)
|
|
#define SPORT1_B_DMA_ADDRSTART (REG_DMA3_ADDRSTART)
|
|
#define SPORT1_B_DMA_CFG (REG_DMA3_CFG)
|
|
#define SPORT1_B_DMA_XCNT (REG_DMA3_XCNT)
|
|
#define SPORT1_B_DMA_XMOD (REG_DMA3_XMOD)
|
|
#define SPORT1_B_DMA_YCNT (REG_DMA3_YCNT)
|
|
#define SPORT1_B_DMA_YMOD (REG_DMA3_YMOD)
|
|
#define SPORT1_B_DMA_DSCPTR_CUR (REG_DMA3_DSCPTR_CUR)
|
|
#define SPORT1_B_DMA_DSCPTR_PRV (REG_DMA3_DSCPTR_PRV)
|
|
#define SPORT1_B_DMA_ADDR_CUR (REG_DMA3_ADDR_CUR)
|
|
#define SPORT1_B_DMA_STAT (REG_DMA3_STAT)
|
|
#define SPORT1_B_DMA_XCNT_CUR (REG_DMA3_XCNT_CUR)
|
|
#define SPORT1_B_DMA_YCNT_CUR (REG_DMA3_YCNT_CUR)
|
|
#define SPORT1_B_DMA_BWLCNT (REG_DMA3_BWLCNT)
|
|
#define SPORT1_B_DMA_BWLCNT_CUR (REG_DMA3_BWLCNT_CUR)
|
|
#define SPORT1_B_DMA_BWMCNT (REG_DMA3_BWMCNT)
|
|
#define SPORT1_B_DMA_BWMCNT_CUR (REG_DMA3_BWMCNT_CUR)
|
|
#define SPORT2_A_DMA_DSCPTR_NXT (REG_DMA4_DSCPTR_NXT)
|
|
#define SPORT2_A_DMA_ADDRSTART (REG_DMA4_ADDRSTART)
|
|
#define SPORT2_A_DMA_CFG (REG_DMA4_CFG)
|
|
#define SPORT2_A_DMA_XCNT (REG_DMA4_XCNT)
|
|
#define SPORT2_A_DMA_XMOD (REG_DMA4_XMOD)
|
|
#define SPORT2_A_DMA_YCNT (REG_DMA4_YCNT)
|
|
#define SPORT2_A_DMA_YMOD (REG_DMA4_YMOD)
|
|
#define SPORT2_A_DMA_DSCPTR_CUR (REG_DMA4_DSCPTR_CUR)
|
|
#define SPORT2_A_DMA_DSCPTR_PRV (REG_DMA4_DSCPTR_PRV)
|
|
#define SPORT2_A_DMA_ADDR_CUR (REG_DMA4_ADDR_CUR)
|
|
#define SPORT2_A_DMA_STAT (REG_DMA4_STAT)
|
|
#define SPORT2_A_DMA_XCNT_CUR (REG_DMA4_XCNT_CUR)
|
|
#define SPORT2_A_DMA_YCNT_CUR (REG_DMA4_YCNT_CUR)
|
|
#define SPORT2_A_DMA_BWLCNT (REG_DMA4_BWLCNT)
|
|
#define SPORT2_A_DMA_BWLCNT_CUR (REG_DMA4_BWLCNT_CUR)
|
|
#define SPORT2_A_DMA_BWMCNT (REG_DMA4_BWMCNT)
|
|
#define SPORT2_A_DMA_BWMCNT_CUR (REG_DMA4_BWMCNT_CUR)
|
|
#define SPORT2_B_DMA_DSCPTR_NXT (REG_DMA5_DSCPTR_NXT)
|
|
#define SPORT2_B_DMA_ADDRSTART (REG_DMA5_ADDRSTART)
|
|
#define SPORT2_B_DMA_CFG (REG_DMA5_CFG)
|
|
#define SPORT2_B_DMA_XCNT (REG_DMA5_XCNT)
|
|
#define SPORT2_B_DMA_XMOD (REG_DMA5_XMOD)
|
|
#define SPORT2_B_DMA_YCNT (REG_DMA5_YCNT)
|
|
#define SPORT2_B_DMA_YMOD (REG_DMA5_YMOD)
|
|
#define SPORT2_B_DMA_DSCPTR_CUR (REG_DMA5_DSCPTR_CUR)
|
|
#define SPORT2_B_DMA_DSCPTR_PRV (REG_DMA5_DSCPTR_PRV)
|
|
#define SPORT2_B_DMA_ADDR_CUR (REG_DMA5_ADDR_CUR)
|
|
#define SPORT2_B_DMA_STAT (REG_DMA5_STAT)
|
|
#define SPORT2_B_DMA_XCNT_CUR (REG_DMA5_XCNT_CUR)
|
|
#define SPORT2_B_DMA_YCNT_CUR (REG_DMA5_YCNT_CUR)
|
|
#define SPORT2_B_DMA_BWLCNT (REG_DMA5_BWLCNT)
|
|
#define SPORT2_B_DMA_BWLCNT_CUR (REG_DMA5_BWLCNT_CUR)
|
|
#define SPORT2_B_DMA_BWMCNT (REG_DMA5_BWMCNT)
|
|
#define SPORT2_B_DMA_BWMCNT_CUR (REG_DMA5_BWMCNT_CUR)
|
|
#define SPI0_TXDMA_DSCPTR_NXT (REG_DMA6_DSCPTR_NXT)
|
|
#define SPI0_TXDMA_ADDRSTART (REG_DMA6_ADDRSTART)
|
|
#define SPI0_TXDMA_CFG (REG_DMA6_CFG)
|
|
#define SPI0_TXDMA_XCNT (REG_DMA6_XCNT)
|
|
#define SPI0_TXDMA_XMOD (REG_DMA6_XMOD)
|
|
#define SPI0_TXDMA_YCNT (REG_DMA6_YCNT)
|
|
#define SPI0_TXDMA_YMOD (REG_DMA6_YMOD)
|
|
#define SPI0_TXDMA_DSCPTR_CUR (REG_DMA6_DSCPTR_CUR)
|
|
#define SPI0_TXDMA_DSCPTR_PRV (REG_DMA6_DSCPTR_PRV)
|
|
#define SPI0_TXDMA_ADDR_CUR (REG_DMA6_ADDR_CUR)
|
|
#define SPI0_TXDMA_STAT (REG_DMA6_STAT)
|
|
#define SPI0_TXDMA_XCNT_CUR (REG_DMA6_XCNT_CUR)
|
|
#define SPI0_TXDMA_YCNT_CUR (REG_DMA6_YCNT_CUR)
|
|
#define SPI0_TXDMA_BWLCNT (REG_DMA6_BWLCNT)
|
|
#define SPI0_TXDMA_BWLCNT_CUR (REG_DMA6_BWLCNT_CUR)
|
|
#define SPI0_TXDMA_BWMCNT (REG_DMA6_BWMCNT)
|
|
#define SPI0_TXDMA_BWMCNT_CUR (REG_DMA6_BWMCNT_CUR)
|
|
#define SPI0_RXDMA_DSCPTR_NXT (REG_DMA7_DSCPTR_NXT)
|
|
#define SPI0_RXDMA_ADDRSTART (REG_DMA7_ADDRSTART)
|
|
#define SPI0_RXDMA_CFG (REG_DMA7_CFG)
|
|
#define SPI0_RXDMA_XCNT (REG_DMA7_XCNT)
|
|
#define SPI0_RXDMA_XMOD (REG_DMA7_XMOD)
|
|
#define SPI0_RXDMA_YCNT (REG_DMA7_YCNT)
|
|
#define SPI0_RXDMA_YMOD (REG_DMA7_YMOD)
|
|
#define SPI0_RXDMA_DSCPTR_CUR (REG_DMA7_DSCPTR_CUR)
|
|
#define SPI0_RXDMA_DSCPTR_PRV (REG_DMA7_DSCPTR_PRV)
|
|
#define SPI0_RXDMA_ADDR_CUR (REG_DMA7_ADDR_CUR)
|
|
#define SPI0_RXDMA_STAT (REG_DMA7_STAT)
|
|
#define SPI0_RXDMA_XCNT_CUR (REG_DMA7_XCNT_CUR)
|
|
#define SPI0_RXDMA_YCNT_CUR (REG_DMA7_YCNT_CUR)
|
|
#define SPI0_RXDMA_BWLCNT (REG_DMA7_BWLCNT)
|
|
#define SPI0_RXDMA_BWLCNT_CUR (REG_DMA7_BWLCNT_CUR)
|
|
#define SPI0_RXDMA_BWMCNT (REG_DMA7_BWMCNT)
|
|
#define SPI0_RXDMA_BWMCNT_CUR (REG_DMA7_BWMCNT_CUR)
|
|
#define SPI1_TXDMA_DSCPTR_NXT (REG_DMA8_DSCPTR_NXT)
|
|
#define SPI1_TXDMA_ADDRSTART (REG_DMA8_ADDRSTART)
|
|
#define SPI1_TXDMA_CFG (REG_DMA8_CFG)
|
|
#define SPI1_TXDMA_XCNT (REG_DMA8_XCNT)
|
|
#define SPI1_TXDMA_XMOD (REG_DMA8_XMOD)
|
|
#define SPI1_TXDMA_YCNT (REG_DMA8_YCNT)
|
|
#define SPI1_TXDMA_YMOD (REG_DMA8_YMOD)
|
|
#define SPI1_TXDMA_DSCPTR_CUR (REG_DMA8_DSCPTR_CUR)
|
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#define SPI1_TXDMA_DSCPTR_PRV (REG_DMA8_DSCPTR_PRV)
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#define SPI1_TXDMA_ADDR_CUR (REG_DMA8_ADDR_CUR)
|
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#define SPI1_TXDMA_STAT (REG_DMA8_STAT)
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#define SPI1_TXDMA_XCNT_CUR (REG_DMA8_XCNT_CUR)
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#define SPI1_TXDMA_YCNT_CUR (REG_DMA8_YCNT_CUR)
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#define SPI1_TXDMA_BWLCNT (REG_DMA8_BWLCNT)
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#define SPI1_TXDMA_BWLCNT_CUR (REG_DMA8_BWLCNT_CUR)
|
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#define SPI1_TXDMA_BWMCNT (REG_DMA8_BWMCNT)
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#define SPI1_TXDMA_BWMCNT_CUR (REG_DMA8_BWMCNT_CUR)
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#define SPI1_RXDMA_DSCPTR_NXT (REG_DMA9_DSCPTR_NXT)
|
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#define SPI1_RXDMA_ADDRSTART (REG_DMA9_ADDRSTART)
|
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#define SPI1_RXDMA_CFG (REG_DMA9_CFG)
|
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#define SPI1_RXDMA_XCNT (REG_DMA9_XCNT)
|
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#define SPI1_RXDMA_XMOD (REG_DMA9_XMOD)
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#define SPI1_RXDMA_YCNT (REG_DMA9_YCNT)
|
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#define SPI1_RXDMA_YMOD (REG_DMA9_YMOD)
|
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#define SPI1_RXDMA_DSCPTR_CUR (REG_DMA9_DSCPTR_CUR)
|
|
#define SPI1_RXDMA_DSCPTR_PRV (REG_DMA9_DSCPTR_PRV)
|
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#define SPI1_RXDMA_ADDR_CUR (REG_DMA9_ADDR_CUR)
|
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#define SPI1_RXDMA_STAT (REG_DMA9_STAT)
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#define SPI1_RXDMA_XCNT_CUR (REG_DMA9_XCNT_CUR)
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#define SPI1_RXDMA_YCNT_CUR (REG_DMA9_YCNT_CUR)
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#define SPI1_RXDMA_BWLCNT (REG_DMA9_BWLCNT)
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#define SPI1_RXDMA_BWLCNT_CUR (REG_DMA9_BWLCNT_CUR)
|
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#define SPI1_RXDMA_BWMCNT (REG_DMA9_BWMCNT)
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#define SPI1_RXDMA_BWMCNT_CUR (REG_DMA9_BWMCNT_CUR)
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#define RSI0_DMA_DSCPTR_NXT (REG_DMA10_DSCPTR_NXT)
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#define RSI0_DMA_ADDRSTART (REG_DMA10_ADDRSTART)
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#define RSI0_DMA_CFG (REG_DMA10_CFG)
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#define RSI0_DMA_XCNT (REG_DMA10_XCNT)
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#define RSI0_DMA_XMOD (REG_DMA10_XMOD)
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#define RSI0_DMA_YCNT (REG_DMA10_YCNT)
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#define RSI0_DMA_YMOD (REG_DMA10_YMOD)
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#define RSI0_DMA_DSCPTR_CUR (REG_DMA10_DSCPTR_CUR)
|
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#define RSI0_DMA_DSCPTR_PRV (REG_DMA10_DSCPTR_PRV)
|
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#define RSI0_DMA_ADDR_CUR (REG_DMA10_ADDR_CUR)
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#define RSI0_DMA_STAT (REG_DMA10_STAT)
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#define RSI0_DMA_XCNT_CUR (REG_DMA10_XCNT_CUR)
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#define RSI0_DMA_YCNT_CUR (REG_DMA10_YCNT_CUR)
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#define RSI0_DMA_BWLCNT (REG_DMA10_BWLCNT)
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#define RSI0_DMA_BWLCNT_CUR (REG_DMA10_BWLCNT_CUR)
|
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#define RSI0_DMA_BWMCNT (REG_DMA10_BWMCNT)
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#define RSI0_DMA_BWMCNT_CUR (REG_DMA10_BWMCNT_CUR)
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#define SDU0_DMA_DSCPTR_NXT (REG_DMA11_DSCPTR_NXT)
|
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#define SDU0_DMA_ADDRSTART (REG_DMA11_ADDRSTART)
|
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#define SDU0_DMA_CFG (REG_DMA11_CFG)
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#define SDU0_DMA_XCNT (REG_DMA11_XCNT)
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#define SDU0_DMA_XMOD (REG_DMA11_XMOD)
|
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#define SDU0_DMA_YCNT (REG_DMA11_YCNT)
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#define SDU0_DMA_YMOD (REG_DMA11_YMOD)
|
|
#define SDU0_DMA_DSCPTR_CUR (REG_DMA11_DSCPTR_CUR)
|
|
#define SDU0_DMA_DSCPTR_PRV (REG_DMA11_DSCPTR_PRV)
|
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#define SDU0_DMA_ADDR_CUR (REG_DMA11_ADDR_CUR)
|
|
#define SDU0_DMA_STAT (REG_DMA11_STAT)
|
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#define SDU0_DMA_XCNT_CUR (REG_DMA11_XCNT_CUR)
|
|
#define SDU0_DMA_YCNT_CUR (REG_DMA11_YCNT_CUR)
|
|
#define SDU0_DMA_BWLCNT (REG_DMA11_BWLCNT)
|
|
#define SDU0_DMA_BWLCNT_CUR (REG_DMA11_BWLCNT_CUR)
|
|
#define SDU0_DMA_BWMCNT (REG_DMA11_BWMCNT)
|
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#define SDU0_DMA_BWMCNT_CUR (REG_DMA11_BWMCNT_CUR)
|
|
#define LP0_DMA_DSCPTR_NXT (REG_DMA13_DSCPTR_NXT)
|
|
#define LP0_DMA_ADDRSTART (REG_DMA13_ADDRSTART)
|
|
#define LP0_DMA_CFG (REG_DMA13_CFG)
|
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#define LP0_DMA_XCNT (REG_DMA13_XCNT)
|
|
#define LP0_DMA_XMOD (REG_DMA13_XMOD)
|
|
#define LP0_DMA_YCNT (REG_DMA13_YCNT)
|
|
#define LP0_DMA_YMOD (REG_DMA13_YMOD)
|
|
#define LP0_DMA_DSCPTR_CUR (REG_DMA13_DSCPTR_CUR)
|
|
#define LP0_DMA_DSCPTR_PRV (REG_DMA13_DSCPTR_PRV)
|
|
#define LP0_DMA_ADDR_CUR (REG_DMA13_ADDR_CUR)
|
|
#define LP0_DMA_STAT (REG_DMA13_STAT)
|
|
#define LP0_DMA_XCNT_CUR (REG_DMA13_XCNT_CUR)
|
|
#define LP0_DMA_YCNT_CUR (REG_DMA13_YCNT_CUR)
|
|
#define LP0_DMA_BWLCNT (REG_DMA13_BWLCNT)
|
|
#define LP0_DMA_BWLCNT_CUR (REG_DMA13_BWLCNT_CUR)
|
|
#define LP0_DMA_BWMCNT (REG_DMA13_BWMCNT)
|
|
#define LP0_DMA_BWMCNT_CUR (REG_DMA13_BWMCNT_CUR)
|
|
#define LP1_DMA_DSCPTR_NXT (REG_DMA14_DSCPTR_NXT)
|
|
#define LP1_DMA_ADDRSTART (REG_DMA14_ADDRSTART)
|
|
#define LP1_DMA_CFG (REG_DMA14_CFG)
|
|
#define LP1_DMA_XCNT (REG_DMA14_XCNT)
|
|
#define LP1_DMA_XMOD (REG_DMA14_XMOD)
|
|
#define LP1_DMA_YCNT (REG_DMA14_YCNT)
|
|
#define LP1_DMA_YMOD (REG_DMA14_YMOD)
|
|
#define LP1_DMA_DSCPTR_CUR (REG_DMA14_DSCPTR_CUR)
|
|
#define LP1_DMA_DSCPTR_PRV (REG_DMA14_DSCPTR_PRV)
|
|
#define LP1_DMA_ADDR_CUR (REG_DMA14_ADDR_CUR)
|
|
#define LP1_DMA_STAT (REG_DMA14_STAT)
|
|
#define LP1_DMA_XCNT_CUR (REG_DMA14_XCNT_CUR)
|
|
#define LP1_DMA_YCNT_CUR (REG_DMA14_YCNT_CUR)
|
|
#define LP1_DMA_BWLCNT (REG_DMA14_BWLCNT)
|
|
#define LP1_DMA_BWLCNT_CUR (REG_DMA14_BWLCNT_CUR)
|
|
#define LP1_DMA_BWMCNT (REG_DMA14_BWMCNT)
|
|
#define LP1_DMA_BWMCNT_CUR (REG_DMA14_BWMCNT_CUR)
|
|
#define LP2_DMA_DSCPTR_NXT (REG_DMA15_DSCPTR_NXT)
|
|
#define LP2_DMA_ADDRSTART (REG_DMA15_ADDRSTART)
|
|
#define LP2_DMA_CFG (REG_DMA15_CFG)
|
|
#define LP2_DMA_XCNT (REG_DMA15_XCNT)
|
|
#define LP2_DMA_XMOD (REG_DMA15_XMOD)
|
|
#define LP2_DMA_YCNT (REG_DMA15_YCNT)
|
|
#define LP2_DMA_YMOD (REG_DMA15_YMOD)
|
|
#define LP2_DMA_DSCPTR_CUR (REG_DMA15_DSCPTR_CUR)
|
|
#define LP2_DMA_DSCPTR_PRV (REG_DMA15_DSCPTR_PRV)
|
|
#define LP2_DMA_ADDR_CUR (REG_DMA15_ADDR_CUR)
|
|
#define LP2_DMA_STAT (REG_DMA15_STAT)
|
|
#define LP2_DMA_XCNT_CUR (REG_DMA15_XCNT_CUR)
|
|
#define LP2_DMA_YCNT_CUR (REG_DMA15_YCNT_CUR)
|
|
#define LP2_DMA_BWLCNT (REG_DMA15_BWLCNT)
|
|
#define LP2_DMA_BWLCNT_CUR (REG_DMA15_BWLCNT_CUR)
|
|
#define LP2_DMA_BWMCNT (REG_DMA15_BWMCNT)
|
|
#define LP2_DMA_BWMCNT_CUR (REG_DMA15_BWMCNT_CUR)
|
|
#define LP3_DMA_DSCPTR_NXT (REG_DMA16_DSCPTR_NXT)
|
|
#define LP3_DMA_ADDRSTART (REG_DMA16_ADDRSTART)
|
|
#define LP3_DMA_CFG (REG_DMA16_CFG)
|
|
#define LP3_DMA_XCNT (REG_DMA16_XCNT)
|
|
#define LP3_DMA_XMOD (REG_DMA16_XMOD)
|
|
#define LP3_DMA_YCNT (REG_DMA16_YCNT)
|
|
#define LP3_DMA_YMOD (REG_DMA16_YMOD)
|
|
#define LP3_DMA_DSCPTR_CUR (REG_DMA16_DSCPTR_CUR)
|
|
#define LP3_DMA_DSCPTR_PRV (REG_DMA16_DSCPTR_PRV)
|
|
#define LP3_DMA_ADDR_CUR (REG_DMA16_ADDR_CUR)
|
|
#define LP3_DMA_STAT (REG_DMA16_STAT)
|
|
#define LP3_DMA_XCNT_CUR (REG_DMA16_XCNT_CUR)
|
|
#define LP3_DMA_YCNT_CUR (REG_DMA16_YCNT_CUR)
|
|
#define LP3_DMA_BWLCNT (REG_DMA16_BWLCNT)
|
|
#define LP3_DMA_BWLCNT_CUR (REG_DMA16_BWLCNT_CUR)
|
|
#define LP3_DMA_BWMCNT (REG_DMA16_BWMCNT)
|
|
#define LP3_DMA_BWMCNT_CUR (REG_DMA16_BWMCNT_CUR)
|
|
#define UART0_TXDMA_DSCPTR_NXT (REG_DMA17_DSCPTR_NXT)
|
|
#define UART0_TXDMA_ADDRSTART (REG_DMA17_ADDRSTART)
|
|
#define UART0_TXDMA_CFG (REG_DMA17_CFG)
|
|
#define UART0_TXDMA_XCNT (REG_DMA17_XCNT)
|
|
#define UART0_TXDMA_XMOD (REG_DMA17_XMOD)
|
|
#define UART0_TXDMA_YCNT (REG_DMA17_YCNT)
|
|
#define UART0_TXDMA_YMOD (REG_DMA17_YMOD)
|
|
#define UART0_TXDMA_DSCPTR_CUR (REG_DMA17_DSCPTR_CUR)
|
|
#define UART0_TXDMA_DSCPTR_PRV (REG_DMA17_DSCPTR_PRV)
|
|
#define UART0_TXDMA_ADDR_CUR (REG_DMA17_ADDR_CUR)
|
|
#define UART0_TXDMA_STAT (REG_DMA17_STAT)
|
|
#define UART0_TXDMA_XCNT_CUR (REG_DMA17_XCNT_CUR)
|
|
#define UART0_TXDMA_YCNT_CUR (REG_DMA17_YCNT_CUR)
|
|
#define UART0_TXDMA_BWLCNT (REG_DMA17_BWLCNT)
|
|
#define UART0_TXDMA_BWLCNT_CUR (REG_DMA17_BWLCNT_CUR)
|
|
#define UART0_TXDMA_BWMCNT (REG_DMA17_BWMCNT)
|
|
#define UART0_TXDMA_BWMCNT_CUR (REG_DMA17_BWMCNT_CUR)
|
|
#define UART0_RXDMA_DSCPTR_NXT (REG_DMA18_DSCPTR_NXT)
|
|
#define UART0_RXDMA_ADDRSTART (REG_DMA18_ADDRSTART)
|
|
#define UART0_RXDMA_CFG (REG_DMA18_CFG)
|
|
#define UART0_RXDMA_XCNT (REG_DMA18_XCNT)
|
|
#define UART0_RXDMA_XMOD (REG_DMA18_XMOD)
|
|
#define UART0_RXDMA_YCNT (REG_DMA18_YCNT)
|
|
#define UART0_RXDMA_YMOD (REG_DMA18_YMOD)
|
|
#define UART0_RXDMA_DSCPTR_CUR (REG_DMA18_DSCPTR_CUR)
|
|
#define UART0_RXDMA_DSCPTR_PRV (REG_DMA18_DSCPTR_PRV)
|
|
#define UART0_RXDMA_ADDR_CUR (REG_DMA18_ADDR_CUR)
|
|
#define UART0_RXDMA_STAT (REG_DMA18_STAT)
|
|
#define UART0_RXDMA_XCNT_CUR (REG_DMA18_XCNT_CUR)
|
|
#define UART0_RXDMA_YCNT_CUR (REG_DMA18_YCNT_CUR)
|
|
#define UART0_RXDMA_BWLCNT (REG_DMA18_BWLCNT)
|
|
#define UART0_RXDMA_BWLCNT_CUR (REG_DMA18_BWLCNT_CUR)
|
|
#define UART0_RXDMA_BWMCNT (REG_DMA18_BWMCNT)
|
|
#define UART0_RXDMA_BWMCNT_CUR (REG_DMA18_BWMCNT_CUR)
|
|
#define UART1_TXDMA_DSCPTR_NXT (REG_DMA19_DSCPTR_NXT)
|
|
#define UART1_TXDMA_ADDRSTART (REG_DMA19_ADDRSTART)
|
|
#define UART1_TXDMA_CFG (REG_DMA19_CFG)
|
|
#define UART1_TXDMA_XCNT (REG_DMA19_XCNT)
|
|
#define UART1_TXDMA_XMOD (REG_DMA19_XMOD)
|
|
#define UART1_TXDMA_YCNT (REG_DMA19_YCNT)
|
|
#define UART1_TXDMA_YMOD (REG_DMA19_YMOD)
|
|
#define UART1_TXDMA_DSCPTR_CUR (REG_DMA19_DSCPTR_CUR)
|
|
#define UART1_TXDMA_DSCPTR_PRV (REG_DMA19_DSCPTR_PRV)
|
|
#define UART1_TXDMA_ADDR_CUR (REG_DMA19_ADDR_CUR)
|
|
#define UART1_TXDMA_STAT (REG_DMA19_STAT)
|
|
#define UART1_TXDMA_XCNT_CUR (REG_DMA19_XCNT_CUR)
|
|
#define UART1_TXDMA_YCNT_CUR (REG_DMA19_YCNT_CUR)
|
|
#define UART1_TXDMA_BWLCNT (REG_DMA19_BWLCNT)
|
|
#define UART1_TXDMA_BWLCNT_CUR (REG_DMA19_BWLCNT_CUR)
|
|
#define UART1_TXDMA_BWMCNT (REG_DMA19_BWMCNT)
|
|
#define UART1_TXDMA_BWMCNT_CUR (REG_DMA19_BWMCNT_CUR)
|
|
#define UART1_RXDMA_DSCPTR_NXT (REG_DMA20_DSCPTR_NXT)
|
|
#define UART1_RXDMA_ADDRSTART (REG_DMA20_ADDRSTART)
|
|
#define UART1_RXDMA_CFG (REG_DMA20_CFG)
|
|
#define UART1_RXDMA_XCNT (REG_DMA20_XCNT)
|
|
#define UART1_RXDMA_XMOD (REG_DMA20_XMOD)
|
|
#define UART1_RXDMA_YCNT (REG_DMA20_YCNT)
|
|
#define UART1_RXDMA_YMOD (REG_DMA20_YMOD)
|
|
#define UART1_RXDMA_DSCPTR_CUR (REG_DMA20_DSCPTR_CUR)
|
|
#define UART1_RXDMA_DSCPTR_PRV (REG_DMA20_DSCPTR_PRV)
|
|
#define UART1_RXDMA_ADDR_CUR (REG_DMA20_ADDR_CUR)
|
|
#define UART1_RXDMA_STAT (REG_DMA20_STAT)
|
|
#define UART1_RXDMA_XCNT_CUR (REG_DMA20_XCNT_CUR)
|
|
#define UART1_RXDMA_YCNT_CUR (REG_DMA20_YCNT_CUR)
|
|
#define UART1_RXDMA_BWLCNT (REG_DMA20_BWLCNT)
|
|
#define UART1_RXDMA_BWLCNT_CUR (REG_DMA20_BWLCNT_CUR)
|
|
#define UART1_RXDMA_BWMCNT (REG_DMA20_BWMCNT)
|
|
#define UART1_RXDMA_BWMCNT_CUR (REG_DMA20_BWMCNT_CUR)
|
|
#define MDMA0_SRC_DSCPTR_NXT (REG_DMA21_DSCPTR_NXT)
|
|
#define MDMA0_SRC_ADDRSTART (REG_DMA21_ADDRSTART)
|
|
#define MDMA0_SRC_CFG (REG_DMA21_CFG)
|
|
#define MDMA0_SRC_XCNT (REG_DMA21_XCNT)
|
|
#define MDMA0_SRC_XMOD (REG_DMA21_XMOD)
|
|
#define MDMA0_SRC_YCNT (REG_DMA21_YCNT)
|
|
#define MDMA0_SRC_YMOD (REG_DMA21_YMOD)
|
|
#define MDMA0_SRC_DSCPTR_CUR (REG_DMA21_DSCPTR_CUR)
|
|
#define MDMA0_SRC_DSCPTR_PRV (REG_DMA21_DSCPTR_PRV)
|
|
#define MDMA0_SRC_ADDR_CUR (REG_DMA21_ADDR_CUR)
|
|
#define MDMA0_SRC_STAT (REG_DMA21_STAT)
|
|
#define MDMA0_SRC_XCNT_CUR (REG_DMA21_XCNT_CUR)
|
|
#define MDMA0_SRC_YCNT_CUR (REG_DMA21_YCNT_CUR)
|
|
#define MDMA0_SRC_BWLCNT (REG_DMA21_BWLCNT)
|
|
#define MDMA0_SRC_BWLCNT_CUR (REG_DMA21_BWLCNT_CUR)
|
|
#define MDMA0_SRC_BWMCNT (REG_DMA21_BWMCNT)
|
|
#define MDMA0_SRC_BWMCNT_CUR (REG_DMA21_BWMCNT_CUR)
|
|
#define MDMA0_DST_DSCPTR_NXT (REG_DMA22_DSCPTR_NXT)
|
|
#define MDMA0_DST_ADDRSTART (REG_DMA22_ADDRSTART)
|
|
#define MDMA0_DST_CFG (REG_DMA22_CFG)
|
|
#define MDMA0_DST_XCNT (REG_DMA22_XCNT)
|
|
#define MDMA0_DST_XMOD (REG_DMA22_XMOD)
|
|
#define MDMA0_DST_YCNT (REG_DMA22_YCNT)
|
|
#define MDMA0_DST_YMOD (REG_DMA22_YMOD)
|
|
#define MDMA0_DST_DSCPTR_CUR (REG_DMA22_DSCPTR_CUR)
|
|
#define MDMA0_DST_DSCPTR_PRV (REG_DMA22_DSCPTR_PRV)
|
|
#define MDMA0_DST_ADDR_CUR (REG_DMA22_ADDR_CUR)
|
|
#define MDMA0_DST_STAT (REG_DMA22_STAT)
|
|
#define MDMA0_DST_XCNT_CUR (REG_DMA22_XCNT_CUR)
|
|
#define MDMA0_DST_YCNT_CUR (REG_DMA22_YCNT_CUR)
|
|
#define MDMA0_DST_BWLCNT (REG_DMA22_BWLCNT)
|
|
#define MDMA0_DST_BWLCNT_CUR (REG_DMA22_BWLCNT_CUR)
|
|
#define MDMA0_DST_BWMCNT (REG_DMA22_BWMCNT)
|
|
#define MDMA0_DST_BWMCNT_CUR (REG_DMA22_BWMCNT_CUR)
|
|
#define MDMA1_SRC_DSCPTR_NXT (REG_DMA23_DSCPTR_NXT)
|
|
#define MDMA1_SRC_ADDRSTART (REG_DMA23_ADDRSTART)
|
|
#define MDMA1_SRC_CFG (REG_DMA23_CFG)
|
|
#define MDMA1_SRC_XCNT (REG_DMA23_XCNT)
|
|
#define MDMA1_SRC_XMOD (REG_DMA23_XMOD)
|
|
#define MDMA1_SRC_YCNT (REG_DMA23_YCNT)
|
|
#define MDMA1_SRC_YMOD (REG_DMA23_YMOD)
|
|
#define MDMA1_SRC_DSCPTR_CUR (REG_DMA23_DSCPTR_CUR)
|
|
#define MDMA1_SRC_DSCPTR_PRV (REG_DMA23_DSCPTR_PRV)
|
|
#define MDMA1_SRC_ADDR_CUR (REG_DMA23_ADDR_CUR)
|
|
#define MDMA1_SRC_STAT (REG_DMA23_STAT)
|
|
#define MDMA1_SRC_XCNT_CUR (REG_DMA23_XCNT_CUR)
|
|
#define MDMA1_SRC_YCNT_CUR (REG_DMA23_YCNT_CUR)
|
|
#define MDMA1_SRC_BWLCNT (REG_DMA23_BWLCNT)
|
|
#define MDMA1_SRC_BWLCNT_CUR (REG_DMA23_BWLCNT_CUR)
|
|
#define MDMA1_SRC_BWMCNT (REG_DMA23_BWMCNT)
|
|
#define MDMA1_SRC_BWMCNT_CUR (REG_DMA23_BWMCNT_CUR)
|
|
#define MDMA1_DST_DSCPTR_NXT (REG_DMA24_DSCPTR_NXT)
|
|
#define MDMA1_DST_ADDRSTART (REG_DMA24_ADDRSTART)
|
|
#define MDMA1_DST_CFG (REG_DMA24_CFG)
|
|
#define MDMA1_DST_XCNT (REG_DMA24_XCNT)
|
|
#define MDMA1_DST_XMOD (REG_DMA24_XMOD)
|
|
#define MDMA1_DST_YCNT (REG_DMA24_YCNT)
|
|
#define MDMA1_DST_YMOD (REG_DMA24_YMOD)
|
|
#define MDMA1_DST_DSCPTR_CUR (REG_DMA24_DSCPTR_CUR)
|
|
#define MDMA1_DST_DSCPTR_PRV (REG_DMA24_DSCPTR_PRV)
|
|
#define MDMA1_DST_ADDR_CUR (REG_DMA24_ADDR_CUR)
|
|
#define MDMA1_DST_STAT (REG_DMA24_STAT)
|
|
#define MDMA1_DST_XCNT_CUR (REG_DMA24_XCNT_CUR)
|
|
#define MDMA1_DST_YCNT_CUR (REG_DMA24_YCNT_CUR)
|
|
#define MDMA1_DST_BWLCNT (REG_DMA24_BWLCNT)
|
|
#define MDMA1_DST_BWLCNT_CUR (REG_DMA24_BWLCNT_CUR)
|
|
#define MDMA1_DST_BWMCNT (REG_DMA24_BWMCNT)
|
|
#define MDMA1_DST_BWMCNT_CUR (REG_DMA24_BWMCNT_CUR)
|
|
#define MDMA2_SRC_DSCPTR_NXT (REG_DMA25_DSCPTR_NXT)
|
|
#define MDMA2_SRC_ADDRSTART (REG_DMA25_ADDRSTART)
|
|
#define MDMA2_SRC_CFG (REG_DMA25_CFG)
|
|
#define MDMA2_SRC_XCNT (REG_DMA25_XCNT)
|
|
#define MDMA2_SRC_XMOD (REG_DMA25_XMOD)
|
|
#define MDMA2_SRC_YCNT (REG_DMA25_YCNT)
|
|
#define MDMA2_SRC_YMOD (REG_DMA25_YMOD)
|
|
#define MDMA2_SRC_DSCPTR_CUR (REG_DMA25_DSCPTR_CUR)
|
|
#define MDMA2_SRC_DSCPTR_PRV (REG_DMA25_DSCPTR_PRV)
|
|
#define MDMA2_SRC_ADDR_CUR (REG_DMA25_ADDR_CUR)
|
|
#define MDMA2_SRC_STAT (REG_DMA25_STAT)
|
|
#define MDMA2_SRC_XCNT_CUR (REG_DMA25_XCNT_CUR)
|
|
#define MDMA2_SRC_YCNT_CUR (REG_DMA25_YCNT_CUR)
|
|
#define MDMA2_SRC_BWLCNT (REG_DMA25_BWLCNT)
|
|
#define MDMA2_SRC_BWLCNT_CUR (REG_DMA25_BWLCNT_CUR)
|
|
#define MDMA2_SRC_BWMCNT (REG_DMA25_BWMCNT)
|
|
#define MDMA2_SRC_BWMCNT_CUR (REG_DMA25_BWMCNT_CUR)
|
|
#define MDMA2_DST_DSCPTR_NXT (REG_DMA26_DSCPTR_NXT)
|
|
#define MDMA2_DST_ADDRSTART (REG_DMA26_ADDRSTART)
|
|
#define MDMA2_DST_CFG (REG_DMA26_CFG)
|
|
#define MDMA2_DST_XCNT (REG_DMA26_XCNT)
|
|
#define MDMA2_DST_XMOD (REG_DMA26_XMOD)
|
|
#define MDMA2_DST_YCNT (REG_DMA26_YCNT)
|
|
#define MDMA2_DST_YMOD (REG_DMA26_YMOD)
|
|
#define MDMA2_DST_DSCPTR_CUR (REG_DMA26_DSCPTR_CUR)
|
|
#define MDMA2_DST_DSCPTR_PRV (REG_DMA26_DSCPTR_PRV)
|
|
#define MDMA2_DST_ADDR_CUR (REG_DMA26_ADDR_CUR)
|
|
#define MDMA2_DST_STAT (REG_DMA26_STAT)
|
|
#define MDMA2_DST_XCNT_CUR (REG_DMA26_XCNT_CUR)
|
|
#define MDMA2_DST_YCNT_CUR (REG_DMA26_YCNT_CUR)
|
|
#define MDMA2_DST_BWLCNT (REG_DMA26_BWLCNT)
|
|
#define MDMA2_DST_BWLCNT_CUR (REG_DMA26_BWLCNT_CUR)
|
|
#define MDMA2_DST_BWMCNT (REG_DMA26_BWMCNT)
|
|
#define MDMA2_DST_BWMCNT_CUR (REG_DMA26_BWMCNT_CUR)
|
|
#define MDMA3_SRC_DSCPTR_NXT (REG_DMA27_DSCPTR_NXT)
|
|
#define MDMA3_SRC_ADDRSTART (REG_DMA27_ADDRSTART)
|
|
#define MDMA3_SRC_CFG (REG_DMA27_CFG)
|
|
#define MDMA3_SRC_XCNT (REG_DMA27_XCNT)
|
|
#define MDMA3_SRC_XMOD (REG_DMA27_XMOD)
|
|
#define MDMA3_SRC_YCNT (REG_DMA27_YCNT)
|
|
#define MDMA3_SRC_YMOD (REG_DMA27_YMOD)
|
|
#define MDMA3_SRC_DSCPTR_CUR (REG_DMA27_DSCPTR_CUR)
|
|
#define MDMA3_SRC_DSCPTR_PRV (REG_DMA27_DSCPTR_PRV)
|
|
#define MDMA3_SRC_ADDR_CUR (REG_DMA27_ADDR_CUR)
|
|
#define MDMA3_SRC_STAT (REG_DMA27_STAT)
|
|
#define MDMA3_SRC_XCNT_CUR (REG_DMA27_XCNT_CUR)
|
|
#define MDMA3_SRC_YCNT_CUR (REG_DMA27_YCNT_CUR)
|
|
#define MDMA3_SRC_BWLCNT (REG_DMA27_BWLCNT)
|
|
#define MDMA3_SRC_BWLCNT_CUR (REG_DMA27_BWLCNT_CUR)
|
|
#define MDMA3_SRC_BWMCNT (REG_DMA27_BWMCNT)
|
|
#define MDMA3_SRC_BWMCNT_CUR (REG_DMA27_BWMCNT_CUR)
|
|
#define MDMA3_DST_DSCPTR_NXT (REG_DMA28_DSCPTR_NXT)
|
|
#define MDMA3_DST_ADDRSTART (REG_DMA28_ADDRSTART)
|
|
#define MDMA3_DST_CFG (REG_DMA28_CFG)
|
|
#define MDMA3_DST_XCNT (REG_DMA28_XCNT)
|
|
#define MDMA3_DST_XMOD (REG_DMA28_XMOD)
|
|
#define MDMA3_DST_YCNT (REG_DMA28_YCNT)
|
|
#define MDMA3_DST_YMOD (REG_DMA28_YMOD)
|
|
#define MDMA3_DST_DSCPTR_CUR (REG_DMA28_DSCPTR_CUR)
|
|
#define MDMA3_DST_DSCPTR_PRV (REG_DMA28_DSCPTR_PRV)
|
|
#define MDMA3_DST_ADDR_CUR (REG_DMA28_ADDR_CUR)
|
|
#define MDMA3_DST_STAT (REG_DMA28_STAT)
|
|
#define MDMA3_DST_XCNT_CUR (REG_DMA28_XCNT_CUR)
|
|
#define MDMA3_DST_YCNT_CUR (REG_DMA28_YCNT_CUR)
|
|
#define MDMA3_DST_BWLCNT (REG_DMA28_BWLCNT)
|
|
#define MDMA3_DST_BWLCNT_CUR (REG_DMA28_BWLCNT_CUR)
|
|
#define MDMA3_DST_BWMCNT (REG_DMA28_BWMCNT)
|
|
#define MDMA3_DST_BWMCNT_CUR (REG_DMA28_BWMCNT_CUR)
|
|
#define EPPI0_CH0_DMA_DSCPTR_NXT (REG_DMA29_DSCPTR_NXT)
|
|
#define EPPI0_CH0_DMA_ADDRSTART (REG_DMA29_ADDRSTART)
|
|
#define EPPI0_CH0_DMA_CFG (REG_DMA29_CFG)
|
|
#define EPPI0_CH0_DMA_XCNT (REG_DMA29_XCNT)
|
|
#define EPPI0_CH0_DMA_XMOD (REG_DMA29_XMOD)
|
|
#define EPPI0_CH0_DMA_YCNT (REG_DMA29_YCNT)
|
|
#define EPPI0_CH0_DMA_YMOD (REG_DMA29_YMOD)
|
|
#define EPPI0_CH0_DMA_DSCPTR_CUR (REG_DMA29_DSCPTR_CUR)
|
|
#define EPPI0_CH0_DMA_DSCPTR_PRV (REG_DMA29_DSCPTR_PRV)
|
|
#define EPPI0_CH0_DMA_ADDR_CUR (REG_DMA29_ADDR_CUR)
|
|
#define EPPI0_CH0_DMA_STAT (REG_DMA29_STAT)
|
|
#define EPPI0_CH0_DMA_XCNT_CUR (REG_DMA29_XCNT_CUR)
|
|
#define EPPI0_CH0_DMA_YCNT_CUR (REG_DMA29_YCNT_CUR)
|
|
#define EPPI0_CH0_DMA_BWLCNT (REG_DMA29_BWLCNT)
|
|
#define EPPI0_CH0_DMA_BWLCNT_CUR (REG_DMA29_BWLCNT_CUR)
|
|
#define EPPI0_CH0_DMA_BWMCNT (REG_DMA29_BWMCNT)
|
|
#define EPPI0_CH0_DMA_BWMCNT_CUR (REG_DMA29_BWMCNT_CUR)
|
|
#define EPPI0_CH1_DMA_DSCPTR_NXT (REG_DMA30_DSCPTR_NXT)
|
|
#define EPPI0_CH1_DMA_ADDRSTART (REG_DMA30_ADDRSTART)
|
|
#define EPPI0_CH1_DMA_CFG (REG_DMA30_CFG)
|
|
#define EPPI0_CH1_DMA_XCNT (REG_DMA30_XCNT)
|
|
#define EPPI0_CH1_DMA_XMOD (REG_DMA30_XMOD)
|
|
#define EPPI0_CH1_DMA_YCNT (REG_DMA30_YCNT)
|
|
#define EPPI0_CH1_DMA_YMOD (REG_DMA30_YMOD)
|
|
#define EPPI0_CH1_DMA_DSCPTR_CUR (REG_DMA30_DSCPTR_CUR)
|
|
#define EPPI0_CH1_DMA_DSCPTR_PRV (REG_DMA30_DSCPTR_PRV)
|
|
#define EPPI0_CH1_DMA_ADDR_CUR (REG_DMA30_ADDR_CUR)
|
|
#define EPPI0_CH1_DMA_STAT (REG_DMA30_STAT)
|
|
#define EPPI0_CH1_DMA_XCNT_CUR (REG_DMA30_XCNT_CUR)
|
|
#define EPPI0_CH1_DMA_YCNT_CUR (REG_DMA30_YCNT_CUR)
|
|
#define EPPI0_CH1_DMA_BWLCNT (REG_DMA30_BWLCNT)
|
|
#define EPPI0_CH1_DMA_BWLCNT_CUR (REG_DMA30_BWLCNT_CUR)
|
|
#define EPPI0_CH1_DMA_BWMCNT (REG_DMA30_BWMCNT)
|
|
#define EPPI0_CH1_DMA_BWMCNT_CUR (REG_DMA30_BWMCNT_CUR)
|
|
#define EPPI2_CH0_DMA_DSCPTR_NXT (REG_DMA31_DSCPTR_NXT)
|
|
#define EPPI2_CH0_DMA_ADDRSTART (REG_DMA31_ADDRSTART)
|
|
#define EPPI2_CH0_DMA_CFG (REG_DMA31_CFG)
|
|
#define EPPI2_CH0_DMA_XCNT (REG_DMA31_XCNT)
|
|
#define EPPI2_CH0_DMA_XMOD (REG_DMA31_XMOD)
|
|
#define EPPI2_CH0_DMA_YCNT (REG_DMA31_YCNT)
|
|
#define EPPI2_CH0_DMA_YMOD (REG_DMA31_YMOD)
|
|
#define EPPI2_CH0_DMA_DSCPTR_CUR (REG_DMA31_DSCPTR_CUR)
|
|
#define EPPI2_CH0_DMA_DSCPTR_PRV (REG_DMA31_DSCPTR_PRV)
|
|
#define EPPI2_CH0_DMA_ADDR_CUR (REG_DMA31_ADDR_CUR)
|
|
#define EPPI2_CH0_DMA_STAT (REG_DMA31_STAT)
|
|
#define EPPI2_CH0_DMA_XCNT_CUR (REG_DMA31_XCNT_CUR)
|
|
#define EPPI2_CH0_DMA_YCNT_CUR (REG_DMA31_YCNT_CUR)
|
|
#define EPPI2_CH0_DMA_BWLCNT (REG_DMA31_BWLCNT)
|
|
#define EPPI2_CH0_DMA_BWLCNT_CUR (REG_DMA31_BWLCNT_CUR)
|
|
#define EPPI2_CH0_DMA_BWMCNT (REG_DMA31_BWMCNT)
|
|
#define EPPI2_CH0_DMA_BWMCNT_CUR (REG_DMA31_BWMCNT_CUR)
|
|
#define EPPI2_CH1_DMA_DSCPTR_NXT (REG_DMA32_DSCPTR_NXT)
|
|
#define EPPI2_CH1_DMA_ADDRSTART (REG_DMA32_ADDRSTART)
|
|
#define EPPI2_CH1_DMA_CFG (REG_DMA32_CFG)
|
|
#define EPPI2_CH1_DMA_XCNT (REG_DMA32_XCNT)
|
|
#define EPPI2_CH1_DMA_XMOD (REG_DMA32_XMOD)
|
|
#define EPPI2_CH1_DMA_YCNT (REG_DMA32_YCNT)
|
|
#define EPPI2_CH1_DMA_YMOD (REG_DMA32_YMOD)
|
|
#define EPPI2_CH1_DMA_DSCPTR_CUR (REG_DMA32_DSCPTR_CUR)
|
|
#define EPPI2_CH1_DMA_DSCPTR_PRV (REG_DMA32_DSCPTR_PRV)
|
|
#define EPPI2_CH1_DMA_ADDR_CUR (REG_DMA32_ADDR_CUR)
|
|
#define EPPI2_CH1_DMA_STAT (REG_DMA32_STAT)
|
|
#define EPPI2_CH1_DMA_XCNT_CUR (REG_DMA32_XCNT_CUR)
|
|
#define EPPI2_CH1_DMA_YCNT_CUR (REG_DMA32_YCNT_CUR)
|
|
#define EPPI2_CH1_DMA_BWLCNT (REG_DMA32_BWLCNT)
|
|
#define EPPI2_CH1_DMA_BWLCNT_CUR (REG_DMA32_BWLCNT_CUR)
|
|
#define EPPI2_CH1_DMA_BWMCNT (REG_DMA32_BWMCNT)
|
|
#define EPPI2_CH1_DMA_BWMCNT_CUR (REG_DMA32_BWMCNT_CUR)
|
|
#define EPPI1_CH0_DMA_DSCPTR_NXT (REG_DMA33_DSCPTR_NXT)
|
|
#define EPPI1_CH0_DMA_ADDRSTART (REG_DMA33_ADDRSTART)
|
|
#define EPPI1_CH0_DMA_CFG (REG_DMA33_CFG)
|
|
#define EPPI1_CH0_DMA_XCNT (REG_DMA33_XCNT)
|
|
#define EPPI1_CH0_DMA_XMOD (REG_DMA33_XMOD)
|
|
#define EPPI1_CH0_DMA_YCNT (REG_DMA33_YCNT)
|
|
#define EPPI1_CH0_DMA_YMOD (REG_DMA33_YMOD)
|
|
#define EPPI1_CH0_DMA_DSCPTR_CUR (REG_DMA33_DSCPTR_CUR)
|
|
#define EPPI1_CH0_DMA_DSCPTR_PRV (REG_DMA33_DSCPTR_PRV)
|
|
#define EPPI1_CH0_DMA_ADDR_CUR (REG_DMA33_ADDR_CUR)
|
|
#define EPPI1_CH0_DMA_STAT (REG_DMA33_STAT)
|
|
#define EPPI1_CH0_DMA_XCNT_CUR (REG_DMA33_XCNT_CUR)
|
|
#define EPPI1_CH0_DMA_YCNT_CUR (REG_DMA33_YCNT_CUR)
|
|
#define EPPI1_CH0_DMA_BWLCNT (REG_DMA33_BWLCNT)
|
|
#define EPPI1_CH0_DMA_BWLCNT_CUR (REG_DMA33_BWLCNT_CUR)
|
|
#define EPPI1_CH0_DMA_BWMCNT (REG_DMA33_BWMCNT)
|
|
#define EPPI1_CH0_DMA_BWMCNT_CUR (REG_DMA33_BWMCNT_CUR)
|
|
#define EPPI1_CH1_DMA_DSCPTR_NXT (REG_DMA34_DSCPTR_NXT)
|
|
#define EPPI1_CH1_DMA_ADDRSTART (REG_DMA34_ADDRSTART)
|
|
#define EPPI1_CH1_DMA_CFG (REG_DMA34_CFG)
|
|
#define EPPI1_CH1_DMA_XCNT (REG_DMA34_XCNT)
|
|
#define EPPI1_CH1_DMA_XMOD (REG_DMA34_XMOD)
|
|
#define EPPI1_CH1_DMA_YCNT (REG_DMA34_YCNT)
|
|
#define EPPI1_CH1_DMA_YMOD (REG_DMA34_YMOD)
|
|
#define EPPI1_CH1_DMA_DSCPTR_CUR (REG_DMA34_DSCPTR_CUR)
|
|
#define EPPI1_CH1_DMA_DSCPTR_PRV (REG_DMA34_DSCPTR_PRV)
|
|
#define EPPI1_CH1_DMA_ADDR_CUR (REG_DMA34_ADDR_CUR)
|
|
#define EPPI1_CH1_DMA_STAT (REG_DMA34_STAT)
|
|
#define EPPI1_CH1_DMA_XCNT_CUR (REG_DMA34_XCNT_CUR)
|
|
#define EPPI1_CH1_DMA_YCNT_CUR (REG_DMA34_YCNT_CUR)
|
|
#define EPPI1_CH1_DMA_BWLCNT (REG_DMA34_BWLCNT)
|
|
#define EPPI1_CH1_DMA_BWLCNT_CUR (REG_DMA34_BWLCNT_CUR)
|
|
#define EPPI1_CH1_DMA_BWMCNT (REG_DMA34_BWMCNT)
|
|
#define EPPI1_CH1_DMA_BWMCNT_CUR (REG_DMA34_BWMCNT_CUR)
|
|
|
|
/* ==================================
|
|
DMA Error CHID Definitions
|
|
================================== */
|
|
#define CHID_SPORT0_A_DMA 0 /* Channel A DMA */
|
|
#define CHID_SPORT0_B_DMA 1 /* Channel B DMA */
|
|
#define CHID_SPORT1_A_DMA 2 /* Channel A DMA */
|
|
#define CHID_SPORT1_B_DMA 3 /* Channel B DMA */
|
|
#define CHID_SPORT2_A_DMA 4 /* Channel A DMA */
|
|
#define CHID_SPORT2_B_DMA 5 /* Channel B DMA */
|
|
#define CHID_SPI0_TXDMA 6 /* TX DMA Channel */
|
|
#define CHID_SPI0_RXDMA 7 /* RX DMA Channel */
|
|
#define CHID_SPI1_TXDMA 8 /* TX DMA Channel */
|
|
#define CHID_SPI1_RXDMA 9 /* RX DMA Channel */
|
|
#define CHID_RSI0_DMA 10 /* DMA Channel */
|
|
#define CHID_SDU0_DMA 11 /* DMA */
|
|
/* -- RESERVED -- 12 */
|
|
#define CHID_LP0_DMA 13 /* DMA Channel */
|
|
#define CHID_LP1_DMA 14 /* DMA Channel */
|
|
#define CHID_LP2_DMA 15 /* DMA Channel */
|
|
#define CHID_LP3_DMA 16 /* DMA Channel */
|
|
#define CHID_UART0_TXDMA 17 /* Transmit DMA */
|
|
#define CHID_UART0_RXDMA 18 /* Receive DMA */
|
|
#define CHID_UART1_TXDMA 19 /* Transmit DMA */
|
|
#define CHID_UART1_RXDMA 20 /* Receive DMA */
|
|
#define CHID_MDMA0_SRC 21 /* Memory DMA Stream 0 Source / CRC0 Input Channel */
|
|
#define CHID_MDMA0_DST 22 /* Memory DMA Stream 0 Destination / CRC0 Output Channel */
|
|
#define CHID_MDMA1_SRC 23 /* Memory DMA Stream 1 Source / CRC1 Input Channel */
|
|
#define CHID_MDMA1_DST 24 /* Memory DMA Stream 1 Destination / CRC1 Output Channel */
|
|
#define CHID_MDMA2_SRC 25 /* Memory DMA Stream 2 Source Channel */
|
|
#define CHID_MDMA2_DST 26 /* Memory DMA Stream 2 Destination Channel */
|
|
#define CHID_MDMA3_SRC 27 /* Memory DMA Stream 3 Source Channel */
|
|
#define CHID_MDMA3_DST 28 /* Memory DMA Stream 3 Destination Channel */
|
|
#define CHID_EPPI0_CH0_DMA 29 /* Channel 0 DMA */
|
|
#define CHID_EPPI0_CH1_DMA 30 /* Channel 1 DMA */
|
|
#define CHID_EPPI2_CH0_DMA 31 /* Channel 0 DMA */
|
|
#define CHID_EPPI2_CH1_DMA 32 /* Channel 1 DMA */
|
|
#define CHID_EPPI1_CH0_DMA 33 /* Channel 0 DMA */
|
|
#define CHID_EPPI1_CH1_DMA 34 /* Channel 1 DMA */
|
|
|
|
/* ==============================
|
|
Interrupt Definitions
|
|
============================== */
|
|
#define INTR_SEC0_ERR 0 /* Error */
|
|
#define INTR_CGU0_EVT 1 /* Event */
|
|
#define INTR_WDOG0_EXP 2 /* Expiration */
|
|
#define INTR_WDOG1_EXP 3 /* Expiration */
|
|
#define INTR_L2CTL0_ECC_ERR 4 /* ECC Error */
|
|
#define INTR_L2CTL0_ECC_WARNING 5 /* ECC Warning */
|
|
#define INTR_C0_DBL_FAULT 6 /* Core 0 Double Fault */
|
|
#define INTR_C1_DBL_FAULT 7 /* Core 1 Double Fault */
|
|
#define INTR_C0_HW_ERR 8 /* Core 0 Hardware Error */
|
|
#define INTR_C1_HW_ERR 9 /* Core 1 Hardware Error */
|
|
#define INTR_C0_NMI_L1_PARITY_ERR 10 /* Core 0 Unhandled NMI or L1 Memory Parity Error */
|
|
#define INTR_C1_NMI_L1_PARITY_ERR 11 /* Core 1 Unhandled NMI or L1 Memory Parity Error */
|
|
#define INTR_TIMER0_TMR0 12 /* Timer 0 */
|
|
#define INTR_TIMER0_TMR1 13 /* Timer 1 */
|
|
#define INTR_TIMER0_TMR2 14 /* Timer 2 */
|
|
#define INTR_TIMER0_TMR3 15 /* Timer 3 */
|
|
#define INTR_TIMER0_TMR4 16 /* Timer 4 */
|
|
#define INTR_TIMER0_TMR5 17 /* Timer 5 */
|
|
#define INTR_TIMER0_TMR6 18 /* Timer 6 */
|
|
#define INTR_TIMER0_TMR7 19 /* Timer 7 */
|
|
#define INTR_TIMER0_STAT 20 /* Status */
|
|
#define INTR_PINT0_BLOCK 21 /* Pin Interrupt Block */
|
|
#define INTR_PINT1_BLOCK 22 /* Pin Interrupt Block */
|
|
#define INTR_PINT2_BLOCK 23 /* Pin Interrupt Block */
|
|
#define INTR_PINT3_BLOCK 24 /* Pin Interrupt Block */
|
|
#define INTR_PINT4_BLOCK 25 /* Pin Interrupt Block */
|
|
#define INTR_PINT5_BLOCK 26 /* Pin Interrupt Block */
|
|
#define INTR_CNT0_STAT 27 /* Status */
|
|
#define INTR_PWM0_SYNC 28 /* Sync */
|
|
#define INTR_PWM0_TRIP 29 /* Trip */
|
|
#define INTR_PWM1_SYNC 30 /* Sync */
|
|
#define INTR_PWM1_TRIP 31 /* Trip */
|
|
#define INTR_TWI0_DATA 32 /* Data Interrupt */
|
|
#define INTR_TWI1_DATA 33 /* Data Interrupt */
|
|
#define INTR_SOFT0 34 /* Software-driven Interrupt 0 */
|
|
#define INTR_SOFT1 35 /* Software-driven Interrupt 1 */
|
|
#define INTR_SOFT2 36 /* Software-driven Interrupt 2 */
|
|
#define INTR_SOFT3 37 /* Software-driven Interrupt 3 */
|
|
#define INTR_ACM0_EVT_MISS 38 /* Event Miss */
|
|
#define INTR_ACM0_EVT_COMPLETE 39 /* Event Complete */
|
|
#define INTR_CAN0_RX 40 /* Receive */
|
|
#define INTR_CAN0_TX 41 /* Transmit */
|
|
#define INTR_CAN0_STAT 42 /* Status */
|
|
#define INTR_SPORT0_A_DMA 43 /* Channel A DMA */
|
|
#define INTR_SPORT0_A_STAT 44 /* Channel A Status */
|
|
#define INTR_SPORT0_B_DMA 45 /* Channel B DMA */
|
|
#define INTR_SPORT0_B_STAT 46 /* Channel B Status */
|
|
#define INTR_SPORT1_A_DMA 47 /* Channel A DMA */
|
|
#define INTR_SPORT1_A_STAT 48 /* Channel A Status */
|
|
#define INTR_SPORT1_B_DMA 49 /* Channel B DMA */
|
|
#define INTR_SPORT1_B_STAT 50 /* Channel B Status */
|
|
#define INTR_SPORT2_A_DMA 51 /* Channel A DMA */
|
|
#define INTR_SPORT2_A_STAT 52 /* Channel A Status */
|
|
#define INTR_SPORT2_B_DMA 53 /* Channel B DMA */
|
|
#define INTR_SPORT2_B_STAT 54 /* Channel B Status */
|
|
#define INTR_SPI0_TXDMA 55 /* TX DMA Channel */
|
|
#define INTR_SPI0_RXDMA 56 /* RX DMA Channel */
|
|
#define INTR_SPI0_STAT 57 /* Status */
|
|
#define INTR_SPI1_TXDMA 58 /* TX DMA Channel */
|
|
#define INTR_SPI1_RXDMA 59 /* RX DMA Channel */
|
|
#define INTR_SPI1_STAT 60 /* Status */
|
|
#define INTR_RSI0_DMA 61 /* DMA Channel */
|
|
#define INTR_RSI0_INT0 62 /* Interrupt 0 */
|
|
#define INTR_RSI0_INT1 63 /* Interrupt 1 */
|
|
#define INTR_SDU0_DMA 64 /* DMA */
|
|
/* -- RESERVED -- 65 */
|
|
/* -- RESERVED -- 66 */
|
|
/* -- RESERVED -- 67 */
|
|
#define INTR_EMAC0_STAT 68 /* Status */
|
|
/* -- RESERVED -- 69 */
|
|
#define INTR_EMAC1_STAT 70 /* Status */
|
|
/* -- RESERVED -- 71 */
|
|
#define INTR_LP0_DMA 72 /* DMA Channel */
|
|
#define INTR_LP0_STAT 73 /* Status */
|
|
#define INTR_LP1_DMA 74 /* DMA Channel */
|
|
#define INTR_LP1_STAT 75 /* Status */
|
|
#define INTR_LP2_DMA 76 /* DMA Channel */
|
|
#define INTR_LP2_STAT 77 /* Status */
|
|
#define INTR_LP3_DMA 78 /* DMA Channel */
|
|
#define INTR_LP3_STAT 79 /* Status */
|
|
#define INTR_UART0_TXDMA 80 /* Transmit DMA */
|
|
#define INTR_UART0_RXDMA 81 /* Receive DMA */
|
|
#define INTR_UART0_STAT 82 /* Status */
|
|
#define INTR_UART1_TXDMA 83 /* Transmit DMA */
|
|
#define INTR_UART1_RXDMA 84 /* Receive DMA */
|
|
#define INTR_UART1_STAT 85 /* Status */
|
|
#define INTR_MDMA0_SRC 86 /* Memory DMA Stream 0 Source / CRC0 Input Channel */
|
|
#define INTR_MDMA0_DST 87 /* Memory DMA Stream 0 Destination / CRC0 Output Channel */
|
|
#define INTR_CRC0_DCNTEXP 88 /* Datacount expiration */
|
|
#define INTR_CRC0_ERR 89 /* Error */
|
|
#define INTR_MDMA1_SRC 90 /* Memory DMA Stream 1 Source / CRC1 Input Channel */
|
|
#define INTR_MDMA1_DST 91 /* Memory DMA Stream 1 Destination / CRC1 Output Channel */
|
|
#define INTR_CRC1_DCNTEXP 92 /* Datacount expiration */
|
|
#define INTR_CRC1_ERR 93 /* Error */
|
|
#define INTR_MDMA2_SRC 94 /* Memory DMA Stream 2 Source Channel */
|
|
#define INTR_MDMA2_DST 95 /* Memory DMA Stream 2 Destination Channel */
|
|
#define INTR_MDMA3_SRC 96 /* Memory DMA Stream 3 Source Channel */
|
|
#define INTR_MDMA3_DST 97 /* Memory DMA Stream 3 Destination Channel */
|
|
#define INTR_EPPI0_CH0_DMA 98 /* Channel 0 DMA */
|
|
#define INTR_EPPI0_CH1_DMA 99 /* Channel 1 DMA */
|
|
#define INTR_EPPI0_STAT 100 /* Status */
|
|
#define INTR_EPPI2_CH0_DMA 101 /* Channel 0 DMA */
|
|
#define INTR_EPPI2_CH1_DMA 102 /* Channel 1 DMA */
|
|
#define INTR_EPPI2_STAT 103 /* Status */
|
|
#define INTR_EPPI1_CH0_DMA 104 /* Channel 0 DMA */
|
|
#define INTR_EPPI1_CH1_DMA 105 /* Channel 1 DMA */
|
|
#define INTR_EPPI1_STAT 106 /* Status */
|
|
#define INTR_USB0_STAT 122 /* Status/FIFO Data Ready */
|
|
#define INTR_USB0_DATA 123 /* DMA Status/Transfer Complete */
|
|
#define INTR_TRU0_INT0 124 /* Interrupt 0 */
|
|
#define INTR_TRU0_INT1 125 /* Interrupt 1 */
|
|
#define INTR_TRU0_INT2 126 /* Interrupt 2 */
|
|
#define INTR_TRU0_INT3 127 /* Interrupt 3 */
|
|
#define INTR_DMAC_ERR 128 /* DMA Controller Error */
|
|
#define INTR_CGU0_ERR 129 /* Error */
|
|
/* -- RESERVED -- 130 */
|
|
#define INTR_DPM0_EVT 131 /* Event */
|
|
/* -- RESERVED -- 132 */
|
|
#define INTR_SWU0_EVT 133 /* Event */
|
|
#define INTR_SWU1_EVT 134 /* Event */
|
|
#define INTR_SWU2_EVT 135 /* Event */
|
|
#define INTR_SWU3_EVT 136 /* Event */
|
|
#define INTR_SWU4_EVT 137 /* Event */
|
|
#define INTR_SWU5_EVT 138 /* Event */
|
|
#define INTR_SWU6_EVT 139 /* Event */
|
|
|
|
/* ==============================
|
|
Parameters
|
|
============================== */
|
|
|
|
|
|
/* Generic System Module Parameters */
|
|
|
|
#define PARAM_SYS0_NUM_BMODE 3
|
|
#define PARAM_SYS0_NUM_CORES 2
|
|
#define PARAM_SYS0_NUM_MDMA_STREAMS 4
|
|
#define PARAM_SYS0_NUM_RSVD_INT 7
|
|
#define PARAM_SYS0_NUM_RSVD_TRIG 6
|
|
#define PARAM_SYS0_NUM_SW_INT 4
|
|
#define PARAM_SYS0_NUM_SW_TRIG 6
|
|
|
|
|
|
|
|
|
|
/* RSI Parameters */
|
|
|
|
#define PARAM_RSI0_NUM_DATA 8
|
|
#define PARAM_RSI0_NUM_INT 2
|
|
|
|
|
|
|
|
/* Link Port Parameters */
|
|
|
|
#define PARAM_LP0_NUM_DATA 8
|
|
#define PARAM_LP1_NUM_DATA 8
|
|
#define PARAM_LP2_NUM_DATA 8
|
|
#define PARAM_LP3_NUM_DATA 8
|
|
|
|
|
|
/* General Purpose Timer Block Parameters */
|
|
|
|
#define PARAM_TIMER0_NUMTIMERS 8
|
|
|
|
|
|
|
|
|
|
|
|
/* General Purpose Input/Output Parameters */
|
|
|
|
#define PARAM_PORTA_PORT_WIDTH 16
|
|
#define PARAM_PORTB_PORT_WIDTH 16
|
|
#define PARAM_PORTC_PORT_WIDTH 16
|
|
#define PARAM_PORTD_PORT_WIDTH 16
|
|
#define PARAM_PORTE_PORT_WIDTH 16
|
|
#define PARAM_PORTF_PORT_WIDTH 16
|
|
#define PARAM_PORTG_PORT_WIDTH 16
|
|
|
|
|
|
|
|
|
|
/* Static Memory Controller Parameters */
|
|
|
|
#define PARAM_SMC0_NUM_ABE 2
|
|
#define PARAM_SMC0_NUM_ADDR 26
|
|
#define PARAM_SMC0_NUM_AMS 4
|
|
#define PARAM_SMC0_NUM_DATA 16
|
|
|
|
|
|
|
|
/* EPPI Parameters */
|
|
|
|
#define PARAM_EPPI0_MAXWIDTH 24
|
|
#define PARAM_EPPI0_NUM_DATA 24
|
|
#define PARAM_EPPI1_MAXWIDTH 24
|
|
#define PARAM_EPPI1_NUM_DATA 18
|
|
#define PARAM_EPPI2_MAXWIDTH 24
|
|
#define PARAM_EPPI2_NUM_DATA 18
|
|
|
|
|
|
/* Pulse-Width Modulator Parameters */
|
|
|
|
#define PARAM_PWM0_ASYM_DEADTIME 0
|
|
#define PARAM_PWM0_COMPRESS 1
|
|
#define PARAM_PWM0_DOUBLE_UPDATE 0
|
|
#define PARAM_PWM0_FULL_DUTY_REGS 0
|
|
#define PARAM_PWM0_HI_HP_REGS_PRIVATE 1
|
|
#define PARAM_PWM0_LO_HP_REGS 0
|
|
#define PARAM_PWM0_NUM_TRIP 2
|
|
#define PARAM_PWM0_NUM_TRIP_PINS 2
|
|
#define PARAM_PWM0_NUM_TRIP_TRIG 0
|
|
#define PARAM_PWM0_REVID_MAJOR 0
|
|
#define PARAM_PWM0_REVID_REV 0
|
|
#define PARAM_PWM1_ASYM_DEADTIME 0
|
|
#define PARAM_PWM1_COMPRESS 1
|
|
#define PARAM_PWM1_DOUBLE_UPDATE 0
|
|
#define PARAM_PWM1_FULL_DUTY_REGS 0
|
|
#define PARAM_PWM1_HI_HP_REGS_PRIVATE 1
|
|
#define PARAM_PWM1_LO_HP_REGS 0
|
|
#define PARAM_PWM1_NUM_TRIP 2
|
|
#define PARAM_PWM1_NUM_TRIP_PINS 2
|
|
#define PARAM_PWM1_NUM_TRIP_TRIG 0
|
|
#define PARAM_PWM1_REVID_MAJOR 0
|
|
#define PARAM_PWM1_REVID_REV 0
|
|
|
|
|
|
/* Video Subsystem Registers Parameters */
|
|
|
|
#define PARAM_VID0_PIXC_ABSENT 1
|
|
#define PARAM_VID0_PVP_ABSENT 1
|
|
|
|
|
|
|
|
/* System Debug Unit Parameters */
|
|
|
|
#define PARAM_SDU0_IDCODE_PRID 0
|
|
#define PARAM_SDU0_IDCODE_REVID 0
|
|
|
|
|
|
/* Ethernet MAC Parameters */
|
|
|
|
#define PARAM_EMAC0_NUM_RX 2
|
|
#define PARAM_EMAC0_NUM_TX 2
|
|
#define PARAM_EMAC1_NUM_RX 2
|
|
#define PARAM_EMAC1_NUM_TX 2
|
|
|
|
|
|
|
|
/* Serial Peripheral Interface Parameters */
|
|
|
|
#define PARAM_SPI0_MEM_MAPPED 0
|
|
#define PARAM_SPI0_NUM_SEL 7
|
|
#define PARAM_SPI0_PTM_EXISTS 1
|
|
#define PARAM_SPI0_REVID_MAJOR 3
|
|
#define PARAM_SPI0_REVID_REV 0
|
|
#define PARAM_SPI1_MEM_MAPPED 0
|
|
#define PARAM_SPI1_NUM_SEL 7
|
|
#define PARAM_SPI1_PTM_EXISTS 1
|
|
#define PARAM_SPI1_REVID_MAJOR 3
|
|
#define PARAM_SPI1_REVID_REV 0
|
|
|
|
|
|
|
|
/* ACM Parameters */
|
|
|
|
#define PARAM_ACM0_NUM_ADDR 5
|
|
#define PARAM_ACM0_NUM_TRIG 2
|
|
|
|
|
|
/* DDR Parameters */
|
|
|
|
#define PARAM_DMC0_NUM_ADDR 14
|
|
#define PARAM_DMC0_NUM_BA 3
|
|
#define PARAM_DMC0_NUM_CS 1
|
|
#define PARAM_DMC0_NUM_DATA 16
|
|
|
|
|
|
/* System Cross Bar Parameters */
|
|
|
|
#define PARAM_SCB0_NUM_MASTERS 6
|
|
#define PARAM_SCB0_NUM_SLOTS 32
|
|
#define PARAM_SCB1_NUM_MASTERS 1
|
|
#define PARAM_SCB1_NUM_SLOTS 32
|
|
#define PARAM_SCB2_NUM_MASTERS 1
|
|
#define PARAM_SCB2_NUM_SLOTS 32
|
|
#define PARAM_SCB3_NUM_MASTERS 1
|
|
#define PARAM_SCB3_NUM_SLOTS 32
|
|
#define PARAM_SCB4_NUM_MASTERS 1
|
|
#define PARAM_SCB4_NUM_SLOTS 32
|
|
#define PARAM_SCB5_NUM_MASTERS 1
|
|
#define PARAM_SCB5_NUM_SLOTS 32
|
|
#define PARAM_SCB6_NUM_MASTERS 1
|
|
#define PARAM_SCB6_NUM_SLOTS 32
|
|
#define PARAM_SCB7_NUM_MASTERS 1
|
|
#define PARAM_SCB7_NUM_SLOTS 32
|
|
#define PARAM_SCB8_NUM_MASTERS 1
|
|
#define PARAM_SCB8_NUM_SLOTS 32
|
|
#define PARAM_SCB9_NUM_MASTERS 1
|
|
#define PARAM_SCB9_NUM_SLOTS 32
|
|
#define PARAM_SCB10_NUM_MASTERS 3
|
|
#define PARAM_SCB10_NUM_SLOTS 32
|
|
#define PARAM_SCB11_NUM_MASTERS 7
|
|
#define PARAM_SCB11_NUM_SLOTS 32
|
|
|
|
|
|
|
|
/* System Event Controller Parameters */
|
|
|
|
#define PARAM_SEC0_CCOUNT 2
|
|
#define PARAM_SEC0_SCOUNT 140
|
|
|
|
|
|
/* Trigger Routing Unit Parameters */
|
|
|
|
#define PARAM_TRU0_NUM_INTS 4
|
|
#define PARAM_TRU0_NUM_TRIGS 4
|
|
#define PARAM_TRU0_SSRCOUNT 87
|
|
|
|
|
|
/* Reset Control Unit Parameters */
|
|
|
|
#define PARAM_RCU0_CCOUNT 2
|
|
#define PARAM_RCU0_CRCTL_CR_INIT 2
|
|
#define PARAM_RCU0_CRSTAT_CR_INIT 3
|
|
#define PARAM_RCU0_SICOUNT 2
|
|
#define PARAM_RCU0_SVECT_INIT 65440
|
|
|
|
|
|
/* System Protection Unit Parameters */
|
|
|
|
#define PARAM_SPU0_CM_COUNT 2
|
|
#define PARAM_SPU0_END_POINT_COUNT 86
|
|
#define PARAM_SPU0_SM_COUNT 2
|
|
|
|
|
|
/* Clock Generation Unit Parameters */
|
|
|
|
#define PARAM_CGU0_CSEL_DEFAULT 4
|
|
#define PARAM_CGU0_DSEL_DEFAULT 8
|
|
#define PARAM_CGU0_MSEL_DEFAULT 16
|
|
#define PARAM_CGU0_OSEL_DEFAULT 16
|
|
#define PARAM_CGU0_PLLBP_DEFAULT 0
|
|
#define PARAM_CGU0_S0SEL_DEFAULT 2
|
|
#define PARAM_CGU0_S1SEL_DEFAULT 2
|
|
#define PARAM_CGU0_SYSSEL_DEFAULT 8
|
|
|
|
|
|
/* Dynamic Power Management Parameters */
|
|
|
|
#define PARAM_DPM0_NUM_CCLK 2
|
|
#define PARAM_DPM0_NUM_HV 8
|
|
#define PARAM_DPM0_NUM_SCLK 4
|
|
#define PARAM_DPM0_NUM_WAKE 8
|
|
|
|
|
|
|
|
/* Universal Serial Bus Controller Parameters */
|
|
|
|
#define PARAM_USB0_DMA_CHAN 8
|
|
#define PARAM_USB0_DYN_FIFO_SIZE 1
|
|
#define PARAM_USB0_FS_PHY 0
|
|
#define PARAM_USB0_HS_PHY 1
|
|
#define PARAM_USB0_LOOPBACK 1
|
|
#define PARAM_USB0_NUM_ENDPTS 12
|
|
#define PARAM_USB0_NUM_ENDPTS_MINUS_1 11
|
|
|
|
|
|
/* Data Memory Unit Parameters */
|
|
|
|
#define PARAM_L1DM0_L1_BASE_ADDRESS 1111111110
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* ===================================
|
|
Trigger Master Definitions
|
|
=================================== */
|
|
/* -- RESERVED -- 0 */
|
|
#define TRGM_CGU0_EVT 1 /* Event */
|
|
#define TRGM_TIMER0_TMR0 2 /* Timer 0 */
|
|
#define TRGM_TIMER0_TMR1 3 /* Timer 1 */
|
|
#define TRGM_TIMER0_TMR2 4 /* Timer 2 */
|
|
#define TRGM_TIMER0_TMR3 5 /* Timer 3 */
|
|
#define TRGM_TIMER0_TMR4 6 /* Timer 4 */
|
|
#define TRGM_TIMER0_TMR5 7 /* Timer 5 */
|
|
#define TRGM_TIMER0_TMR6 8 /* Timer 6 */
|
|
#define TRGM_TIMER0_TMR7 9 /* Timer 7 */
|
|
#define TRGM_PINT0_BLOCK 10 /* Pin Interrupt Block */
|
|
#define TRGM_PINT1_BLOCK 11 /* Pin Interrupt Block */
|
|
#define TRGM_PINT2_BLOCK 12 /* Pin Interrupt Block */
|
|
#define TRGM_PINT3_BLOCK 13 /* Pin Interrupt Block */
|
|
#define TRGM_PINT4_BLOCK 14 /* Pin Interrupt Block */
|
|
#define TRGM_PINT5_BLOCK 15 /* Pin Interrupt Block */
|
|
#define TRGM_CNT0_STAT 16 /* Status */
|
|
#define TRGM_PWM0_SYNC 17 /* Sync */
|
|
#define TRGM_PWM1_SYNC 18 /* Sync */
|
|
#define TRGM_ACM0_EVT_COMPLETE 19 /* Event Complete */
|
|
#define TRGM_SPORT0_A_DMA 20 /* Channel A DMA */
|
|
#define TRGM_SPORT0_B_DMA 21 /* Channel B DMA */
|
|
#define TRGM_SPORT1_A_DMA 22 /* Channel A DMA */
|
|
#define TRGM_SPORT1_B_DMA 23 /* Channel B DMA */
|
|
#define TRGM_SPORT2_A_DMA 24 /* Channel A DMA */
|
|
#define TRGM_SPORT2_B_DMA 25 /* Channel B DMA */
|
|
#define TRGM_SPI0_TXDMA 26 /* TX DMA Channel */
|
|
#define TRGM_SPI0_RXDMA 27 /* RX DMA Channel */
|
|
#define TRGM_SPI1_TXDMA 28 /* TX DMA Channel */
|
|
#define TRGM_SPI1_RXDMA 29 /* RX DMA Channel */
|
|
#define TRGM_RSI0_DMA 30 /* DMA Channel */
|
|
#define TRGM_SDU0_DMA 31 /* DMA */
|
|
/* -- RESERVED -- 32 */
|
|
#define TRGM_EMAC0_STAT 33 /* Status */
|
|
#define TRGM_EMAC1_STAT 34 /* Status */
|
|
#define TRGM_LP0_DMA 35 /* DMA Channel */
|
|
#define TRGM_LP1_DMA 36 /* DMA Channel */
|
|
#define TRGM_LP2_DMA 37 /* DMA Channel */
|
|
#define TRGM_LP3_DMA 38 /* DMA Channel */
|
|
#define TRGM_UART0_TXDMA 39 /* Transmit DMA */
|
|
#define TRGM_UART0_RXDMA 40 /* Receive DMA */
|
|
#define TRGM_UART1_TXDMA 41 /* Transmit DMA */
|
|
#define TRGM_UART1_RXDMA 42 /* Receive DMA */
|
|
#define TRGM_MDMA0_SRC 43 /* Memory DMA Stream 0 Source / CRC0 Input Channel */
|
|
#define TRGM_MDMA0_DST 44 /* Memory DMA Stream 0 Destination / CRC0 Output Channel */
|
|
#define TRGM_MDMA1_SRC 45 /* Memory DMA Stream 1 Source / CRC1 Input Channel */
|
|
#define TRGM_MDMA1_DST 46 /* Memory DMA Stream 1 Destination / CRC1 Output Channel */
|
|
#define TRGM_MDMA2_SRC 47 /* Memory DMA Stream 2 Source Channel */
|
|
#define TRGM_MDMA2_DST 48 /* Memory DMA Stream 2 Destination Channel */
|
|
#define TRGM_MDMA3_SRC 49 /* Memory DMA Stream 3 Source Channel */
|
|
#define TRGM_MDMA3_DST 50 /* Memory DMA Stream 3 Destination Channel */
|
|
#define TRGM_EPPI0_CH0_DMA 51 /* Channel 0 DMA */
|
|
#define TRGM_EPPI0_CH1_DMA 52 /* Channel 1 DMA */
|
|
#define TRGM_EPPI2_CH0_DMA 53 /* Channel 0 DMA */
|
|
#define TRGM_EPPI2_CH1_DMA 54 /* Channel 1 DMA */
|
|
#define TRGM_EPPI1_CH0_DMA 55 /* Channel 0 DMA */
|
|
#define TRGM_EPPI1_CH1_DMA 56 /* Channel 1 DMA */
|
|
#define TRGM_USB0_DATA 69 /* DMA Status/Transfer Complete */
|
|
/* -- RESERVED -- 70 */
|
|
#define TRGM_SEC0_FAULT 71 /* Fault */
|
|
#define TRGM_SOFT0 72 /* Software-driven Trigger 0 */
|
|
#define TRGM_SOFT1 73 /* Software-driven Trigger 1 */
|
|
#define TRGM_SOFT2 74 /* Software-driven Trigger 2 */
|
|
#define TRGM_SOFT3 75 /* Software-driven Trigger 3 */
|
|
#define TRGM_SOFT4 76 /* Software-driven Trigger 4 */
|
|
#define TRGM_SOFT5 77 /* Software-driven Trigger 5 */
|
|
#define TRGM_SWU0_EVT 80 /* Event */
|
|
#define TRGM_SWU1_EVT 81 /* Event */
|
|
#define TRGM_SWU2_EVT 82 /* Event */
|
|
#define TRGM_SWU3_EVT 83 /* Event */
|
|
#define TRGM_SWU4_EVT 84 /* Event */
|
|
#define TRGM_SWU5_EVT 85 /* Event */
|
|
#define TRGM_SWU6_EVT 86 /* Event */
|
|
|
|
/* ===================================
|
|
Trigger Slave Definitions
|
|
=================================== */
|
|
#define TRGS_RCU0_SYSRST0 0 /* System Reset 0 */
|
|
#define TRGS_RCU0_SYSRST1 1 /* System Reset 1 */
|
|
#define TRGS_TIMER0_TMR0 2 /* Timer 0 */
|
|
#define TRGS_TIMER0_TMR1 3 /* Timer 1 */
|
|
#define TRGS_TIMER0_TMR2 4 /* Timer 2 */
|
|
#define TRGS_TIMER0_TMR3 5 /* Timer 3 */
|
|
#define TRGS_TIMER0_TMR4 6 /* Timer 4 */
|
|
#define TRGS_TIMER0_TMR5 7 /* Timer 5 */
|
|
#define TRGS_TIMER0_TMR6 8 /* Timer 6 */
|
|
#define TRGS_TIMER0_TMR7 9 /* Timer 7 */
|
|
/* -- RESERVED -- 10 */
|
|
/* -- RESERVED -- 11 */
|
|
#define TRGS_C0_NMI_S0 12 /* NMI (Core 0) Slave 0 */
|
|
#define TRGS_C0_NMI_S1 13 /* NMI (Core 0) Slave 1 */
|
|
#define TRGS_C1_NMI_S0 14 /* NMI (Core 1) Slave 0 */
|
|
#define TRGS_C1_NMI_S1 15 /* NMI (Core 1) Slave 1 */
|
|
#define TRGS_TRU0_IRQ0 16 /* Interrupt Request 0 */
|
|
#define TRGS_TRU0_IRQ1 17 /* Interrupt Request 1 */
|
|
#define TRGS_TRU0_IRQ2 18 /* Interrupt Request 2 */
|
|
#define TRGS_TRU0_IRQ3 19 /* Interrupt Request 3 */
|
|
#define TRGS_SPORT0_A_DMA 20 /* Channel A DMA */
|
|
#define TRGS_SPORT0_B_DMA 21 /* Channel B DMA */
|
|
#define TRGS_SPORT1_A_DMA 22 /* Channel A DMA */
|
|
#define TRGS_SPORT1_B_DMA 23 /* Channel B DMA */
|
|
#define TRGS_SPORT2_A_DMA 24 /* Channel A DMA */
|
|
#define TRGS_SPORT2_B_DMA 25 /* Channel B DMA */
|
|
#define TRGS_SPI0_TXDMA 26 /* TX DMA Channel */
|
|
#define TRGS_SPI0_RXDMA 27 /* RX DMA Channel */
|
|
#define TRGS_SPI1_TXDMA 28 /* TX DMA Channel */
|
|
#define TRGS_SPI1_RXDMA 29 /* RX DMA Channel */
|
|
#define TRGS_RSI0_DMA 30 /* DMA Channel */
|
|
#define TRGS_SDU0_DMA 31 /* DMA */
|
|
/* -- RESERVED -- 32 */
|
|
#define TRGS_ACM0_TRIG2 33 /* Trigger Input 2 */
|
|
#define TRGS_ACM0_TRIG3 34 /* Trigger Input 3 */
|
|
#define TRGS_LP0_DMA 35 /* DMA Channel */
|
|
#define TRGS_LP1_DMA 36 /* DMA Channel */
|
|
#define TRGS_LP2_DMA 37 /* DMA Channel */
|
|
#define TRGS_LP3_DMA 38 /* DMA Channel */
|
|
#define TRGS_UART0_TXDMA 39 /* Transmit DMA */
|
|
#define TRGS_UART0_RXDMA 40 /* Receive DMA */
|
|
#define TRGS_UART1_TXDMA 41 /* Transmit DMA */
|
|
#define TRGS_UART1_RXDMA 42 /* Receive DMA */
|
|
#define TRGS_MDMA0_SRC 43 /* Memory DMA Stream 0 Source / CRC0 Input Channel */
|
|
#define TRGS_MDMA0_DST 44 /* Memory DMA Stream 0 Destination / CRC0 Output Channel */
|
|
#define TRGS_MDMA1_SRC 45 /* Memory DMA Stream 1 Source / CRC1 Input Channel */
|
|
#define TRGS_MDMA1_DST 46 /* Memory DMA Stream 1 Destination / CRC1 Output Channel */
|
|
#define TRGS_MDMA2_SRC 47 /* Memory DMA Stream 2 Source Channel */
|
|
#define TRGS_MDMA2_DST 48 /* Memory DMA Stream 2 Destination Channel */
|
|
#define TRGS_MDMA3_SRC 49 /* Memory DMA Stream 3 Source Channel */
|
|
#define TRGS_MDMA3_DST 50 /* Memory DMA Stream 3 Destination Channel */
|
|
#define TRGS_EPPI0_CH0_DMA 51 /* Channel 0 DMA */
|
|
#define TRGS_EPPI0_CH1_DMA 52 /* Channel 1 DMA */
|
|
#define TRGS_EPPI2_CH0_DMA 53 /* Channel 0 DMA */
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#define TRGS_EPPI2_CH1_DMA 54 /* Channel 1 DMA */
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#define TRGS_EPPI1_CH0_DMA 55 /* Channel 0 DMA */
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#define TRGS_EPPI1_CH1_DMA 56 /* Channel 1 DMA */
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#define TRGS_SDU0_SLAVE 69 /* Slave Trigger */
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/* -- RESERVED -- 70 */
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#define TRGS_C0_WAKE0 71 /* Core 0 Wakeup Input 0 */
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#define TRGS_C0_WAKE1 72 /* Core 0 Wakeup Input 1 */
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#define TRGS_C0_WAKE2 73 /* Core 0 Wakeup Input 2 */
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#define TRGS_C0_WAKE3 74 /* Core 0 Wakeup Input 3 */
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#define TRGS_C1_WAKE0 75 /* Core 1 Wakeup Input 0 */
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#define TRGS_C1_WAKE1 76 /* Core 1 Wakeup Input 1 */
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#define TRGS_C1_WAKE2 77 /* Core 1 Wakeup Input 2 */
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#define TRGS_C1_WAKE3 78 /* Core 1 Wakeup Input 3 */
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/* -- RESERVED -- 79 */
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#define TRGS_SWU0_EVT 80 /* Event */
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#define TRGS_SWU1_EVT 81 /* Event */
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#define TRGS_SWU2_EVT 82 /* Event */
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#define TRGS_SWU3_EVT 83 /* Event */
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#define TRGS_SWU4_EVT 84 /* Event */
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#define TRGS_SWU5_EVT 85 /* Event */
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#define TRGS_SWU6_EVT 86 /* Event */
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/* ============================================================================
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Memory Map Macros
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============================================================================ */
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/* ADSP-BF606 is a multi-core processor */
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#define MEM_NUM_CORES 2
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/* Internal memory range */
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#define MEM_BASE_INTERNAL 0xC0000000
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#define MEM_END_INTERNAL 0xFFFFFFFF
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#define MEM_SIZE_INTERNAL 0x40000000
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/* External memory range */
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#define MEM_BASE_EXTERNAL 0x00000000
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#define MEM_END_EXTERNAL 0xBFFFFFFF
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#define MEM_SIZE_EXTERNAL 0xC0000000
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/* Shared DDR2 or LPDDR Memory (256 MB) */
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#define MEM_BASE_DDR 0x00000000
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#define MEM_END_DDR 0x0FFFFFFF
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#define MEM_SIZE_DDR 0x10000000
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/* Shared Async Memory (256 MB) */
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#define MEM_BASE_ASYNC 0xB0000000
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#define MEM_END_ASYNC 0xBFFFFFFF
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#define MEM_SIZE_ASYNC 0x10000000
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/* Shared Async Memory Bank 0 (64 MB) */
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#define MEM_BASE_ASYNC_0 0xB0000000
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#define MEM_END_ASYNC_0 0xB3FFFFFF
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#define MEM_SIZE_ASYNC_0 0x4000000
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/* Shared Async Memory Bank 1 (64 MB) */
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#define MEM_BASE_ASYNC_1 0xB4000000
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#define MEM_END_ASYNC_1 0xB7FFFFFF
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#define MEM_SIZE_ASYNC_1 0x4000000
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/* Shared Async Memory Bank 2 (64 MB) */
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#define MEM_BASE_ASYNC_2 0xB8000000
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#define MEM_END_ASYNC_2 0xBBFFFFFF
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#define MEM_SIZE_ASYNC_2 0x4000000
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/* Shared Async Memory Bank 3 (64 MB) */
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#define MEM_BASE_ASYNC_3 0xBC000000
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#define MEM_END_ASYNC_3 0xBFFFFFFF
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#define MEM_SIZE_ASYNC_3 0x4000000
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/* Shared L2 ROM (32 KB) */
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#define MEM_BASE_L2_ROM 0xC8000000
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#define MEM_END_L2_ROM 0xC8007FFF
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#define MEM_SIZE_L2_ROM 0x8000
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/* Shared L2 SRAM (128 KB) */
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#define MEM_BASE_L2_SRAM 0xC8080000
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#define MEM_END_L2_SRAM 0xC809FFFF
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#define MEM_SIZE_L2_SRAM 0x20000
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|
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/* Core 1 L1 Data Bank A (32 KB) */
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#define MEM_C1_BASE_L1DM_A 0xFF400000
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#define MEM_C1_END_L1DM_A 0xFF407FFF
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#define MEM_C1_SIZE_L1DM_A 0x8000
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/* Core 1 L1 Data Bank A SRAM (16 KB) */
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#define MEM_C1_BASE_L1DM_A_SRAM 0xFF400000
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#define MEM_C1_END_L1DM_A_SRAM 0xFF403FFF
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#define MEM_C1_SIZE_L1DM_A_SRAM 0x4000
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/* Core 1 L1 Data Bank A SRAM/Cache (16 KB) */
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#define MEM_C1_BASE_L1DM_A_SRAM_CACHE 0xFF404000
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#define MEM_C1_END_L1DM_A_SRAM_CACHE 0xFF407FFF
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#define MEM_C1_SIZE_L1DM_A_SRAM_CACHE 0x4000
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|
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/* Core 1 L1 Data Bank B (32 KB) */
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|
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#define MEM_C1_BASE_L1DM_B 0xFF500000
|
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#define MEM_C1_END_L1DM_B 0xFF507FFF
|
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#define MEM_C1_SIZE_L1DM_B 0x8000
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|
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/* Core 1 L1 Data Bank B SRAM (16 KB) */
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|
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#define MEM_C1_BASE_L1DM_B_SRAM 0xFF500000
|
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#define MEM_C1_END_L1DM_B_SRAM 0xFF503FFF
|
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#define MEM_C1_SIZE_L1DM_B_SRAM 0x4000
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|
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/* Core 1 L1 Data Bank B SRAM/Cache (16 KB) */
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|
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#define MEM_C1_BASE_L1DM_B_SRAM_CACHE 0xFF504000
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#define MEM_C1_END_L1DM_B_SRAM_CACHE 0xFF507FFF
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#define MEM_C1_SIZE_L1DM_B_SRAM_CACHE 0x4000
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|
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/* Core 1 L1 Instruction (80 KB) */
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|
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#define MEM_C1_BASE_L1IM 0xFF600000
|
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#define MEM_C1_END_L1IM 0xFF613FFF
|
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#define MEM_C1_SIZE_L1IM 0x14000
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|
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/* Core 1 L1 Instruction SRAM (64 KB) */
|
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|
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#define MEM_C1_BASE_L1IM_SRAM 0xFF600000
|
|
#define MEM_C1_END_L1IM_SRAM 0xFF60FFFF
|
|
#define MEM_C1_SIZE_L1IM_SRAM 0x10000
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|
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/* Core 1 L1 Instruction SRAM/Cache (16 KB) */
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|
|
|
#define MEM_C1_BASE_L1IM_SRAM_CACHE 0xFF610000
|
|
#define MEM_C1_END_L1IM_SRAM_CACHE 0xFF613FFF
|
|
#define MEM_C1_SIZE_L1IM_SRAM_CACHE 0x4000
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|
|
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/* Core 1 L1 Scratchpad SRAM (4 KB) */
|
|
|
|
#define MEM_C1_BASE_L1_XPAD_SRAM 0xFF700000
|
|
#define MEM_C1_END_L1_XPAD_SRAM 0xFF700FFF
|
|
#define MEM_C1_SIZE_L1_XPAD_SRAM 0x1000
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|
|
|
/* Core 0 L1 Data Bank A (32 KB) */
|
|
|
|
#define MEM_C0_BASE_L1DM_A 0xFF800000
|
|
#define MEM_C0_END_L1DM_A 0xFF807FFF
|
|
#define MEM_C0_SIZE_L1DM_A 0x8000
|
|
|
|
/* Core 0 L1 Data Bank A SRAM (16 KB) */
|
|
|
|
#define MEM_C0_BASE_L1DM_A_SRAM 0xFF800000
|
|
#define MEM_C0_END_L1DM_A_SRAM 0xFF803FFF
|
|
#define MEM_C0_SIZE_L1DM_A_SRAM 0x4000
|
|
|
|
/* Core 0 L1 Data Bank A SRAM/Cache (16 KB) */
|
|
|
|
#define MEM_C0_BASE_L1DM_A_SRAM_CACHE 0xFF804000
|
|
#define MEM_C0_END_L1DM_A_SRAM_CACHE 0xFF807FFF
|
|
#define MEM_C0_SIZE_L1DM_A_SRAM_CACHE 0x4000
|
|
|
|
/* Core 0 L1 Data Bank B (32 KB) */
|
|
|
|
#define MEM_C0_BASE_L1DM_B 0xFF900000
|
|
#define MEM_C0_END_L1DM_B 0xFF907FFF
|
|
#define MEM_C0_SIZE_L1DM_B 0x8000
|
|
|
|
/* Core 0 L1 Data Bank B SRAM (16 KB) */
|
|
|
|
#define MEM_C0_BASE_L1DM_B_SRAM 0xFF900000
|
|
#define MEM_C0_END_L1DM_B_SRAM 0xFF903FFF
|
|
#define MEM_C0_SIZE_L1DM_B_SRAM 0x4000
|
|
|
|
/* Core 0 L1 Data Bank B SRAM/Cache (16 KB) */
|
|
|
|
#define MEM_C0_BASE_L1DM_B_SRAM_CACHE 0xFF904000
|
|
#define MEM_C0_END_L1DM_B_SRAM_CACHE 0xFF907FFF
|
|
#define MEM_C0_SIZE_L1DM_B_SRAM_CACHE 0x4000
|
|
|
|
/* Core 0 L1 Instruction (80 KB) */
|
|
|
|
#define MEM_C0_BASE_L1IM 0xFFA00000
|
|
#define MEM_C0_END_L1IM 0xFFA13FFF
|
|
#define MEM_C0_SIZE_L1IM 0x14000
|
|
|
|
/* Core 0 L1 Instruction SRAM (64 KB) */
|
|
|
|
#define MEM_C0_BASE_L1IM_SRAM 0xFFA00000
|
|
#define MEM_C0_END_L1IM_SRAM 0xFFA0FFFF
|
|
#define MEM_C0_SIZE_L1IM_SRAM 0x10000
|
|
|
|
/* Core 0 L1 Instruction SRAM/Cache (16 KB) */
|
|
|
|
#define MEM_C0_BASE_L1IM_SRAM_CACHE 0xFFA10000
|
|
#define MEM_C0_END_L1IM_SRAM_CACHE 0xFFA13FFF
|
|
#define MEM_C0_SIZE_L1IM_SRAM_CACHE 0x4000
|
|
|
|
/* Core 0 L1 Scratchpad SRAM (4 KB) */
|
|
|
|
#define MEM_C0_BASE_L1_XPAD_SRAM 0xFFB00000
|
|
#define MEM_C0_END_L1_XPAD_SRAM 0xFFB00FFF
|
|
#define MEM_C0_SIZE_L1_XPAD_SRAM 0x1000
|
|
|
|
/* Shared System MMR Registers (2 MB) */
|
|
|
|
#define MEM_BASE_MMR_SYSTEM 0xFFC00000
|
|
#define MEM_END_MMR_SYSTEM 0xFFDFFFFF
|
|
#define MEM_SIZE_MMR_SYSTEM 0x200000
|
|
|
|
/* Core 0 Core MMR Registers (2 MB) */
|
|
|
|
#define MEM_C0_BASE_MMR_CORE 0xFFE00000
|
|
#define MEM_C0_END_MMR_CORE 0xFFFFFFFF
|
|
#define MEM_C0_SIZE_MMR_CORE 0x200000
|
|
|
|
/* Core 1 Core MMR Registers (2 MB) */
|
|
|
|
#define MEM_C1_BASE_MMR_CORE 0xFFE00000
|
|
#define MEM_C1_END_MMR_CORE 0xFFFFFFFF
|
|
#define MEM_C1_SIZE_MMR_CORE 0x200000
|
|
|
|
|
|
#endif /* end ifndef _DEF_BF606_H */
|