a4ed1daa7f
* elf/sparc.h (R_SPARC_GOTDATA_HIX22,
...
R_SPARC_GOTDATA_LOX10, R_SPARC_GOTDATA_OP_HIX22,
R_SPARC_GOTDATA_OP_LOX10, R_SPARC_GOTDATA_OP,
R_SPARC_H34, R_SPARC_SIZE32, R_SPARC_SIZE64): New relocs.
2008-04-16 08:35:17 +00:00
7ed2b9c492
Move entries for changes in sub-directories into the changelogs in those sub-
...
directories.
2008-04-16 08:33:54 +00:00
962c961a36
ppc e500mc support
2008-04-14 11:01:38 +00:00
1d0a4e1490
2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
...
* s390-dis.c (init_disasm): Evaluate disassembler_options.
(print_s390_disassembler_options): New function.
* disassemble.c (disassembler_usage): Invoke
print_s390_disassembler_options.
2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
* dis-asm.h (print_s390_disassembler_options):
Prototype added.
2008-04-10 13:36:43 +00:00
3322254d27
sim-cr16.h: New file. Added for cr16 target.
2008-04-08 08:33:51 +00:00
f47b47fb18
binutils/
...
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* dwarf.c (dwarf_regnames_i386): Add AVX registers.
(dwarf_regnames_x86_64): Likewise.
gas/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.
* doc/c-i386.texi: Add avx, aes, clmul and fma to -march=.
Document -msse2avx, .avx, .aes, .clmul and .fma.
* config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New.
(vex_prefix): Likewise.
(sse2avx): Likewise.
(CPU_FLAGS_ARCH_MATCH): Likewise.
(CPU_FLAGS_64BIT_MATCH): Likewise.
(CPU_FLAGS_32BIT_MATCH): Likewise.
(CPU_FLAGS_PERFECT_MATCH): Likewise.
(regymm): Likewise.
(vex_imm4): Likewise.
(fits_in_imm4): Likewise.
(build_vex_prefix): Likewise.
(VEX_check_operands): Likewise.
(bad_implicit_operand): Likewise.
(OPTION_MSSE2AVX): Likewise.
(T_YMMWORD): Likewise.
(_i386_insn): Add vex.
(cpu_arch): Add .avx, .aes, .clmul and .fma.
(cpu_flags_match): Changed to take a pointer to const template.
Enable encoding SSE instructions with VEX prefix for -msse2avx.
(match_mem_size): Also check ymmword.
(operand_type_match): Clear ymmword.
(md_begin): Allow '_' in mnemonic.
(type_names): Add OPERAND_TYPE_VEX_IMM4.
(process_immext): Update assert.
(md_assemble): Don't call process_immext if sse2avx and immext
are true. Call build_vex_prefix if vex is true.
(parse_insn): Updated for cpu_flags_match.
(swap_operands): Handle 5 operands.
(match_template): Handle 5 operands. Updated for cpu_flags_match.
Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX.
(process_suffix): Handle YMMWORD_MNEM_SUFFIX.
(check_byte_reg): Check regymm.
(process_operands): Duplicate the destination register for
-msse2avx if needed.
(build_modrm_byte): Updated for instructions with VEX encoding.
(output_insn): Output VEX prefix if needed.
(md_longopts): Add msse2avx.
(md_parse_option): Handle OPTION_MSSE2AVX.
(md_show_usage): Add avx, aes, clmul, fma and -msse2avx.
(intel_e09): Support YMMWORD.
(intel_e11): Likewise.
(intel_get_token): Likewise.
gas/testsuite/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,
x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx,
x86-64-avx-intel and x86-64-inval-avx.
* gas/cfi/cfi-i386.s: Add tests for AVX register maps.
* gas/cfi/cfi-x86_64.s: Likewise.
* gas/i386/aes.d: New.
* gas/i386/aes.s: Likewise.
* gas/i386/aes-intel.d: Likewise.
* gas/i386/avx.d: Likewise.
* gas/i386/avx.s: Likewise.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/clmul.d: Likewise.
* gas/i386/clmul-intel.d: Likewise.
* gas/i386/clmul.s: Likewise.
* gas/i386/i386.exp: Likewise.
* gas/i386/inval-avx.l: Likewise.
* gas/i386/inval-avx.s: Likewise.
* gas/i386/sse2avx.d: Likewise.
* gas/i386/sse2avx.s: Likewise.
* gas/i386/x86-64-aes.d: Likewise.
* gas/i386/x86-64-aes.s: Likewise.
* gas/i386/x86-64-aes-intel.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx.s: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
* gas/i386/x86-64-clmul.d: Likewise.
* gas/i386/x86-64-clmul-intel.d: Likewise.
* gas/i386/x86-64-clmul.s: Likewise.
* gas/i386/x86-64-inval-avx.l: Likewise.
* gas/i386/x86-64-inval-avx.s: Likewise.
* gas/i386/x86-64-sse2avx.d: Likewise.
* gas/i386/x86-64-sse2avx.s: Likewise.
* gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/rexw.s: Add AVX tests.
* gas/i386/x86-64-opcode-inval.s: Remove lds/les test.
* gas/cfi/cfi-i386.d: Updated.
* gas/cfi/cfi-x86_64.d: Likewise.
* gas/i386/arch-10.d: Likewise.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/rexw.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-opcode-inval.d: Likewise.
* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
include/opcode/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (MAX_OPERANDS): Set to 5.
(MAX_MNEM_SIZE): Changed to 20.
opcodes/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_E_register): New.
(OP_E_memory): Likewise.
(OP_VEX): Likewise.
(OP_EX_Vex): Likewise.
(OP_EX_VexW): Likewise.
(OP_XMM_Vex): Likewise.
(OP_XMM_VexW): Likewise.
(OP_REG_VexI4): Likewise.
(PCLMUL_Fixup): Likewise.
(VEXI4_Fixup): Likewise.
(VZERO_Fixup): Likewise.
(VCMP_Fixup): Likewise.
(VPERMIL2_Fixup): Likewise.
(rex_original): Likewise.
(rex_ignored): Likewise.
(Mxmm): Likewise.
(XMM): Likewise.
(EXxmm): Likewise.
(EXxmmq): Likewise.
(EXymmq): Likewise.
(Vex): Likewise.
(Vex128): Likewise.
(Vex256): Likewise.
(VexI4): Likewise.
(EXdVex): Likewise.
(EXqVex): Likewise.
(EXVexW): Likewise.
(EXdVexW): Likewise.
(EXqVexW): Likewise.
(XMVex): Likewise.
(XMVexW): Likewise.
(XMVexI4): Likewise.
(PCLMUL): Likewise.
(VZERO): Likewise.
(VCMP): Likewise.
(VPERMIL2): Likewise.
(xmm_mode): Likewise.
(xmmq_mode): Likewise.
(ymmq_mode): Likewise.
(vex_mode): Likewise.
(vex128_mode): Likewise.
(vex256_mode): Likewise.
(USE_VEX_C4_TABLE): Likewise.
(USE_VEX_C5_TABLE): Likewise.
(USE_VEX_LEN_TABLE): Likewise.
(VEX_C4_TABLE): Likewise.
(VEX_C5_TABLE): Likewise.
(VEX_LEN_TABLE): Likewise.
(REG_VEX_XX): Likewise.
(MOD_VEX_XXX): Likewise.
(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
(PREFIX_0F3A44): Likewise.
(PREFIX_0F3ADF): Likewise.
(PREFIX_VEX_XXX): Likewise.
(VEX_OF): Likewise.
(VEX_OF38): Likewise.
(VEX_OF3A): Likewise.
(VEX_LEN_XXX): Likewise.
(vex): Likewise.
(need_vex): Likewise.
(need_vex_reg): Likewise.
(vex_i4_done): Likewise.
(vex_table): Likewise.
(vex_len_table): Likewise.
(OP_REG_VexI4): Likewise.
(vex_cmp_op): Likewise.
(pclmul_op): Likewise.
(vpermil2_op): Likewise.
(m_mode): Updated.
(es_reg): Likewise.
(PREFIX_0F38F0): Likewise.
(PREFIX_0F3A60): Likewise.
(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
and PREFIX_VEX_XXX entries.
(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
PREFIX_0F3ADF.
(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
Add MOD_VEX_XXX entries.
(ckprefix): Initialize rex_original and rex_ignored. Store the
REX byte in rex_original.
(get_valid_dis386): Handle the implicit prefix in VEX prefix
bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
calling get_valid_dis386. Use rex_original and rex_ignored when
printing out REX.
(putop): Handle "XY".
(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
ymmq_mode.
(OP_E_extended): Updated to use OP_E_register and
OP_E_memory.
(OP_XMM): Handle VEX.
(OP_EX): Likewise.
(XMM_Fixup): Likewise.
(CMP_Fixup): Use ARRAY_SIZE.
* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
CPU_FMA_FLAGS and CPU_AVX_FLAGS.
(operand_type_init): Add OPERAND_TYPE_REGYMM and
OPERAND_TYPE_VEX_IMM4.
(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
VexImmExt and SSE2AVX.
(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
* i386-opc.h (CpuAVX): New.
(CpuAES): Likewise.
(CpuCLMUL): Likewise.
(CpuFMA): Likewise.
(Vex): Likewise.
(Vex256): Likewise.
(VexNDS): Likewise.
(VexNDD): Likewise.
(VexW0): Likewise.
(VexW1): Likewise.
(Vex0F): Likewise.
(Vex0F38): Likewise.
(Vex0F3A): Likewise.
(Vex3Sources): Likewise.
(VexImmExt): Likewise.
(SSE2AVX): Likewise.
(RegYMM): Likewise.
(Ymmword): Likewise.
(Vex_Imm4): Likewise.
(Implicit1stXmm0): Likewise.
(CpuXsave): Updated.
(CpuLM): Likewise.
(ByteOkIntel): Likewise.
(OldGcc): Likewise.
(Control): Likewise.
(Unspecified): Likewise.
(OTMax): Likewise.
(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
vex3sources, veximmext and sse2avx.
(i386_operand_type): Add regymm, ymmword and vex_imm4.
* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-04-03 14:03:20 +00:00
07e2a8f376
/gas:
...
2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
* config/tc-avr.c (mcu_types): Add attiny167.
* doc/c-avr.texi: Likewise.
/include:
2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
* opcode/avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
2008-03-28 21:51:38 +00:00
cb411288ce
Add support for thin archives.
...
* bfd/archive.c (_bfd_find_nested_archive): New function.
(get_extended_arelt_filename): Add origin parameter.
(_bfd_generic_read_ar_hdr_mag): Deal with extended name
combined with a file offset.
(append_relative_path): New function.
(_bfd_get_elt_at_filepos): Deal with external members and
nested archives.
(bfd_generic_openr_next_archived_file): Thin archives.
(bfd_generic_archive_p): Recognize new magic string.
(adjust_relative_path): New function.
(_bfd_construct_extended_name_table): Construct extended
names for thin archive members.
(_bfd_write_archive_contents): Emit new magic string, skip
copying files for thin archives.
* bfd/bfd-in.h (bfd_is_thin_archive): New macro.
* bfd/bfd.c (struct bfd): New fields for thin archives.
* bfd/libbfd-in.h (struct areltdata): New field for thin archives.
* bfd/opncls.c (bfd_close): Delete BFDs for nested archives.
* binutils/ar.c (make_thin_archive): New global flag.
(map_over_members): Deal with full pathnames in thin archives.
(usage, main): Add 'T' option for building thin archives.
(replace_members): Pass thin archive flag to ar_emul_append.
* binutils/arsup.c (ar_open): Initialize new flag.
* binutils/binemul.c (ar_emul_append): Add new parameter for
flattening nested archives.
(do_ar_emul_default_append): New function.
(ar_emul_default_append): Factored out recursive code.
* binutils/binemul.h (ar_emul_default_append): Add new parameter.
(struct bin_emulation_xfer_struct): New parameter for ar_append.
* binutils/dlltool.c (gen_lib_file): Initialize thin archive flag.
* binutils/emul_aix.c (ar_emul_aix_internal): Add new flatten
parameter, currently unimplemented.
All callers changed.
* binutils/objcopy.c (copy_archive): Preserve thin archive flag.
* binutils/doc/binutils.texi: Update ar documentation.
* binutils/testsuite/binutils-all/ar.exp: Add thin archive tests.
* include/aout/ar.h (ARMAGT): New magic string for thin archives.
2008-03-28 06:49:44 +00:00
73de02f44b
* common.h (NT_GNU_GOLD_VERSION): Define.
2008-03-25 04:58:21 +00:00
f63cadb81a
merge from gcc
2008-03-25 01:02:08 +00:00
c01f99ec87
Bring patch correction over from gcc repository.
2008-03-25 00:21:18 +00:00
f45a832315
* md5.h: Add extern "C" when compiled with C++.
2008-03-24 23:43:26 +00:00
b00c2ef98f
* filenames.h: Add extern "C" when compiled with C++.
2008-03-21 23:40:18 +00:00
197dffcbd6
2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
...
* opcodes/s390-mkopc.c (s390_opcode_cpu_val): S390_OPCODE_Z10 added.
(s390_cond_extensions): Reduced extensions to the compare related.
(main): z10 cpu type option added.
(expandConditionalJump): Renamed to ...
(insertExpandedMnemonic): ... this.
* opcodes/s390-opc.c: Re-group the operand format makros.
(INSTR_RIE_RRPU, INSTR_RIE_RRP0, INSTR_RIE_RUPI,
INSTR_RIE_R0PI, INSTR_RIE_RUPU, INSTR_RIE_R0PU, INSTR_RIE_R0IU,
INSTR_RIE_R0I0, INSTR_RIE_R0UU, INSTR_RIE_R0U0,
INSTR_RIE_RRUUU, INSTR_RIS_RURDI, INSTR_RIS_R0RDI, INSTR_RIS_RURDU,
INSTR_RIS_R0RDU, INSTR_RRF_U0RR, INSTR_RRF_00RR, INSTR_RRS_RRRDU,
INSTR_RRS_RRRD0, INSTR_RXY_URRD, INSTR_SIY_IRD, INSTR_SIL_RDI,
INSTR_SIL_RDU): New instruction formats added.
(MASK_RIE_RRPU, MASK_RIE_RRP0, MASK_RIE_RUPI, MASK_RIE_R0PI,
MASK_RIE_RUPU, MASK_RIE_R0PU, MASK_RIE_R0IU, MASK_RIE_R0I0,
MASK_RIE_R0UU, MASK_RIE_R0U0, MASK_RIE_RRUUU, MASK_RIS_RURDI,
MASK_RIS_R0RDI, MASK_RIS_RURDU, MASK_RIS_R0RDU, MASK_RRF_U0RR,
MASK_RRF_00RR, MASK_RRS_RRRDU, MASK_RRS_RRRD0, MASK_RXY_URRD,
MASK_SIY_IRD, MASK_SIL_RDI, MASK_SIL_RDU): New instruction format
masks added.
(s390_opformats): New formats added "ris", "rrs", "sil".
* opcodes/s390-opc.txt: Add the conditional jumps with the
extensions removed from automatic expansion in s390-mkopc.c manually.
(asi - trtre): Add new System z10 EC instructions.
* include/opcode/s390.h (s390_opcode_cpu_val): S390_OPCODE_Z10 added.
2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
* config/tc-s390.c (md_parse_option): z10 option added.
2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
* gas/s390/zarch-z10.d: New file.
* gas/s390/zarch-z10.s: New file.
* gas/s390/s390.exp: Run the z10 testcases.
2008-03-19 10:29:18 +00:00
fe389b5bfa
include/elf/
...
* internal.h (Elf_Internal_Shdr): Change sh_link and sh_info from
unsigned long to unsigned int. Change sh_addralign to bfd_vma.
Order struct as for external version.
bfd/
* elf.c (_bfd_elf_make_section_from_shdr): Remove unnecessary cast.
(_bfd_elf_assign_file_position_for_section): Simplify align.
(_bfd_elf_init_reloc_shdr): Ensure shift expression wide enough
for sh_addralign.
(elf_fake_sections, swap_out_syms): Likewise.
* elflink.c (bfd_elf_final_link): Likewise.
binutils/
* readelf.c: Use %u throughout when printing sh_link or sh_info,
%lu when printing sh_addralign.
(process_version_sections): Use identical formats when printing
all offset and sh_link fields.
2008-03-13 05:27:41 +00:00
674310fb40
include/elf/
...
PR 5900
* common.h (SHN_BAD): Delete.
(SHN_LORESERVE .. SHN_HIRESERVE): Move to..
* external.h: ..here.
* internal.h (SHN_LORESERVE, SHN_HIRESERVE): Define.
(SHN_LOPROC, SHN_HIPROC, SHN_LOOS, SHN_HIOS): Define.
(SHN_ABS, SHN_COMMON, SHN_XINDEX, SHN_BAD): Define.
bfd/
PR 5900
* elf-bfd.h: Include elf/internal.h after elf/external.h.
* elfcode.h (elf_swap_symbol_in): Map reserved shndx range.
(elf_swap_symbol_out): Adjust SHN_XINDEX test.
(elf_swap_ehdr_out): Mask SHN_LORESERVE and SHN_XINDEX to values
seen in external structs.
(valid_section_index_p): Delete.
(elf_object_p): Don't increment section numbers over reserved range.
Simplify test for valid sh_link, sh_info and e_shstrndx fields.
(elf_write_shdrs_and_ehdr): Mask SHN_LORESERVE and SHN_XINDEX to values
seen in external structs. Don't increment section numbers over
reserved range.
* elf.c (bfd_elf_sym_name): Remove redundant tests on st_shndx.
(bfd_section_from_shdr): Likewise.
(group_signature): Range check before accessing elf_elfsections.
(_bfd_elf_setup_sections): Likewise.
(bfd_section_from_shdr): Likewise.
(bfd_section_from_shdr): Don't increment section number over
reserved sections.
(assign_file_positions_for_non_load_sections): Likewise.
(assign_file_positions_except_relocs): Likewise.
(_bfd_elf_write_object_contents): Likewise.
(assign_section_numbers): Likewise. Adjust for changed SHN_*.
(prep_headers): Delete unused variable.
* elflink.c (bfd_elf_link_record_local_dynamic_symbol): Adjust
for changed SHN_* values.
(check_dynsym, elf_link_input_bfd): Likewise.
(bfd_elf_final_link): Likewise. Don't skip over reserved section
range.
(elf_fixup_link_order): Check that sh_link field is valid.
* elf-hppa.h (elf_hppa_add_symbol_hook): Make "index" unsigned.
* elf32-arm.c (elf32_arm_gc_mark_extra_sections): Range check before
accesssing elf_elfsections.
* elf32-avr.c (elf32_avr_size_stubs): Likewise.
* elf32-hppa.c (elf32_hppa_size_stubs): Likewise.
* elf32-m68hc1x.c (elf32_m68hc11_size_stubs): Likewise.
* elf64-hppa.c (elf64_hppa_check_relocs): Adjust for changed
SHN_* defines. Test for SHN_BAD return from
_bfd_elf_section_from_bfd_section
binutils/
PR 5900
* readelf.c (SECTION_HEADER_INDEX, SECTION_HEADER_NUM): Delete.
Remove use throughout file.
(SECTION_HEADER): Likewise.
(dump_relocations): Don't adjust st_shndx for reserved range.
(process_file_header): Mask SHN_XINDEX to values seen in external
elf structs. Simplify valid section index tests.
(get_32bit_elf_symbols, get_64bit_elf_symbols): Mask SHN_XINDEX.
Map reserved st_shndx to internal form.
(process_section_groups): Test that group symbol st_shndx is in
range, not just non-zero. Delete reserved range check.
(get_symbol_index_type): Mask "type" to 16 bits when printing PRC,
OS or RSV.
gdb/
PR 5900
* elfread.c (elf_symtab_read): Make shndx an unsigned int.
* mipsread.c: Include elf/internal.h.
(read_alphacoff_dynamic_symtab): Map external reserved sym_shndx
to internal range.
ld/testsuite/
PR 5900
* ld-elf/sec64k.exp: Update.
2008-03-12 08:36:58 +00:00
93f73715d1
* elf/cr16c.h (SHN_CR16C_FCOMMON): Define using SHN_LORESERVE.
...
(SHN_CR16C_NCOMMON): Likewise.
* elf/hppa.h (SHN_PARISC_ANSI_COMMON): Likewise.
(SHN_PARISC_HUGE_COMMON): Likewise.
* elf/ia64.h (SHN_IA_64_ANSI_COMMON): Likewise.
(SHN_IA_64_VMS_SYMVEC): Define using SHN_LOOS.
* elf/m32r.h (SHN_M32R_SCOMMON): Define using SHN_LORESERVE.
* elf/mips.h (SHN_MIPS_ACOMMON, SHN_MIPS_TEXT): Likewise.
(SHN_MIPS_DATA, SHN_MIPS_SCOMMON, SHN_MIPS_SUNDEFINED): Likewise.
* elf/score.h (SHN_SCORE_TEXT, SHN_SCORE_DATA): Likewise.
(SHN_SCORE_SCOMMON): Likewise.
* elf/sparc.h (SHN_BEFORE, SHN_AFTER): Likewise.
* elf/v850.h (SHN_V850_SCOMMON, SHN_V850_TCOMMON): Likewise.
(SHN_V850_ZCOMMON): Likewise.
* elf/x86-64.h (SHN_X86_64_LCOMMON): Likewise.
2008-03-11 23:21:08 +00:00
3461c83a05
2008-03-09 Paul Brook <paul@codesourcery.com>
...
bfd/
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Handle new
Tag_VFP_arch values.
binutils/
* readelf.c (arm_attr_tag_VFP_arch): Add "VFPv3-D16".
gas/
* config/tc-arm.c (fpu_vfp_ext_d32): New vairable.
(parse_vfp_reg_list, encode_arm_vfp_reg): Use it.
(arm_option_cpu_value): Add vfpv3-d16, vfpv2 and vfpv3.
(aeabi_set_public_attributes): Handle Tag_VFP_arch=VFPV3-D16.
* doc/c-arm.texi: Document new ARM FPU variants.
gas/testsuite/
* gas/arm/vfpv3-d16-bad.d: New test.
* gas/arm/vfpv3-d16-bad.l: New test.
include/opcode/
* arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
2008-03-09 13:23:29 +00:00
e3bf57046b
2008-03-04 Paul Brook <paul@codesourcery.com>
...
gas/
* config/tc-arm.c (arm_ext_barrier, arm_ext_msr): New.
(arm_ext_v7m): Rename...
(arm_ext_m): ... to this. Include v6-M.
(do_t_add_sub): Allow narrow low-reg non flag setting adds.
(do_t_mrs, do_t_msr, aeabi_set_public_attributes): Use arm_ext_m.
(md_assemble): Allow wide msr instructions.
(insns): Add classifications for v6-m instructions.
(arm_cpu_option_table): Add cortex-m1.
(arm_arch_option_table): Add armv6-m.
(cpu_arch): Add ARM_ARCH_V6M. Fix numbering of other v6 variants.
gas/testsuite/
* gas/arm/archv6m.d: New test.
* gas/arm/archv6m.s: New test.
* gas/arm/t16-bad.s: Test low register non flag setting add.
* gas/arm/t16-bad.l: Update expected output.
include/opcode/
* arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
(ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
(ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
2008-03-05 01:31:26 +00:00
193b9a616d
* dwarf2.h: (enum dwarf_location_atom): Add new DW_OP,
...
DW_OP_PGI_omp_thread_num.
* dwarf.c (decode_location_expression): Handle
DW_OP_PGI_omp_thread_num.
2008-03-03 10:19:01 +00:00
fb91cb7a41
Change accreditation for patch for PR3134
2008-02-29 14:43:17 +00:00
ca504a0dee
PR 3134
...
* h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
with a 32-bit displacement but without the top bit of the 4th byte
set.
* gas/h8300/pr3134.s: New test.
* gas/h8300/pr3134.d: Expected disassembly
* gas/h8300/h8300.exp: Run the new test.
* gas/h8300/h8300-coff.exp: Fix test for COFF based ports to
accept h8300-rtemscoff not just h8300-rtems.
2008-02-27 12:33:42 +00:00
344f17f1fa
* cr16.h (cr16_num_optab): Declared.
...
* cr16-opc.c (cr16_num_optab): Defined
2008-02-18 13:46:45 +00:00
d039978069
include/
...
* bfdlink.h (struct bfd_link_hash_table): Delete creator field.
(struct bfd_link_info): Add output_bfd.
bfd/
* elflink.c: Replace all accesses to hash->creator field with
output_bfd->xvec.
* cofflink.c: Likewise.
* coff-h8300.c: Likewise.
* ecoff.c: Likewise.
* elf32-m68hc1x.c: Likewise.
* elf32-ppc.c: Likewise.
* elf64-alpha.c: Likewise.
* elf64-ppc.c: Likewise.
* elf64-sparc.c: Likewise.
* elfxx-mips.c: Likewise.
* i386linux.c: Likewise.
* m68klinux.c: Likewise.
* sparclinux.c: Likewise.
* sunos.c: Likewise.
* xcofflink.c: Likewise.
* linker.c: Likewise.
(_bfd_link_hash_table_init): Don't store creator.
ld/
* ldmain.h (output_bfd): Delete.
* ldmain.c (output_bfd): Delete.
Replace all occurrences of output_bfd with link_info.output_bfd.
* ldcref.c: Likewise.
* ldctor.c: Likewise.
* ldemul.c: Likewise.
* ldexp.c: Likewise.
* ldfile.c: Likewise.
* ldlang.c: Likewise.
* ldmisc.c: Likewise.
* ldwrite.c: Likewise.
* pe-dll.c: Likewise.
* emultempl/aix.em: Likewise.
* emultempl/alphaelf.em: Likewise.
* emultempl/armcoff.em: Likewise.
* emultempl/armelf.em: Likewise.
* emultempl/avrelf.em: Likewise.
* emultempl/beos.em: Likewise.
* emultempl/elf-generic.em: Likewise.
* emultempl/elf32.em: Likewise.
* emultempl/gld960.em: Likewise.
* emultempl/hppaelf.em: Likewise.
* emultempl/irix.em: Likewise.
* emultempl/linux.em: Likewise.
* emultempl/lnk960.em: Likewise.
* emultempl/m68hc1xelf.em: Likewise.
* emultempl/mmix-elfnmmo.em: Likewise.
* emultempl/mmo.em: Likewise.
* emultempl/pe.em: Likewise.
* emultempl/pep.em: Likewise.
* emultempl/ppc32elf.em: Likewise.
* emultempl/ppc64elf.em: Likewise.
* emultempl/scoreelf.em: Likewise.
* emultempl/sh64elf.em: Likewise.
* emultempl/spuelf.em: Likewise.
* emultempl/sunos.em: Likewise.
* emultempl/vanilla.em: Likewise.
* emultempl/vxworks.em: Likewise.
* emultempl/xtensaelf.em: Likewise.
* emultempl/z80.em: Likewise.
* ldlang.c (open_output): Don't return output, instead write
link_info_output_bfd directly.
* emultempl/alphaelf.em: Replace occurrences of link_info.hash->creator
with link_info.output_bfd->xvec.
* emultempl/hppaelf.em: Likewise.
* emultempl/ppc32elf.em: Likewise.
* emultempl/ppc64elf.em: Likewise.
* emultempl/spuelf.em: Likewise.
2008-02-15 03:35:51 +00:00
f16db7f54e
PR gas/2626
...
* avr.h (AVR_ISA_2xxe): Define.
* config/tc-avr.c (mcu_types): Change the ISA tyoe of the attiny26
to AVR_ISA_2xxe.
(avr_operand): Disallow post-increment addressing in the lpm
instruction for the attiny26.
2008-02-14 13:04:29 +00:00
001e850653
* xtensa-config.h (XCHAL_HAVE_THREADPTR): Redefine to zero.
...
(XCHAL_NUM_AREGS, XCHAL_MAX_INSTRUCTION_SIZE): New.
2008-02-11 17:53:04 +00:00
58d470721b
* mips.h: Update copyright.
...
(INSN_CHIP_MASK): New macro.
(INSN_OCTEON): New macro.
(CPU_OCTEON): New macro.
(OPCODE_IS_MEMBER): Handle Octeon instructions.
2008-02-04 19:25:05 +00:00
ce4a642382
* mips.h: Update copyright.
...
(E_MIPS_MACH_OCTEON): New macro.
2008-02-04 19:21:25 +00:00
f022e6b98e
Add OpenVMS extensions.
...
* ia64.h (SHF_IA_64_VMS_GLOBAL, SHF_IA_64_VMS_OVERLAID)
(SHF_IA_64_VMS_SHARED, SHF_IA_64_VMS_VECTOR)
(SHF_IA_64_VMS_ALLOC_64BIT, SHF_IA_64_VMS_PROTECTED)
(SHT_IA_64_VMS_TRACE, SHT_IA_64_VMS_TIE_SIGNATURES)
(SHT_IA_64_VMS_DEBUG, SHT_IA_64_VMS_DEBUG_STR)
(SHT_IA_64_VMS_LINKAGES, SHT_IA_64_VMS_SYMBOL_VECTOR)
(SHT_IA_64_VMS_FIXUP, DT_IA_64_VMS_SUBTYPE)
(DT_IA_64_VMS_IMGIOCNT, DT_IA_64_VMS_LNKFLAGS)
(DT_IA_64_VMS_VIR_MEM_BLK_SIZ, DT_IA_64_VMS_IDENT)
(DT_IA_64_VMS_NEEDED_IDENT, DT_IA_64_VMS_IMG_RELA_CNT)
(DT_IA_64_VMS_SEG_RELA_CNT, DT_IA_64_VMS_FIXUP_RELA_CNT)
(DT_IA_64_VMS_FIXUP_NEEDED, DT_IA_64_VMS_SYMVEC_CNT)
(DT_IA_64_VMS_XLATED, DT_IA_64_VMS_STACKSIZE)
(DT_IA_64_VMS_UNWINDSZ, DT_IA_64_VMS_UNWIND_CODSEG)
(DT_IA_64_VMS_UNWIND_INFOSEG, DT_IA_64_VMS_LINKTIME)
(DT_IA_64_VMS_SEG_NO, DT_IA_64_VMS_SYMVEC_OFFSET)
(DT_IA_64_VMS_SYMVEC_SEG, DT_IA_64_VMS_UNWIND_OFFSET)
(DT_IA_64_VMS_UNWIND_SEG, DT_IA_64_VMS_STRTAB_OFFSET)
(DT_IA_64_VMS_SYSVER_OFFSET, DT_IA_64_VMS_IMG_RELA_OFF)
(DT_IA_64_VMS_SEG_RELA_OFF, DT_IA_64_VMS_FIXUP_RELA_OFF)
(DT_IA_64_VMS_PLTGOT_OFFSET, DT_IA_64_VMS_PLTGOT_SEG)
(DT_IA_64_VMS_FPMODE, SHN_IA_64_VMS_SYMVEC): Define
* readelf.c (dump_relocations): Decode OpenVMS-specific sections.
(get_ia64_dynamic_type): Decode OpenVMS-specific tags.
(get_dynamic_type): Handle IA64-specific tags.
(get_ia64_section_type_name): Handle OpenVMS-specific sections.
(get_section_type_name): Handle OS-specific sections (and
particularly IA64 OpenVMS one).
(get_elf_section_flags): Makes flags static. Add entries for IA64 and
decode them.
2008-01-30 10:37:43 +00:00
a665fef641
include/
...
2008-01-26 David Daney <ddaney@avtrex.com>
* demangle.h (demangle_component_type): Add
DEMANGLE_COMPONENT_JAVA_RESOURCE,
DEMANGLE_COMPONENT_COMPOUND_NAME, and
DEMANGLE_COMPONENT_CHARACTER as new enum values.
(demangle_component): Add struct s_character to union u.
libiberty/
2008-01-26 David Daney <ddaney@avtrex.com>
* cp-demangle.c (d_dump): Handle DEMANGLE_COMPONENT_JAVA_RESOURCE,
DEMANGLE_COMPONENT_COMPOUND_NAME, and
DEMANGLE_COMPONENT_CHARACTER cases.
(d_make_comp): Handle DEMANGLE_COMPONENT_COMPOUND_NAME and
DEMANGLE_COMPONENT_JAVA_RESOURCE cases.
(d_make_character): New function.
(d_java_resource): Same.
(d_special_name): Handle "Gr" case.
(d_print_comp): Handle DEMANGLE_COMPONENT_JAVA_RESOURCE,
DEMANGLE_COMPONENT_COMPOUND_NAME, and
DEMANGLE_COMPONENT_CHARACTER cases.
* testsuite/demangle-expected: Add test for java resource name
mangling.
2008-01-27 06:25:45 +00:00
4be948a34a
/gas:
...
2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
* config/tc-avr.c (mcu_types): Change opcode set for at86rf401.
/include:
2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
* opcode/avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
2008-01-23 17:36:23 +00:00
60308c48f2
* common.h (AT_SUN_AUXFLAGS): Define.
2008-01-16 22:01:42 +00:00
c7b8bedfb2
/gas:
...
2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
* config/tc-avr.c (mcu_types): Change opcode set for avr3,
at90usb82, at90usb162.
* doc/c-avr.texi: Change architecture grouping for at90usb82,
at90usb162.
These changes support the new avr35 architecture group in gcc.
/include:
2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
* opcode/avr.h (AVR_ISA_USB162): Add new opcode set.
(AVR_ISA_AVR3): Likewise.
2008-01-16 17:59:07 +00:00
2dba9eb2d4
Updated copyright notices for most files.
2008-01-01 22:53:22 +00:00
fb09a73e93
* dwarf2.h (DW_AT_hi_user): Correct value.
2007-12-11 12:56:21 +00:00
1995e606d8
2007-12-07 Bob Wilson <bob.wilson@acm.org>
...
include/elf/
* xtensa.h (R_XTENSA_32_PCREL): New.
bfd/
* elf32-xtensa.c (elf_howto_table): Add R_XTENSA_32_PCREL.
(elf_xtensa_reloc_type_lookup): Handle BFD_RELOC_32_PCREL.
(elf_xtensa_check_relocs): Use default case for all relocations that
need nothing done here.
(elf_xtensa_do_reloc): Compute self_address for all relocation types.
Handle R_XTENSA_32_PCREL.
(elf_xtensa_relocate_section): Check for R_XTENSA_32_PCREL for dynamic
symbols.
(check_section_ebb_pcrels_fit): Ignore R_XTENSA_32_PCREL relocations.
gas/
* config/tc-xtensa.c (O_pcrel): Define.
(suffix_relocs): Add pcrel suffix.
(md_pseudo_table): Add 4byte and 2byte directives.
(xtensa_elf_cons): Pass correct pcrel argument to fix_new_exp.
(xg_assemble_literal): Likewise. Check for O_pcrel.
(expression_maybe_register): Reorganize. Handle BFD_RELOC_32_PCREL.
(xg_valid_literal_expression): Allow O_pcrel.
(md_pcrel_from, md_apply_fix): Handle BFD_RELOC_32_PCREL.
(tc_gen_reloc): Fix punctuation in error message.
gas/testsuite/
* gas/xtensa/all.exp: Run new pcrel test.
* gas/xtensa/err-pcrel.s: New.
* gas/xtensa/pcrel.d: New.
* gas/xtensa/pcrel.s: New.
* gas/xtensa/xtensa-err.exp: New.
2007-12-07 22:52:08 +00:00
47c9864a0a
bfd/
...
* archures.c (bfd_mach_mips_loongson_2e): New.
(bfd_mach_mips_loongson_2f): New.
* bfd-in2.h (bfd_mach_mips_loongson_2e): New.
(bfd_mach_mips_loongson_2f): New.
* cpu-mips.c: Add I_loongson_2e and I_loongson_2f to
anonymous enum.
(arch_info_struct): Add Loongson-2E and Loongson-2F entries.
* elfxx-mips.c (_bfd_elf_mips_mach): Handle Loongson-2E
and Loongson-2F flags.
(mips_set_isa_flags): Likewise.
(mips_mach_extensions): Add Loongson-2E and Loongson-2F
entries.
binutils/
* readelf.c (get_machine_flags): Handle Loongson-2E and -2F
flags.
gas/
* config/tc-mips.c (mips_cpu_info_table): Add loongson2e
and loongson2f entries.
* doc/c-mips.texi: Document -march=loongson{2e,2f} options.
gas/testsuite/
* gas/mips/mips.exp: Add loongson-2e and -2f tests.
* gas/mips/loongson-2e.d: New.
* gas/mips/loongson-2e.s: New.
* gas/mips/loongson-2f.d: New.
* gas/mips/loongson-2f.s: New.
include/elf/
* mips.h (E_MIPS_MACH_LS2E): New.
(E_MIPS_MACH_LS2F): New.
include/opcode/
* mips.h (INSN_LOONGSON_2E): New.
(INSN_LOONGSON_2F): New.
(CPU_LOONGSON_2E): New.
(CPU_LOONGSON_2F): New.
(OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
opcodes/
* mips-dis.c (mips_arch_choices): Add Loongson-2E and -2F
entries.
* mips-opc.c (IL2E): New.
(IL2F): New.
(mips_builtin_opcodes): Add Loongson-2E and -2F instructions.
Allow movz and movn for Loongson-2E and -2F. Add movnz entry.
Move coprocessor encodings to the end of the table. Allow
certain MIPS V .ps instructions on the Loongson-2E and -2F.
2007-11-29 12:23:44 +00:00
35e137475d
include/opcode/
...
* mips.h (INSN_ISA*): Redefine certain values as an
enumeration. Update comments.
(mips_isa_table): New.
(ISA_MIPS*): Redefine to match enumeration.
(OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
values.
opcodes/
* mips-opc.c (I3_32, I3_33, I4_32, I4_33, I5_33): New.
(mips_builtin_opcodes): Use these new I* values.
2007-11-29 11:55:19 +00:00
02cb1fd853
* internal.h (ELF_IS_SECTION_IN_SEGMENT): Adjust to cope with
...
segments at the end of memory.
2007-11-28 13:53:05 +00:00
91f2f75ac8
[ld/testsuite/ChangeLog]
...
* ld-mips-elf/attr-gnu-4-14.d, ld-mips-elf/attr-gnu-4-41.d:
Adjust warning message for -mfp64 flag.
* ld-mips-elf/attr-gnu-4-5.s, ld-mips-elf/attr-gnu-4-04.d,
ld-mips-elf/attr-gnu-4-51.d, ld-mips-elf/attr-gnu-4-05.d,
ld-mips-elf/attr-gnu-4-15.d, ld-mips-elf/attr-gnu-4-24.d,
ld-mips-elf/attr-gnu-4-25.d, ld-mips-elf/attr-gnu-4-34.d,
ld-mips-elf/attr-gnu-4-35.d, ld-mips-elf/attr-gnu-4-42.d,
ld-mips-elf/attr-gnu-4-43.d, ld-mips-elf/attr-gnu-4-44.d,
ld-mips-elf/attr-gnu-4-45.d, ld-mips-elf/attr-gnu-4-40.d,
ld-mips-elf/attr-gnu-4-14.d: New testcases files.
* ld-mips-elf/mips-elf.exp: Run new testcases.
[binutils/ChangeLog]
* readelf.c (display_mips_gnu_attribute): Recognize -mips32r2 -mfp64
objects.
[include/ChangeLog]
* elf/mips.h (Tag_GNU_MIPS_ABI_FP): Mention -mips32r2 -mfp64 variant
in comment.
[bfd/ChangeLog]
* elfxx-mips.c (mips_elf_merge_obj_attributes): Handle -mips32r2
-mfp64 attribute.
[gas/ChangeLog]
* doc/as.texinfo: Document the new attribute value.
2007-11-17 13:38:57 +00:00
3c48ef66da
* dwarf2.h: Mention the location of the DWARF3 spec on the web.
...
(DW_AT_stride_size): Rename to DW_AT_bit_stride.
(DW_AT_stride): Rename to DW_AT_byte_stride.
* dwarf.c (process_extended_line_op): Add cases for HP extensions to the line ops.
Mention if an unknown op code is in the user defined range.
(decode_location_expression): Add cases for HP extensions, the DW_OP_GNU_uninit extension and the DW_OP_call_frame_cfa and DW_OP_bit_piece DWARF3 operators.
(read_and_display_attr): Correct list of attributes which can reference a location list.
(read_and_display_attr_value): Add cases for DWARF3 values and HP extensions.
Correct list of attributes which can reference a location list.
(get_AT_name): Add cases for DWARF3 values and HP and PGI extensions.
2007-11-16 15:36:21 +00:00
75a1688a39
include/elf/
...
* vxworks.h: New.
bfd/
* elf-vxworks.h (elf_vxworks_add_dynamic_entries): Declare.
(elf_vxworks_finish_dynamic_entry): Declare.
* elf-vxworks.c: Include elf/vxworks.h.
(elf_vxworks_add_dynamic_entries): New.
(elf_vxworks_finish_dynamic_entry): New.
* Makefile.am (elf-vxworks.lo): Add dependency.
* Makefile.in (elf-vxworks.lo): Add dependency.
* elf32-i386.c (elf_i386_size_dynamic_sections,
elf_i386_finish_dynamic_sections): Call
elf_vxworks_add_dynamic_entries and
elf_vxworks_finish_dynamic_entry.
* elf32-ppc.c (ppc_elf_size_dynamic_sections,
ppc_elf_finish_dynamic_sections): Likewise.
* elfxx-sparc.c (_bfd_sparc_elf_size_dynamic_sections,
sparc_finish_dyn): Likewise.
* elf32-sh.c (sh_elf_size_dynamic_sections,
sh_elf_finish_dynamic_sections): Likewise.
* elfxx-mips.c (_bfd_mips_elf_size_dynamic_sections,
_bfd_mips_elf_finish_dynamic_sections): Likewise.
* elf32-arm.c (elf32_arm_size_dynamic_sections,
elf32_arm_finish_dynamic_sections): Likewise.
ld/
* ld-vxworks/tls-2.d: New.
* ld-vxworks/tls-2.s: New.
2007-11-08 13:51:07 +00:00
33e178064d
include:
...
2007-11-07 Joseph Myers <joseph@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
* floatformat.h (struct floatformat): Add split_half field.
(floatformat_ibm_long_double): New.
libiberty:
2007-11-07 Joseph Myers <joseph@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
* floatformat.c (mant_bits_set): New.
(floatformat_to_double): Use it. Note no special handling of
split formats.
(floatformat_from_double): Note no special handing of split
formats.
(floatformat_ibm_long_double_is_valid,
floatformat_ibm_long_double): New.
(floatformat_ieee_single_big, floatformat_ieee_single_little,
floatformat_ieee_double_big, floatformat_ieee_double_little,
floatformat_ieee_double_littlebyte_bigword, floatformat_vax_f,
floatformat_vax_d, floatformat_vax_g, floatformat_i387_ext,
floatformat_m68881_ext, floatformat_i960_ext,
floatformat_m88110_ext, floatformat_m88110_harris_ext,
floatformat_arm_ext_big, floatformat_arm_ext_littlebyte_bigword,
floatformat_ia64_spill_big, floatformat_ia64_spill_little,
floatformat_ia64_quad_big, floatformat_ia64_quad_little): Update
for addition of split_half field.
gdb:
2007-11-07 Joseph Myers <joseph@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
* gdbtypes.c (floatformats_ibm_long_double): New.
* gdbtypes.h (floatformats_ibm_long_double): Declare.
* ia64-tdep.c (floatformat_ia64_ext): Update for addition of
split_half field.
* mips-tdep.c (n32n64_floatformat_always_valid,
floatformat_n32n64_long_double_big, floatformats_n32n64_long):
Remove.
(mips_gdbarch_init): Use floatformats_ibm_long_double instead of
floatformats_n32n64_long.
* ppc-linux-tdep.c (ppc_linux_init_abi): Use 128-bit IBM long
double.
* doublest.c (convert_floatformat_to_doublest,
convert_doublest_to_floatformat): Handle split floating-point
formats.
* ppc-sysv-tdep.c (ppc_sysv_abi_push_dummy_call): Handle IBM long
double arguments.
(ppc64_sysv_abi_push_dummy_call): Likewise.
(do_ppc_sysv_return_value): Handle IBM long double return.
2007-11-08 00:08:48 +00:00
026d54aa23
include
...
* coff/pe.h (COFF_ENCODE_ALIGNMENT) Define.
gas
* read.c (ALIGN_LIMIT): Rename to ...
(TC_ALIGN_LIMIT): Guard against prior definition.
* config/tc-i386.h (TC_ALIGN_LIMIT)[TE_PE]: Define.
bfd
* pe-i386.c (COFF_SECTION_ALIGNMENT_ENTRIES): Let .data, .text
and .bss section use the default.
* pei-i386.c (COFF_SECTION_ALIGNMENT_ENTRIES): Likewise.
ld/testsuite
* ld-scripts/align.exp: Enable for PECOFF.
* ld-scripts/alignof.exp: Likewise.
2007-11-04 23:49:08 +00:00
3ce8215a01
* mn10300.h (R_MN10300_ALIGN): Define.
...
* reloc.c (BFD_RELOC_MN10300_ALIGN): Add.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf-m10300.h: Handle R_MN10300_ALIGN relocs.
* mn10300_elf_relax_delete_bytes): Honour R_MN10300_ALIGN relocs.
Re-fix off by one error in comparisons.
* config/tc-mn10300.c (tc_gen_reloc): Fix test that decides when
sym_diff relocs should be generated.
(md_apply_fix): Skip R_MN10300_ALIGN relocs.
(mn10300_fix_adjustable): Do not adjust R_MN10300_ALIGN relocs.
(mn10300_handle_align): New function. Generate R_MN10300_ALIGN
relocs to record alignment requests.
* config/tc-mn10300.h (TC_FORCE_RELOCATION_SUB_SAME): Also force
R_MN10300_ALIGN relocs.
(HANDLE_ALIGN): Define. Call mn10300_handle_align.
* gas/all/gas.exp: Do not run diff1.s test for mn10300.
* ld-mn10300/mn10300.exp: Run new tests. Skip i126256 test if
a compiler is not available.
* ld-mn10300/i112045-3.s: New test.
* ld-mn10300/i112045-3.d: Expected disassembly.
* ld-mn10300/i135409.s: Rename to i135409-1.s.
* ld-mn10300/i135409.d: Rename to i135409-1.d
* ld-mn10300/i135409-2.s: New test.
* ld-mn10300/i135409-2.d: Expected symbol table.
* ld-mn10300/i36434.d: Adjust expected disassembly.
2007-10-30 15:18:29 +00:00
2b50cd503e
* elf32-ppc.c (ppc_elf_merge_obj_attributes): Add support for
...
Tag_GNU_Power_ABI_Vector.
* readelf.c (display_power_gnu_attribute): Add support for
Tag_GNU_Power_ABI_Vector.
* ppc.h (Tag_GNU_Power_ABI_Vector): New.
* ld-powerpc/attr-gnu-8-1.s, ld-powerpc/attr-gnu-8-11.d,
ld-powerpc/attr-gnu-8-2.s, ld-powerpc/attr-gnu-8-23.d,
ld-powerpc/attr-gnu-8-3.s, ld-powerpc/attr-gnu-8-31.d: New.
* ld-powerpc/powerpc.exp: Run new tests.
2007-10-25 15:20:24 +00:00
873e6f9d97
Add MN10300 linker relaxation support for symbol differences
2007-10-19 17:31:31 +00:00
ffa1a46abd
.
2007-10-18 09:57:07 +00:00
5565177f97
2007-10-18 Roland McGrath <roland@redhat.com>
...
* common.h (NT_PPC_VMX): New macro.
2007-10-18 09:57:04 +00:00
dd52035079
* NEWS: Document target described register support for PowerPC.
...
* ppc-tdep.h: Remove ppc_spr constants.
(struct gdbarch_tdep): Remove regs, ppc_sr0_regnum, and
ppc_builtin_type_vec128 members.
(PPC_R0_REGNUM, PPC_F0_REGNUM, PPC_PC_REGNUM, PPC_MSR_REGNUM)
(PPC_CR_REGNUM, PPC_LR_REGNUM, PPC_CTR_REGNUM, PPC_XER_REGNUM)
(PPC_FPSCR_REGNUM, PPC_MQ_REGNUM, PPC_SPE_UPPER_GP0_REGNUM)
(PPC_SPE_ACC_REGNUM, PPC_SPE_FSCR_REGNUM, PPC_VR0_REGNUM)
(PPC_VSCR_REGNUM, PPC_VRSAVE_REGNUM, PPC_NUM_REGS): New constants.
* rs6000-tdep.c: Include preparsed descriptions.
(init_sim_regno_table): Do not iterate over pseudo registers.
Look up segment registers by name. Use sim_spr_register_name
for SPRs.
(rs6000_register_sim_regno): Call init_sim_regno_table here.
(rs6000_builtin_type_vec128): Delete.
(rs6000_register_name): Only handle SPE pseudo registers and upper
halves. Call tdesc_register_name for everything else.
(rs6000_register_type): Delete. Replace with...
(rs6000_pseudo_register_type): ...this new function. Only handle
SPE pseudo registers.
(rs6000_register_reggroup_p): Delete. Replace with...
(rs6000_pseudo_register_reggroup_p): ...this new function. Only
handle SPE pseudo registers.
(rs6000_convert_register_p): Use ppc_fp0_regnum instead of
"struct reg".
(rs6000_register_to_value, rs6000_value_to_register): Remove check
of reg->fpr.
(e500_register_reggroup_p): Delete.
(STR, R, R4, R8, R16, F, P8, R32, R64, R0, A4, S, S4, SN4, S64)
(COMMON_UISA_REGS, PPC_UISA_SPRS, PPC_UISA_NOFP_SPRS)
(PPC_SEGMENT_REGS, PPC_OEA_SPRS, PPC_ALTIVEC_REGS, PPC_SPE_GP_REGS)
(PPC_SPE_UPPER_GP_REGS, PPC_EV_PSEUDO_REGS): Delete macros.
(registers_powerpc, registers_403, registers_403GC, registers_505)
(registers_860, registers_601, registers_602, registers_603)
(registers_604, registers_750, registers_7400, registers_e500): Delete
variables.
(struct variant): Delete nregs, npregs, num_tot_regs, and regs. Add
tdesc.
(tot_num_registers, num_registers, num_pseudo_registers): Delete.
(variants): Delete outdated comment. Use standard target descriptions
instead of "struct reg" arrays.
(init_variants): Delete.
(rs6000_gdbarch_init): Do not guess word size from the BFD
architecture if we have a target description. Select a variant
before creating a new architecture. Use the variant's target
description if the target did not define a register layout.
Validate target-supplied registers. Reject mismatches. Use
fixed register numbers and new constants instead of magic
numbers. Call set_gdbarch_ps_regnum. Call tdesc_use_registers.
(_initialize_rs6000_tdep): Initialize the preparsed target
descriptions.
* target-descriptions.c (tdesc_predefined_types): Add int128 and
uint128.
(tdesc_find_register_early): New function.
(tdesc_numbered_register): Use it.
(tdesc_register_size): New function.
(tdesc_use_registers): Take a target_desc argument. Do not use
gdbarch_target_desc.
* target-descriptions.h (tdesc_use_registers): Update prototype
and comment.
(tdesc_register_size): New prototype.
* Makefile.in (powerpc_32_c, powerpc_403_c, powerpc_403gc_c)
(powerpc_505_c, powerpc_601_c, powerpc_602_c, powerpc_603_c)
(powerpc_604_c, powerpc_64_c, powerpc_7400_c, powerpc_750_c)
(powerpc_860_c, powerpc_e500_c, rs6000_c): New macros.
(rs6000-tdep.o): Update.
* arm-tdep.c (arm_gdbarch_init): Update call to tdesc_use_registers.
* m68k-tdep.c (m68k_gdbarch_init): Likewise.
* mips-tdep.c (mips_gdbarch_init): Likewise.
* gdb.texinfo (Predefined Target Types): Add int128
and uint128.
(Standard Target Features): Add PowerPC features.
* gdb.xml/tdesc-regs.exp: Add PowerPC support.
* sim-ppc.h (sim_spr_register_name): New prototype.
* gdb-sim.c (regnum2spr): Rename to...
(sim_spr_register_name): ... this. Make global.
2007-10-15 19:45:31 +00:00
David S. Miller
Nick Clifton
Alan Modra
Andreas Krebbel
Swami Reddy M R
H.J. Lu
Eric Weddington
Ian Lance Taylor
DJ Delorie
Paul Brook
Bob Wilson
Adam Nemet
David Daney
Mark Kettenis
Daniel Jacobowitz
Mark Shinwell
Nathan Sidwell
Thiemo Seufer
Joseph Myers
Danny Smith
Roland McGrath