Allow exceptions to be nested, which is especially useful with urgent
interrupts while processing an exception.
The implementation counts up the nesting level with each call to an
exception. In the outer exception (level 1), the exception stack is
started. All nested exceptions just reserve the redzone (scratch
memory that may be used by compiler) and exception context on the
stack, but then process on the same scratch.
Restriction: Impure pointers are shared among all exceptions. This may
be solved by creating an impure data structure in the stack frame with
each nested exception.
* or1k/crt0.S: Add exception nesting
* or1k/exceptions-asm.S: ditto
* or1k/util.c: ditto
- With the gzll kernel we have two different loading options:
- If the image is loaded to the global memory, the bootstrapping
loads the kernel to local memory. Applications are loaded on
demand. The heap then starts right after bss.
- If the image is pre-loaded to the local memory it includes the
application binaries right after bss. The heap then starts after
the application objects.
- We can check if this is a gzll kernel as it has the string "gzll" at
0x2000. At 0x200c we then find the end of the application objects in
the image. If there is no global memory we set _or1k_heap_start to
this value.
* or1k/boards/optimsoc.S: Heap for gzll kernel
- Previously the heap started right after the bss section. This can now
be configured by changing the _or1k_heap_start symbol that defaults to
the old value (&end). In board_init_early, we can now set this to
another value.
* or1k/sbrk.c: Allow for different heap start
- Store the exception program counter (from EPCR) and exception status
register (from ESR) also during the exception. A runtime system may
replace them thereby to implement a thread switch.
* or1k/exception-asm.S: Store missing state
- We do not need a red zone here, as we do not operate on the current
stack, but always use the clear exception stack. Also reserve two
extra words for the context to store EPCR and ESR.
* or1k/crt0.S: Fix exception stack frame
* or1k/exception-asm.S: ditto
- During interrupt handling the PICSR, table pointers and current
interrupt line have been saved in incorrect registers and/or stored on
the stack.
- Save the pointer in r16/r18, PICSR in r20 and the current interrupt
line in r22. Those are callee-saved registers, so that the register
values will be preserved.
* or1k/interruts-asm.S: Change registers to callee-saved.
* msp430/msp430-sim.ld (.stack): Add an assertion to make sure
that the data area does not overrun the stack. PROVIDE a new
symbol __stack_size to allow the user to set the limit.
* msp430/msp430xl-sim.ld (.stack): Likewise.
* rl78/rl78-sim.ld (.stack): Likewise.
* rl78/rl78.ld (.stack): Likewise.
* rx/rx-sim.ld (.stack): Likewise.
* rx/rx.ld (.stack): Likewise.
* msp430/msp430.ld: Delete.
* msp430/msp430F5438A-l.ld: Delete.
* msp430/msp430F5438A-s.ld: Delete.
* msp430/crt_movedata.S: Delete.
* msp430/Makefile.in (SCRIPTS): Remove msp430.ld.
(CRT_OBJS): Add crt_move_highdata.o.
* msp430/memmodel.h (START_CRT_FUNC): New macro.
(END_CRT_FUNC): New macro.
(WEAK_DEF): New macro.
* msp430/crt0.S: Use new macros.
(move_highdata): New code to initialise the .data section if it is
held in high memory.
* msp430/msp430-sim.ld (.data): Add .either.data.
(.rodata2): Move some read-only data sections here.
(.text): Add .either.text.
(.rodata): Add .either.rodata.
(.bss): Add .either.bss.
* msp430/msp430xl-sim.ld (MEMORY): Add HIROM.
(.rodata2): Move some read-only data sections here.
(.upper.data): New section. Include notes about how to initialise
it.
This header was clearly copied from the common syscall.h and customized,
but the header comment is no longer accurate -- this isn't the general
file anymore.
* or1k/Makefile.in: Build and install board libraries
* or1k/board.h: New file
* or1k/boards/README: New file
* or1k/boards/atlys.S: New file
* or1k/boards/de0_nano.S: New file
* or1k/boards/ml501.S: New file
* or1k/boards/ml509.S: New file
* or1k/boards/optimsoc.S: New file
* or1k/boards/or1ksim-uart.S: New file
* or1k/boards/or1ksim.S: New file
* or1k/boards/ordb1a3pe1500.S: New file
* or1k/boards/ordb2a.S: New file
* or1k/boards/orpsocrefdesign.S: New file
* or1k/boards/tmpl.S: New file
* or1k/boards/tmpl.c: New file
* or1k/Makefile.in: Add libor1k
* or1k/README: New file
* or1k/caches-asm.S: New file
* or1k/exceptions-asm.S: New file
* or1k/exceptions.c: New file
* or1k/impure.c: New file
* or1k/include/or1k-nop.h: New file
* or1k/include/or1k-support.h: New file
* or1k/interrupts-asm.S: New file
* or1k/interrupts.c: New file
* or1k/mmu-asm.S: New file
* or1k/or1k-internals.h: New file
* or1k/or1k_uart.c: New file
* or1k/or1k_uart.h: New file
* or1k/outbyte.S: New file
* or1k/sbrk.c: New file
* or1k/sync-asm.S: New file
* or1k/syscalls.c: New file
* or1k/timer.c: New file
* or1k/util.c: New file
Remove FPU availability check, just use the pre-processor flags
to indicicate what the user wanted.
* mips/abiflags.S: New file.
* mips/regs.S (SR_MSA): Define macro.
* mips/mti32.ld: Place .MIPS.abiflags and wrap in marker symbols.
* mips/mti64.ld: Likewise.
* mips/mti64_64.ld: Likewise.
* mips/mti64_n32.ld: Likewise.
* mips/crt0.S: Remove .set noreorder throughout.
(zerobss): Open code the bltu macro instruction so that the
zero-loop does not have a NOP in the branch delay slot.
* msp430/crt0.S (high_bss): Add.
* msp430/msp430-sim.ld: Add error message if .upper sections are
detected.
* msp430/msp430xl-sim.ld (MEMORY): Adjust to better mimic real
life MCUs. Add support for upper and lower sections.
