* elf32-xtensa.c (extend_ebb_bounds_forward): Use renamed
XTENSA_PROP_NO_TRANSFORM flag instead of XTENSA_PROP_INSN_NO_TRANSFORM.
(extend_ebb_bounds_backward, compute_text_actions): Likewise.
(compute_ebb_proposed_actions, coalesce_shared_literal): Likewise.
(xtensa_get_property_predef_flags): Likewise.
(compute_removed_literals): Pass new arguments to is_removable_literal.
(is_removable_literal): Add sec, prop_table and ptblsize arguments.
Do not remove literal if the NO_TRANSFORM property flag is set.
gas/
* config/tc-xtensa.c (XTENSA_PROP_INSN_NO_TRANSFORM): Renamed to...
(XTENSA_PROP_NO_TRANSFORM): ...this.
(frag_flags_struct): Move is_no_transform out of the insn sub-struct.
(xtensa_mark_frags_for_org): New.
(xtensa_handle_align): Set RELAX_ORG frag subtype for rs_org.
(xtensa_post_relax_hook): Call xtensa_mark_frags_for_org.
(get_frag_property_flags): Adjust reference to is_no_transform flag.
(xtensa_frag_flags_combinable): Likewise.
(frag_flags_to_number): Likewise. Use XTENSA_PROP_NO_TRANSFORM.
* config/tc-xtensa.h (xtensa_relax_statesE): Add RELAX_ORG.
include/elf/
* xtensa.h (XTENSA_PROP_INSN_NO_TRANSFORM): Renamed to...
(XTENSA_PROP_NO_TRANSFORM): ...this.
ld/
* emultempl/xtensaelf.em (replace_insn_sec_with_prop_sec): Use renamed
XTENSA_PROP_NO_TRANSFORM flag instead of XTENSA_PROP_INSN_NO_TRANSFORM.
* spu.h (R_SPU_PPU32, R_SPU_PPU64): Define.
bfd/
* reloc.c (BFD_RELOC_SPU_PPU32, BFD_RELOC_SPU_PPU64): Define.
* elf-bfd.h (struct elf_backend_data): Change return type of
elf_backend_relocate_section to int.
* elf32-spu.c (elf_howto_table): Add howtos for R_SPU_PPU32 and
R_SPU_PPU64.
(spu_elf_bfd_to_reloc_type): Convert new relocs.
(spu_elf_count_relocs): New function.
(elf_backend_count_relocs): Define.
(spu_elf_relocate_section): Arrange to emit R_SPU_PPU32 and
R_SPU_PPU64 relocs.
* elflink.c (elf_link_input_bfd): Emit relocs if relocate_section
returns 2.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-spu.c (md_pseudo_table): Add int, long, quad. Call
spu_cons for word.
(md_assemble): Tidy use of insn.flag.
(get_imm): Likewise. Handle uppercase input too.
(spu_cons): New function.
* config/tc-spu.h (tc_fix_adjustable): Don't adjust SPU_PPU relocs.
(TC_FORCE_RELOCATION): Don't resolve them either.
binutils/
* embedspu.sh (find_prog): Prefer prog in same dir as embedspu
over one found on the users path.
(main): Generate .reloc for each R_SPU_PPU* reloc.
* internal.h (ELF_IS_SECTION_IN_SEGMENT): Check both file offset
and vma for appropriate sections.
bfd/
* elf.c (assign_file_positions_for_load_sections): Set sh_offset
here. Set sh_type to SHT_NOBITS if we won't be allocating
file space. Don't bump p_memsz for non-alloc sections. Adjust
section-in-segment check.
(assign_file_positions_for_non_load_sections): Don't set sh_offset
here for sections that have already been handled above.
surprisingly) the value isn't really being used anywhere, henc no other
changes are needed.
include/elf/
2007-04-26 Jan Beulich <jbeulich@novell.com>
* common.h (DT_ENCODING): Correct value (back to spec mandated
value).
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
* config/tc-i386.h (Seg2ShortForm, Seg3ShortForm): Delete.
* config/tc-i386.c: Wrap overly long lines, whitespace fixes.
(process_operands): Move old Seg2ShortForm and Seg3ShortForm
code, and test for these insns using a combination of
opcode_modifier and operand_types.
include/opcode/
* i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
and Seg3ShortFrom with Shortform.
2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
PR gas/4027
* gas/i386/opcode.s: Add more tests for "test".
* i386/opcode-intel.d: Updated.
* gas/i386/opcode-suffix.d: Likewise.
* gas/i386/opcode.d: Likewise.
include/opcode/
2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
PR gas/4027
* i386.h (i386_optab): Put the real "test" before the pseudo
one.
* Contribute the following Changes:
2005-08-22 Dave Brolley <brolley@redhat.com>
* mep.h (EF_MEP_CPU_C4): New macro.
(EF_MEP_CPU_H1): Change to 0x10000000.
2005-04-22 Richard Sandiford <rsandifo@redhat.com>
* mep.h (EF_MEP_LIBRARY): New flag.
(EF_MEP_ALL_FLAGS): Update accordingly.
2004-06-21 Dave Brolley <brolley@redhat.com>
* mep.h (EF_MEP_CPU_MASK, EF_MEP_CPU_MEP, EF_MEP_CPU_C2)
(EF_MEP_CPU_C3, EF_MEP_CPU_H1, EF_MEP_INDEX_MASK)
(EF_MEP_ALL_FLAGS): New macros.
2001-09-28 Richard Henderson <rth@redhat.com>
* mep.h (SHF_MEP_VLIW, SEC_MEP_VLIW): New.
2001-07-12 DJ Delorie <dj@redhat.com>
* mep.h (R_MEP_GNU_VTINHERIT, R_MEP_GNU_VTENTRY): Mark as no-overflow.
2001-06-25 DJ Delorie <dj@redhat.com>
* mep.h: Add vtable relocs.
2001-05-10 DJ Delorie <dj@redhat.com>
* mep.h: Fix bit offsets for HI16*, make them no-overflow. Add
comment about mep-relocs.pl.
2001-05-01 DJ Delorie <dj@redhat.com>
* mep.h: Add MeP-specific relocs.
2001-03-22 Ben Elliston <bje@redhat.com>
* mep.h: New file.
2001-03-20 Ben Elliston <bje@redhat.com>
* common.h (EM_CYGNUS_MEP): Define.
* Contribute the following Changes:
2005-08-22 Dave Brolley <brolley@redhat.com>
* mep.h (EF_MEP_CPU_C4): New macro.
(EF_MEP_CPU_H1): Change to 0x10000000.
2005-04-22 Richard Sandiford <rsandifo@redhat.com>
* mep.h (EF_MEP_LIBRARY): New flag.
(EF_MEP_ALL_FLAGS): Update accordingly.
2004-06-21 Dave Brolley <brolley@redhat.com>
* mep.h (EF_MEP_CPU_MASK, EF_MEP_CPU_MEP, EF_MEP_CPU_C2)
(EF_MEP_CPU_C3, EF_MEP_CPU_H1, EF_MEP_INDEX_MASK)
(EF_MEP_ALL_FLAGS): New macros.
2001-09-28 Richard Henderson <rth@redhat.com>
* mep.h (SHF_MEP_VLIW, SEC_MEP_VLIW): New.
2001-07-12 DJ Delorie <dj@redhat.com>
* mep.h (R_MEP_GNU_VTINHERIT, R_MEP_GNU_VTENTRY): Mark as no-overflow.
2001-06-25 DJ Delorie <dj@redhat.com>
* mep.h: Add vtable relocs.
2001-05-10 DJ Delorie <dj@redhat.com>
* mep.h: Fix bit offsets for HI16*, make them no-overflow. Add
comment about mep-relocs.pl.
2001-05-01 DJ Delorie <dj@redhat.com>
* mep.h: Add MeP-specific relocs.
2001-03-22 Ben Elliston <bje@redhat.com>
* mep.h: New file.
2001-03-20 Ben Elliston <bje@redhat.com>
* common.h (EM_CYGNUS_MEP): Define.
2007-02-15 Dave Brolley <brolley@redhat.com>
From Graydon Hoare <graydon@redhat.com>:
* common.h (STT_RELC, STT_SRELC, R_RELC): New macros.
2076-02-02 H.J. Lu <hongjiu.lu@intel.com>
* doc/binutils.texi (objdump): Document the new addr64 option
for i386 disassembler.
include/
2076-02-02 H.J. Lu <hongjiu.lu@intel.com>
* dis-asm.h (print_i386_disassembler_options): New.
opcodes/
2076-02-02 H.J. Lu <hongjiu.lu@intel.com>
* disassemble.c (disassembler_usage): Call
print_i386_disassembler_options for i386 disassembler.
* i386-dis.c (print_i386_disassembler_options): New.
(print_insn): Support the new addr64 option.
2007-01-16 H.J. Lu <hongjiu.lu@intel.com>
PR ld/3831
* elf-bfd.h (bfd_elf_link_mark_dynamic_symbol): Add an
argument, Elf_Internal_Sym *.
* elflink.c (bfd_elf_link_mark_dynamic_symbol): Mark a data
symbol dynamic if info->dynamic_data is TRUE.
(bfd_elf_record_link_assignment): Updated call to
bfd_elf_record_link_assignment.
(_bfd_elf_merge_symbol): Likewise. Always call
bfd_elf_link_mark_dynamic_symbol.
include/
2007-01-16 H.J. Lu <hongjiu.lu@intel.com>
PR ld/3831
* bfdlink.h (bfd_link_info): Rename dynamic to dynamic_list.
Add dynamic and dynamic_data.
ld/
2007-01-16 H.J. Lu <hongjiu.lu@intel.com>
PR ld/3831
* NEWS: Mention -Bsymbolic-functions, --dynamic-list-data and
--dynamic-list-cpp-new.
* ld.texinfo: Document -Bsymbolic-functions, --dynamic-list-data
and --dynamic-list-cpp-new.
* ldlang.c (lang_append_dynamic_list_cpp_new): New.
(lang_process): Change link_info.dynamic to
link_info.dynamic_list.
(lang_append_dynamic_list): Likewise.
* ldmain.c (main): Likewise. Initialize link_info.dynamic and
link_info.dynamic_data to FALSE.
* ldlang.h (lang_append_dynamic_list_cpp_new): New.
* lexsup.c (option_values): Add OPTION_DYNAMIC_LIST_DATA and
OPTION_DYNAMIC_LIST_CPP_NEW.
(ld_options): Add entries for -Bsymbolic-functions,
--dynamic-list-data and --dynamic-list-cpp-new. Make
-Bsymbolic-functions an alias of --dynamic-list-data.
(parse_args): Change link_info.dynamic to link_info.dynamic_list.
Set link_info.dynamic to TRUE for --dynamic-list and
--dynamic-list-cpp-typeinfo. Handle --dynamic-list-data and
--dynamic-list-cpp-new.
ld/testsuite/
2007-01-16 H.J. Lu <hongjiu.lu@intel.com>
PR ld/3831
* ld-elf/del.cc: New.
* ld-elf/dl5.cc: Likewise.
* ld-elf/dl5.out: Likewise.
* ld-elf/new.cc: Likewise.
* ld-elf/shared.exp: Add tests for --dynamic-list-data and
--dynamic-list-cpp-new.
* archures.c (bfd_mach_cpu32_fido): Rename to bfd_mach_fido.
* bfd-in2.h: Regenerate.
* cpu-m68k.c (arch_info_struct): Use bfd_mach_fido instead of
bfd_mach_cpu32_fido.
(m68k_arch_features): Use fido_a instead of cpu32.
(bfd_m68k_compatible): Reject the combination of Fido and
ColdFire. Accept the combination of CPU32 and Fido with a
warning.
* elf32-m68k.c (elf32_m68k_object_p,
elf32_m68k_merge_private_bfd_data,
elf32_m68k_print_private_bfd_data): Treat Fido as an
architecture by itself.
binutils/
* readelf.c (get_machine_flags): Treat Fido as an architecture
by itself.
gas/
* config/tc-m68k.c (m68k_archs, m68k_cpus): Treat Fido as an
architecture by itself.
(m68k_ip): Don't issue a warning for tbl instructions on fido.
(m68k_elf_final_processing): Treat Fido as an architecture by
itself.
include/elf/
* m68k.h (EF_M68K_FIDO): New.
(EF_M68K_ARCH_MASK): OR EF_M68K_FIDO.
(EF_M68K_CPU32_FIDO_A, EF_M68K_CPU32_MASK): Remove.
include/opcode/
* m68k.h (m68010up): OR fido_a.
opcodes/
* m68k-opc.c (m68k_opcodes): Replace cpu32 with
cpu32 | fido_a except on tbl instructions.
* elf.c (assign_file_positions_for_load_sections): Adjust p_vaddr
by p_vaddr_offset. Copy alignment & use if it is valid.
(rewrite_elf_program_headers): Cope with leading padding in a
segment that does not contain file or program headers.
(copy_elf_program_header): Likewise.
include/elf/
* internal.h (struct elf_segment_map): Add p_vaddr_offset field.
2006-05-03 Andrew Stubbs <andrew.stubbs@st.com>
J"orn Rennecke <joern.rennecke@st.com>
PR driver/29931
* libiberty.h (make_relative_prefix_ignore_links): Declare.
libiberty:
2006-05-03 Andrew Stubbs <andrew.stubbs@st.com>
J"orn Rennecke <joern.rennecke@st.com>
PR driver/29931
* make-relative-prefix.c (make_relative_prefix_1): New function,
broken out of make_relative_prefix. Make link resolution dependent
on new parameter.
(make_relative_prefix): Use make_relative_prefix_1.
(make_relative_prefix_ignore_links): New function.
* elf32-xtensa.c (elf_xtensa_special_sections): Add .xtensa.info.
gas/
* config/tc-xtensa.c (XSHAL_ABI): Add default definition.
(directive_state): Disable scheduling by default.
(xtensa_add_config_info): New.
(xtensa_end): Call xtensa_add_config_info.
gas/testsuite/
* gas/elf/section2.e-xtensa: New file.
* gas/elf/elf.exp: Use it.
include/
* xtensa-config.h (XSHAL_ABI): New.
(XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New.
ld/
* emultempl/xtensaelf.em (XSHAL_ABI): Add default definition.
(replace_insn_sec_with_prop_sec): Use bfd_make_section_with_flags.
Delete redundant code to set sections flags and alignment.
(xt_config_info_unpack_and_check, check_xtensa_info): New.
(elf_xtensa_after_open): Iterate over input statements instead of
link_info.input_bfds.
(elf_xtensa_before_allocation): Likewise. Call check_xtensa_info for
each input, and write a new .xtensa.info section in the output.
(dir_names): Added CLR Runtime Header to dir_names[].
(_bfd_XX_print_private_bfd_data_common): Added EFI_ROM and XBOX subsystem names
(_bfd_XXi_swap_aouthdr_in, _bfd_XXi_swap_aouthdr_out)
(pe_print_idata, pe_print_edata)
(_bfd_XX_bfd_copy_private_bfd_data_common)
(_bfd_XXi_final_link_postscript): Use #DEFINEs for index into DataDirectory.
* pe.h: Added defines for IMAGE_SUBSYSTEM_EFI_ROM and IMAGE_SUBSYSTEM_XBOX.
* internal.h: Added defines for PE directory entry types.
NB: in internal.h because IMAGE_NUMBEROF_DIRECTORY_ENTRYIES is in pe.h
(my_get_expression): Const operand of some instructions can not be symbol in assembly.
(get_insn_class_from_type): Handle instruction type Insn_internal.
(do_macro_ldst_label): Modify inst.type.
(Insn_PIC): Delete.
* score-inst.h (enum score_insn_type): Add Insn_internal.
* tc-score.c (data_op2): The immediate value in lw is 15 bit signed.
* score-dis.c (print_insn): Correct the error code to print correct PCE instruction disassembly.
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* archures.c: Add definition for bfd_mach_arm_iWMMXt2.
* cpu-arm.c (processors): Add bfd_mach_arm_iWMMXt2.
(arch_info_struct, bfd_arm_update_notes): Likewise.
(architectures): Likewise.
(bfd_arm_merge_machines): Check for iWMMXt2.
* bfd-in2.h: Rebuild.
gas/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* config/tc-arm.c (arm_cext_iwmmxt2): New.
(enum operand_parse_code): New code OP_RIWR_I32z.
(parse_operands): Handle OP_RIWR_I32z.
(do_iwmmxt_wmerge): New function.
(do_iwmmxt_wldstd): Handle iwmmxt2 case where second operand is
a register.
(do_iwmmxt_wrwrwr_or_imm5): New function.
(insns): Mark instructions as RIWR_I32z as appropriate.
Also add torvsc<b,h,w>, wabs<b,h,w>, wabsdiff<b,h,w>,
waddbhus<l,m>, waddhc, waddwc, waddsubhx, wavg4{r}, wmaddu{x,n},
wmadds{x,n}, wmerge, wmiaxy{n}, wmiawxy{n}, wmul<sm,um>{r},
wmulw<um,sm,l>{r}, wqmiaxy{n}, wqmulm{r}, wqmulwm{r}, wsubaddhx.
(md_begin): Handle IWMMXT2.
(arm_cpus): Add iwmmxt2.
(arm_extensions): Likewise.
(arm_archs): Likewise.
gas/testsuite/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* gas/arm/iwmmxt2.s: New file.
* gas/arm/iwmmxt2.d: New file.
include/opcode/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
opcodes/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
only be used with the default multiply-add operation, so if N is
set, don't bother printing X. Add new iwmmxt instructions.
(IWMMXT_INSN_COUNT): Update.
(iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
with a 'c' suffix.
(print_insn_coprocessor): Check for iWMMXt2. Handle format
specifiers 'r', 'i'.
* lexsup.c: Add --print-gc-sections and --no-print-gc-sections switches.
* ld.texinfo: Document new switches.
* NEWS: Mention new switches.
* bfdlink.h (struct bfd_link_info): New field: print_gc_sections.
* elflink.c (elf_gc_sweep): If info.print_gc_sections is true, list removed sections to stderr.
to R_ARM_LDC_SB_G{0,1,2} respectively.
bfd/
* bfd-in2.h: Regenerate.
* elf32-arm.c (R_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0,
R_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1, R_ARM_ALU_PC_G2,
R_ARM_LDR_PC_G1, R_ARM_LDR_PC_G2, R_ARM_LDRS_PC_G0,
R_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G2, R_ARM_LDC_PC_G0,
R_ARM_LDC_PC_G1, R_ARM_LDC_PC_G2, R_ARM_ALU_SB_G0_NC,
R_ARM_ALU_SB_G0, R_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1,
R_ARM_ALU_SB_G2, R_ARM_LDR_SB_G0, R_ARM_LDR_SB_G1,
R_ARM_LDR_SB_G2, R_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G1,
R_ARM_LDRS_SB_G2, R_ARM_LDC_SB_G0, R_ARM_LDC_SB_G1,
R_ARM_LDC_SB_G2): New relocation types.
(R_ARM_PC13): Rename to AAELF name R_ARM_LDR_PC_G0 and
adjust HOWTO entry to be consistent with R_ARM_LDR_PC_G1
and friends.
(elf32_arm_howto_table_3): Delete; contents merged into
elf32_arm_howto_table_2.
(elf32_arm_howto_from_type): Adjust correspondingly.
(elf32_arm_reloc_map): Extend with the above relocations.
(calculate_group_reloc_mask): New function.
(identify_add_or_sub): New function.
(elf32_arm_final_link_relocate): Support for the above
relocations.
* reloc.c: Add enumeration entries for BFD_RELOC_ARM_...
codes to correspond to the above relocations.
gas/
* config/tc-arm.c (enum parse_operand_result): New.
(struct group_reloc_table_entry): New.
(enum group_reloc_type): New.
(group_reloc_table): New array.
(find_group_reloc_table_entry): New function.
(parse_shifter_operand_group_reloc): New function.
(parse_address_main): New function, incorporating code
from the old parse_address function. To be used via...
(parse_address): wrapper for parse_address_main; and
(parse_address_group_reloc): new function, likewise.
(enum operand_parse_code): New codes OP_SHG, OP_ADDRGLDR,
OP_ADDRGLDRS, OP_ADDRGLDC.
(parse_operands): Support for these new operand codes.
New macro po_misc_or_fail_no_backtrack.
(encode_arm_cp_address): Preserve group relocations.
(insns): Modify to use the above operand codes where group
relocations are permitted.
(md_apply_fix): Handle the group relocations
ALU_PC_G0_NC through LDC_SB_G2.
(tc_gen_reloc): Likewise.
(arm_force_relocation): Leave group relocations for the linker.
(arm_fix_adjustable): Likewise.
gas/testsuite/
* gas/arm/group-reloc-alu.d: New test.
* gas/arm/group-reloc-alu-encoding-bad.d: New test.
* gas/arm/group-reloc-alu-encoding-bad.l: New test.
* gas/arm/group-reloc-alu-encoding-bad.s: New test.
* gas/arm/group-reloc-alu-parsing-bad.d: New test.
* gas/arm/group-reloc-alu-parsing-bad.l: New test.
* gas/arm/group-reloc-alu-parsing-bad.s: New test.
* gas/arm/group-reloc-alu.s: New test.
* gas/arm/group-reloc-ldc.d: New test.
* gas/arm/group-reloc-ldc-encoding-bad.d: New test.
* gas/arm/group-reloc-ldc-encoding-bad.l: New test.
* gas/arm/group-reloc-ldc-encoding-bad.s: New test.
* gas/arm/group-reloc-ldc-parsing-bad.d: New test.
* gas/arm/group-reloc-ldc-parsing-bad.l: New test.
* gas/arm/group-reloc-ldc-parsing-bad.s: New test.
* gas/arm/group-reloc-ldc.s: New test.
* gas/arm/group-reloc-ldr.d: New test.
* gas/arm/group-reloc-ldr-encoding-bad.d: New test.
* gas/arm/group-reloc-ldr-encoding-bad.l: New test.
* gas/arm/group-reloc-ldr-encoding-bad.s: New test.
* gas/arm/group-reloc-ldr-parsing-bad.d: New test.
* gas/arm/group-reloc-ldr-parsing-bad.l: New test.
* gas/arm/group-reloc-ldr-parsing-bad.s: New test.
* gas/arm/group-reloc-ldr.s: New test.
* gas/arm/group-reloc-ldrs.d: New test.
* gas/arm/group-reloc-ldrs-encoding-bad.d: New test.
* gas/arm/group-reloc-ldrs-encoding-bad.l: New test.
* gas/arm/group-reloc-ldrs-encoding-bad.s: New test.
* gas/arm/group-reloc-ldrs-parsing-bad.d: New test.
* gas/arm/group-reloc-ldrs-parsing-bad.l: New test.
* gas/arm/group-reloc-ldrs-parsing-bad.s: New test.
* gas/arm/group-reloc-ldrs.s: New test.
ld/testsuite/
* ld-arm/group-relocs-alu-bad.d: New test.
* ld-arm/group-relocs-alu-bad.s: New test.
* ld-arm/group-relocs.d: New test.
* ld-arm/group-relocs-ldc-bad.d: New test.
* ld-arm/group-relocs-ldc-bad.s: New test.
* ld-arm/group-relocs-ldr-bad.d: New test.
* ld-arm/group-relocs-ldr-bad.s: New test.
* ld-arm/group-relocs-ldrs-bad.d: New test.
* ld-arm/group-relocs-ldrs-bad.s: New test.
* ld-arm/group-relocs.s: New test.
* ld-arm/arm-elf.exp: Wire in new tests.
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run nops and x86-64-nops.
* gas/i386/nops.d: New file.
* gas/i386/nops.s: Likewise.
* gas/i386/x86-64-nops.d: Likewise.
* gas/i386/x86-64-nops.s: Likewise.
include/opcode/
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Add "nop" with memory reference.
opcodes/
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
(twobyte_has_modrm): Set 1 for 0x1f.
* config/tc-mips.c (macro_build): Use INSERT_OPERAND wherew
appropriate.
(mips16_macro_build): Use MIPS16_INSERT_OPERAND where appropriate.
(mips_ip): Make overflowed/underflowed constant arguments in DSP
and MT instructions a fatal error. Use INSERT_OPERAND where
appropriate. Improve warnings for break and wait code overflows.
Use symbolic constant of OP_MASK_COPZ.
(mips16_ip): Use MIPS16_INSERT_OPERAND where appropriate.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dsp.d, gas/mips/mips32-dsp.s, gas/mips/mips32-mt.d,
gas/mips/mips32-mt.s: Remove instructions with invalid arguments.
* gas/mips/mips32-dsp.l, gas/mips/mips32-mt.l: Delete file.
[ include/opcode/ChangeLog ]
* mips.h: Improve description of MT flags.
* elf.c (assign_file_positions_for_load_sections): Retrieve
maxpagesize from m->p_align if it is valid. Set p_vaddr,
p_paddr and p_align earlier. Revert 2006-05-19 change to p_align.
(copy_elf_program_header): Copy p_align. Set p_align_valid.
include/elf/
* internal.h (elf_segment_map): Add p_align and p_align_valid.
* m68k.h (mcf_mask): Define.
opcodes/
* m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
and fmovem entries. Put register list entries before immediate
mask entries. Use "l" rather than "L" in the fmovem entries.
* m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
out from INFO.
(m68k_scan_mask): New function, split out from...
(print_insn_m68k): ...here. If no architecture has been set,
first try printing an m680x0 instruction, then try a Coldfire one.
gas/testsuite/
* gas/m68k/mcf-fpu.s: Add fmovemd and fmovem instructions.
* gas/m68k/mcf-fpu.d: Adjust accordingly.
2006-04-30 Thiemo Seufer <ths@mips.com>
David Ung <davidu@mips.com>
* config/tc-mips.c (validate_mips_insn): Handling of udi cases.
(mips_immed): New table that records various handling of udi
instruction patterns.
(mips_ip): Adds udi handling.
[ include/opcode/ChangeLog ]
2006-04-30 Thiemo Seufer <ths@mips.com>
David Ung <davidu@mips.com>
* mips.h: Defines udi bits and masks. Add description of
characters which may appear in the args field of udi
instructions.
[ opcodes/ChangeLog ]
2006-04-30 Thiemo Seufer <ths@mips.com>
David Ung <davidu@mips.com>
* mips-opc.c (mips_builtin_opcodes): Add udi instructions
"udi0" to "udi15".
* mips-dis.c (print_insn_args): Adds udi argument handling.
Joseph Myers
Nick Clifton
Bob Wilson
Alan Modra
Caroline Tice
DJ Delorie
Jan Beulich
Nathan Sidwell
Richard Henderson
H.J. Lu
Martin Schwidefsky
Thiemo Seufer
Dave Brolley
Vladimir Prus
Daniel Jacobowitz
Kazu Hirata
Joern Rennecke
Paul Brook
Richard Sandiford
Michael Meissner
Mark Shinwell
Jakub Jelinek
Julian Brown
Andreas Jaeger