crt0.S for ARC used to use instruction "asr.f lp_count, r3, 2" for all cores
except ARC601. However instructions which shift more than 1 bit are
optional, so this crt0.S didn't worked for all ARC cores.
Luckily this is a shift just by 2 bits on all occassions, so fix is trivial
- use two single-bit shifts.
libgloss/ChangeLog
2016-04-29 Anton Kolesov <anton.kolesov@synopsys.com>
* arc/crt0.S: Fix support for processors without barrel-shifter.
Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
This is similar to commit 06537f05d4 to the
newlib for ARC.
GCC for ARC has been updated to provide consistent naming of preprocessor
definitions for different optional architecture features:
* __ARC_BARREL_SHIFTER__ instead of __Xbarrel_shifter for
-mbarrel-shifter
* __ARCEM__ instead of __EM__ for ARC EM cores
* __ARCHS__ instead of __HS__ for ARC HS cores
* etc (not used in libgloss)
This patch updates crt0.S for ARC to use new definitions instead of a
deprecated ones. To ensure compatibility with older compiler new definitions
are also defined in crt0.S if needed, based on presence of deprecated
preprocessor definitions.
libgloss/ChangeLog
2016-04-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
* arc/crt0.S: Use new GCC defines to detect processor features.
ARC aproach to this feature is similiar to ARM's one here.
2016-04-29 Anton Kolesov <anton.kolesov@synopsys.com>
* arc/nano.specs: New file.
* arc/Makefile.in: Support nano.specs.
* arc/nsim.specs: Likewise.
While running tests on internal systems, we identified an issue in the
startup code for newlib on AArch32 systems with Multiprocessor
Extensions to the architecture.
The issue is we were configuring page table flags to be Inner
cacheable/Outer non-cacheable, while for at least architectures with
Multiprocessor Extension, we'd configure it to Inner/Outer write-back, no
write-allocate, and cacheable.
The attached patch fixes this, and no regression on arm-none-eabi
bare-metal tests.
Adopted suggestion given by Richard offline to avoid using jump.
libgloss/
* arm/cpu-init/rdimon-aem.S: Set TTBR0 to inner/outer
cacheable WB, and no allocate on WB for arch with multiprocessor
extension.
Change the type of the stack pointers to enable pointer calculations at byte
granularity, which is needed for the calculation of _or1k_stack_core[c] and
_or1k_exception_stack_core[c] with _or1k_stack_size and
_or1k_exception_stack_size. (util.c:53-54)
libgloss:
* arm/Makefile.in: Add newlib/libc/machine/arm to the include path if
newlib is present.
* arm/arm.h: Include acle-compat.h.
(THUMB_V7_V6M): Rename to ...
(PREFER_THUMB): This. Use ACLE macros __ARM_ARCH_ISA_ARM instead of
__ARM_ARCH_6M__ to decide whether to define it.
(THUMB1_ONLY): Define for Thumb-1 only targets.
(THUMB_V7M_V6M): Rename to ...
(THUMB_VXM): This. Defined based on __ARM_ARCH_ISA_ARM, excluding
ARMv7.
* arm/crt0.S: Use THUMB1_ONLY rather than __ARM_ARCH_6M__,
!__ARM_ARCH_ISA_ARM rather than THUMB_V7M_V6M for fp enabling, and
PREFER_THUMB rather than THUMB_V7_V6M. Rename other occurences of
THUMB_V7M_V6M to THUMB_VXM.
* arm/linux-crt0.c: Likewise.
* arm/redboot-crt0.S: Likewise.
* arm/swi.h: Likewise.
* arm/trap.S: Likewise.
newlib:
* libc/machine/arm/memcpy-stub.c: Use ACLE macros __ARM_ARCH_ISA_THUMB
and __ARM_ARCH_ISA_ARM to check for Thumb-2 only targets rather than
__ARM_ARCH and __ARM_ARCH_PROFILE.
* libc/machine/arm/memcpy.S: Likewise.
* libc/machine/arm/setjmp.S: Likewise for Thumb-1 only target and
include acle-compat.h.
* libc/machine/arm/strcmp.S: Likewise for Thumb-1 and Thumb-2 only
target and include acle-compat.h.
* libc/sys/arm/arm.h: Include acle-compat.h.
(THUMB_V7_V6M): Rename to ...
(PREFER_THUMB): This. Use ACLE macro __ARM_ARCH_ISA_ARM instead of
__ARM_ARCH_6M__ to decide whether to define it.
(THUMB1_ONLY): Define for Thumb-1 only targets.
(THUMB_V7M_V6M): Rename to ...
(THUMB_VXM): This. Defined based on __ARM_ARCH_ISA_ARM, excluding
ARMv7.
* libc/sys/arm/crt0.S: Use PREFER_THUMB rather than THUMB_V7_V6M and
rename THUMB_V7M_V6M into THUMB_VXM.
* libc/sys/arm/swi.h: Likewise.
The MSP430 debuggers support I/O on hardware through CIO, so
we can use a CIO-enabled library as the "nosys" library (in
addition to the libsim library, which talks to our simulator)
* configure.in: Don't build default libnosys for msp430
* configure: Regenerate.
* msp430/Makefile: Rename libcio to libnosys.
The file libgloss/rl78/write.c currently contains code which outputs
\r when \n is seen. The code will then output the \n as well.
This patch removes the bit of code that tests for \n and then outputs
\r.
I made this change to fix some failures in gdb.base/call-ar-st.exp. In
that test, I see two carriage returns followed by a newline. One CR is
output by the libgloss code. The other is output by the terminal driver.
The total list of failures fixed (using the default rl78 multilib) are:
FAIL: gdb.base/call-ar-st.exp: print print_double_array(double_array) (timeout)
FAIL: gdb.base/call-ar-st.exp: print print_char_array(char_array) (timeout)
FAIL: gdb.base/call-ar-st.exp: continue to tbreak2 (timeout)
FAIL: gdb.base/call-ar-st.exp: continuing to tbreak3 (timeout)
FAIL: gdb.base/call-ar-st.exp: print print_double_array(array_d) (timeout)
FAIL: gdb.base/call-ar-st.exp: continuing to tbreak4 (timeout)
FAIL: gdb.base/call-ar-st.exp: print sum_array_print(10, *list1, *list2, *list3, *list4) (timeout)
FAIL: gdb.base/call-ar-st.exp: print print_small_structs (timeout)
FAIL: gdb.base/call-ar-st.exp: print print_ten_doubles(123.456, 123.456, -0.12, -1.23, 343434.8, 89.098, 3.14, -5678.12345, -0.11111111, 216.97065) (timeout)
FAIL: gdb.base/call-ar-st.exp: print print_small_structs from print_long_arg_list (timeout)
FAIL: gdb.base/call-ar-st.exp: print print_struct_rep(*struct1, *struct2, *struct3) (timeout)
FAIL: gdb.base/dprintf.exp: call: printf: 1st dprintf (timeout)
FAIL: gdb.base/dprintf.exp: call: printf: 2nd dprintf (timeout)
FAIL: gdb.base/interrupt.exp: process is alive (the program exited)
There are no regressions.
libgloss/ChangeLog:
* rl78/write.c (_write): Don't output CR when LF is encountered.
Allow exceptions to be nested, which is especially useful with urgent
interrupts while processing an exception.
The implementation counts up the nesting level with each call to an
exception. In the outer exception (level 1), the exception stack is
started. All nested exceptions just reserve the redzone (scratch
memory that may be used by compiler) and exception context on the
stack, but then process on the same scratch.
Restriction: Impure pointers are shared among all exceptions. This may
be solved by creating an impure data structure in the stack frame with
each nested exception.
* or1k/crt0.S: Add exception nesting
* or1k/exceptions-asm.S: ditto
* or1k/util.c: ditto
- With the gzll kernel we have two different loading options:
- If the image is loaded to the global memory, the bootstrapping
loads the kernel to local memory. Applications are loaded on
demand. The heap then starts right after bss.
- If the image is pre-loaded to the local memory it includes the
application binaries right after bss. The heap then starts after
the application objects.
- We can check if this is a gzll kernel as it has the string "gzll" at
0x2000. At 0x200c we then find the end of the application objects in
the image. If there is no global memory we set _or1k_heap_start to
this value.
* or1k/boards/optimsoc.S: Heap for gzll kernel
- Previously the heap started right after the bss section. This can now
be configured by changing the _or1k_heap_start symbol that defaults to
the old value (&end). In board_init_early, we can now set this to
another value.
* or1k/sbrk.c: Allow for different heap start
- Store the exception program counter (from EPCR) and exception status
register (from ESR) also during the exception. A runtime system may
replace them thereby to implement a thread switch.
* or1k/exception-asm.S: Store missing state
- We do not need a red zone here, as we do not operate on the current
stack, but always use the clear exception stack. Also reserve two
extra words for the context to store EPCR and ESR.
* or1k/crt0.S: Fix exception stack frame
* or1k/exception-asm.S: ditto
- During interrupt handling the PICSR, table pointers and current
interrupt line have been saved in incorrect registers and/or stored on
the stack.
- Save the pointer in r16/r18, PICSR in r20 and the current interrupt
line in r22. Those are callee-saved registers, so that the register
values will be preserved.
* or1k/interruts-asm.S: Change registers to callee-saved.
* msp430/msp430-sim.ld (.stack): Add an assertion to make sure
that the data area does not overrun the stack. PROVIDE a new
symbol __stack_size to allow the user to set the limit.
* msp430/msp430xl-sim.ld (.stack): Likewise.
* rl78/rl78-sim.ld (.stack): Likewise.
* rl78/rl78.ld (.stack): Likewise.
* rx/rx-sim.ld (.stack): Likewise.
* rx/rx.ld (.stack): Likewise.
* msp430/msp430.ld: Delete.
* msp430/msp430F5438A-l.ld: Delete.
* msp430/msp430F5438A-s.ld: Delete.
* msp430/crt_movedata.S: Delete.
* msp430/Makefile.in (SCRIPTS): Remove msp430.ld.
(CRT_OBJS): Add crt_move_highdata.o.
* msp430/memmodel.h (START_CRT_FUNC): New macro.
(END_CRT_FUNC): New macro.
(WEAK_DEF): New macro.
* msp430/crt0.S: Use new macros.
(move_highdata): New code to initialise the .data section if it is
held in high memory.
* msp430/msp430-sim.ld (.data): Add .either.data.
(.rodata2): Move some read-only data sections here.
(.text): Add .either.text.
(.rodata): Add .either.rodata.
(.bss): Add .either.bss.
* msp430/msp430xl-sim.ld (MEMORY): Add HIROM.
(.rodata2): Move some read-only data sections here.
(.upper.data): New section. Include notes about how to initialise
it.
This header was clearly copied from the common syscall.h and customized,
but the header comment is no longer accurate -- this isn't the general
file anymore.
Yaakov Selkowitz
Jeff Johnston
David Hoover
Nick Clifton
Jiong Wang
Stefan Roesch
Thomas Preud'homme
Corinna Vinschen
DJ Delorie
Kevin Buettner
Anton Kolesov
Andre Simoes Dias Vieira
Mike Frysinger