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Add MIPS V and MIPS 64 machine numbers

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This commit is contained in:
Nick Clifton
2000-12-02 00:55:22 +00:00
parent 388732e7f6
commit f9fe8a8ead
4 changed files with 16 additions and 0 deletions
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2
include/elf/ChangeLog
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@@ -4,6 +4,8 @@
(E_MIPS_MACH_MIPS32, E_MIPS_MACH_MIPS32_4K): Replace the (E_MIPS_MACH_MIPS32, E_MIPS_MACH_MIPS32_4K): Replace the
former with the latter. former with the latter.
* mips.h (E_MIPS_ARCH_5, E_MIPS_ARCH_64): New definitions.
2000-11-30 Jan Hubicka <jh@suse.cz> 2000-11-30 Jan Hubicka <jh@suse.cz>
* common.h (EM_X86_64): New macro. * common.h (EM_X86_64): New macro.

6
include/elf/mips.h
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@@ -121,9 +121,15 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
/* -mips4 code. */ /* -mips4 code. */
#define E_MIPS_ARCH_4 0x30000000 #define E_MIPS_ARCH_4 0x30000000
/* -mips5 code. */
#define E_MIPS_ARCH_5 0x40000000
/* -mips32 code. */ /* -mips32 code. */
#define E_MIPS_ARCH_32 0x50000000 #define E_MIPS_ARCH_32 0x50000000
/* -mips64 code. */
#define E_MIPS_ARCH_64 0x60000000
/* The ABI of the file. Also see EF_MIPS_ABI2 above. */ /* The ABI of the file. Also see EF_MIPS_ABI2 above. */
#define EF_MIPS_ABI 0x0000F000 #define EF_MIPS_ABI 0x0000F000

3
include/opcode/ChangeLog
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@@ -25,6 +25,9 @@
(OPCODE_IS_MEMBER): Update for new ISA membership-related (OPCODE_IS_MEMBER): Update for new ISA membership-related
constant meanings. constant meanings.
* mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New
definitions.
2000-10-20 Jakub Jelinek <jakub@redhat.com> 2000-10-20 Jakub Jelinek <jakub@redhat.com>
* sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B. * sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.

5
include/opcode/mips.h
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@@ -313,6 +313,7 @@ struct mips_opcode
#define INSN_ISA4 0x00000080 #define INSN_ISA4 0x00000080
#define INSN_ISA5 0x00000100 #define INSN_ISA5 0x00000100
#define INSN_ISA32 0x00000200 #define INSN_ISA32 0x00000200
#define INSN_ISA64 0x00000400
/* Chip specific instructions. These are bitmasks. */ /* Chip specific instructions. These are bitmasks. */
@@ -334,7 +335,9 @@ struct mips_opcode
#define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2) #define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3) #define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4) #define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
#define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5)
#define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32) #define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
#define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
/* CPU defines, use instead of hardcoding processor number. Keep this /* CPU defines, use instead of hardcoding processor number. Keep this
in sync with bfd/archures.c in order for machine selection to work. */ in sync with bfd/archures.c in order for machine selection to work. */
@@ -357,6 +360,8 @@ struct mips_opcode
#define CPU_MIPS16 16 #define CPU_MIPS16 16
#define CPU_MIPS32 32 #define CPU_MIPS32 32
#define CPU_MIPS32_4K 3204113 /* 32, 04, octal 'K' */ #define CPU_MIPS32_4K 3204113 /* 32, 04, octal 'K' */
#define CPU_MIPS5 5
#define CPU_MIPS64 64
/* Test for membership in an ISA including chip specific ISAs. /* Test for membership in an ISA including chip specific ISAs.
INSN is pointer to an element of the opcode table; ISA is the INSN is pointer to an element of the opcode table; ISA is the