PR binutils/15068
* tic6x-dis.c: Add support for displaying 16-bit insns. * tic6xc-insn-formats.h (FLD): Add use of bitfield array. Add 16-bit opcodes. * tic6xc-opcode-table.h: Add 16-bit insns. * tic6x.h: Add support for 16-bit insns. * config/tc-tic6x.c (tic6x_try_encode): Add use of bitfields array. * gas/tic6x/insns16-d-unit.s: New test. * gas/tic6x/insns16-d-unit.d: Expected disassembly. * gas/tic6x/insns16-ddec.s: New test. * gas/tic6x/insns16-ddec.d: Expected disassembly. * gas/tic6x/insns16-dinc.s: New test. * gas/tic6x/insns16-dinc.d: Expected disassembly. * gas/tic6x/insns16-dind.s: New test. * gas/tic6x/insns16-dind.d: Expected disassembly. * gas/tic6x/insns16-doff4.s: New test. * gas/tic6x/insns16-doff4.d: Expected disassembly. * gas/tic6x/insns16-l-unit.s: New test. * gas/tic6x/insns16-l-unit.d: Expected disassembly. * gas/tic6x/insns16-lsd-unit.s: New test. * gas/tic6x/insns16-lsd-unit.d: Expected disassembly. * gas/tic6x/insns16-m-unit.s: New test. * gas/tic6x/insns16-m-unit.d: Expected disassembly. * gas/tic6x/insns16-s-unit-pcrel.s: New test. * gas/tic6x/insns16-s-unit-pcrel.d: Expected disassembly. * gas/tic6x/insns16-s-unit: New test. * gas/tic6x/insns16-s-unit.d: Expected disassembly.
This commit is contained in:
Nick Clifton
@ -27,18 +27,25 @@
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typedef enum
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{
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tic6x_field_baseR,
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tic6x_field_cc,
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tic6x_field_creg,
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tic6x_field_cst,
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tic6x_field_csta,
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tic6x_field_cstb,
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tic6x_field_dst,
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tic6x_field_dstms,
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tic6x_field_dw,
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tic6x_field_fstgfcyc,
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tic6x_field_h,
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tic6x_field_ii,
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tic6x_field_mask,
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tic6x_field_mode,
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tic6x_field_n,
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tic6x_field_na,
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tic6x_field_offsetR,
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tic6x_field_op,
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tic6x_field_p,
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tic6x_field_ptr,
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tic6x_field_r,
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tic6x_field_s,
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tic6x_field_sc,
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@ -46,6 +53,11 @@ typedef enum
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tic6x_field_src1,
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tic6x_field_src2,
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tic6x_field_srcdst,
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tic6x_field_srcms,
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tic6x_field_sn,
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tic6x_field_sz,
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tic6x_field_unit,
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tic6x_field_t,
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tic6x_field_x,
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tic6x_field_y,
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tic6x_field_z
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@ -53,14 +65,24 @@ typedef enum
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typedef struct
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{
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/* The name used to reference the field. */
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tic6x_insn_field_id field_id;
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/* The least-significant bit position in the field. */
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unsigned short low_pos;
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unsigned short low_pos;
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/* The number of bits in the field. */
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unsigned short width;
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/* The position of the bitfield in the field. */
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unsigned short pos;
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} tic6x_bitfield;
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/* Maximum number of subfields in composite field. */
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#define TIC6X_MAX_BITFIELDS 4
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typedef struct
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{
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/* The name used to reference the field. */
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tic6x_insn_field_id field_id;
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unsigned int num_bitfields;
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tic6x_bitfield bitfields[TIC6X_MAX_BITFIELDS];
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} tic6x_insn_field;
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/* Maximum number of variable fields in an instruction format. */
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@ -119,6 +141,13 @@ typedef struct
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unsigned int max_val;
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} tic6x_fixed_field;
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/* Pseudo opcode fields position for compact instructions
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If 16 bits instruction detected, the opcode is enriched
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[DSZ/3][BR][SAT][opcode] */
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#define TIC6X_COMPACT_SAT_POS 16
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#define TIC6X_COMPACT_BR_POS 17
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#define TIC6X_COMPACT_DSZ_POS 18
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/* Bit-masks for defining instructions present on some subset of
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processors; each indicates an instruction present on that processor
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and those that are supersets of it. The options passed to the
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@ -188,6 +217,29 @@ typedef struct
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values here. */
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#define TIC6X_PREFER_VAL(n) (((n) & 0x8000) >> 15)
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#define TIC6X_FLAG_PREFER(n) ((n) << 15)
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/* 16 bits opcode is predicated by register a0 (s = 0) or b0 (s = 1) */
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#define TIC6X_FLAG_INSN16_SPRED 0x00100000
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/* 16 bits opcode ignores RS bit of fetch packet header */
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#define TIC6X_FLAG_INSN16_NORS 0x00200000
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/* 16 bits opcode only on side B */
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#define TIC6X_FLAG_INSN16_BSIDE 0x00400000
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/* 16 bits opcode ptr reg is b15 */
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#define TIC6X_FLAG_INSN16_B15PTR 0x00800000
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/* 16 bits opcode memory access modes */
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#define TIC6X_INSN16_MEM_MODE(n) ((n) << 16)
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#define TIC6X_INSN16_MEM_MODE_VAL(n) (((n) & 0x000F0000) >> 16)
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#define TIC6X_MEM_MODE_NEGATIVE 0
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#define TIC6X_MEM_MODE_POSITIVE 1
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#define TIC6X_MEM_MODE_REG_NEGATIVE 4
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#define TIC6X_MEM_MODE_REG_POSITIVE 5
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#define TIC6X_MEM_MODE_PREDECR 8
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#define TIC6X_MEM_MODE_PREINCR 9
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#define TIC6X_MEM_MODE_POSTDECR 10
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#define TIC6X_MEM_MODE_POSTINCR 11
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#define TIC6X_FLAG_INSN16_MEM_MODE(mode) TIC6X_INSN16_MEM_MODE(TIC6X_MEM_MODE_##mode)
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#define TIC6X_NUM_PREFER 2
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/* Maximum number of fixed fields for a particular opcode. */
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@ -230,6 +282,13 @@ typedef enum
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/* A register, from the same side as the functional unit
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selected. */
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tic6x_operand_reg,
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/* A register, from the same side as the functional unit
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selected that ignore RS header bit */
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tic6x_operand_reg_nors,
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/* A register, from the b side */
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tic6x_operand_reg_bside,
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/* A register, from the b side and from the low register set */
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tic6x_operand_reg_bside_nors,
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/* A register, that is from the other side if a cross path is
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used. */
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tic6x_operand_xreg,
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@ -241,6 +300,14 @@ typedef enum
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path is not used, and the other side if a cross path is
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used. */
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tic6x_operand_areg,
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/* The B15 register */
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tic6x_operand_b15reg,
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/* A register coded as an offset from either A16 or B16 depending
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on the value of the t bit. */
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tic6x_operand_treg,
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/* A register (A0 or B0), from the same side as the
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functional unit selected. */
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tic6x_operand_zreg,
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/* A return address register (A3 or B3), from the same side as the
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functional unit selected. */
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tic6x_operand_retreg,
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@ -252,10 +319,15 @@ typedef enum
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tic6x_operand_xregpair,
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/* A register pair, from the side of the data path selected. */
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tic6x_operand_dregpair,
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/* A register pair coded as an offset from either A16 or B16 depending
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on the value of the t bit. */
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tic6x_operand_tregpair,
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/* The literal string "irp" (case-insensitive). */
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tic6x_operand_irp,
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/* The literal string "nrp" (case-insensitive). */
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tic6x_operand_nrp,
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/* The literal string "ilc" (case-insensitive). */
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tic6x_operand_ilc,
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/* A control register. */
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tic6x_operand_ctrl,
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/* A memory reference (base and offset registers from the side of
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@ -277,7 +349,16 @@ typedef enum
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tic6x_operand_mem_deref,
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/* A functional unit name or a list thereof (for SPMASK and
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SPMASKR). */
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tic6x_operand_func_unit
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tic6x_operand_func_unit,
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/* Hardwired constant '5' in Sbu8 Scs10 and Sbu8c 16 bits
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instruction formats - spru732j.pdf Appendix F.4 */
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tic6x_operand_hw_const_minus_1,
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tic6x_operand_hw_const_0,
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tic6x_operand_hw_const_1,
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tic6x_operand_hw_const_5,
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tic6x_operand_hw_const_16,
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tic6x_operand_hw_const_24,
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tic6x_operand_hw_const_31
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} tic6x_operand_form;
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/* Whether something is, or can be, read or written. */
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@ -375,6 +456,8 @@ typedef enum
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/* Likewise, but counting in half-words if in a header-based fetch
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packet. */
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tic6x_coding_pcrel_half,
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/* Store an unsigned PC-relative value used in compact insn */
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tic6x_coding_pcrel_half_unsigned,
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/* Encode the register number (even number for a register pair) in
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the field. When applied to a memory reference, encode the base
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register. */
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@ -388,6 +471,8 @@ typedef enum
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/* Store 0 for register B14, 1 for register B15. When applied to
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a memory reference, encode the base register. */
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tic6x_coding_areg,
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/* Compact instruction offset base register */
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tic6x_coding_reg_ptr,
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/* Store the low part of a control register address. */
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tic6x_coding_crlo,
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/* Store the high part of a control register address. */
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@ -435,7 +520,16 @@ typedef enum
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destination for load) is on side B, 0 for side A. */
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tic6x_coding_data_fu,
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/* Store 1 if the cross path is being used, 0 otherwise. */
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tic6x_coding_xpath
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tic6x_coding_xpath,
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/* L3i constant coding */
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tic6x_coding_scst_l3i,
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/* S3i constant coding */
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tic6x_coding_cst_s3i,
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/* mem offset minus 1 */
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tic6x_coding_mem_offset_minus_one,
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/* non aligned mem offset minus 1 */
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tic6x_coding_mem_offset_minus_one_noscale,
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tic6x_coding_rside
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} tic6x_coding_method;
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/* How to generate the value of a particular field. */
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@ -530,7 +624,7 @@ typedef struct
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unsigned short isa_variants;
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/* Flags for this instruction. */
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unsigned short flags;
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unsigned int flags;
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/* Number of fixed fields, or fields with restricted value ranges,
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for this instruction. */
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@ -570,9 +664,15 @@ typedef enum
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CONCAT6(tic6x_opcode_,name,_,func_unit,_,format),
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#define INSNE(name, e, func_unit, format, type, isa, flags, fixed, ops, var) \
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CONCAT4(tic6x_opcode_,name,_,e),
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#define INSNU(name, func_unit, format, type, isa, flags, fixed, ops, var) \
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CONCAT6(tic6x_opcode_,name,_,func_unit,_,format),
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#define INSNUE(name, e, func_unit, format, type, isa, flags, fixed, ops, var) \
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CONCAT6(tic6x_opcode_,name,_,func_unit,_,e),
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#include "tic6x-opcode-table.h"
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#undef INSN
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#undef INSNE
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#undef INSNU
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#undef INSNUE
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tic6x_opcode_max
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} tic6x_opcode_id;
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