For include/opcode:
* d30v.h: Fix declaration of reg_name_cnt. * d10v.h: Fix declaration of d10v_reg_name_cnt. * arc.h: Add prototypes from opcodes/arc-opc.c. For opcodes: * tic54x-dis.c: Add unused attributes where needed. * z8k-dis.c (output_instr): Add unused attribute. * h8300-dis.c: Add missing prototypes. (bfd_h8_disassemble): Make static. * cris-dis.c: Add missing prototype. * h8500-dis.c: Likewise. * m68hc11-dis.c: Likewise. * pj-dis.c: Likewise. * tic54x-dis.c: Likewise. * v850-dis.c: Likewise. * vax-dis.c: Likewise. * w65-dis.c: Likewise. * z8k-dis.c: Likewise. * d10v-dis.c: Add missing prototype. (dis_long): Remove unused variable. (dis_2_short): Likewise. * sh-dis.c: Add missing prototypes. * v850-opc.c: Likewise. Add unused attributes where needed. * ns32k-dis.c: Add missing prototypes. (bit_extract_simple): Remove unused variable.
This commit is contained in:
Andreas Jaeger
parent
8e26d5b5a7
commit
e451b2c504
@ -1,3 +1,11 @@
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2001-08-25 Andreas Jaeger <aj@suse.de>
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* d30v.h: Fix declaration of reg_name_cnt.
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* d10v.h: Fix declaration of d10v_reg_name_cnt.
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* arc.h: Add prototypes from opcodes/arc-opc.c.
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2001-08-16 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
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* mips.h (INSN_10000): Define.
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@ -223,14 +231,14 @@
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CPU_R5000, CPU_R6000, CPU_R8000, CPU_R10000, CPU_MIPS32, CPU_4K,
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CPU_4KC, CPU_4KM, CPU_4KP): Define..
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(OPCODE_IS_MEMBER): Use new defines.
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(OP_MASK_SEL, OP_SH_SEL): Define.
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(OP_MASK_SEL, OP_SH_SEL): Define.
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(OP_MASK_CODE20, OP_SH_CODE20): Define.
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Add 'P' to used characters.
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Use 'H' for coprocessor select field.
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Add 'P' to used characters.
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Use 'H' for coprocessor select field.
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Use 'm' for 20 bit breakpoint code.
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Document new arg characters and add to used characters.
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(INSN_MIPS32): New define for MIPS32 extensions.
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(OPCODE_IS_MEMBER): Recognize MIPS32 instructions.
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Document new arg characters and add to used characters.
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(INSN_MIPS32): New define for MIPS32 extensions.
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(OPCODE_IS_MEMBER): Recognize MIPS32 instructions.
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2000-09-05 Alan Modra <alan@linuxcare.com.au>
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@ -811,16 +819,16 @@ Mon Feb 1 21:09:14 1999 Catherine Moore <clm@cygnus.com>
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Wed Dec 9 10:38:48 1998 David Taylor <taylor@texas.cygnus.com>
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The following is part of a change made by Edith Epstein
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<eepstein@sophia.cygnus.com> as part of a project to merge in
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changes by HP; HP did not create ChangeLog entries.
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<eepstein@sophia.cygnus.com> as part of a project to merge in
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changes by HP; HP did not create ChangeLog entries.
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* hppa.h (completer_chars): list of chars to not put a space
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after.
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after.
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Sun Dec 6 13:21:34 1998 Ian Lance Taylor <ian@cygnus.com>
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* i386.h (i386_optab): Permit w suffix on processor control and
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status word instructions.
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status word instructions.
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1998-11-30 Doug Evans <devans@casey.cygnus.com>
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@ -1540,9 +1548,9 @@ Mon Nov 4 12:52:48 1996 Jeffrey A Law (law@cygnus.com)
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Fri Nov 1 10:31:02 1996 Richard Henderson <rth@tamu.edu>
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* alpha.h: Don't include "bfd.h"; private relocation types are now
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negative to minimize problems with shared libraries. Organize
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instruction subsets by AMASK extensions and PALcode
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implementation.
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negative to minimize problems with shared libraries. Organize
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instruction subsets by AMASK extensions and PALcode
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implementation.
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(struct alpha_operand): Move flags slot for better packing.
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Tue Oct 29 12:19:10 1996 Jeffrey A Law (law@cygnus.com)
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@ -1595,9 +1603,9 @@ Fri Aug 23 10:39:08 1996 Jeffrey A Law (law@cygnus.com)
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Thu Aug 22 16:51:25 1996 J.T. Conklin <jtc@rtl.cygnus.com>
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* v850.h (v850_operands): Add insert and extract fields, pointers
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to functions used to handle unusual operand encoding.
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to functions used to handle unusual operand encoding.
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(V850_OPERAND_REG, V850_OPERAND_SRG, V850_OPERAND_CC,
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V850_OPERAND_SIGNED): Defined.
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V850_OPERAND_SIGNED): Defined.
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Wed Aug 21 17:45:10 1996 J.T. Conklin <jtc@rtl.cygnus.com>
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@ -1611,11 +1619,11 @@ Tue Aug 20 14:52:02 1996 J.T. Conklin <jtc@rtl.cygnus.com>
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Fri Aug 16 14:44:15 1996 James G. Smith <jsmith@cygnus.co.uk>
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* mips.h (OP_SH_LOCC, OP_SH_HICC, OP_MASK_CC, OP_SH_COP1NORM,
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OP_MASK_COP1NORM, OP_SH_COP1SPEC, OP_MASK_COP1SPEC,
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OP_MASK_COP1SCLR, OP_MASK_COP1CMP, OP_SH_COP1CMP, OP_SH_FORMAT,
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OP_MASK_FORMAT, OP_SH_TRUE, OP_MASK_TRUE, OP_SH_GE, OP_MASK_GE,
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OP_SH_UNSIGNED, OP_MASK_UNSIGNED, OP_SH_HINT, OP_MASK_HINT):
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Defined.
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OP_MASK_COP1NORM, OP_SH_COP1SPEC, OP_MASK_COP1SPEC,
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OP_MASK_COP1SCLR, OP_MASK_COP1CMP, OP_SH_COP1CMP, OP_SH_FORMAT,
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OP_MASK_FORMAT, OP_SH_TRUE, OP_MASK_TRUE, OP_SH_GE, OP_MASK_GE,
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OP_SH_UNSIGNED, OP_MASK_UNSIGNED, OP_SH_HINT, OP_MASK_HINT):
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Defined.
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Fri Aug 16 00:15:15 1996 Jeffrey A Law (law@cygnus.com)
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@ -1625,7 +1633,7 @@ Fri Aug 16 00:15:15 1996 Jeffrey A Law (law@cygnus.com)
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Thu Aug 15 13:11:46 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
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* d10v.h: Add some additional defines to support the
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assembler in determining which operations can be done in parallel.
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assembler in determining which operations can be done in parallel.
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Tue Aug 6 11:13:22 1996 Jeffrey A Law (law@cygnus.com)
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@ -1641,7 +1649,7 @@ Fri Jul 26 11:47:10 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
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Thu Jul 25 12:06:22 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
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* d10v.h: Changes for divs, parallel-only instructions, and
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signed numbers.
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signed numbers.
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Mon Jul 22 11:21:15 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
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@ -1663,7 +1671,7 @@ Thu Jul 11 12:09:15 1996 Jeffrey A Law (law@cygnus.com)
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Wed Jul 3 14:30:12 1996 J.T. Conklin <jtc@rtl.cygnus.com>
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* m68k.h (mcf5200): New macro.
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* m68k.h (mcf5200): New macro.
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Document names of coldfire control registers.
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Tue Jul 2 23:05:45 1996 Jeffrey A Law (law@cygnus.com)
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@ -1813,7 +1821,7 @@ Tue Oct 24 10:49:10 1995 Jeffrey A Law (law@cygnus.com)
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Mon Oct 23 11:09:16 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
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* mips.h: Added INSN_4100 flag to mark NEC VR4100 specific
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instructions.
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instructions.
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Mon Oct 16 10:28:15 1995 Michael Meissner <meissner@tiktok.cygnus.com>
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@ -313,3 +313,9 @@ const struct arc_operand_value *arc_opcode_lookup_suffix
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PARAMS ((const struct arc_operand *type, int value));
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int arc_opcode_supported PARAMS ((const struct arc_opcode *));
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int arc_opval_supported PARAMS ((const struct arc_operand_value *));
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int arc_limm_fixup_adjust PARAMS ((arc_insn));
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int arc_insn_is_j PARAMS ((arc_insn));
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int arc_insn_not_jl PARAMS ((arc_insn));
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int arc_operand_type PARAMS ((int));
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struct arc_operand_value *get_ext_suffix PARAMS ((char *));
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int arc_get_noshortcut_flag PARAMS ((void));
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@ -190,7 +190,7 @@ struct pd_reg
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};
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extern const struct pd_reg d10v_predefined_registers[];
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int d10v_reg_name_cnt();
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int d10v_reg_name_cnt PARAMS ((void));
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/* an expressionS only has one register type, so we fake it */
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/* by setting high bits to indicate type */
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@ -32,7 +32,7 @@ struct pd_reg
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};
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extern const struct pd_reg pre_defined_registers[];
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int reg_name_cnt();
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int reg_name_cnt PARAMS ((void));
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/* the number of control registers */
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#define MAX_CONTROL_REG 64
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