* mips.h: Document new field descriptors +Q.
(OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI. opcodes/ * mips-dis.c (print_insn_args): Handle field descriptor +Q. * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq, seqi, sne and snei. gas/ * config/tc-mips.c (validate_mips_insn): Handle field descriptor +Q. (mips_ip): Likewise. (macro_build): Likewise. (CPU_HAS_SEQ): New macro. (macro2) <M_SEQ_I, M_SNE_I>: Use it. Emit seq/sne and seqi/snei. gas/testsuite/ * gas/mips/octeon.s, gas/mips/octeon.d: Add tests for seq* and sne*. * gas/mips/octeon-ill.s, gas/mips/octeon-ill.s: Add tests for seqi and snei.
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@ -7,6 +7,9 @@
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(OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
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New bit masks and shift counts for cins and exts.
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* mips.h: Document new field descriptors +Q.
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(OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
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2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
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* mips.h (INSN_MACRO): Move it up to the the pinfo macros.
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@ -222,6 +222,8 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US
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#define OP_MASK_CINSPOS 0x1f
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#define OP_SH_CINSLM1 11
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#define OP_MASK_CINSLM1 0x1f
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#define OP_SH_SEQI 6
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#define OP_MASK_SEQI 0x3ff
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/* This structure holds information for a particular instruction. */
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@ -385,6 +387,7 @@ struct mips_opcode
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"+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32.
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"+P" Position field of cins/exts aliasing cins32/exts32. Matches if
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32 <= pos < 64, otherwise skips to next candidate.
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"+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512.
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"+s" Length-minus-one field of cins/exts. Enforces: 0 <= lenm1 < 32.
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"+S" Length-minus-one field of cins32/exts32 or cins/exts aliasing
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cint32/exts32. Enforces non-negative value and that
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@ -406,7 +409,7 @@ struct mips_opcode
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Extension character sequences used so far ("+" followed by the
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following), for quick reference when adding more:
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"1234"
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"ABCDEFGHIPSTX"
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"ABCDEFGHIPQSTX"
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"pstx"
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*/
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