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* ppc.h (PPC_OPCODE_ALTIVEC): New opcode flag for vector unit.

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(PPC_OPERAND_VR): New operand flag for vector registers.
This commit is contained in:
J.T. Conklin
2000-05-03 22:19:45 +00:00
parent 07a135a6bf
commit cf3eb87bef
2 changed files with 13 additions and 0 deletions
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5
include/opcode/ChangeLog
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@@ -1,3 +1,8 @@
2000-05-03 J.T. Conklin <jtc@redback.com>
* ppc.h (PPC_OPCODE_ALTIVEC): New opcode flag for vector unit.
(PPC_OPERAND_VR): New operand flag for vector registers.
2000-05-01 Kazu Hirata <kazu@hxi.com> 2000-05-01 Kazu Hirata <kazu@hxi.com>
* h8300.h (EOP): Add missing initializer. * h8300.h (EOP): Add missing initializer.

8
include/opcode/ppc.h
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@@ -88,6 +88,9 @@ extern const int powerpc_num_opcodes;
/* Opcode is supported as part of the 64-bit bridge. */ /* Opcode is supported as part of the 64-bit bridge. */
#define PPC_OPCODE_64_BRIDGE (0400) #define PPC_OPCODE_64_BRIDGE (0400)
/* Opcode is supported by Altivec Vector Unit */
#define PPC_OPCODE_ALTIVEC (01000)
/* A macro to extract the major opcode from an instruction. */ /* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f) #define PPC_OP(i) (((i) >> 26) & 0x3f)
@@ -221,6 +224,11 @@ extern const struct powerpc_operand powerpc_operands[];
number is allowed). This flag will only be set for a signed number is allowed). This flag will only be set for a signed
operand. */ operand. */
#define PPC_OPERAND_NEGATIVE (04000) #define PPC_OPERAND_NEGATIVE (04000)
/* This operand names a vector unit register. The disassembler
prints these with a leading 'v'. */
#define PPC_OPERAND_VR (010000)
/* The POWER and PowerPC assemblers use a few macros. We keep them /* The POWER and PowerPC assemblers use a few macros. We keep them
with the operands table for simplicity. The macro table is an with the operands table for simplicity. The macro table is an