2012-09-26 Ian Bolton <ian.bolton@arm.com>
Jim MacArthur <jim.macarthur@arm.com> Marcus Shawcroft <marcus.shawcroft@arm.com> Nigel Stephens <nigel.stephens@arm.com> Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> Richard Earnshaw <rearnsha@arm.com> Sofiane Naci <sofiane.naci@arm.com> Tejas Belagod <tejas.belagod@arm.com> Yufeng Zhang <yufeng.zhang@arm.com> * aarch64/Makefile.in: New file. * aarch64/_exit.c: New file. * aarch64/_kill.c: New file. * aarch64/aclocal.m4: Generated. * aarch64/configure: Generated. * aarch64/configure.in: New file. * aarch64/cpu-init/Makefile.in: New file. * aarch64/cpu-init/rdimon-aem-el3.S: New file. * aarch64/crt0.S: New file. * aarch64/elf-rdimon.specs: New file. * aarch64/libcfunc.c: New file. * aarch64/svc.h: New file. * aarch64/syscalls.c: New file. * configure.in: Add AArch64. * configure: Re-generated.
This commit is contained in:
Jeff Johnston
110
libgloss/aarch64/cpu-init/Makefile.in
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110
libgloss/aarch64/cpu-init/Makefile.in
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@@ -0,0 +1,110 @@
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# Copyright (c) 2012 ARM Ltd. All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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# 1. Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# 2. Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution.
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# 3. The name of the company may not be used to endorse or promote
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# products derived from this software without specific prior written
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# permission.
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#
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# THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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# TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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DESTDIR =
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VPATH = @srcdir@ @srcdir@/.. @srcdir@/../..
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srcdir = @srcdir@
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objdir = .
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srcroot = $(srcdir)/../../..
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objroot = $(objdir)/../../..
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prefix = @prefix@
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exec_prefix = @exec_prefix@
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host_alias = @host_alias@
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target_alias = @target_alias@
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bindir = @bindir@
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libdir = @libdir@
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tooldir = $(exec_prefix)/$(target_alias)
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objtype = @objtype@
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INSTALL = @INSTALL@
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INSTALL_PROGRAM = @INSTALL_PROGRAM@
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INSTALL_DATA = @INSTALL_DATA@
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# Multilib support variables.
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# TOP is used instead of MULTI{BUILD,SRC}TOP.
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MULTISRCTOP =
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MULTIBUILDTOP =
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MULTIDIRS =
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MULTISUBDIR =
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MULTIDO = true
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MULTICLEAN = true
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SHELL = /bin/sh
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CC = @CC@
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AS = @AS@
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AR = @AR@
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LD = @LD@
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RANLIB = @RANLIB@
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CPU_INIT_OBJS = rdimon-aem-el3.o
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CPU_INIT_INSTALL = install-cpu-init
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CFLAGS = -g
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# Host specific makefile fragment comes in here.
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@host_makefile_frag@
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.PHONY: all
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all: ${CPU_INIT_OBJS}
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#
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# here's where we build the test programs for each target
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#
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.PHONY: test
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test:
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# Static pattern rule for assembling cpu init files to object files.
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${CPU_INIT_OBJS}: %.o: %.S
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$(CC) $(CFLAGS_FOR_TARGET) $(INCLUDES) -DARM_RDI_MONITOR -o $@ -c $<
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clean mostlyclean:
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rm -f a.out core *.i *.o *-test *.srec *.dis *.x
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distclean maintainer-clean realclean: clean
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rm -f Makefile *~
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.PHONY: install info install-info clean-info
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install: ${CPU_INIT_INSTALL}
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install-cpu-init:
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test -d $(DESTDIR)${tooldir}/lib${MULTISUBDIR}/cpu-init || mkdir $(DESTDIR)${tooldir}/lib${MULTISUBDIR}/cpu-init
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set -e; for x in ${CPU_INIT_OBJS}; do ${INSTALL_DATA} $$x $(DESTDIR)${tooldir}/lib${MULTISUBDIR}/cpu-init/$$x; done
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doc:
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info:
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install-info:
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clean-info:
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Makefile: Makefile.in ../config.status @host_makefile_frag_path@
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$(SHELL) ../config.status --file cpu-init/Makefile
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../config.status: ../configure
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$(SHELL) ../config.status --recheck
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167
libgloss/aarch64/cpu-init/rdimon-aem-el3.S
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167
libgloss/aarch64/cpu-init/rdimon-aem-el3.S
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/* Copyright (c) 2009, 2010, 2011, 2012 ARM Ltd. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. The name of the company may not be used to endorse or promote
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products derived from this software without specific prior written
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permission.
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THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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#include "newlib.h"
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#include "svc.h"
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/* ANSI concatenation macros. */
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#define CONCAT(a, b) CONCAT2(a, b)
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#define CONCAT2(a, b) a ## b
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#ifdef __USER_LABEL_PREFIX__
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#define FUNCTION( name ) CONCAT (__USER_LABEL_PREFIX__, name)
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#else
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#error __USER_LABEL_PREFIX is not defined
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#endif
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.text
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.align 2
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_init_vectors:
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/* Installs a table of exception vectors to catch and handle all
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exceptions by terminating the process with a diagnostic. */
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adr x0, vectors
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msr vbar_el3, x0
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msr vbar_el2, x0
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msr vbar_el1, x0
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ret
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curr_sp0_sync:
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curr_sp0_irq:
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curr_sp0_fiq:
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curr_sp0_serror:
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curr_spx_sync:
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curr_spx_irq:
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curr_spx_fiq:
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curr_spx_serror:
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lower_a64_sync:
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lower_a64_irq:
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lower_a64_fiq:
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lower_a64_serror:
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lower_a32_sync:
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lower_a32_irq:
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lower_a32_fiq:
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lower_a32_serror:
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mov x0, 2
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adr x1, .LC3
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mov x2, 26
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bl FUNCTION (write)
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mov x0, 126
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b FUNCTION (exit) /* Cannot return. */
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.LC3:
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.string "Terminated by exception.\n"
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.macro ventry label
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.align 7
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b \label
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.endm
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.align 7
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/* AArch64 Exception Model -- 3.5.5 Exception Vectors. */
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vectors:
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/* Current EL with SP0. */
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ventry curr_sp0_sync /* Synchronous */
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ventry curr_sp0_irq /* Irq/vIRQ */
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ventry curr_sp0_fiq /* Fiq/vFIQ */
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ventry curr_sp0_serror /* SError/VSError */
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/* Current EL with SPx. */
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ventry curr_spx_sync /* Synchronous */
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ventry curr_spx_irq /* IRQ/vIRQ */
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ventry curr_spx_fiq /* FIQ/vFIQ */
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ventry curr_spx_serror /* SError/VSError */
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/* Lower EL using AArch64. */
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ventry lower_a64_sync /* Synchronous */
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ventry lower_a64_irq /* IRQ/vIRQ */
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ventry lower_a64_fiq /* FIQ/vFIQ */
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ventry lower_a64_serror /* SError/VSError */
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/* Lower EL using AArch32. */
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ventry lower_a32_sync /* Synchronous */
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ventry lower_a32_irq /* IRQ/vIRQ */
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ventry lower_a32_fiq /* FIQ/vFIQ */
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ventry lower_a32_serror /* SError/VSError */
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.text
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.align 2
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_flat_map:
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/* Page table setup (identity mapping). */
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adrp x0, ttb
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add x0, x0, :lo12:ttb
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msr ttbr0_el3, x0
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adr x1, . /* phys address */
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bic x1, x1, #(1 << 30) - 1 /* 1GB block alignment */
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add x2, x0, x1, lsr #(30 - 3) /* offset in level 1 page
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table */
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mov x3, #0x401 /* page table attributes
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(AF, block) */
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orr x1, x1, x3
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mov x3, #(1 << 30) /* 1GB block */
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str x1, [x2], #8 /* 1st GB */
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add x1, x1, x3
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str x1, [x2] /* 2nd GB */
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/* Setup/enable the MMU. */
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/* RES1, RES1, 40-bit PA, 39-bit VA, inner/outer cacheable WB */
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ldr x0, =(1 << 31) | (1 << 23) | (2 << 16) | 25 | (3 << 10) | (3 << 8)
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msr tcr_el3, x0
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mov x0, #0xee /* Inner/outer cacheable WB */
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msr mair_el3, x0
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isb
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mrs x0, sctlr_el3
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ldr x1, =0x100d /* bits I(12) SA(3) C(2) M(0) */
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bic x0, x0, #2 /* clear bit A(1) */
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orr x0, x0, x1 /* set bits */
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msr sctlr_el3, x0
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isb
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ret
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.data
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.align 12
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ttb:
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.space 4096, 0
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.text
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.align 2
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.global FUNCTION (_cpu_init_hook)
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.type FUNCTION (_cpu_init_hook), %function
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FUNCTION (_cpu_init_hook):
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sub sp, sp, #16
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str x30, [sp, xzr]
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bl _init_vectors
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bl _flat_map
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ldr x30, [sp, xzr]
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add sp, sp, #16
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ret
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.size FUNCTION (_cpu_init_hook), .-FUNCTION (_cpu_init_hook)
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