* arm.h: Remove all old content. Replace with architecture defines
from gas/config/tc-arm.c.
This commit is contained in:
Richard Earnshaw
parent
63b9dcc472
commit
cc304ef63e
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@ -1,3 +1,8 @@
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2004-07-16 Richard Earnshaw <rearnsha@arm.com>
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* arm.h: Remove all old content. Replace with architecture defines
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from gas/config/tc-arm.c.
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2004-07-09 Andreas Schwab <schwab@suse.de>
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2004-07-09 Andreas Schwab <schwab@suse.de>
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* m68k.h: Fix comment.
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* m68k.h: Fix comment.
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@ -1,294 +1,91 @@
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/* ARM opcode list.
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/* ARM assembler/disassembler support.
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Copyright 1989, 1991 Free Software Foundation, Inc.
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Copyright 2004 Free Software Foundation, Inc.
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This file is part of GDB and GAS.
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This file is part of GDB and GAS.
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GDB and GAS are free software; you can redistribute it and/or modify
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GDB and GAS are free software; you can redistribute it and/or
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it under the terms of the GNU General Public License as published by
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modify it under the terms of the GNU General Public License as
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the Free Software Foundation; either version 1, or (at your option)
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published by the Free Software Foundation; either version 1, or (at
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any later version.
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your option) any later version.
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GDB and GAS are distributed in the hope that it will be useful,
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GDB and GAS are distributed in the hope that it will be useful, but
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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GNU General Public License for more details.
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General Public License for more details.
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You should have received a copy of the GNU General Public License
|
You should have received a copy of the GNU General Public License
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along with GDB or GAS; see the file COPYING. If not, write to
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along with GDB or GAS; see the file COPYING. If not, write to the
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the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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02111-1307, USA. */
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/* types of instruction (encoded in bits 26 and 27 of the instruction) */
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/* The following bitmasks control CPU extensions: */
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#define ARM_EXT_V1 0x00000001 /* All processors (core set). */
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#define ARM_EXT_V2 0x00000002 /* Multiply instructions. */
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#define ARM_EXT_V2S 0x00000004 /* SWP instructions. */
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#define ARM_EXT_V3 0x00000008 /* MSR MRS. */
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#define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */
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#define ARM_EXT_V4 0x00000020 /* Allow half word loads. */
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#define ARM_EXT_V4T 0x00000040 /* Thumb v1. */
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#define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
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#define ARM_EXT_V5T 0x00000100 /* Thumb v2. */
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#define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */
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#define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */
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#define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */
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#define ARM_EXT_V6 0x00001000 /* ARM V6. */
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#define TYPE_ARITHMETIC 0
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/* Co-processor space extensions. */
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#define TYPE_LDR_STR 1
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#define ARM_CEXT_XSCALE 0x00800000 /* Allow MIA etc. */
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#define TYPE_BLOCK_BRANCH 2
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#define ARM_CEXT_MAVERICK 0x00400000 /* Use Cirrus/DSP coprocessor. */
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#define TYPE_SWI 3
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#define ARM_CEXT_IWMMXT 0x00200000 /* Intel Wireless MMX technology coprocessor. */
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/* bit 25 decides whether an instruction is a block move or a branch */
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/* Architectures are the sum of the base and extensions. The ARM ARM (rev E)
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#define SUBTYPE_BLOCK 0
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defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
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#define SUBTYPE_BRANCH 1
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ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add
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three more to cover cores prior to ARM6. Finally, there are cores which
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implement further extensions in the co-processor space. */
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#define ARM_ARCH_V1 ARM_EXT_V1
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#define ARM_ARCH_V2 (ARM_ARCH_V1 | ARM_EXT_V2)
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#define ARM_ARCH_V2S (ARM_ARCH_V2 | ARM_EXT_V2S)
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#define ARM_ARCH_V3 (ARM_ARCH_V2S | ARM_EXT_V3)
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#define ARM_ARCH_V3M (ARM_ARCH_V3 | ARM_EXT_V3M)
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#define ARM_ARCH_V4xM (ARM_ARCH_V3 | ARM_EXT_V4)
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#define ARM_ARCH_V4 (ARM_ARCH_V3M | ARM_EXT_V4)
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#define ARM_ARCH_V4TxM (ARM_ARCH_V4xM | ARM_EXT_V4T)
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#define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_EXT_V4T)
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#define ARM_ARCH_V5xM (ARM_ARCH_V4xM | ARM_EXT_V5)
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#define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5)
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#define ARM_ARCH_V5TxM (ARM_ARCH_V5xM | ARM_EXT_V4T | ARM_EXT_V5T)
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#define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_EXT_V4T | ARM_EXT_V5T)
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#define ARM_ARCH_V5TExP (ARM_ARCH_V5T | ARM_EXT_V5ExP)
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#define ARM_ARCH_V5TE (ARM_ARCH_V5TExP | ARM_EXT_V5E)
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#define ARM_ARCH_V5TEJ (ARM_ARCH_V5TE | ARM_EXT_V5J)
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#define ARM_ARCH_V6 (ARM_ARCH_V5TEJ | ARM_EXT_V6)
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/* codes to distinguish the arithmetic instructions */
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/* Processors with specific extensions in the co-processor space. */
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#define ARM_ARCH_XSCALE (ARM_ARCH_V5TE | ARM_CEXT_XSCALE)
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#define ARM_ARCH_IWMMXT (ARM_ARCH_XSCALE | ARM_CEXT_IWMMXT)
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#define OPCODE_AND 0
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#define FPU_FPA_EXT_V1 0x80000000 /* Base FPA instruction set. */
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#define OPCODE_EOR 1
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#define FPU_FPA_EXT_V2 0x40000000 /* LFM/SFM. */
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#define OPCODE_SUB 2
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#define FPU_VFP_EXT_NONE 0x20000000 /* Use VFP word-ordering. */
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#define OPCODE_RSB 3
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#define FPU_VFP_EXT_V1xD 0x10000000 /* Base VFP instruction set. */
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#define OPCODE_ADD 4
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#define FPU_VFP_EXT_V1 0x08000000 /* Double-precision insns. */
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#define OPCODE_ADC 5
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#define FPU_VFP_EXT_V2 0x04000000 /* ARM10E VFPr1. */
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#define OPCODE_SBC 6
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#define FPU_MAVERICK 0x02000000 /* Cirrus Maverick. */
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#define OPCODE_RSC 7
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#define FPU_NONE 0
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#define OPCODE_TST 8
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#define OPCODE_TEQ 9
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#define OPCODE_CMP 10
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#define OPCODE_CMN 11
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#define OPCODE_ORR 12
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#define OPCODE_MOV 13
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#define OPCODE_BIC 14
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#define OPCODE_MVN 15
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/* condition codes */
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#define FPU_ARCH_FPE FPU_FPA_EXT_V1
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#define FPU_ARCH_FPA (FPU_ARCH_FPE | FPU_FPA_EXT_V2)
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#define COND_EQ 0
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#define FPU_ARCH_VFP FPU_VFP_EXT_NONE
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#define COND_NE 1
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#define FPU_ARCH_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_NONE)
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#define COND_CS 2
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#define FPU_ARCH_VFP_V1 (FPU_ARCH_VFP_V1xD | FPU_VFP_EXT_V1)
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#define COND_CC 3
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#define FPU_ARCH_VFP_V2 (FPU_ARCH_VFP_V1 | FPU_VFP_EXT_V2)
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#define COND_MI 4
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#define COND_PL 5
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#define COND_VS 6
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#define COND_VC 7
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#define COND_HI 8
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#define COND_LS 9
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#define COND_GE 10
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#define COND_LT 11
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#define COND_GT 12
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#define COND_LE 13
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#define COND_AL 14
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#define COND_NV 15
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/* Describes the format of an ARM machine instruction */
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#define FPU_ARCH_MAVERICK FPU_MAVERICK
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struct generic_fmt {
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/* Some useful combinations: */
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unsigned rest :25; /* the rest of the instruction */
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#define ARM_ANY 0x0000ffff /* Any basic core. */
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unsigned subtype :1; /* used to decide between block and branch */
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#define ARM_ALL 0x00ffffff /* Any core + co-processor */
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unsigned type :2; /* one of TYPE_* */
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#define CPROC_ANY 0x00ff0000 /* Any co-processor */
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unsigned cond :4; /* one of COND_* defined above */
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#define FPU_ANY 0xff000000 /* Note this is ~ARM_ALL. */
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};
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struct arith_fmt {
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unsigned operand2 :12; /* #nn or rn or rn shift #m or rn shift rm */
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unsigned dest :4; /* place where the answer goes */
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unsigned operand1 :4; /* first operand to instruction */
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unsigned set :1; /* == 1 means set processor flags */
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unsigned opcode :4; /* one of OPCODE_* defined above */
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unsigned immed :1; /* operand2 is an immediate value */
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unsigned type :2; /* == TYPE_ARITHMETIC */
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unsigned cond :4; /* one of COND_* defined above */
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};
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struct ldr_str_fmt {
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unsigned offset :12; /* #nn or rn or rn shift #m */
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unsigned reg :4; /* destination for LDR, source for STR */
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unsigned base :4; /* base register */
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unsigned is_load :1; /* == 1 for LDR */
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unsigned writeback :1; /* == 1 means write back (base+offset) into base */
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unsigned byte :1; /* == 1 means byte access else word */
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unsigned up :1; /* == 1 means add offset else subtract it */
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unsigned pre_index :1; /* == 1 means [a,b] form else [a],b form */
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unsigned immed :1; /* == 0 means immediate offset */
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unsigned type :2; /* == TYPE_LDR_STR */
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unsigned cond :4; /* one of COND_* defined above */
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};
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struct block_fmt {
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unsigned mask :16; /* register mask */
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unsigned base :4; /* register used as base of move */
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unsigned is_load :1; /* == 1 for LDM */
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unsigned writeback :1; /* == 1 means update base after move */
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unsigned set :1; /* == 1 means set flags in pc if included in mask */
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unsigned increment :1; /* == 1 means increment base register */
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unsigned before :1; /* == 1 means inc/dec before each move */
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unsigned is_block :1; /* == SUBTYPE_BLOCK */
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unsigned type :2; /* == TYPE_BLOCK_BRANCH */
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unsigned cond :4; /* one of COND_* defined above */
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};
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struct branch_fmt {
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unsigned dest :24; /* destination of the branch */
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unsigned link :1; /* branch with link (function call) */
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unsigned is_branch :1; /* == SUBTYPE_BRANCH */
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unsigned type :2; /* == TYPE_BLOCK_BRANCH */
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unsigned cond :4; /* one of COND_* defined above */
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};
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#define ROUND_N 0
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#define ROUND_P 1
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#define ROUND_M 2
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#define ROUND_Z 3
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#define FLOAT2_MVF 0
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#define FLOAT2_MNF 1
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#define FLOAT2_ABS 2
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#define FLOAT2_RND 3
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#define FLOAT2_SQT 4
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#define FLOAT2_LOG 5
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#define FLOAT2_LGN 6
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#define FLOAT2_EXP 7
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#define FLOAT2_SIN 8
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#define FLOAT2_COS 9
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#define FLOAT2_TAN 10
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#define FLOAT2_ASN 11
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#define FLOAT2_ACS 12
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#define FLOAT2_ATN 13
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#define FLOAT3_ADF 0
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#define FLOAT3_MUF 1
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#define FLOAT3_SUF 2
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#define FLOAT3_RSF 3
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#define FLOAT3_DVF 4
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#define FLOAT3_RDF 5
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#define FLOAT3_POW 6
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#define FLOAT3_RPW 7
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#define FLOAT3_RMF 8
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#define FLOAT3_FML 9
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#define FLOAT3_FDV 10
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#define FLOAT3_FRD 11
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#define FLOAT3_POL 12
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struct float2_fmt {
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unsigned operand2 :3; /* second operand */
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unsigned immed :1; /* == 1 if second operand is a constant */
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unsigned pad1 :1; /* == 0 */
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unsigned rounding :2; /* ROUND_* */
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unsigned is_double :1; /* == 1 if precision is double (only if not extended) */
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unsigned pad2 :4; /* == 1 */
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unsigned dest :3; /* destination */
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unsigned is_2_op :1; /* == 1 if 2 operand ins */
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unsigned operand1 :3; /* first operand (only of is_2_op == 0) */
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unsigned is_extended :1; /* == 1 if precision is extended */
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unsigned opcode :4; /* FLOAT2_* or FLOAT3_* depending on is_2_op */
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unsigned must_be_2 :2; /* == 2 */
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unsigned type :2; /* == TYPE_SWI */
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unsigned cond :4; /* COND_* */
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};
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struct swi_fmt {
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unsigned argument :24; /* argument to SWI (syscall number) */
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unsigned must_be_3 :2; /* == 3 */
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unsigned type :2; /* == TYPE_SWI */
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unsigned cond :4; /* one of COND_* defined above */
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};
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union insn_fmt {
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struct generic_fmt generic;
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struct arith_fmt arith;
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struct ldr_str_fmt ldr_str;
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struct block_fmt block;
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struct branch_fmt branch;
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struct swi_fmt swi;
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unsigned long ins;
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};
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struct opcode {
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unsigned long value, mask; /* recognise instruction if (op&mask)==value */
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char *assembler; /* how to disassemble this instruction */
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};
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/* format of the assembler string :
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%% %
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%<bitfield>d print the bitfield in decimal
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%<bitfield>x print the bitfield in hex
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%<bitfield>r print as an ARM register
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%<bitfield>f print a floating point constant if >7 else an fp register
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%c print condition code (always bits 28-31)
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%P print floating point precision in arithmetic insn
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%Q print floating point precision in ldf/stf insn
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%R print floating point rounding mode
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%<bitnum>'c print specified char iff bit is one
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%<bitnum>`c print specified char iff bit is zero
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%<bitnum>?ab print a if bit is one else print b
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%p print 'p' iff bits 12-15 are 15
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%o print operand2 (immediate or register + shift)
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%a print address for ldr/str instruction
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%b print branch destination
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%A print address for ldc/stc/ldf/stf instruction
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%m print register mask for ldm/stm instruction
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*/
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static struct opcode opcodes[] = {
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/* ARM instructions */
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0x00000090, 0x0fe000f0, "mul%20's %12-15r, %16-19r, %0-3r",
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0x00200090, 0x0fe000f0, "mla%20's %12-15r, %16-19r, %0-3r, %8-11r",
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0x00000000, 0x0de00000, "and%c%20's %12-15r, %16-19r, %o",
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0x00200000, 0x0de00000, "eor%c%20's %12-15r, %16-19r, %o",
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0x00400000, 0x0de00000, "sub%c%20's %12-15r, %16-19r, %o",
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0x00600000, 0x0de00000, "rsb%c%20's %12-15r, %16-19r, %o",
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0x00800000, 0x0de00000, "add%c%20's %12-15r, %16-19r, %o",
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0x00a00000, 0x0de00000, "adc%c%20's %12-15r, %16-19r, %o",
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0x00c00000, 0x0de00000, "sbc%c%20's %12-15r, %16-19r, %o",
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0x00e00000, 0x0de00000, "rsc%c%20's %12-15r, %16-19r, %o",
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0x01000000, 0x0de00000, "tst%c%p %16-19r, %o",
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0x01200000, 0x0de00000, "teq%c%p %16-19r, %o",
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0x01400000, 0x0de00000, "cmp%c%p %16-19r, %o",
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0x01600000, 0x0de00000, "cmn%c%p %16-19r, %o",
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0x01800000, 0x0de00000, "orr%c%20's %12-15r, %16-19r, %o",
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0x01a00000, 0x0de00000, "mov%c%20's %12-15r, %o",
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0x01c00000, 0x0de00000, "bic%c%20's %12-15r, %16-19r, %o",
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0x01e00000, 0x0de00000, "mvn%c%20's %12-15r, %o",
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0x04000000, 0x0c100000, "str%c%22'b %12-15r, %a",
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0x04100000, 0x0c100000, "ldr%c%22'b %12-15r, %a",
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0x08000000, 0x0e100000, "stm%c%23?id%24?ba %16-19r%22`!, %m",
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0x08100000, 0x0e100000, "ldm%c%23?id%24?ba %16-19r%22`!, %m%22'^",
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0x0a000000, 0x0e000000, "b%c%24'l %b",
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0x0f000000, 0x0f000000, "swi%c %0-23x",
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/* Floating point coprocessor instructions */
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0x0e000100, 0x0ff08f10, "adf%c%P%R %12-14f, %16-18f, %0-3f",
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0x0e100100, 0x0ff08f10, "muf%c%P%R %12-14f, %16-18f, %0-3f",
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0x0e200100, 0x0ff08f10, "suf%c%P%R %12-14f, %16-18f, %0-3f",
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0x0e300100, 0x0ff08f10, "rsf%c%P%R %12-14f, %16-18f, %0-3f",
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0x0e400100, 0x0ff08f10, "dvf%c%P%R %12-14f, %16-18f, %0-3f",
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0x0e500100, 0x0ff08f10, "rdf%c%P%R %12-14f, %16-18f, %0-3f",
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0x0e600100, 0x0ff08f10, "pow%c%P%R %12-14f, %16-18f, %0-3f",
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0x0e700100, 0x0ff08f10, "rpw%c%P%R %12-14f, %16-18f, %0-3f",
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|
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0x0e800100, 0x0ff08f10, "rmf%c%P%R %12-14f, %16-18f, %0-3f",
|
|
||||||
0x0e900100, 0x0ff08f10, "fml%c%P%R %12-14f, %16-18f, %0-3f",
|
|
||||||
0x0ea00100, 0x0ff08f10, "fdv%c%P%R %12-14f, %16-18f, %0-3f",
|
|
||||||
0x0eb00100, 0x0ff08f10, "frd%c%P%R %12-14f, %16-18f, %0-3f",
|
|
||||||
0x0ec00100, 0x0ff08f10, "pol%c%P%R %12-14f, %16-18f, %0-3f",
|
|
||||||
0x0e008100, 0x0ff08f10, "mvf%c%P%R %12-14f, %0-3f",
|
|
||||||
0x0e108100, 0x0ff08f10, "mnf%c%P%R %12-14f, %0-3f",
|
|
||||||
0x0e208100, 0x0ff08f10, "abs%c%P%R %12-14f, %0-3f",
|
|
||||||
0x0e308100, 0x0ff08f10, "rnd%c%P%R %12-14f, %0-3f",
|
|
||||||
0x0e408100, 0x0ff08f10, "sqt%c%P%R %12-14f, %0-3f",
|
|
||||||
0x0e508100, 0x0ff08f10, "log%c%P%R %12-14f, %0-3f",
|
|
||||||
0x0e608100, 0x0ff08f10, "lgn%c%P%R %12-14f, %0-3f",
|
|
||||||
0x0e708100, 0x0ff08f10, "exp%c%P%R %12-14f, %0-3f",
|
|
||||||
0x0e808100, 0x0ff08f10, "sin%c%P%R %12-14f, %0-3f",
|
|
||||||
0x0e908100, 0x0ff08f10, "cos%c%P%R %12-14f, %0-3f",
|
|
||||||
0x0ea08100, 0x0ff08f10, "tan%c%P%R %12-14f, %0-3f",
|
|
||||||
0x0eb08100, 0x0ff08f10, "asn%c%P%R %12-14f, %0-3f",
|
|
||||||
0x0ec08100, 0x0ff08f10, "acs%c%P%R %12-14f, %0-3f",
|
|
||||||
0x0ed08100, 0x0ff08f10, "atn%c%P%R %12-14f, %0-3f",
|
|
||||||
0x0e000110, 0x0ff00f1f, "flt%c%P%R %16-18f, %12-15r",
|
|
||||||
0x0e100110, 0x0fff0f98, "fix%c%R %12-15r, %0-2f",
|
|
||||||
0x0e200110, 0x0fff0fff, "wfs%c %12-15r",
|
|
||||||
0x0e300110, 0x0fff0fff, "rfs%c %12-15r",
|
|
||||||
0x0e400110, 0x0fff0fff, "wfc%c %12-15r",
|
|
||||||
0x0e500110, 0x0fff0fff, "rfc%c %12-15r",
|
|
||||||
0x0e90f110, 0x0ff8fff0, "cmf%c %16-18f, %0-3f",
|
|
||||||
0x0eb0f110, 0x0ff8fff0, "cnf%c %16-18f, %0-3f",
|
|
||||||
0x0ed0f110, 0x0ff8fff0, "cmfe%c %16-18f, %0-3f",
|
|
||||||
0x0ef0f110, 0x0ff8fff0, "cnfe%c %16-18f, %0-3f",
|
|
||||||
0x0c000100, 0x0e100f00, "stf%c%Q %12-14f, %A",
|
|
||||||
0x0c100100, 0x0e100f00, "ldf%c%Q %12-14f, %A",
|
|
||||||
/* Generic coprocessor instructions */
|
|
||||||
0x0e000000, 0x0f000010, "cdp%c %8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}",
|
|
||||||
0x0e000010, 0x0f100010, "mrc%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}",
|
|
||||||
0x0e100010, 0x0f100010, "mcr%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}",
|
|
||||||
0x0c000000, 0x0e100000, "stc%c%22`l %8-11d, cr%12-15d, %A",
|
|
||||||
0x0c100000, 0x0e100000, "ldc%c%22`l %8-11d, cr%12-15d, %A",
|
|
||||||
/* the rest */
|
|
||||||
0x00000000, 0x00000000, "undefined instruction %0-31x",
|
|
||||||
};
|
|
||||||
#define N_OPCODES (sizeof opcodes / sizeof opcodes[0])
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue