2001-10-17 Chris Demetriou <cgd@broadcom.com>
* mips.h: Sort coprocessor instruction argument characters
       in comment, add a few more words of description for "H".
			
			
This commit is contained in:
		| @@ -1,3 +1,8 @@ | ||||
| 2001-10-17  Chris Demetriou  <cgd@broadcom.com> | ||||
|  | ||||
| 	* mips.h: Sort coprocessor instruction argument characters | ||||
| 	in comment, add a few more words of description for "H". | ||||
|  | ||||
| 2001-10-17  Chris Demetriou  <cgd@broadcom.com> | ||||
|  | ||||
| 	* mips.h (INSN_SB1): New cpu-specific instruction bit. | ||||
|   | ||||
| @@ -209,8 +209,8 @@ struct mips_opcode | ||||
|    Coprocessor instructions: | ||||
|    "E" 5 bit target register (OP_*_RT) | ||||
|    "G" 5 bit destination register (OP_*_RD) | ||||
|    "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) | ||||
|    "P" 5 bit performance-monitor register (OP_*_PERFREG) | ||||
|    "H" 3 bit sel field (OP_*_SEL) | ||||
|  | ||||
|    Macro instructions: | ||||
|    "A" General 32 bit expression | ||||
|   | ||||
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