Add support for ARC to libgloss
ChangeLog: 2015-11-12 Anton Kolesov <Anton.Kolesov@synopsys.com> * configure.in: Add ARC support to libgloss. * configure: Regenerate. libgloss/ChangeLog: 2015-11-12 Anton Kolesov <Anton.Kolesov@synopsys.com> * configure: Add ARC support. * configure.in: Likewise. * arc/Makefile.in: Likewise. * arc/aclocal.m4: Likewise. * arc/configure: Likewise. * arc/configure.in: Likewise. * arc/crt0.S: Likewise. * arc/libcfunc.c: Likewise. * arc/nsim-syscall.h: Likewise. * arc/nsim-syscalls.c: Likewise. * arc/nsim.specs: Likewise. * arc/sbrk.c: Likewise.
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Anton Kolesov
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Corinna Vinschen
Corinna Vinschen
parent
e945a19cb2
commit
acdfcb0a0a
241
libgloss/arc/crt0.S
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241
libgloss/arc/crt0.S
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/*
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Copyright (c) 2015, Synopsys, Inc. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1) Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2) Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3) Neither the name of the Synopsys, Inc., nor the names of its contributors
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may be used to endorse or promote products derived from this software
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without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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The startup code for the ARC family of processors does the following before
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transferring control to user defined main label:
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1. Set sp to __stack_top (link time variable)
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2. Set fp to zero
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3. Zero out the bss section (for uninitialized globals)
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After returning from main, the processor is halted and the pipeline is
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flushed out.
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We expect argc in r0 and argv in r1. These are saved in r13 / r14 during
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the initialization code.
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*/
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.file "crt0.S"
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.extern main
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#if defined (__EM__) || defined (__HS__)
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.section .ivt, "a", @progbits
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; handler's name, type, number,name, offset in IVT (hex/dec)
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.word __start ; exception 0 program entry point 0x0 0
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.word memory_error ; exception 1 memory_error 0x4 4
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.word instruction_error ; exception 2 instruction_error 0x8 8
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.word EV_MachineCheck ; exception 3 EV_MachineCheck 0xC 12
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.word EV_TLBMissI ; exception 4 EV_TLBMissI 0x10 16
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.word EV_TLBMissD ; exception 5 EV_TLBMissD 0x14 20
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.word EV_ProtV ; exception 6 EV_ProtV 0x18 24
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.word EV_PrivilegeV ; exception 7 EV_PrivilegeV 0x1C 28
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.word EV_SWI ; exception 8 EV_SWI 0x20 32
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.word EV_Trap ; exception 9 EV_Trap 0x24 36
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.word EV_Extension ; exception 10 EV_Extension 0x28 40
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.word EV_DivZero ; exception 11 EV_DivZero 0x2C 44
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.word EV_DCError ; exception 12 EV_DCError 0x30 48
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.word EV_Malignedr ; exception 13 EV_Maligned 0x34 52
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.word _exit_halt ; exception 14 unused 0x38 56
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.word _exit_halt ; exception 15 unused 0x3C 60
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.word IRQ_Timer0 ; IRQ 16 Timer 0 0x40 64
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.word IRQ_Timer1 ; IRQ 17 Timer 1 0x44 68
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.word IRQ_18 ; IRQ 18 0x48 72
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.word IRQ_19 ; IRQ 19 0x4C 76
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.word IRQ_20 ; IRQ 20 0x50 80
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.section .text.__startup, "ax", @progbits
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#else
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.text
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#endif
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.global __start
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.type __start, @function
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#ifdef __ARC601__
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; Startup code for the ARC601 processor
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__start:
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mov gp, @__SDATA_BEGIN__
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mov sp, @__stack_top ; Point to top of stack
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mov r5, 0 ; Zero value
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mov_s r2, @__sbss_start ; r2 = start of the bss section
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sub r3, @_end, r2 ; r3 = size of the bss section in bytes
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asr_s r3, r3
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asr_s r3, r3 ; r3 = size of bss in words
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.Lbss_loop:
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cmp r3, 0xff ; Check for max lp_count
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mov.le lp_count, r3
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mov.gt lp_count, 0xff
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lpnz 2f ; Loop to zero bss
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st.ab r5,[r2, 4] ; Write word of zeros
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nop
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2:
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sub.f r3, r3, 0xff ; Decrement word count
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jp .Lbss_loop
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#else /* __ARC601__ */
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; Startup code for the ARC600, ARC700 and ARCv2 processors
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; NOTE: The following restrictions apply on zero overhead loops (other
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; restrictions are not pertinent to this code)
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; - loop end should be 4 instruction words away from the lp_count setting
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; instruction
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; - loop body should have at least two instruction words
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__start:
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#if defined (__HS__)
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; Allow unaligned accesses.
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lr r2, [0xA]
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bset r2, r2, 19
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flag r2
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#endif
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mov gp, @__SDATA_BEGIN__
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mov_s r2, @__sbss_start ; r2 = start of the bss section
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sub r3, @_end, r2 ; r3 = size of the bss section in bytes
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; set up the loop counter register to the size (in words) of the bss section
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asr.f lp_count, r3, 2
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#if defined (__ARC600__)
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; loop to zero out the bss. Enter loop only if lp_count != 0
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lpnz @.Lend_zbss
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add r3, pcl, 20
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sr r3, [2] ; LP_END
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; initialize stack pointer, and this instruction has 2 words
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mov sp, @__stack_top
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mov_s r3, 0
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st.ab r3, [r2, 4] ; zero out the word
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.Lend_zbss:
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#else
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mov sp, @__stack_top ; initialize stack pointer
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mov_s r3,0
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; loop to zero out the bss. Enter loop only if lp_count != 0
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lpnz @.Lend_zbss
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st.ab r3,[r2, 4] ; zero out the word
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nop
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.Lend_zbss:
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#endif
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#endif /* !__ARC601__ */
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; Some targets use the .init and .fini sections to create constructors and
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; destructors, and for these targets we need to call the _init function and
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; arrange for _fini to be called at program exit.
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mov_s r13, r0
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mov_s r14, r1
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; calling atexit drags in malloc, so instead poke the function
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; address directly into the reent structure
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ld r1, [gp, @_impure_ptr@sda]
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mov_s r0, @_fini
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add r1, r1, 0x14c ; &_GLOBAL_REENT->atexit0
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st r1, [r1, -4] ; _GLOBAL_REENT->atexit
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st_s r0, [r1, 8] ; _GLOBAL_REENT->atexit0._fns[0]
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mov_s r0, 1
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st_s r0, [r1, 4] ; _GLOBAL_REENT->atexit0._ind
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; branch to _init
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#if defined (__EM__) || defined (__HS__)
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jl @_init
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#else
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bl @_init
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#endif
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mov_s r0, r13
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mov_s r1, r14
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; branch to main
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#if defined (__EM__) || defined (__HS__)
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mov fp,0 ; initialize frame pointer
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jl @main
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#else
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bl.d @main
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mov fp, 0 ; initialize frame pointer
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#endif
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; r0 contains exit code
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j @exit
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#if defined (__EM__) || defined (__HS__)
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; ARCv2 default interrupt routines, defined as weak symbols.
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; Default implementation halts the core. To conserve code size those symbols
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; share a single implementation, however as a downside debugger and
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; disassembler will not be able to distinguish one from another.
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.weak memory_error
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.weak instruction_error
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.weak EV_MachineCheck
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.weak EV_TLBMissI
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.weak EV_TLBMissD
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.weak EV_ProtV
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.weak EV_PrivilegeV
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.weak EV_SWI
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.weak EV_Trap
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.weak EV_Extension
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.weak EV_DivZero
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.weak EV_DCError
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.weak EV_Malignedr
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.weak IRQ_Timer0
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.weak IRQ_Timer1
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.weak IRQ_18
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.weak IRQ_19
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.weak IRQ_20
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.balign 4
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memory_error :
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instruction_error :
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EV_MachineCheck :
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EV_TLBMissI :
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EV_TLBMissD :
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EV_ProtV :
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EV_PrivilegeV :
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EV_SWI :
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EV_Trap :
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EV_Extension :
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EV_DivZero :
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EV_DCError :
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EV_Malignedr :
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IRQ_Timer0 :
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IRQ_Timer1 :
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IRQ_18 :
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IRQ_19 :
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IRQ_20 :
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.Lloop_halt:
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flag 0x01
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nop
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b .Lloop_halt
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nop
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#endif
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.section .text._exit_halt,"ax",@progbits
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.global _exit_halt
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.type _exit_halt, @function
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_exit_halt:
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; r0 contains exit code
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flag 0x01
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nop
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nop ; ARCompact requires 3 nops after flag 1
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nop
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b @_exit_halt
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nop
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