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fhandler_proc.cc(format_proc_cpuinfo): fix cache size

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Fix cache size return code handling and make AMD/Intel code common.
This commit is contained in:
Brian Inglis 2019-10-07 10:22:58 -06:00 committed by Ken Brown
parent e06f2fbde7
commit acc8849f84
1 changed files with 18 additions and 27 deletions
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45
winsup/cygwin/fhandler_proc.cc
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@ -744,6 +744,8 @@ format_proc_cpuinfo (void *, char *&destbuf)
int cache_size = -1, int cache_size = -1,
clflush = 64, clflush = 64,
cache_alignment = 64; cache_alignment = 64;
long (*get_cpu_cache) (int, uint32_t) = NULL;
uint32_t max;
if (features1 & (1 << 19)) /* CLFSH */ if (features1 & (1 << 19)) /* CLFSH */
clflush = ((extra_info >> 8) & 0xff) << 3; clflush = ((extra_info >> 8) & 0xff) << 3;
if (is_intel && family == 15) if (is_intel && family == 15)
@ -751,45 +753,34 @@ format_proc_cpuinfo (void *, char *&destbuf)
if (is_intel) if (is_intel)
{ {
extern long get_cpu_cache_intel (int sysc, uint32_t maxf); extern long get_cpu_cache_intel (int sysc, uint32_t maxf);
long cs; get_cpu_cache = get_cpu_cache_intel;
max = maxf; /* Intel uses normal cpuid levels */
cs = get_cpu_cache_intel (_SC_LEVEL3_CACHE_SIZE, maxf);
if (cs == -1)
cs = get_cpu_cache_intel (_SC_LEVEL2_CACHE_SIZE, maxf);
if (cs == -1)
{
cs = get_cpu_cache_intel (_SC_LEVEL1_ICACHE_SIZE, maxf);
if (cs != -1)
cache_size = cs;
cs = get_cpu_cache_intel (_SC_LEVEL1_DCACHE_SIZE, maxf);
if (cs != -1)
cache_size += cs;
}
else
cache_size = cs;
if (cache_size != -1)
cache_size >>= 10;
} }
else if (is_amd) else if (is_amd)
{ {
extern long get_cpu_cache_amd (int sysc, uint32_t maxe); extern long get_cpu_cache_amd (int sysc, uint32_t maxe);
get_cpu_cache = get_cpu_cache_amd;
max = maxe; /* AMD uses extended cpuid levels */
}
if (get_cpu_cache)
{
long cs; long cs;
cs = get_cpu_cache_amd (_SC_LEVEL3_CACHE_SIZE, maxe); cs = get_cpu_cache (_SC_LEVEL3_CACHE_SIZE, max);
if (cs == -1) if (cs <= 0)
cs = get_cpu_cache_amd (_SC_LEVEL2_CACHE_SIZE, maxe); cs = get_cpu_cache (_SC_LEVEL2_CACHE_SIZE, max);
if (cs == -1) if (cs <= 0)
{ {
cs = get_cpu_cache_amd (_SC_LEVEL1_ICACHE_SIZE, maxe); cs = get_cpu_cache (_SC_LEVEL1_ICACHE_SIZE, max);
if (cs != -1) if (cs > 0)
cache_size = cs; cache_size = cs;
cs = get_cpu_cache_amd (_SC_LEVEL1_DCACHE_SIZE, maxe); cs = get_cpu_cache (_SC_LEVEL1_DCACHE_SIZE, max);
if (cs != -1) if (cs > 0)
cache_size += cs; cache_size += cs;
} }
else else
cache_size = cs; cache_size = cs;
if (cache_size != -1) if (cache_size > 0)
cache_size >>= 10; cache_size >>= 10;
} }
bufptr += __small_sprintf (bufptr, "cpu family\t: %d\n" bufptr += __small_sprintf (bufptr, "cpu family\t: %d\n"