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(ldmac, stmac): Replace MACREG with MS32 and MD32.

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Nick Clifton 2003-02-21 11:36:59 +00:00
parent 5cd8241242
commit a55f9cd4fa
2 changed files with 50 additions and 44 deletions
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4
include/opcode/ChangeLog
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@ -1,3 +1,7 @@
2003-02-21 Noida D.Venkatasubramanian <dvenkat@noida.hcltech.com>
* h8300.h (ldmac, stmac): Replace MACREG with MS32 and MD32.
2003-01-23 Alan Modra <amodra@bigpond.net.au> 2003-01-23 Alan Modra <amodra@bigpond.net.au>
* m68hc11.h (cpu6812s): Define. * m68hc11.h (cpu6812s): Define.

16
include/opcode/h8300.h
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@ -1,5 +1,5 @@
/* Opcode table for the H8/300 /* Opcode table for the H8/300
Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, 2002 Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, 2002, 2003
Free Software Foundation, Inc. Free Software Foundation, Inc.
Written by Steve Chamberlain <sac@cygnus.com>. Written by Steve Chamberlain <sac@cygnus.com>.
@ -48,7 +48,7 @@ typedef int op_type;
#define L_32 0x04 #define L_32 0x04
#define L_P 0x08 #define L_P 0x08
#define L_24 0x10 #define L_24 0x10
#define MEMRELAX 0x20 /* move insn which may relax */ #define MEMRELAX 0x20 /* Move insn which may relax. */
#define SRC 0x40 #define SRC 0x40
#define DST 0x80 #define DST 0x80
@ -68,8 +68,8 @@ typedef int op_type;
#define IGNORE 0x200000 #define IGNORE 0x200000
#define E 0x400000 /* FIXME: end of nibble sequence? */ #define E 0x400000 /* FIXME: end of nibble sequence? */
#define L_2 0x800000 #define L_2 0x800000
#define B30 0x1000000 /* bit 3 must be low */ #define B30 0x1000000 /* Bit 3 must be low. */
#define B31 0x2000000 /* bit 3 must be high */ #define B31 0x2000000 /* Bit 3 must be high. */
#define CCR 0x4000000 #define CCR 0x4000000
#define ABS 0x8000000 #define ABS 0x8000000
#define ABSJMP 0x10000000 #define ABSJMP 0x10000000
@ -123,6 +123,9 @@ typedef int op_type;
#define RDIND (DST | IND) #define RDIND (DST | IND)
#define RSIND (SRC | IND) #define RSIND (SRC | IND)
#define MS32 (SRC | L_32 | MACREG)
#define MD32 (DST | L_32 | MACREG)
#if 1 #if 1
#define OR8 RS8 /* ??? OR as in One Register? */ #define OR8 RS8 /* ??? OR as in One Register? */
#define OR16 RS16 #define OR16 RS16
@ -316,7 +319,6 @@ struct h8_opcode
#define SL 2 #define SL 2
#define SN 3 #define SN 3
/* FIXME: Lots of insns have "E, 0, 0, 0, 0" in the nibble code sequences. /* FIXME: Lots of insns have "E, 0, 0, 0, 0" in the nibble code sequences.
Methinks the zeroes aren't necessary. Once confirmed, nuke 'em. */ Methinks the zeroes aren't necessary. Once confirmed, nuke 'em. */
@ -596,8 +598,8 @@ const struct h8_opcode h8_opcodes[] =
NEW_SOP(O(O_CLRMAC,SN),1,2,"clrmac"),{{E, 0, 0}},{{0x0,0x1,0xa,0x0,E}} EOP, NEW_SOP(O(O_CLRMAC,SN),1,2,"clrmac"),{{E, 0, 0}},{{0x0,0x1,0xa,0x0,E}} EOP,
NEW_SOP(O(O_MAC,SL),1,2,"mac"),{{RSINC,RDINC,E}},{{0x0,0x1,0x6,0x0,0x6,0xd,B30|RSINC,B30|RDINC,E}} EOP, NEW_SOP(O(O_MAC,SL),1,2,"mac"),{{RSINC,RDINC,E}},{{0x0,0x1,0x6,0x0,0x6,0xd,B30|RSINC,B30|RDINC,E}} EOP,
NEW_SOP(O(O_LDMAC,SL),1,2,"ldmac"),{{RS32,MACREG,E}},{{0x0,0x3,MACREG,RS32,E}} EOP, NEW_SOP(O(O_LDMAC,SL),1,2,"ldmac"),{{RS32,MD32,E}},{{0x0,0x3,MD32,RS32,E}} EOP,
NEW_SOP(O(O_STMAC,SL),1,2,"stmac"),{{MACREG,RD32,E}},{{0x0,0x2,MACREG,RD32,E}} EOP, NEW_SOP(O(O_STMAC,SL),1,2,"stmac"),{{MS32,RD32,E}},{{0x0,0x2,MS32,RD32,E}} EOP,
NEW_SOP(O(O_LDM,SL),0,6,"ldm.l"),{{RSINC, RS32, E}},{{ 0x0,0x1,IGNORE,0x0,0x6,0xD,0x7,IGNORE,E}}EOP, NEW_SOP(O(O_LDM,SL),0,6,"ldm.l"),{{RSINC, RS32, E}},{{ 0x0,0x1,IGNORE,0x0,0x6,0xD,0x7,IGNORE,E}}EOP,
NEW_SOP(O(O_STM,SL),0,6,"stm.l"),{{RS32, RDDEC, E}},{{0x0,0x1,IGNORE,0x0,0x6,0xD,0xF,IGNORE,E}}EOP, NEW_SOP(O(O_STM,SL),0,6,"stm.l"),{{RS32, RDDEC, E}},{{0x0,0x1,IGNORE,0x0,0x6,0xD,0xF,IGNORE,E}}EOP,
{0, 0, 0, NULL, {{0,0,0}}, {{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}}} {0, 0, 0, NULL, {{0,0,0}}, {{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}}}