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bfd:

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2011-12-08  Andrew Pinski  <apinski@cavium.com>
            Adam Nemet  <anemet@caviumnetworks.com>

	* archures.c (bfd_mach_mips_octeon2): New macro
	* bfd-in2.h: Regenerate.
	* cpu-mips.c (I_mipsocteon2): New enum value.
	(arch_info_struct): Add bfd_mach_mips_octeon2.
	* elfxx-mips.c (_bfd_elf_mips_mach): Support E_MIPS_MACH_OCTEON2.
	(mips_set_isa_flags): Add bfd_mach_mips_octeon2.
	(mips_mach_extensions): Add bfd_mach_mips_octeon2.

gas:
2011-12-08  Andrew Pinski  <apinski@cavium.com>
            Adam Nemet  <anemet@caviumnetworks.com>

        * tc-mips.c (CPU_IS_OCTEON): Add Octeon2.
        (mips_cpu_info_table): Add Octeon2.
        * doc/c-mips.texi: Document octeon2 as an acceptable value for -march=.

gas/testsuite:
2011-12-08  Andrew Pinski  <apinski@cavium.com>
            Adam Nemet  <anemet@caviumnetworks.com>

        * gas/mips/mips.exp: Add Octeon2 for an architecture.
        Run octeon2 test.
        * gas/mips/octeon2.d: New file.
        * gas/mips/octeon2.s: New file.

include/opcode:
2011-12-08  Andrew Pinski  <apinski@cavium.com>
            Adam Nemet  <anemet@caviumnetworks.com>

        * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
        (INSN_OCTEON2): New macro.
        (CPU_OCTEON2): New macro.
        (OPCODE_IS_MEMBER): Add Octeon2.

opcodes:
2011-12-08  Andrew Pinski  <apinski@cavium.com>
            Adam Nemet  <anemet@caviumnetworks.com>

	* mips-dis.c (mips_arch_choices): Add Octeon2.
	For "octeon+", just include OcteonP for the insn.
	* mips-opc.c (IOCT): Include Octeon2.
	(IOCTP): Include Octeon2.
	(IOCT2): New macro.
	(mips_builtin_opcodes): Add "laa", "laad", "lac", "lacd", "lad",
	"ladd", "lai", "laid", "las", "lasd", "law", "lawd".
	Move "lbux", "ldx", "lhx", "lwx", and "lwux" up to where the standard
	loads are, and add IOCT2 to them.
	Add "lbx" and "lhux".
	Add "qmac.00", "qmac.01", "qmac.02", "qmac.03", "qmacs.00",
	"qmacs.01", "qmacs.01", "qmacs.02" and "qmacs.03".
	Add "zcb" and "zcbt".
This commit is contained in:
Andrew Pinski 2011-12-08 20:47:27 +00:00
parent 203f973789
commit 9b80fa0f92
2 changed files with 13 additions and 1 deletions
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8
include/opcode/ChangeLog
View File

@ -1,3 +1,11 @@
2011-12-08 Andrew Pinski <apinski@cavium.com>
Adam Nemet <anemet@caviumnetworks.com>
* mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
(INSN_OCTEON2): New macro.
(CPU_OCTEON2): New macro.
(OPCODE_IS_MEMBER): Add Octeon2.
2011-11-29 Andrew Pinski <apinski@cavium.com> 2011-11-29 Andrew Pinski <apinski@cavium.com>
* mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP. * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.

6
include/opcode/mips.h
View File

@ -713,11 +713,12 @@ static const unsigned int mips_isa_table[] =
{ 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff }; { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
/* Masks used for Chip specific instructions. */ /* Masks used for Chip specific instructions. */
#define INSN_CHIP_MASK 0xc3ff0e20 #define INSN_CHIP_MASK 0xc3ff0f20
/* Cavium Networks Octeon instructions. */ /* Cavium Networks Octeon instructions. */
#define INSN_OCTEON 0x00000800 #define INSN_OCTEON 0x00000800
#define INSN_OCTEONP 0x00000200 #define INSN_OCTEONP 0x00000200
#define INSN_OCTEON2 0x00000100
/* Masks used for MIPS-defined ASEs. */ /* Masks used for MIPS-defined ASEs. */
#define INSN_ASE_MASK 0x3c00f010 #define INSN_ASE_MASK 0x3c00f010
@ -825,6 +826,7 @@ static const unsigned int mips_isa_table[] =
#define CPU_LOONGSON_3A 3003 #define CPU_LOONGSON_3A 3003
#define CPU_OCTEON 6501 #define CPU_OCTEON 6501
#define CPU_OCTEONP 6601 #define CPU_OCTEONP 6601
#define CPU_OCTEON2 6502
#define CPU_XLR 887682 /* decimal 'XLR' */ #define CPU_XLR 887682 /* decimal 'XLR' */
/* Test for membership in an ISA including chip specific ISAs. INSN /* Test for membership in an ISA including chip specific ISAs. INSN
@ -863,6 +865,8 @@ static const unsigned int mips_isa_table[] =
&& ((insn)->membership & INSN_OCTEON) != 0) \ && ((insn)->membership & INSN_OCTEON) != 0) \
|| (cpu == CPU_OCTEONP \ || (cpu == CPU_OCTEONP \
&& ((insn)->membership & INSN_OCTEONP) != 0) \ && ((insn)->membership & INSN_OCTEONP) != 0) \
|| (cpu == CPU_OCTEON2 \
&& ((insn)->membership & INSN_OCTEON2) != 0) \
|| (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \ || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \
|| 0) /* Please keep this term for easier source merging. */ || 0) /* Please keep this term for easier source merging. */