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* crt0.S: Add recognition of the e3v5 architecture variant.

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This commit is contained in:
Nick Clifton
2013-02-01 08:29:04 +00:00
parent 118e51be1d
commit 92825fd954
4 changed files with 14 additions and 4 deletions
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5
libgloss/ChangeLog
View File

@@ -1,3 +1,8 @@
2013-02-01 Nick Clifton <nickc@redhat.com>
* v850/crt0.S: Add recognition of the e3v5
architecture variant.
2013-01-18 Marcus Shawcroft <marcus.shawcroft@arm.com> 2013-01-18 Marcus Shawcroft <marcus.shawcroft@arm.com>
* aarch64/Machine.in (RDIMON_SCRIPTS): * aarch64/Machine.in (RDIMON_SCRIPTS):

4
libgloss/v850/crt0.S
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@@ -5,7 +5,7 @@
_start: _start:
#if defined(__v850e__) || defined(__v850e2__) || defined(__v850e2v3__) #if defined(__v850e__) || defined(__v850e2__) || defined(__v850e2v3__) || defined(__v850e3v5__)
movea 255, r0, r20 movea 255, r0, r20
mov 65535, r21 mov 65535, r21
@@ -14,7 +14,7 @@ _start:
mov hilo(__gp), gp mov hilo(__gp), gp
mov hilo(__ctbp), r6 mov hilo(__ctbp), r6
ldsr r6, ctbp ldsr r6, ctbp
#if defined(__v850e2v3__) #if defined(__v850e2v3__) || defined(__v850e3v5__)
// FPU enable // FPU enable
stsr psw, r6 stsr psw, r6
movhi 1, r0, r7 movhi 1, r0, r7

5
newlib/ChangeLog
View File

@@ -1,3 +1,8 @@
2013-02-01 Nick Clifton <nickc@redhat.com>
* libc/sys/sysnecv850/crt0.S: Add recognition of the e3v5
architecture variant.
2013-01-22 Joel Sherrill <joel.sherrill@oarcorp.com> 2013-01-22 Joel Sherrill <joel.sherrill@oarcorp.com>
* libc/include/pthread.h: Add PTHREAD_RWLOCK_INITIALIZER. * libc/include/pthread.h: Add PTHREAD_RWLOCK_INITIALIZER.

4
newlib/libc/sys/sysnecv850/crt0.S
View File

@@ -5,7 +5,7 @@
_start: _start:
#if defined(__v850e__) || defined(__v850e2__) || defined(__v850e2v3__) #if defined(__v850e__) || defined(__v850e2__) || defined(__v850e2v3__) || defined(__v850e3v5__)
movea 255, r0, r20 movea 255, r0, r20
mov 65535, r21 mov 65535, r21
@@ -15,7 +15,7 @@ _start:
mov hilo(__ctbp), r6 mov hilo(__ctbp), r6
ldsr r6, ctbp ldsr r6, ctbp
#if defined(__v850e2v3__) #if defined(__v850e2v3__) || defined(__v850e3v5__)
// FPU enable // FPU enable
stsr psw, r6 stsr psw, r6
movhi 1, r0, r7 movhi 1, r0, r7