ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com> * configure.in: Add cases for Renesas m32c. * configure: Regenerated. bfd/ChangeLog: 2005-07-14 Jim Blandy <jimb@redhat.com> Add support for m32c-*-elf (Renesas m32c and m16c). * Makefile.am (ALL_MACHINES): Add cpu-m32c.lo. (ALL_MACHINES_CFILES): Add cpu-m32c.c. (BFD32_BACKENDS): Add elf32-m32c.lo. (BFD32_BACKENDS_CFILES): Add elf32-m32c.c. (cpu-m32c.lo, elf32-m32c.lo): New rules, generated by 'make dep-am'. * Makefile.in: Regenerated. * archures.c (bfd_arch_m32c, bfd_mach_m16c, bfd_mach_m32c): New arch and mach codes. (bfd_m32c_arch): New arch info object. (bfd_archures_list): List bfd_m32c_arch. * bfd-in2.h: Regenerated. * config.bfd: Add case for the m32c. * configure.in: Add case for the m32c. * configure: Regenerated. * cpu-m32c.c, elf32-m32c.c: New files. * libbfd.h: Regenerated. * targets.c (bfd_elf32_m32c_vec): Declare. (_bfd_target_vector): List bfd_elf32_m32c_vec. binutils/ChangeLog: 2005-07-14 Jim Blandy <jimb@redhat.com> * readelf.c: #include "elf/m32c.h" (guess_is_rela, dump_relocations, get_machine_name): Add cases for EM_M32C. * Makefile.am (readelf.o): Update dependencies. * Makefile.in: Regenerated. cpu/ChangeLog: 2005-07-14 Jim Blandy <jimb@redhat.com> * m32c.cpu, m32c.opc: Machine description for the Renesas M32C. gas/ChangeLog: 2005-07-14 Jim Blandy <jimb@redhat.com> Add support for the Renesas M32C. * Makefile.am (CPU_TYPES): List m32c. (TARGET_CPU_CFILES): List config/tc-m32c.c. (TARGET_CPU_HFILES): List config/tc-m32c.h. * configure.in: Add case for m32c. * configure.tgt: Add cases for m32c and m32c-*-elf. * configure: Regenerated. * config/tc-m32c.c, config/tc-m32c.h: New files. * doc/Makefile.am (CPU_DOCS): Add c-m32c.texi. * doc/Makefile.in: Regenerated. * doc/all.texi: Set M32C. * doc/as.texinfo: Add text for the M32C-specific options and line comment characters, and refer to c-m32c.texi. * doc/c-m32c.texi: New file. include/ChangeLog: 2005-07-14 Jim Blandy <jimb@redhat.com> * dis-asm.h (print_insn_m32c): New declaration. include/elf/ChangeLog: 2005-07-14 Jim Blandy <jimb@redhat.com> Add support for Renesas M32C and M16C. * common.h (EM_M32C): New machine number. * m32c.h: New file. ld/ChangeLog: 2005-07-14 Jim Blandy <jimb@redhat.com> Add support for the Renesas M32C and M16C. * Makefile.am (ALL_EMULATIONS): Add eelf32m32c.o. (eelf32m32c.c): New target. * Makefile.in: Regenerated. * configure.tgt: Add case for m32c-*-elf. * emulparams/elf32m32c.sh: New file. opcodes/ChangeLog: 2005-07-14 Jim Blandy <jimb@redhat.com> Add support for the Renesas M32C and M16C. * m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c: New. * m32c-desc.h, m32c-opc.h: New. * Makefile.am (HFILES): List m32c-desc.h and m32c-opc.h. (CFILES): List m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c. (ALL_MACHINES): List m32c-asm.lo, m32c-desc.lo, m32c-dis.lo, m32c-ibld.lo, m32c-opc.lo. (CLEANFILES): List stamp-m32c. (M32C_DEPS): List stamp-m32c, if CGEN_MAINT. (CGEN_CPUS): Add m32c. (m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c) (m32c-desc.h, m32c-opc.h): Depend on M32C_DEPS. (m32c_opc_h): New variable. (stamp-m32c, m32c-asm.lo, m32c-desc.lo, m32c-dis.lo, m32c-ibld.lo) (m32c-opc.lo): New rules. * Makefile.in: Regenerated. * configure.in: Add case for bfd_m32c_arch. * configure: Regenerated. * disassemble.c (ARCH_m32c): New. [ARCH_m32c]: #include "m32c-desc.h". (disassembler) [ARCH_m32c]: Add case for bfd_arch_m32c. (disassemble_init_for_target) [ARCH_m32c]: Same. * cgen-ops.h, cgen-types.h: New files. * Makefile.am (HFILES): List them. * Makefile.in: Regenerated.
This commit is contained in:
Jim Blandy
@@ -1,3 +1,7 @@
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2005-07-14 Jim Blandy <jimb@redhat.com>
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* dis-asm.h (print_insn_m32c): New declaration.
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2005-07-12 Ben Elliston <bje@au.ibm.com>
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* xregex2.h (regexec): Qualify this prototype with __extension__
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@@ -264,6 +264,7 @@ extern int print_insn_sh64 (bfd_vma, disassemble_info *);
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extern int print_insn_sh64x_media (bfd_vma, disassemble_info *);
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extern int print_insn_frv (bfd_vma, disassemble_info *);
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extern int print_insn_iq2000 (bfd_vma, disassemble_info *);
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extern int print_insn_m32c (bfd_vma, disassemble_info *);
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extern disassembler_ftype arc_get_disassembler (void *);
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extern disassembler_ftype cris_get_disassembler (bfd *);
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@@ -1,3 +1,9 @@
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2005-07-14 Jim Blandy <jimb@redhat.com>
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Add support for Renesas M32C and M16C.
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* common.h (EM_M32C): New machine number.
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* m32c.h: New file.
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2005-06-17 Jan Beulich <jbeulich@novell.com>
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* x86-64.h (elf_x86_64_reloc_type): Adjust comment for
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@@ -211,6 +211,9 @@
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/* (Deprecated) Temporary number for the OpenRISC processor. */
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#define EM_OR32 0x8472
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/* Renesas M32C and M16C. */
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#define EM_M32C 0xFEB0
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/* Cygnus M32R ELF backend. Written in the absence of an ABI. */
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#define EM_CYGNUS_M32R 0x9041
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49
include/elf/m32c.h
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49
include/elf/m32c.h
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@@ -0,0 +1,49 @@
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/* M32C ELF support for BFD.
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Copyright (C) 2004 Free Software Foundation, Inc.
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This file is part of BFD, the Binary File Descriptor library.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#ifndef _ELF_M32C_H
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#define _ELF_M32C_H
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#include "elf/reloc-macros.h"
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/* Relocations. */
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START_RELOC_NUMBERS (elf_m32c_reloc_type)
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RELOC_NUMBER (R_M32C_NONE, 0)
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RELOC_NUMBER (R_M32C_16, 1)
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RELOC_NUMBER (R_M32C_24, 2)
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RELOC_NUMBER (R_M32C_32, 3)
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RELOC_NUMBER (R_M32C_8_PCREL, 4)
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RELOC_NUMBER (R_M32C_16_PCREL, 5)
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END_RELOC_NUMBERS (R_M32C_max)
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#define EF_M32C_CPU_M16C 0x00000075 /* default */
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#define EF_M32C_CPU_M32C 0x00000078 /* m32c */
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#define EF_M32C_CPU_MASK 0x0000007F /* specific cpu bits */
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#define EF_M32C_ALL_FLAGS (EF_M32C_CPU_MASK)
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/* Define the data & instruction memory discriminator. In a linked
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executable, an symbol should be deemed to point to an instruction
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if ((address & M16C_INSN_MASK) == M16C_INSN_VALUE), and similarly
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for the data space. See also `ld/emulparams/elf32m32c.sh'. */
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#define M32C_DATA_MASK 0xffc00000
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#define M32C_DATA_VALUE 0x00000000
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#define M32C_INSN_MASK 0xffc00000
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#define M32C_INSN_VALUE 0x00400000
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#endif /* _ELF_M32C_H */
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63
include/gdb/sim-m32c.h
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63
include/gdb/sim-m32c.h
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@@ -0,0 +1,63 @@
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/* This file defines the interface between the m32c simulator and gdb.
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Copyright (C) 2005 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#ifndef SIM_M32C_H
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#define SIM_M32C_H
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enum m32c_sim_reg {
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m32c_sim_reg_r0_bank0,
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m32c_sim_reg_r1_bank0,
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m32c_sim_reg_r2_bank0,
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m32c_sim_reg_r3_bank0,
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m32c_sim_reg_a0_bank0,
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m32c_sim_reg_a1_bank0,
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m32c_sim_reg_fb_bank0,
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m32c_sim_reg_sb_bank0,
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m32c_sim_reg_r0_bank1,
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m32c_sim_reg_r1_bank1,
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m32c_sim_reg_r2_bank1,
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m32c_sim_reg_r3_bank1,
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m32c_sim_reg_a0_bank1,
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m32c_sim_reg_a1_bank1,
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m32c_sim_reg_fb_bank1,
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m32c_sim_reg_sb_bank1,
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m32c_sim_reg_usp,
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m32c_sim_reg_isp,
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m32c_sim_reg_pc,
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m32c_sim_reg_intb,
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m32c_sim_reg_flg,
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m32c_sim_reg_svf,
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m32c_sim_reg_svp,
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m32c_sim_reg_vct,
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m32c_sim_reg_dmd0,
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m32c_sim_reg_dmd1,
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m32c_sim_reg_dct0,
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m32c_sim_reg_dct1,
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m32c_sim_reg_drc0,
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m32c_sim_reg_drc1,
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m32c_sim_reg_dma0,
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m32c_sim_reg_dma1,
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m32c_sim_reg_dsa0,
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m32c_sim_reg_dsa1,
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m32c_sim_reg_dra0,
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m32c_sim_reg_dra1,
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m32c_sim_reg_num_regs
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};
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#endif /* SIM_M32C_H */
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