bfd/
2006-02-23 H.J. Lu <hongjiu.lu@intel.com> * cpu-ia64-opc.c (ins_immu5b): New. (ext_immu5b): Likewise. (elf64_ia64_operands): Add IMMU5b. gas/ 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> * config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b. gas/testsuite/ 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> * gas/ia64/opc-i.s: Add tests for tf. * gas/ia64/pseudo.s: Likewise. * gas/ia64/opc-i.d: Updated. * gas/ia64/pseudo.d: Likewise. include/opcode/ 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b. opcodes/ 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> * ia64-opc-i.c (bXc): New. (mXc): Likewise. (OpX2TaTbYaXcC): Likewise. (TF). Likewise. (TFCM). Likewise. (ia64_opcodes_i): Add instructions for tf. * ia64-opc.h (IMMU5b): New. * ia64-asmtab.c: Regenerated.
This commit is contained in:
		| @@ -1,3 +1,7 @@ | |||||||
|  | 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com> | ||||||
|  |  | ||||||
|  | 	* ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b. | ||||||
|  |  | ||||||
| 2006-01-31  Paul Brook  <paul@codesourcery.com> | 2006-01-31  Paul Brook  <paul@codesourcery.com> | ||||||
| 	Richard Earnshaw <rearnsha@arm.com> | 	Richard Earnshaw <rearnsha@arm.com> | ||||||
|  |  | ||||||
|   | |||||||
| @@ -1,6 +1,7 @@ | |||||||
| /* ia64.h -- Header file for ia64 opcode table | /* ia64.h -- Header file for ia64 opcode table | ||||||
|    Copyright (C) 1998, 1999, 2000, 2002 Free Software Foundation, Inc. |    Copyright (C) 1998, 1999, 2000, 2002, 2005, 2006 | ||||||
| 	Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */ |    Free Software Foundation, Inc. | ||||||
|  |    Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */ | ||||||
|  |  | ||||||
| #ifndef opcode_ia64_h | #ifndef opcode_ia64_h | ||||||
| #define opcode_ia64_h | #define opcode_ia64_h | ||||||
| @@ -102,6 +103,7 @@ enum ia64_opnd | |||||||
|     IA64_OPND_CPOS6c,	/* 6-bit count (63 - bits 31-36) */ |     IA64_OPND_CPOS6c,	/* 6-bit count (63 - bits 31-36) */ | ||||||
|     IA64_OPND_IMM1,	/* signed 1-bit immediate (bit 36) */ |     IA64_OPND_IMM1,	/* signed 1-bit immediate (bit 36) */ | ||||||
|     IA64_OPND_IMMU2,	/* unsigned 2-bit immediate (bits 13-14) */ |     IA64_OPND_IMMU2,	/* unsigned 2-bit immediate (bits 13-14) */ | ||||||
|  |     IA64_OPND_IMMU5b,	/* unsigned 5-bit immediate (32 + bits 14-18) */ | ||||||
|     IA64_OPND_IMMU7a,	/* unsigned 7-bit immediate (bits 13-19) */ |     IA64_OPND_IMMU7a,	/* unsigned 7-bit immediate (bits 13-19) */ | ||||||
|     IA64_OPND_IMMU7b,	/* unsigned 7-bit immediate (bits 20-26) */ |     IA64_OPND_IMMU7b,	/* unsigned 7-bit immediate (bits 20-26) */ | ||||||
|     IA64_OPND_SOF,	/* 8-bit stack frame size */ |     IA64_OPND_SOF,	/* 8-bit stack frame size */ | ||||||
|   | |||||||
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