Renumber cpu flag bits to avoid collision with PE flag bits
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		| @@ -1,3 +1,9 @@ | ||||
| Mon May 17 13:35:35 1999  Stan Cox  <scox@cygnus.com> | ||||
|  | ||||
| 	* coff/arm.h (F_PIC, F_ARM_2, F_ARM_2a, F_ARM_3, F_ARM_3M, | ||||
| 	F_ARM_4, F_ARM_4T, F_APCS26): Changed values to distinguish | ||||
| 	F_ARM_2a, F_ARM_3M, F_ARM_4T. | ||||
|  | ||||
| 1999-05-15  Nick Clifton  <nickc@cygnus.com> | ||||
|  | ||||
| 	* mcore.h (IMAGE_REL_MCORE_RVA): Define. | ||||
|   | ||||
| @@ -44,16 +44,17 @@ struct external_filehdr { | ||||
| /* Bits stored in flags field of the internal_f structure */ | ||||
|  | ||||
| #define F_INTERWORK	(0x0010) | ||||
| #define F_PIC_INT	(0x0020) | ||||
| #define F_APCS_FLOAT	(0x0040) | ||||
| #define F_ARM_ARCHITECTURE_MASK	(0x0c00) | ||||
| #define F_ARM_2		(0x0000) | ||||
| #define F_ARM_2a	(0x0000) | ||||
| #define F_ARM_3		(0x0400) | ||||
| #define F_ARM_3M	(0x0400) | ||||
| #define F_ARM_4		(0x0800) | ||||
| #define F_ARM_4T	(0x0c00) | ||||
| #define F_APCS26	(0x4000) | ||||
| #define F_PIC		(0x0080) | ||||
| #define F_APCS26	(0x1000) | ||||
| #define F_ARM_ARCHITECTURE_MASK (0x4000+0x0800+0x0400) | ||||
| #define F_ARM_2		(0x0400) | ||||
| #define F_ARM_2a	(0x0800) | ||||
| #define F_ARM_3		(0x0c00) | ||||
| #define F_ARM_3M	(0x4000) | ||||
| #define F_ARM_4		(0x4400) | ||||
| #define F_ARM_4T	(0x4800) | ||||
| #define F_ARM_spare	(0x4c00) | ||||
|  | ||||
| /* | ||||
|  * ARMMAGIC ought to encoded the procesor type, | ||||
|   | ||||
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