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include/opcode/ 

* mips.h: Remove documentation of "[" and "]".  Update documentation
	of "k" and the MDMX formats.

opcodes/
	* mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
	MDMX-like instructions.
	* mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
	printing "Q" operands for INSN_5400 instructions.

gas/
	* config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling.
	(mips_ip): Likewise.  Do not set is_mdmx for INSN_5400 instructions.
	Check constraints on the VR5400 RZU.OB, SLL.OB and SRL.OB instructions.

gas/testsuite/
	* gas/mips/vr5400-ill.s, gas/mips/vr5400-ill.l: New test.
	* gas/mips/mips.exp: Run it.
This commit is contained in:
Richard Sandiford 2013-07-07 10:15:08 +00:00
parent 2428e76364
commit 4e9c217b55
2 changed files with 13 additions and 10 deletions
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5
include/opcode/ChangeLog
View File

@ -1,3 +1,8 @@
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
* mips.h: Remove documentation of "[" and "]". Update documentation
of "k" and the MDMX formats.
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
* mips.h: Update documentation of "+s" and "+S". * mips.h: Update documentation of "+s" and "+S".

18
include/opcode/mips.h
View File

@ -387,7 +387,6 @@ struct mips_opcode
"i" 16 bit unsigned immediate (OP_*_IMMEDIATE) "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
"j" 16 bit signed immediate (OP_*_DELTA) "j" 16 bit signed immediate (OP_*_DELTA)
"k" 5 bit cache opcode in target register position (OP_*_CACHE) "k" 5 bit cache opcode in target register position (OP_*_CACHE)
Also used for immediate operands in vr5400 vector insns.
"o" 16 bit signed offset (OP_*_DELTA) "o" 16 bit signed offset (OP_*_DELTA)
"p" 16 bit PC relative branch target address (OP_*_DELTA) "p" 16 bit PC relative branch target address (OP_*_DELTA)
"q" 10 bit extra breakpoint code (OP_*_CODE2) "q" 10 bit extra breakpoint code (OP_*_CODE2)
@ -446,7 +445,6 @@ struct mips_opcode
"P" 5 bit performance-monitor register (OP_*_PERFREG) "P" 5 bit performance-monitor register (OP_*_PERFREG)
"e" 5 bit vector register byte specifier (OP_*_VECBYTE) "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
"%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
see also "k" above
Macro instructions: Macro instructions:
"A" General 32 bit expression "A" General 32 bit expression
@ -457,13 +455,14 @@ struct mips_opcode
"f" 32 bit floating point constant "f" 32 bit floating point constant
"l" 32 bit floating point constant in .lit4 "l" 32 bit floating point constant in .lit4
MDMX instruction operands (note that while these use the FP register MDMX and VR5400 instruction operands (note that while these use the
fields, they accept both $fN and $vN names for the registers): FP register fields, the MDMX instructions accept both $fN and $vN names
"O" MDMX alignment offset (OP_*_ALN) for the registers):
"Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) "O" alignment offset (OP_*_ALN)
"X" MDMX destination register (OP_*_FD) "Q" vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
"Y" MDMX source register (OP_*_FS) "X" destination register (OP_*_FD)
"Z" MDMX source register (OP_*_FT) "Y" source register (OP_*_FS)
"Z" source register (OP_*_FT)
DSP ASE usage: DSP ASE usage:
"2" 2 bit unsigned immediate for byte align (OP_*_BP) "2" 2 bit unsigned immediate for byte align (OP_*_BP)
@ -526,7 +525,6 @@ struct mips_opcode
Other: Other:
"()" parens surrounding optional value "()" parens surrounding optional value
"," separates operands "," separates operands
"[]" brackets around index for vector-op scalar operand specifier (vr5400)
"+" Start of extension sequence. "+" Start of extension sequence.
Characters used so far, for quick reference when adding more: Characters used so far, for quick reference when adding more: