Add new port: crx-elf
This commit is contained in:
Nick Clifton
395
include/opcode/crx.h
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395
include/opcode/crx.h
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/* crx.h -- Header file for CRX opcode and register tables.
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Copyright 2004 Free Software Foundation, Inc.
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Contributed by Tomer Levi, NSC, Israel.
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Originally written for GAS 2.12 by Tomer Levi, NSC, Israel.
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Updates, BFDizing, GNUifying and ELF support by Tomer Levi.
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This file is part of GAS, GDB and the GNU binutils.
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GAS, GDB, and GNU binutils is free software; you can redistribute it
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and/or modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2, or (at your
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option) any later version.
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GAS, GDB, and GNU binutils are distributed in the hope that they will be
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useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#ifndef _CRX_H_
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#define _CRX_H_
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/* CRX core/debug Registers :
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The enums are used as indices to CRX registers table (crx_regtab).
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Therefore, order MUST be preserved. */
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typedef enum
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{
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/* 32-bit general purpose registers. */
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r0, r1, r2, r3, r4, r5, r6, r7, r8, r9,
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r10, r11, r12, r13, r14, r15, ra, sp,
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/* 32-bit user registers. */
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u0, u1, u2, u3, u4, u5, u6, u7, u8, u9,
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u10, u11, u12, u13, u14, u15, ura, usp,
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/* hi and lo registers. */
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hi, lo,
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/* hi and lo user registers. */
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uhi, ulo,
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/* Processor Status Register. */
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psr,
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/* Configuration Register. */
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cfg,
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/* Coprocessor Configuration Register. */
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cpcfg,
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/* Cashe Configuration Register. */
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ccfg,
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/* Interrupt Base Register. */
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intbase,
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/* Interrupt Stack Pointer Register. */
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isp,
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/* Coprocessor Enable Register. */
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cen,
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/* Program Counter Register. */
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pc,
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/* Not a register. */
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nullregister,
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MAX_REG
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}
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reg;
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/* CRX Coprocessor registers and special registers :
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The enums are used as indices to CRX coprocessor registers table
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(crx_copregtab). Therefore, order MUST be preserved. */
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typedef enum
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{
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/* Coprocessor registers. */
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c0 = MAX_REG, c1, c2, c3, c4, c5, c6, c7, c8,
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c9, c10, c11, c12, c13, c14, c15,
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/* Coprocessor special registers. */
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cs0, cs1 ,cs2, cs3, cs4, cs5, cs6, cs7, cs8,
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cs9, cs10, cs11, cs12, cs13, cs14, cs15,
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/* Not a Coprocessor register. */
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nullcopregister,
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MAX_COPREG
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}
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copreg;
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/* CRX Register types. */
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typedef enum
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{
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CRX_PC_REGTYPE, /* pc type */
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CRX_R_REGTYPE, /* r<N> */
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CRX_U_REGTYPE, /* u<N> */
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CRX_C_REGTYPE, /* c<N> */
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CRX_CS_REGTYPE, /* cs<N> */
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CRX_MTPR_REGTYPE, /* mtpr */
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CRX_CFG_REGTYPE /* *hi|lo, *cfg, psr */
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}
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reg_type;
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/* CRX argument types :
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The argument types correspond to instructions operands
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Argument types :
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r - register
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c - constant
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d - displacement
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ic - immediate
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icr - index register
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rbase - register base
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s - star ('*')
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copr - coprocessor register
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copsr - coprocessor special register. */
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typedef enum
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{
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arg_r, arg_c, arg_cr, arg_dc, arg_dcr, arg_sc,
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arg_ic, arg_icr, arg_rbase, arg_copr, arg_copsr,
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/* Not an argument. */
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nullargs
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}
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argtype;
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/* CRX operand types :
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The operand types correspond to instructions operands
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Operand Types :
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cst4 - 4-bit encoded constant
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iN - N-bit immediate field
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d, dispsN - N-bit immediate signed displacement
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dispuN - N-bit immediate unsigned displacement
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absN - N-bit absolute address
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rbase - 4-bit genaral-purpose register specifier
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regr - 4-bit genaral-purpose register specifier
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regr8 - 8-bit register address space
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copregr - coprocessor register
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copsregr - coprocessor special register
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scl2 - 2-bit scaling factor for memory index
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ridx - register index. */
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typedef enum
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{
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dummy, cst4, disps9,
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i3, i4, i5, i8, i12, i16, i32,
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d5, d9, d17, d25, d33,
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abs16, abs32,
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rbase, rbase_cst4,
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rbase_dispu8, rbase_dispu12, rbase_dispu16, rbase_dispu28, rbase_dispu32,
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rbase_ridx_scl2_dispu6, rbase_ridx_scl2_dispu22,
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regr, regr8, copregr,copregr8,copsregr,
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/* Not an operand. */
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nulloperand,
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/* Maximum supported operand. */
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MAX_OPRD
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}
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operand_type;
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/* CRX instruction types. */
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#define ARITH_INS 1
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#define LD_STOR_INS 2
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#define BRANCH_INS 3
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#define ARITH_BYTE_INS 4
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#define CMPBR_INS 5
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#define SHIFT_INS 6
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#define BRANCH_NEQ_INS 7
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#define LD_STOR_INS_INC 8
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#define STOR_IMM_INS 9
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#define CSTBIT_INS 10
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#define SYS_INS 11
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#define JMP_INS 12
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#define MUL_INS 13
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#define DIV_INS 14
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#define COP_BRANCH_INS 15
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#define COP_REG_INS 16
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#define DCR_BRANCH_INS 17
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#define MMC_INS 18
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#define MMU_INS 19
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/* Maximum value supported for instruction types. */
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#define CRX_INS_MAX (1 << 5)
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/* Mask to record an instruction type. */
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#define CRX_INS_MASK (CRX_INS_MAX - 1)
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/* Return instruction type, given instruction's attributes. */
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#define CRX_INS_TYPE(attr) ((attr) & CRX_INS_MASK)
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/* Indicates whether this instruction has a register list as parameter. */
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#define REG_LIST CRX_INS_MAX
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/* The operands in binary and assembly are placed in reverse order.
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load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */
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#define REVERSE_MATCH (REG_LIST << 1)
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/* Kind of displacement map used DISPU[BWD]4. */
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#define DISPUB4 (REVERSE_MATCH << 1)
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#define DISPUW4 (DISPUB4 << 1)
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#define DISPUD4 (DISPUW4 << 1)
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#define CST4MAP (DISPUB4 | DISPUW4 | DISPUD4)
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/* Printing formats, where the instruction prefix isn't consecutive. */
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#define FMT_1 (DISPUD4 << 1) /* 0xF0F00000 */
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#define FMT_2 (FMT_1 << 1) /* 0xFFF0FF00 */
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#define FMT_3 (FMT_2 << 1) /* 0xFFF00F00 */
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#define FMT_4 (FMT_3 << 1) /* 0xFFF0F000 */
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#define FMT_5 (FMT_4 << 1) /* 0xFFF0FFF0 */
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#define FMT_CRX (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5)
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#define RELAXABLE (FMT_5 << 1)
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/* Maximum operands per instruction. */
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#define MAX_OPERANDS 5
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/* Maximum words per instruction. */
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#define MAX_WORDS 3
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/* Maximum register name length. */
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#define MAX_REGNAME_LEN 10
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/* Maximum instruction length. */
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#define MAX_INST_LEN 256
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/* Single operand description. */
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typedef struct
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{
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/* Operand type. */
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operand_type op_type;
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/* Operand location within the opcode. */
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unsigned int shift;
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}
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operand_desc;
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/* Instruction data structure used in instruction table. */
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typedef struct
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{
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/* Name. */
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const char *mnemonic;
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/* Size (in words). */
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unsigned int size;
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/* Constant prefix (matched by the disassembler). */
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unsigned long match;
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/* Match size (in bits). */
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int match_bits;
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/* Attributes. */
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unsigned int flags;
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/* Operands (always last, so unreferenced operands are initialized). */
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operand_desc operands[MAX_OPERANDS];
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}
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inst;
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/* Data structure for a single instruction's arguments (Operands). */
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typedef struct
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{
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/* Register or base register. */
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reg r;
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/* Index register. */
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reg i_r;
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/* Coprocessor register. */
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copreg cr;
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/* Constant/immediate/absolute value. */
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unsigned long int constant;
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/* Scaled index mode. */
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unsigned int scale;
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/* Argument type. */
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argtype type;
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/* Size of the argument (in bits) required to represent. */
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int size;
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/* Indicates whether a constant is positive or negative. */
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int signflag;
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}
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argument;
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/* Internal structure to hold the various entities
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corresponding to the current assembling instruction. */
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typedef struct
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{
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/* Number of arguments. */
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int nargs;
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/* The argument data structure for storing args (operands). */
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argument arg[MAX_OPERANDS];
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/* The following fields are required only by CRX-assembler. */
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#ifdef TC_CRX
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/* Expression used for setting the fixups (if any). */
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expressionS exp;
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bfd_reloc_code_real_type rtype;
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#endif /* TC_CRX */
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/* Instruction size (in bytes). */
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int size;
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}
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ins;
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/* Structure to hold information about predefined operands. */
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typedef struct
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{
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/* Size (in bits). */
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unsigned int bit_size;
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/* Argument type. */
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argtype arg_type;
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}
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operand_entry;
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/* Structure to hold trap handler information. */
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typedef struct
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{
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/* Trap name. */
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char *name;
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/* Index in dispatch table. */
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unsigned int entry;
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}
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trap_entry;
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/* Structure to hold information about predefined registers. */
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typedef struct
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{
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/* Name (string representation). */
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char *name;
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/* Value (enum representation). */
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union
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{
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/* Register. */
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reg reg_val;
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/* Coprocessor register. */
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copreg copreg_val;
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} value;
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/* Register image. */
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int image;
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/* Register type. */
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reg_type type;
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}
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reg_entry;
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/* Structure to hold a cst4 operand mapping. */
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typedef struct
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{
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/* The binary value which is written to the object file. */
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int binary;
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/* The value which is mapped. */
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int value;
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}
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cst4_entry;
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/* CRX opcode table. */
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extern const inst crx_instruction[];
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extern const int crx_num_opcodes;
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#define NUMOPCODES crx_num_opcodes
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/* CRX operands table. */
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extern const operand_entry crx_optab[];
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/* CRX registers table. */
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extern const reg_entry crx_regtab[];
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extern const int crx_num_regs;
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#define NUMREGS crx_num_regs
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/* CRX coprocessor registers table. */
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extern const reg_entry crx_copregtab[];
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extern const int crx_num_copregs;
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#define NUMCOPREGS crx_num_copregs
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/* CRX trap/interrupt table. */
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extern const trap_entry crx_traps[];
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extern const int crx_num_traps;
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#define NUMTRAPS crx_num_traps
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/* cst4 operand mapping. */
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extern const cst4_entry cst4_map[];
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extern const int cst4_maps;
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/* Current instruction we're assembling. */
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extern const inst *instruction;
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/* A macro for representing the instruction "constant" opcode, that is,
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the FIXED part of the instruction. The "constant" opcode is represented
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as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT)
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over that range. */
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#define BIN(OPC,SHIFT) (OPC << SHIFT)
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/* Is the current instruction type is TYPE ? */
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#define IS_INSN_TYPE(TYPE) \
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(CRX_INS_TYPE(instruction->flags) == TYPE)
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/* Is the current instruction mnemonic is MNEMONIC ? */
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#define IS_INSN_MNEMONIC(MNEMONIC) \
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(strcmp(instruction->mnemonic,MNEMONIC) == 0)
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/* Does the current instruction has register list ? */
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#define INST_HAS_REG_LIST \
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(instruction->flags & REG_LIST)
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/* Long long type handling. */
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/* Replace all appearances of 'long long int' with LONGLONG. */
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typedef long long int LONGLONG;
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typedef unsigned long long ULONGLONG;
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/* A mask for the upper 31 bits of a 64 bits type. */
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#define UPPER31_MASK 0xFFFFFFFE00000000LL
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#endif /* _CRX_H_ */
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