2009-09-16 Mike Frysinger <michael.frysinger@analog.com>
* bfin/include/cdefBF512.h, bfin/include/cdefBF514.h,
bfin/include/cdefBF516.h, bfin/include/cdefBF518.h,
bfin/include/cdefBF51x_base.h, bfin/include/cdefBF523.h,
bfin/include/cdefBF524.h, bfin/include/cdefBF526.h,
bfin/include/cdefBF542M.h, bfin/include/cdefBF544M.h,
bfin/include/cdefBF547M.h, bfin/include/cdefBF548M.h,
bfin/include/cdefBF549M.h, bfin/include/defBF512.h,
bfin/include/defBF514.h, bfin/include/defBF516.h,
bfin/include/defBF518.h, bfin/include/defBF51x_base.h,
bfin/include/defBF523.h, bfin/include/defBF524.h,
bfin/include/defBF526.h, bfin/include/defBF542M.h,
bfin/include/defBF544M.h, bfin/include/defBF547M.h,
bfin/include/defBF548M.h, bfin/include/defBF549M.h:
New file.
* bfin/include/ccblkfn.h, bfin/include/cdefBF525.h,
bfin/include/cdefBF527.h, bfin/include/cdefBF52x_base.h,
bfin/include/cdefBF532.h, bfin/include/cdefBF534.h,
bfin/include/cdefBF535.h, bfin/include/cdefBF538.h,
bfin/include/cdefBF539.h, bfin/include/cdefBF542.h,
bfin/include/cdefBF544.h, bfin/include/cdefBF547.h,
bfin/include/cdefBF548.h, bfin/include/cdefBF549.h,
bfin/include/cdefBF54x_base.h, bfin/include/cdefBF561.h,
bfin/include/cdefblackfin.h, bfin/include/cdef_LPBlackfin.h,
bfin/include/cplb.h, bfin/include/defBF527.h,
bfin/include/defBF52x_base.h, bfin/include/defBF532.h,
bfin/include/defBF534.h, bfin/include/defBF535.h,
bfin/include/defBF537.h, bfin/include/defBF538.h,
bfin/include/defBF539.h, bfin/include/defBF542.h,
bfin/include/defBF544.h, bfin/include/defBF547.h,
bfin/include/defBF548.h, bfin/include/defBF549.h,
bfin/include/defBF54x_base.h, bfin/include/defBF561.h,
bfin/include/defblackfin.h, bfin/include/def_LPBlackfin.h,
bfin/include/sys/_adi_platform.h,
bfin/include/sys/anomaly_macros_rtl.h,
bfin/include/sys/exception.h, bfin/include/sysreg.h:
Update to Visual DSP 5.0 Update 6.
This commit is contained in:
Jeff Johnston
@@ -14,7 +14,7 @@
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*
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* def_LPBlackfin.h
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*
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* Copyright (C) 2008 Analog Devices, Inc.
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* Copyright (C) 2008, 2009 Analog Devices, Inc.
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*
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************************************************************************/
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@@ -34,7 +34,11 @@
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#warning def_LPBlackfin.h should only be included for 532 compatible chips.
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#endif
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/* ensure macro params bracketed to avoid unexpected evaluations. (GA), MISRA Rule 19.10 */
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#ifdef _MISRA_RULES
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#define MK_BMSK_( x ) (1ul<<(x)) /* Make a bit mask from a bit position */
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#else
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#define MK_BMSK_( x ) (1<<(x)) /* Make a bit mask from a bit position */
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#endif /* _MISRA_RULES */
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/*********************************************************************************** */
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/* System Register Bits */
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@@ -367,8 +371,6 @@
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/* IMEM_CONTROL Register */
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/* ** Bit Positions */
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#define ENIM_P 0x00 /* Enable L1 Code Memory */
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#define IMCTL_ENIM_P 0x00 /* "" (older define) */
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#define ENICPLB_P 0x01 /* Enable ICPLB */
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#define IMCTL_ENICPLB_P 0x01 /* "" (older define) */
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#define IMC_P 0x02 /* Enable */
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@@ -379,7 +381,6 @@
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#define ILOC3_P 0x06 /* Lock Way 3 */
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#define LRUPRIORST_P 0x0D /* Least Recently Used Replacement Priority */
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/* ** Masks */
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#define ENIM 0x00000001 /* Enable L1 Code Memory */
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#define ENICPLB 0x00000002 /* Enable ICPLB */
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#define IMC 0x00000004 /* Configure L1 code memory as cache (0=SRAM) */
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#define ILOC0 0x00000008 /* Lock Way 0 */
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@@ -400,12 +401,23 @@
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#define TAUTORLD_P 0x00000002 /* Timer auto reload */
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#define TINT_P 0x00000003 /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
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/* DCPLB_DATA and ICPLB_DATA Registers */
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/*** Bit Positions */
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#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */
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#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry locked */
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#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access allowed (user mode) */
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/*** Masks */
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/* DCPLB_DATA and ICPLB_DATA Registers - bit positions */
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#define CPLB_VALID_P 0 /* 0=invalid entry, 1=valid entry */
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#define CPLB_LOCK_P 1 /* 0=entry may be replaced, 1=entry locked */
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#define CPLB_USER_RD_P 2 /* 0=no read access, 1=read access allowed (user mode) */
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#define CPLB_PORTPRIO_P 9 /* 0=low priority port, 1= high priority port */
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/*** ICPLB_DATA only */
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#define CPLB_LRUPRIO_P 8 /* 0=can be replaced by any line, 1=priority for non-replacement */
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/*** DCPLB_DATA only */
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#define CPLB_USER_WR_P 3 /* 0=no write access, 0=write access allowed (user mode) */
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#define CPLB_SUPV_WR_P 4 /* 0=no write access, 0=write access allowed (supervisor mode) */
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#define CPLB_DIRTY_P 7 /* 1=dirty, 0=clean */
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#define CPLB_L1_CHBL_P 12 /* 0=non-cacheable in L1, 1=cacheable in L1 */
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#define CPLB_WT_P 14 /* 0=write-back, 1=write-through */
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#define CPLB_L1_AOW_P 15 /* 0=do not allocate cache lines on write-through writes, */
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/* 1= allocate cache lines on write-through writes. */
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/* DCPLB_DATA and ICPLB_DATA Registers - Masks */
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#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */
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#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry locked */
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#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access allowed (user mode) */
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@@ -413,16 +425,16 @@
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#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
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#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
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#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
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#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */
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#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */
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#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable in L1 */
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/*** ICPLB_DATA only */
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#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, 1=priority for non-replacement */
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#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, 1=priority for non-replacement */
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/*** DCPLB_DATA only */
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#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write access allowed (user mode) */
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#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write access allowed (supervisor mode) */
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#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */
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#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on write-through writes, */
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/* 1= allocate cache lines on write-through writes. */
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#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on write-through writes, */
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/* 1= allocate cache lines on write-through writes. */
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#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
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@@ -442,7 +454,11 @@
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#define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */
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#define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */
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/* ensure macro params bracketed to avoid unexpected evaluations. (GA) MISRA Rule 19.10 */
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#ifdef _MISRA_RULES
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#define TEST_SET(x) (((x) << 5) & 0x03E0u) /* Set Index 0->31 */
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#else
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#define TEST_SET(x) (((x) << 5) & 0x03E0) /* Set Index 0->31 */
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#endif /* _MISRA_RULES */
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#define TEST_WAY0 0x00000000 /* Access Way0 */
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#define TEST_WAY1 0x04000000 /* Access Way1 */
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/*** ITEST_COMMAND only */
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