2009-09-16 Mike Frysinger <michael.frysinger@analog.com>
* bfin/include/cdefBF512.h, bfin/include/cdefBF514.h,
bfin/include/cdefBF516.h, bfin/include/cdefBF518.h,
bfin/include/cdefBF51x_base.h, bfin/include/cdefBF523.h,
bfin/include/cdefBF524.h, bfin/include/cdefBF526.h,
bfin/include/cdefBF542M.h, bfin/include/cdefBF544M.h,
bfin/include/cdefBF547M.h, bfin/include/cdefBF548M.h,
bfin/include/cdefBF549M.h, bfin/include/defBF512.h,
bfin/include/defBF514.h, bfin/include/defBF516.h,
bfin/include/defBF518.h, bfin/include/defBF51x_base.h,
bfin/include/defBF523.h, bfin/include/defBF524.h,
bfin/include/defBF526.h, bfin/include/defBF542M.h,
bfin/include/defBF544M.h, bfin/include/defBF547M.h,
bfin/include/defBF548M.h, bfin/include/defBF549M.h:
New file.
* bfin/include/ccblkfn.h, bfin/include/cdefBF525.h,
bfin/include/cdefBF527.h, bfin/include/cdefBF52x_base.h,
bfin/include/cdefBF532.h, bfin/include/cdefBF534.h,
bfin/include/cdefBF535.h, bfin/include/cdefBF538.h,
bfin/include/cdefBF539.h, bfin/include/cdefBF542.h,
bfin/include/cdefBF544.h, bfin/include/cdefBF547.h,
bfin/include/cdefBF548.h, bfin/include/cdefBF549.h,
bfin/include/cdefBF54x_base.h, bfin/include/cdefBF561.h,
bfin/include/cdefblackfin.h, bfin/include/cdef_LPBlackfin.h,
bfin/include/cplb.h, bfin/include/defBF527.h,
bfin/include/defBF52x_base.h, bfin/include/defBF532.h,
bfin/include/defBF534.h, bfin/include/defBF535.h,
bfin/include/defBF537.h, bfin/include/defBF538.h,
bfin/include/defBF539.h, bfin/include/defBF542.h,
bfin/include/defBF544.h, bfin/include/defBF547.h,
bfin/include/defBF548.h, bfin/include/defBF549.h,
bfin/include/defBF54x_base.h, bfin/include/defBF561.h,
bfin/include/defblackfin.h, bfin/include/def_LPBlackfin.h,
bfin/include/sys/_adi_platform.h,
bfin/include/sys/anomaly_macros_rtl.h,
bfin/include/sys/exception.h, bfin/include/sysreg.h:
Update to Visual DSP 5.0 Update 6.
This commit is contained in:
Jeff Johnston
@@ -14,7 +14,7 @@
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*
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* defBF561.h
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*
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* Copyright (C) 2008 Analog Devices, Inc.
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* Copyright (C) 2008, 2009 Analog Devices, Inc.
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*
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************************************************************************/
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@@ -866,25 +866,57 @@
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#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */
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#define PLL_OFF 0x0002 /* Shut off PLL clocks */
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#define STOPCK_OFF 0x0008 /* Core clock off */
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#define ALT_TIMING 0x0010 /* Enable Alternate PPI Timing (0.5 Silicon And Beyond) */
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#define ALT_TIMING 0x0010 /* Enable Alternate PPI Timing */
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#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */
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#define BYPASS 0x0100 /* Bypass the PLL */
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#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
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#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
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#define IN_DELAY 0x0040 /* Add 200ps Delay on EBIU Inputs */
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#define OUT_DELAY 0x0080 /* Add 200ps Delay on EBIU Outputs */
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#define SPORT_HYS 0x8000 /* Add 250mV Hysteresis to SPORT Inputs */
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/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
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#ifdef _MISRA_RULES
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#define SET_MSEL(x) (((x)&0x3Fu) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
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#else
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#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
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#endif /* _MISRA_RULES */
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/* PLL_DIV Masks */
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#define SSEL 0x000F /* System Select */
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#define CSEL 0x0030 /* Core Select */
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#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
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/* PLL_DIV Macros */
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#ifdef _MISRA_RULES
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#define SET_SSEL(x) ((x)&0xFu) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
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#else
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#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
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#endif /* _MISRA_RULES */
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/* PLL_STAT Macros */
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#define VSTAT 0x0080 /* Voltage Regulator Status: Regulator at programmed voltage */
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#define CORE_IDLE 0x0040 /* processor is in the IDLE operating mode */
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#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
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#define SLEEP 0x0010 /* processor is in the Sleep operating mode */
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#define DEEP_SLEEP 0x0008 /* processor is in the Deep Sleep operating mode */
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#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
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#define FULL_ON 0x0002 /* Processor In Full On Mode */
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#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
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#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */
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#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
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#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
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#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */
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/* SWRST Mask */
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#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */
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#define SWRST_DBL_FAULT_B 0x00000800 /* SWRST Core B Double Fault */
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#define SWRST_DBL_FAULT_A 0x00001000 /* SWRST Core A Double Fault */
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#define SWRST_WDT_B 0x00002000 /* SWRST Watchdog B */
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#define SWRST_WDT_A 0x00004000 /* SWRST Watchdog A */
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#define SWRST_OCCURRED 0x00008000 /* SWRST Status */
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#define SYSTEM_RESET 0x0007 /* Initiates a system software reset */
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#define SWRST_DBL_FAULT_A 0x0800 /* SWRST Core A Double Fault */
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#define SWRST_DBL_FAULT_B 0x1000 /* SWRST Core B Double Fault */
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#define SWRST_WDT_B 0x2000 /* SWRST Watchdog B */
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#define SWRST_WDT_A 0x4000 /* SWRST Watchdog A */
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#define SWRST_OCCURRED 0x8000 /* SWRST Status */
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/* VR_CTL Masks */
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#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
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@@ -892,6 +924,9 @@
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#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
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#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
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#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
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#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
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#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
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#define GAIN 0x000C /* Voltage Level Gain */
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#define GAIN_5 0x0000 /* GAIN = 5 */
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@@ -911,6 +946,13 @@
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#define VLEV_125 0x00E0 /* VLEV = 1.25 V (See Datasheet for Regulator Tolerance) */
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#define VLEV_130 0x00F0 /* VLEV = 1.30 V (See Datasheet for Regulator Tolerance) */
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/* SYSCR Masks */
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#define BMODE_BYPASS 0x0000 /* Bypass boot ROM, execute from 16-bit external memory */
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#define BMODE_FLASH 0x0001 /* Use Boot ROM to load from 8-bit or 16-bit flash */
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#define BMODE_SPIHOST 0x0002 /* Boot from SPI0 host (slave mode) */
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#define BMODE_SPIMEM 0x0003 /* Boot from serial SPI memory */
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/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
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@@ -942,13 +984,21 @@
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#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
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#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
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/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
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#define PLL_WAKEUP_IRQ 0x00000001 /* PLL Wakeup Interrupt Request */
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#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt Request */
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/* ********* WATCHDOG TIMER MASKS ******************** */
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/* Watchdog Timer WDOG_CTL Register Masks */
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#ifdef _MISRA_RULES
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#define WDEV(x) (((x)<<1) & 0x0006u) /* event generated on roll over */
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#else
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#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
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#endif /* _MISRA_RULES */
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#define WDEV_RESET 0x0000 /* generate reset event on roll over */
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#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
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#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
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@@ -986,7 +1036,11 @@
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#define EPS 0x10
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#define PEN 0x08
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#define STB 0x04
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#ifdef _MISRA_RULES
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#define WLS(x) (((x)-5u) & 0x03u) /* Word Length Select */
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#else
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#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
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#endif /* _MISRA_RULES */
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#define DLAB_P 0x07
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#define SB_P 0x06
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@@ -1028,7 +1082,11 @@
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#define ERBFI_P 0x00
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/* UART_IIR Register */
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#ifdef _MISRA_RULES
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#define STATUS(x) (((x) << 1) & 0x06u)
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#else
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#define STATUS(x) (((x) << 1) & 0x06)
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#endif /* _MISRA_RULES */
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#define NINT 0x01
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#define STATUS_P1 0x02
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#define STATUS_P0 0x01
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@@ -1123,7 +1181,11 @@
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#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */
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#define DLENGTH 0x00003800 /* PPI Data Length */
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#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
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#ifdef _MISRA_RULES
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#define DLEN(x) ((((x)-9u) & 0x07u) << 11) /* PPI Data Length (only works for x=10-->x=16) */
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#else
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#define DLEN(x) ((((x)-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
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#endif /* _MISRA_RULES */
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#define POL 0x0000C000 /* PPI Signal Polarities */
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@@ -1352,7 +1414,11 @@
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#define CLK_SEL 0x0080
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#define TOGGLE_HI 0x0100
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#define EMU_RUN 0x0200
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#ifdef _MISRA_RULES
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#define ERR_TYP(x) (((x) & 0x03u) << 14)
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#else
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#define ERR_TYP(x) (((x) & 0x03) << 14)
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#endif /* _MISRA_RULES */
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#define TMODE_P0 0x00
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#define TMODE_P1 0x01
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@@ -1678,8 +1744,10 @@
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#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
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#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
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#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
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#define CL 0x0000000C /* SDRAM CAS latency */
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#define PFE 0x00000010 /* Enable SDRAM prefetch */
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#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
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#define PASR 0x00000030 /* SDRAM partial array self-refresh */
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#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
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#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
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#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
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@@ -1695,6 +1763,7 @@
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#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
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#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
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#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
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#define TRAS 0x000003C0 /* SDRAM tRAS in SCLK cycles */
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#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
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#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
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#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
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@@ -1702,6 +1771,7 @@
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#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
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#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
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#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
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#define TRP 0x00003800 /* SDRAM tRP in SCLK cycles */
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#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
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#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
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#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
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@@ -1709,9 +1779,11 @@
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#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
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#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
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#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
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#define TRCD 0x00030000 /* SDRAM tRCD in SCLK cycles */
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#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
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#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
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#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
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#define TWR 0x00180000 /* SDRAM tWR in SCLK cycles */
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#define PUPSD 0x00200000 /*Power-up start delay */
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#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
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#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
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@@ -1723,6 +1795,8 @@
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#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
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/* EBIU_SDBCTL Masks */
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#define EBSZ 0x000E /* SDRAM external bank size */
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#define EBCAW 0x0030 /* SDRAM external bank column address width */
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#define EB0_E 0x00000001 /* Enable SDRAM external bank 0 */
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#define EB0_SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
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#define EB0_SZ_32 0x00000002 /* SDRAM external bank size = 32MB */
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