2009-09-16 Mike Frysinger <michael.frysinger@analog.com>
* bfin/include/cdefBF512.h, bfin/include/cdefBF514.h,
bfin/include/cdefBF516.h, bfin/include/cdefBF518.h,
bfin/include/cdefBF51x_base.h, bfin/include/cdefBF523.h,
bfin/include/cdefBF524.h, bfin/include/cdefBF526.h,
bfin/include/cdefBF542M.h, bfin/include/cdefBF544M.h,
bfin/include/cdefBF547M.h, bfin/include/cdefBF548M.h,
bfin/include/cdefBF549M.h, bfin/include/defBF512.h,
bfin/include/defBF514.h, bfin/include/defBF516.h,
bfin/include/defBF518.h, bfin/include/defBF51x_base.h,
bfin/include/defBF523.h, bfin/include/defBF524.h,
bfin/include/defBF526.h, bfin/include/defBF542M.h,
bfin/include/defBF544M.h, bfin/include/defBF547M.h,
bfin/include/defBF548M.h, bfin/include/defBF549M.h:
New file.
* bfin/include/ccblkfn.h, bfin/include/cdefBF525.h,
bfin/include/cdefBF527.h, bfin/include/cdefBF52x_base.h,
bfin/include/cdefBF532.h, bfin/include/cdefBF534.h,
bfin/include/cdefBF535.h, bfin/include/cdefBF538.h,
bfin/include/cdefBF539.h, bfin/include/cdefBF542.h,
bfin/include/cdefBF544.h, bfin/include/cdefBF547.h,
bfin/include/cdefBF548.h, bfin/include/cdefBF549.h,
bfin/include/cdefBF54x_base.h, bfin/include/cdefBF561.h,
bfin/include/cdefblackfin.h, bfin/include/cdef_LPBlackfin.h,
bfin/include/cplb.h, bfin/include/defBF527.h,
bfin/include/defBF52x_base.h, bfin/include/defBF532.h,
bfin/include/defBF534.h, bfin/include/defBF535.h,
bfin/include/defBF537.h, bfin/include/defBF538.h,
bfin/include/defBF539.h, bfin/include/defBF542.h,
bfin/include/defBF544.h, bfin/include/defBF547.h,
bfin/include/defBF548.h, bfin/include/defBF549.h,
bfin/include/defBF54x_base.h, bfin/include/defBF561.h,
bfin/include/defblackfin.h, bfin/include/def_LPBlackfin.h,
bfin/include/sys/_adi_platform.h,
bfin/include/sys/anomaly_macros_rtl.h,
bfin/include/sys/exception.h, bfin/include/sysreg.h:
Update to Visual DSP 5.0 Update 6.
This commit is contained in:
Jeff Johnston
@@ -13,7 +13,7 @@
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/*
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** defBF549.h
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**
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** Copyright (C) 2008 Analog Devices, Inc.
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** Copyright (C) 2008, 2009 Analog Devices, Inc.
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**
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************************************************************************************
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**
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@@ -366,7 +366,7 @@
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#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
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#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
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#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
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#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
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#define CAN1_UCRC 0xffc032c8 /* Universal Counter Reload/Capture Register */
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#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
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/* CAN Controller 1 Mailbox Acceptance Registers */
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@@ -2475,14 +2475,23 @@
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#define KPAD_COLEN 0xe000 /* Column Enable Width */
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#ifdef _MISRA_RULES
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#define SET_KPAD_ROWEN(x) (((x)&0x7u)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
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#define SET_KPAD_COLEN(x) (((x)&0x7u)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
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#else
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#define SET_KPAD_ROWEN(x) (((x)&0x7)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
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#define SET_KPAD_COLEN(x) (((x)&0x7)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
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#endif /* _MISRA_RULES */
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/* Bit masks for KPAD_PRESCALE */
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#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
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#ifdef _MISRA_RULES
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#define SET_KPAD_PRESCALE(x) ((x)&0x3Fu) /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */
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#else
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#define SET_KPAD_PRESCALE(x) ((x)&0x3F) /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */
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#endif /* MISRA_RULES */
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/* Bit masks for KPAD_MSEL */
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@@ -2490,8 +2499,13 @@
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#define DBON_SCALE 0xff /* Debounce Scale Value */
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#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
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#ifdef _MISRA_RULES
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#define SET_KPAD_DBON_SCALE(x) ((x)&0xFFu) /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */
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#define SET_KPAD_COLDRV_SCALE(x) (((x)&0xFFu)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */
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#else
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#define SET_KPAD_DBON_SCALE(x) ((x)&0xFF) /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */
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#define SET_KPAD_COLDRV_SCALE(x) (((x)&0xFF)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */
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#endif /* _MISRA_RULES */
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/* Bit masks for KPAD_ROWCOL */
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@@ -3421,7 +3435,11 @@
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/* MXVR_CONFIG Macros */
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#ifdef _MISRA_RULES
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#define SET_MSB(x) ( ( (x) & 0xFu ) << 9)
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#else
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#define SET_MSB(x) ( ( (x) & 0xF ) << 9)
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#endif /* _MISRA_RULES */
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/* MXVR_INT_STAT_1 Macros */
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@@ -3435,12 +3453,21 @@
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/* MXVR_CDRPLL_CTL Macros */
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#ifdef _MISRA_RULES
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#define SET_CDRSHPSEL(x) ( ( (x) & 0x3Fu ) << 16)
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#else
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#define SET_CDRSHPSEL(x) ( ( (x) & 0x3F ) << 16)
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#endif /* _MISRA_RULES */
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/* MXVR_FMPLL_CTL Macros */
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#ifdef _MISRA_RULES
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#define SET_CDRCPSEL(x) ( ( (x) & 0xFFu ) << 24)
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#define SET_FMCPSEL(x) ( ( (x) & 0xFFu ) << 24)
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#else
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#define SET_CDRCPSEL(x) ( ( (x) & 0xFF ) << 24)
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#define SET_FMCPSEL(x) ( ( (x) & 0xFF ) << 24)
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#endif /* _MISRA_RULES */
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#ifdef _MISRA_RULES
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#pragma diag(pop)
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