2009-09-16 Mike Frysinger <michael.frysinger@analog.com>
* bfin/include/cdefBF512.h, bfin/include/cdefBF514.h,
bfin/include/cdefBF516.h, bfin/include/cdefBF518.h,
bfin/include/cdefBF51x_base.h, bfin/include/cdefBF523.h,
bfin/include/cdefBF524.h, bfin/include/cdefBF526.h,
bfin/include/cdefBF542M.h, bfin/include/cdefBF544M.h,
bfin/include/cdefBF547M.h, bfin/include/cdefBF548M.h,
bfin/include/cdefBF549M.h, bfin/include/defBF512.h,
bfin/include/defBF514.h, bfin/include/defBF516.h,
bfin/include/defBF518.h, bfin/include/defBF51x_base.h,
bfin/include/defBF523.h, bfin/include/defBF524.h,
bfin/include/defBF526.h, bfin/include/defBF542M.h,
bfin/include/defBF544M.h, bfin/include/defBF547M.h,
bfin/include/defBF548M.h, bfin/include/defBF549M.h:
New file.
* bfin/include/ccblkfn.h, bfin/include/cdefBF525.h,
bfin/include/cdefBF527.h, bfin/include/cdefBF52x_base.h,
bfin/include/cdefBF532.h, bfin/include/cdefBF534.h,
bfin/include/cdefBF535.h, bfin/include/cdefBF538.h,
bfin/include/cdefBF539.h, bfin/include/cdefBF542.h,
bfin/include/cdefBF544.h, bfin/include/cdefBF547.h,
bfin/include/cdefBF548.h, bfin/include/cdefBF549.h,
bfin/include/cdefBF54x_base.h, bfin/include/cdefBF561.h,
bfin/include/cdefblackfin.h, bfin/include/cdef_LPBlackfin.h,
bfin/include/cplb.h, bfin/include/defBF527.h,
bfin/include/defBF52x_base.h, bfin/include/defBF532.h,
bfin/include/defBF534.h, bfin/include/defBF535.h,
bfin/include/defBF537.h, bfin/include/defBF538.h,
bfin/include/defBF539.h, bfin/include/defBF542.h,
bfin/include/defBF544.h, bfin/include/defBF547.h,
bfin/include/defBF548.h, bfin/include/defBF549.h,
bfin/include/defBF54x_base.h, bfin/include/defBF561.h,
bfin/include/defblackfin.h, bfin/include/def_LPBlackfin.h,
bfin/include/sys/_adi_platform.h,
bfin/include/sys/anomaly_macros_rtl.h,
bfin/include/sys/exception.h, bfin/include/sysreg.h:
Update to Visual DSP 5.0 Update 6.
This commit is contained in:
Jeff Johnston
@@ -11,7 +11,7 @@
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*/
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/*
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** Copyright (C) 2008 Analog Devices, Inc.
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** Copyright (C) 2008, 2009 Analog Devices, Inc.
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**
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************************************************************************************
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**
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@@ -32,6 +32,7 @@
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#pragma diag(push)
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#pragma diag(suppress:misra_rule_19_4)
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#pragma diag(suppress:misra_rule_19_7)
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#pragma diag(suppress:misra_rule_19_11)
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#endif /* _MISRA_RULES */
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@@ -224,8 +225,13 @@
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#define REGAD 0x000007C0 /* STA Register Address */
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#define PHYAD 0x0000F800 /* PHY Device Address */
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#ifdef _MISRA_RULES
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#define SET_REGAD(x) (((x)&0x1Fu)<< 6 ) /* Set STA Register Address */
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#define SET_PHYAD(x) (((x)&0x1Fu)<< 11 ) /* Set PHY Device Address */
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#else
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#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
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#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
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#endif /* _MISRA_RULES */
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/* EMAC_STADAT Mask */
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#define STADATA 0x0000FFFF /* Station Management Data */
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@@ -237,7 +243,11 @@
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#define BKPRSEN 0x00000008 /* Enable Backpressure */
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#define FLCPAUSE 0xFFFF0000 /* Pause Time */
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#ifdef _MISRA_RULES
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#define SET_FLCPAUSE(x) (((x)&0xFFFFu)<< 16) /* Set Pause Time */
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#else
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#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
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#endif /* _MISRA_RULES */
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/* EMAC_WKUP_CTL Masks */
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#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
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@@ -263,10 +273,18 @@
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#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
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#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
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#ifdef _MISRA_RULES
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#define SET_WF0_OFF(x) (((x)&0xFFu)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
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#define SET_WF1_OFF(x) (((x)&0xFFu)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
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#define SET_WF2_OFF(x) (((x)&0xFFu)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
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#define SET_WF3_OFF(x) (((x)&0xFFu)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
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#else
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#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
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#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
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#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
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#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
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#endif /* _MISRA_RULES */
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/* Set ALL Offsets */
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#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
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@@ -274,23 +292,40 @@
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#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
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#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
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#ifdef _MISRA_RULES
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#define SET_WF0_CRC(x) (((x)&0xFFFFu)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
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#define SET_WF1_CRC(x) (((x)&0xFFFFu)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
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#else
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#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
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#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
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#endif /* _MISRA_RULES */
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/* EMAC_WKUP_FFCRC1 Masks */
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#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
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#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
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#ifdef _MISRA_RULES
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#define SET_WF2_CRC(x) (((x)&0xFFFFu)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
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#define SET_WF3_CRC(x) (((x)&0xFFFFu)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
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#else
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#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
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#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
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#endif /* _MISRA_RULES */
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/* EMAC_SYSCTL Masks */
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#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
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#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
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#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
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#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
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#if !defined(__SILICON_REVISION__) || (__SILICON_REVISION__>0x2)
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/* In BF536/7 revs. 0.0, 0.1 and 0.2, this bit was reserved */
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#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment(Even/Odd*) */
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#endif
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#ifdef _MISRA_RULES
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#define SET_MDCDIV(x) (((x)&0x3Fu)<< 8) /* Set MDC Clock Divisor */
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#else
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#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
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#endif /* _MISRA_RULES */
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/* EMAC_SYSTAT Masks */
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#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
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