2009-09-16 Mike Frysinger <michael.frysinger@analog.com>
* bfin/include/cdefBF512.h, bfin/include/cdefBF514.h,
bfin/include/cdefBF516.h, bfin/include/cdefBF518.h,
bfin/include/cdefBF51x_base.h, bfin/include/cdefBF523.h,
bfin/include/cdefBF524.h, bfin/include/cdefBF526.h,
bfin/include/cdefBF542M.h, bfin/include/cdefBF544M.h,
bfin/include/cdefBF547M.h, bfin/include/cdefBF548M.h,
bfin/include/cdefBF549M.h, bfin/include/defBF512.h,
bfin/include/defBF514.h, bfin/include/defBF516.h,
bfin/include/defBF518.h, bfin/include/defBF51x_base.h,
bfin/include/defBF523.h, bfin/include/defBF524.h,
bfin/include/defBF526.h, bfin/include/defBF542M.h,
bfin/include/defBF544M.h, bfin/include/defBF547M.h,
bfin/include/defBF548M.h, bfin/include/defBF549M.h:
New file.
* bfin/include/ccblkfn.h, bfin/include/cdefBF525.h,
bfin/include/cdefBF527.h, bfin/include/cdefBF52x_base.h,
bfin/include/cdefBF532.h, bfin/include/cdefBF534.h,
bfin/include/cdefBF535.h, bfin/include/cdefBF538.h,
bfin/include/cdefBF539.h, bfin/include/cdefBF542.h,
bfin/include/cdefBF544.h, bfin/include/cdefBF547.h,
bfin/include/cdefBF548.h, bfin/include/cdefBF549.h,
bfin/include/cdefBF54x_base.h, bfin/include/cdefBF561.h,
bfin/include/cdefblackfin.h, bfin/include/cdef_LPBlackfin.h,
bfin/include/cplb.h, bfin/include/defBF527.h,
bfin/include/defBF52x_base.h, bfin/include/defBF532.h,
bfin/include/defBF534.h, bfin/include/defBF535.h,
bfin/include/defBF537.h, bfin/include/defBF538.h,
bfin/include/defBF539.h, bfin/include/defBF542.h,
bfin/include/defBF544.h, bfin/include/defBF547.h,
bfin/include/defBF548.h, bfin/include/defBF549.h,
bfin/include/defBF54x_base.h, bfin/include/defBF561.h,
bfin/include/defblackfin.h, bfin/include/def_LPBlackfin.h,
bfin/include/sys/_adi_platform.h,
bfin/include/sys/anomaly_macros_rtl.h,
bfin/include/sys/exception.h, bfin/include/sysreg.h:
Update to Visual DSP 5.0 Update 6.
This commit is contained in:
Jeff Johnston
@@ -13,7 +13,7 @@
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/*
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** defBF52x_base.h
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**
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** Copyright (C) 2008 Analog Devices, Inc.
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** Copyright (C) 2008, 2009 Analog Devices, Inc.
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**
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************************************************************************************
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**
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@@ -52,7 +52,6 @@
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/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
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#define SWRST 0xFFC00100 /* Software Reset Register */
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#define SYSCR 0xFFC00104 /* System Configuration Register */
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#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
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#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
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/* legacy register name (below) provided for backwards code compatibility */
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@@ -596,14 +595,10 @@
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#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
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#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
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#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
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#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
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#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
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#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
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#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
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#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
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#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
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#define NONGPIO_DRIVE 0xFFC03280 /* Drive strength control for non-GPIO pins */
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#define NONGPIO_SLEW 0xFFC03284 /* Slew control for non-GPIO pins */
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#define NONGPIO_HYSTERESIS 0xFFC03288 /* Schmitt trigger control for non-GPIO pins */
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/***********************************************************************************
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@@ -629,7 +624,11 @@
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#define BYPASS 0x0100 /* Bypass the PLL */
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#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
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/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
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#ifdef _MISRA_RULES
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#define SET_MSEL(x) (((x)&0x3Fu) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
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#else
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#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
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#endif /* _MISRA_RULES */
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/* PLL_DIV Masks */
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#define SSEL 0x000F /* System Select */
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@@ -639,7 +638,11 @@
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#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
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#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
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/* PLL_DIV Macros */
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#ifdef _MISRA_RULES
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#define SET_SSEL(x) ((x)&0xFu) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
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#else
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#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
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#endif /* _MISRA_RULES */
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/* VR_CTL Masks */
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#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
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@@ -667,6 +670,7 @@
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#define FULL_ON 0x0002 /* Processor In Full On Mode */
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#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
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#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
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#define VSTAT 0x0080 /* Voltage Regulator Status: Regulator at programmed voltage */
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/* SWRST Masks */
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#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
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@@ -675,9 +679,38 @@
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#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
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#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
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/* SYSCR Masks */
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#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
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#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
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/* SYSCR Masks */
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#define BMODE_BYPASS 0x0000 /* Bypass boot ROM, execute from 16-bit external memory */
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#define BMODE_FLASH 0x0001 /* Use Boot ROM to load from 8-bit or 16-bit flash */
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#define BMODE_SPIMEM 0x0003 /* Boot from serial SPI memory */
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#define BMODE_SPIHOST 0x0004 /* Boot from SPI0 host (slave mode) */
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#define BMODE_TWIMEM 0x0005 /* Boot from serial TWI memory */
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#define BMODE_TWIHOST 0x0006 /* Boot from TWI0 host (slave mode) */
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#define BMODE_UART0HOST 0x0007 /* Boot from UART0 host */
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#define BMODE_UART1HOST 0x0008 /* Boot from UART1 host */
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#define BMODE_SDRAMMEM 0x000A /* Boot from SDRAM memory (warm boot) */
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#define BMODE_OTPMEM 0x000B /* Boot from OTP memory */
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#define BMODE_HOSTDMA_ACK 0x000E /* Boot from 16-bit host DMA (ACK mode) */
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#define BMODE_HOSTDMA_INT 0x000F /* Boot from 8-bit host DMA (INT mode) */
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#define BMODE 0x000F /* Boot Mode. Mirror of BMODE Mode Pins */
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#define BCODE 0x00F0
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#define BCODE_NORMAL 0x0000 /* normal boot, update PLL/VR, quickboot as by WURESET */
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#define BCODE_NOBOOT 0x0010 /* bypass boot, don't update PLL/VR */
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#define BCODE_QUICKBOOT 0x0020 /* quick boot, overrule WURESET, don't update PLL/VR */
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#define BCODE_ALLBOOT 0x0040 /* no quick boot, overrule WURESET, don't update PLL/VR */
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#define BCODE_FULLBOOT 0x0060 /* no quick boot, overrule WURESET, update PLL/VR */
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#define DCB1_PRIO 0x0100 /* DCB1 requests are urgent */
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#define DCB_ROT_PRIO 0x0200 /* enable rotating DCB priority */
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#define DEB1_PRIO 0x0400 /* DEB1 requests are urgent */
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#define DEB_ROT_PRIO 0x0800 /* enable rotating DEB priority */
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#define WURESET 0x1000 /* wakeup event since last hardware reset */
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#define DFRESET 0x2000 /* recent reset was due to a double fault event */
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#define WDRESET 0x4000 /* recent reset was due to a watchdog event */
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#define SWRESET 0x8000 /* recent reset was issued by software */
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/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
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/* Peripheral Masks For SIC_ISR0, SIC_IWR0, SIC_IMASK0 */
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@@ -742,116 +775,159 @@
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#define IRQ_USB_INT2 0x00400000 /* USB INT1 interrupt */
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#define IRQ_USB_DMAINT 0x00800000 /* USB DMAINT interrupt */
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/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
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#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
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#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
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/* x = pos 0 to 31, for 32-63 use value-32 */
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#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
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#ifdef _MISRA_RULES
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#define IWR_DISABLE(x) (0xFFFFFFFFu^(1<<(x)))/* Wakeup Disable Peripheral #x */
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#else
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#define IWR_DISABLE(x) (0xFFFFFFFF^(1<<(x)))/* Wakeup Disable Peripheral #x */
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#endif /* _MISRA_RULES */
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#ifdef _MISRA_RULES
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#define _MF15 0xFu
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#define _MF7 7u
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#else
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#define _MF15 0xF
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#define _MF7 7
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#endif /* _MISRA_RULES */
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/* SIC_IAR0 Macros */
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#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
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#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
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#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
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#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
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#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
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#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
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#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
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#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
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#define P0_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #0 assigned IVG #x */
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#define P1_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #1 assigned IVG #x */
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#define P2_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #2 assigned IVG #x */
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#define P3_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #3 assigned IVG #x */
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#define P4_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #4 assigned IVG #x */
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#define P5_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #5 assigned IVG #x */
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#define P6_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #6 assigned IVG #x */
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#define P7_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #7 assigned IVG #x */
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/* SIC_IAR1 Macros */
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#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
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#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
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#define P10_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #10 assigned IVG #x */
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#define P11_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #11 assigned IVG #x */
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#define P12_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #12 assigned IVG #x */
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#define P13_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #13 assigned IVG #x */
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#define P8_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #8 assigned IVG #x */
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#define P9_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #9 assigned IVG #x */
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#define P10_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #10 assigned IVG #x */
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#define P11_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #11 assigned IVG #x */
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#define P12_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #12 assigned IVG #x */
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#define P13_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #13 assigned IVG #x */
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/* SIC_IAR2 Macros */
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#define P14_IVG(x) (((x)&0xF)-7) /* Peripheral #14 assigned IVG #x */
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#define P15_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #15 assigned IVG #x */
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#define P16_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #16 assigned IVG #x */
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#define P17_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #17 assigned IVG #x */
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#define P18_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #18 assigned IVG #x */
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#define P19_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #19 assigned IVG #x */
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#define P20_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #20 assigned IVG #x */
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#define P21_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #21 assigned IVG #x */
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#define P14_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #14 assigned IVG #x */
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#define P15_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #15 assigned IVG #x */
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#define P16_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #16 assigned IVG #x */
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#define P17_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #17 assigned IVG #x */
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#define P18_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #18 assigned IVG #x */
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#define P19_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #19 assigned IVG #x */
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#define P20_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #20 assigned IVG #x */
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#define P21_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #21 assigned IVG #x */
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/* SIC_IAR3 Macros */
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#define P22_IVG(x) (((x)&0xF)-7) /* Peripheral #22 assigned IVG #x */
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#define P23_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #23 assigned IVG #x */
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#define P24_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #24 assigned IVG #x */
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#define P25_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #25 assigned IVG #x */
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#define P26_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #26 assigned IVG #x */
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#define P27_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #27 assigned IVG #x */
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#define P28_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #28 assigned IVG #x */
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#define P29_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #29 assigned IVG #x */
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#define P22_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #22 assigned IVG #x */
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#define P23_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #23 assigned IVG #x */
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#define P24_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #24 assigned IVG #x */
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#define P25_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #25 assigned IVG #x */
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#define P26_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #26 assigned IVG #x */
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#define P27_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #27 assigned IVG #x */
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#define P28_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #28 assigned IVG #x */
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#define P29_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #29 assigned IVG #x */
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/* SIC_IAR4 Macros */
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#define P30_IVG(x) (((x)&0xF)-7) /* Peripheral #30 assigned IVG #x */
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#define P31_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #31 assigned IVG #x */
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#define P32_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #32 assigned IVG #x */
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#define P33_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #33 assigned IVG #x */
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#define P34_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #34 assigned IVG #x */
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#define P35_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #35 assigned IVG #x */
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#define P36_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #36 assigned IVG #x */
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#define P37_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #37 assigned IVG #x */
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#define P30_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #30 assigned IVG #x */
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#define P31_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #31 assigned IVG #x */
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#define P32_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #32 assigned IVG #x */
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#define P33_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #33 assigned IVG #x */
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#define P34_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #34 assigned IVG #x */
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#define P35_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #35 assigned IVG #x */
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#define P36_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #36 assigned IVG #x */
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#define P37_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #37 assigned IVG #x */
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/* SIC_IAR5 Macros */
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#define P38_IVG(x) (((x)&0xF)-7) /* Peripheral #38assigned IVG #x */
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#define P39_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #39assigned IVG #x */
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#define P40_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #40 assigned IVG #x */
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#define P41_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #41 assigned IVG #x */
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#define P42_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #42 assigned IVG #x */
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#define P43_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #43 assigned IVG #x */
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#define P44_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #44 assigned IVG #x */
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#define P45_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #45 assigned IVG #x */
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#define P38_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #38assigned IVG #x */
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#define P39_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #39assigned IVG #x */
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#define P40_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #40 assigned IVG #x */
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#define P41_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #41 assigned IVG #x */
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#define P42_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #42 assigned IVG #x */
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#define P43_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #43 assigned IVG #x */
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#define P44_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #44 assigned IVG #x */
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#define P45_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #45 assigned IVG #x */
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/* SIC_IAR6 Macros */
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#define P46_IVG(x) (((x)&0xF)-7) /* Peripheral #46 assigned IVG #x */
|
||||
#define P47_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #47 assigned IVG #x */
|
||||
#define P48_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #48 assigned IVG #x */
|
||||
#define P49_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #49 assigned IVG #x */
|
||||
#define P50_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #50 assigned IVG #x */
|
||||
#define P51_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #51 assigned IVG #x */
|
||||
#define P52_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #52 assigned IVG #x */
|
||||
#define P53_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #53 assigned IVG #x */
|
||||
#define P46_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #46 assigned IVG #x */
|
||||
#define P47_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #47 assigned IVG #x */
|
||||
#define P48_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #48 assigned IVG #x */
|
||||
#define P49_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #49 assigned IVG #x */
|
||||
#define P50_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #50 assigned IVG #x */
|
||||
#define P51_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #51 assigned IVG #x */
|
||||
#define P52_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #52 assigned IVG #x */
|
||||
#define P53_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #53 assigned IVG #x */
|
||||
|
||||
/* SIC_IAR7 Macros */
|
||||
#define P54_IVG(x) (((x)&0xF)-7) /* Peripheral #54 assigned IVG #x */
|
||||
#define P55_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #55 assigned IVG #x */
|
||||
#define P56_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #56 assigned IVG #x */
|
||||
#define P57_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #57 assigned IVG #x */
|
||||
#define P58_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #58 assigned IVG #x */
|
||||
#define P59_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #59 assigned IVG #x */
|
||||
#define P60_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #60 assigned IVG #x */
|
||||
#define P61_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #61 assigned IVG #x */
|
||||
#define P54_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #54 assigned IVG #x */
|
||||
#define P55_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #55 assigned IVG #x */
|
||||
#define P56_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #56 assigned IVG #x */
|
||||
#define P57_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #57 assigned IVG #x */
|
||||
#define P58_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #58 assigned IVG #x */
|
||||
#define P59_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #59 assigned IVG #x */
|
||||
#define P60_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #60 assigned IVG #x */
|
||||
#define P61_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #61 assigned IVG #x */
|
||||
|
||||
/* SIC_IMASK0 Masks */
|
||||
#define SIC_UNMASK0_ALL 0x00000000 /* Unmask all peripheral interrupts */
|
||||
#define SIC_MASK0_ALL 0xFFFFF3FF /* Mask all peripheral interrupts */
|
||||
#ifdef _MISRA_RULES
|
||||
#define SIC_MASK0(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
|
||||
#define SIC_UNMASK0(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */
|
||||
#else
|
||||
#define SIC_MASK0(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
|
||||
#define SIC_UNMASK0(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
|
||||
#endif /* _MISRA_RULES */
|
||||
|
||||
/* SIC_IMASK1 Masks */
|
||||
#define SIC_UNMASK1_ALL 0x00000000 /* Unmask all peripheral interrupts */
|
||||
#define SIC_MASK1_ALL 0xFFFFFF /* Mask all peripheral interrupts */
|
||||
#ifdef _MISRA_RULES
|
||||
#define SIC_MASK1(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
|
||||
#define SIC_UNMASK1(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */
|
||||
#else
|
||||
#define SIC_MASK1(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
|
||||
#define SIC_UNMASK1(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
|
||||
#endif /* _MISRA_RULES */
|
||||
|
||||
|
||||
/* SIC_IWR0 Masks */
|
||||
#define IWR0_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
|
||||
#define IWR0_ENABLE_ALL 0xFFFFF3FF /* Wakeup Enable all peripherals */
|
||||
#ifdef _MISRA_RULES
|
||||
#define IWR0_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
|
||||
#define IWR0_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x */
|
||||
#else
|
||||
#define IWR0_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
|
||||
#define IWR0_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
|
||||
#endif /* _MISRA_RULES */
|
||||
|
||||
/* SIC_IWR1 Masks */
|
||||
#define IWR1_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
|
||||
#define IWR1_ENABLE_ALL 0xFFFFFF /* Wakeup Enable all peripherals */
|
||||
#ifdef _MISRA_RULES
|
||||
#define IWR1_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
|
||||
#define IWR1_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x */
|
||||
#else
|
||||
#define IWR1_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
|
||||
#define IWR1_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
|
||||
#endif /* _MISRA_RULES */
|
||||
|
||||
|
||||
/* ********* WATCHDOG TIMER MASKS ******************** */
|
||||
|
||||
/* Watchdog Timer WDOG_CTL Register Masks */
|
||||
|
||||
#ifdef _MISRA_RULES
|
||||
#define WDEV(x) (((x)<<1) & 0x0006u) /* event generated on roll over */
|
||||
#else
|
||||
#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
|
||||
#endif /* _MISRA_RULES */
|
||||
#define WDEV_RESET 0x0000 /* generate reset event on roll over */
|
||||
#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
|
||||
#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
|
||||
@@ -890,7 +966,11 @@
|
||||
#define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */
|
||||
|
||||
/* RTC_ALARM Macro z=day y=hr x=min w=sec */
|
||||
#ifdef _MISRA_RULES
|
||||
#define SET_ALARM(z,y,x,w) ((((z)&0x7FFFu)<<0x11)|(((y)&0x1Fu)<<0xC)|(((x)&0x3Fu)<<0x6)|((w)&0x3Fu))
|
||||
#else
|
||||
#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
|
||||
#endif /* _MISRA_RULES */
|
||||
|
||||
/* RTC_ICTL and RTC_ISTAT Masks */
|
||||
#define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */
|
||||
@@ -909,7 +989,11 @@
|
||||
|
||||
/* ************** UART CONTROLLER MASKS *************************/
|
||||
/* UARTx_LCR Masks */
|
||||
#ifdef _MISRA_RULES
|
||||
#define WLS(x) (((x)-5u) & 0x03u) /* Word Length Select */
|
||||
#else
|
||||
#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
|
||||
#endif /* _MISRA_RULES */
|
||||
#define STB 0x04 /* Stop Bits */
|
||||
#define PEN 0x08 /* Parity Enable */
|
||||
#define EPS 0x10 /* Even Parity Select */
|
||||
@@ -947,6 +1031,10 @@
|
||||
#define FPE 0x10 /* Force Parity Error On Transmit */
|
||||
#define FFE 0x20 /* Force Framing Error On Transmit */
|
||||
|
||||
/* Bit masks for UART Divisor Latch Registers: UARTx_DLL & UARTx_DLH */
|
||||
#define UARTDLL 0x00FF /* Divisor Latch Low Byte */
|
||||
#define UARTDLH 0xFF00 /* Divisor Latch High Byte */
|
||||
|
||||
|
||||
/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
|
||||
/* SPI_CTL Masks */
|
||||
@@ -1126,7 +1214,7 @@
|
||||
/* SPORTx_TCR1 Masks */
|
||||
#define TSPEN 0x0001 /* Transmit Enable */
|
||||
#define ITCLK 0x0002 /* Internal Transmit Clock Select */
|
||||
#define DTYPE_NORM 0x0004 /* Data Format Normal */
|
||||
#define DTYPE_NORM 0x0000 /* Data Format Normal */
|
||||
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
|
||||
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
|
||||
#define TLSBIT 0x0010 /* Transmit Bit Order */
|
||||
@@ -1138,7 +1226,12 @@
|
||||
#define TCKFE 0x4000 /* Clock Falling Edge Select */
|
||||
|
||||
/* SPORTx_TCR2 Masks and Macro */
|
||||
#ifdef _MISRA_RULES
|
||||
#define SLEN(x) ((x)&0x1Fu) /* SPORT TX Word Length (2 - 31) */
|
||||
#else
|
||||
#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
|
||||
#endif /* _MISRA_RULES */
|
||||
|
||||
#define TXSE 0x0100 /* TX Secondary Enable */
|
||||
#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
|
||||
#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
|
||||
@@ -1146,7 +1239,7 @@
|
||||
/* SPORTx_RCR1 Masks */
|
||||
#define RSPEN 0x0001 /* Receive Enable */
|
||||
#define IRCLK 0x0002 /* Internal Receive Clock Select */
|
||||
#define DTYPE_NORM 0x0004 /* Data Format Normal */
|
||||
#define DTYPE_NORM 0x0000 /* Data Format Normal */
|
||||
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
|
||||
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
|
||||
#define RLSBIT 0x0010 /* Receive Bit Order */
|
||||
@@ -1157,7 +1250,11 @@
|
||||
#define RCKFE 0x4000 /* Clock Falling Edge Select */
|
||||
|
||||
/* SPORTx_RCR2 Masks */
|
||||
#ifdef _MISRA_RULES
|
||||
#define SLEN(x) ((x)&0x1Fu) /* SPORT RX Word Length (2 - 31) */
|
||||
#else
|
||||
#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
|
||||
#endif /* _MISRA_RULES */
|
||||
#define RXSE 0x0100 /* RX Secondary Enable */
|
||||
#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
|
||||
#define RRFST 0x0400 /* Right-First Data Order */
|
||||
@@ -1172,11 +1269,18 @@
|
||||
#define TXHRE 0x0040 /* Transmit Hold Register Empty */
|
||||
|
||||
/* SPORTx_MCMC1 Macros */
|
||||
#define WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
|
||||
#ifdef _MISRA_RULES
|
||||
#define WOFF(x) ((x) & 0x3FFu) /* Multichannel Window Offset Field */
|
||||
/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
|
||||
#define WSIZE(x) (((((x)>>0x3)-1u)&0xFu) << 0xC) /* Multichannel Window Size = (x/8)-1 */
|
||||
|
||||
#else
|
||||
#define WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
|
||||
/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
|
||||
#define WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
|
||||
|
||||
#endif /* _MISRA_RULES */
|
||||
|
||||
/* SPORTx_MCMC2 Masks */
|
||||
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
|
||||
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
|
||||
@@ -1206,6 +1310,7 @@
|
||||
/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
|
||||
/* EBIU_AMGCTL Masks */
|
||||
#define AMCKEN 0x0001 /* Enable CLKOUT */
|
||||
#define AMBEN 0x000e /* Async bank enable */
|
||||
#define AMBEN_NONE 0x0000 /* All Banks Disabled */
|
||||
#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
|
||||
#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
|
||||
@@ -1401,9 +1506,12 @@
|
||||
#define SCTLE 0x00000001 /* Enable SDRAM Signals */
|
||||
#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
|
||||
#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
|
||||
/* EBIU_SDGCTL Masks */
|
||||
#define CL 0x0000000C /* SDRAM CAS latency */
|
||||
#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
|
||||
#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
|
||||
#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
|
||||
#define PASR 0x00000030 /* SDRAM partial array self-refresh */
|
||||
#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
|
||||
#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
|
||||
#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
|
||||
@@ -1419,6 +1527,7 @@
|
||||
#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
|
||||
#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
|
||||
#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
|
||||
#define TRAS 0x000003C0 /* SDRAM tRAS in SCLK cycles */
|
||||
#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
|
||||
#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
|
||||
#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
|
||||
@@ -1426,6 +1535,7 @@
|
||||
#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
|
||||
#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
|
||||
#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
|
||||
#define TRP 0x00003800 /* SDRAM tRP in SCLK cycles */
|
||||
#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
|
||||
#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
|
||||
#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
|
||||
@@ -1433,9 +1543,11 @@
|
||||
#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
|
||||
#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
|
||||
#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
|
||||
#define TRCD 0x00030000 /* SDRAM tRCD in SCLK cycles */
|
||||
#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
|
||||
#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
|
||||
#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
|
||||
#define TWR 0x00180000 /* SDRAM tWR in SCLK cycles */
|
||||
#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
|
||||
#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
|
||||
#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
|
||||
@@ -1452,12 +1564,12 @@
|
||||
#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
|
||||
#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
|
||||
#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
|
||||
#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
|
||||
#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
|
||||
#define EBSZ 0x0006 /* SDRAM external bank size */
|
||||
#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
|
||||
#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
|
||||
#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
|
||||
#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
|
||||
#define EBCAW 0x0030 /* SDRAM external bank column address width */
|
||||
|
||||
/* EBIU_SDSTAT Masks */
|
||||
#define SDCI 0x0001 /* SDRAM Controller Idle */
|
||||
@@ -1553,8 +1665,13 @@
|
||||
|
||||
/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
|
||||
/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
|
||||
#ifdef _MISRA_RULES
|
||||
#define CLKLOW(x) ((x) & 0xFFu) /* Periods Clock Is Held Low */
|
||||
#define CLKHI(y) (((y)&0xFFu)<<0x8) /* Periods Before New Clock Low */
|
||||
#else
|
||||
#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
|
||||
#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
|
||||
#endif /* _MISRA_RULES */
|
||||
|
||||
/* TWI_PRESCALE Masks */
|
||||
#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
|
||||
@@ -1625,51 +1742,7 @@
|
||||
/* Omit CAN masks from defBF534.h */
|
||||
|
||||
/* ******************* PIN CONTROL REGISTER MASKS ************************/
|
||||
/* PORT_MUX Masks */
|
||||
#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
|
||||
#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
|
||||
#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
|
||||
|
||||
#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
|
||||
#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
|
||||
#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
|
||||
#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
|
||||
|
||||
#define PFDE 0x0008 /* Port F DMA Request Enable */
|
||||
#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
|
||||
#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
|
||||
|
||||
#define PFTE 0x0010 /* Port F Timer Enable */
|
||||
#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
|
||||
#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
|
||||
|
||||
#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
|
||||
#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
|
||||
#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
|
||||
|
||||
#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
|
||||
#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
|
||||
#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
|
||||
|
||||
#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
|
||||
#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
|
||||
#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
|
||||
|
||||
#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
|
||||
#define PFFE_TIMER 0x0000 /* Enable TMR2 */
|
||||
#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
|
||||
|
||||
#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
|
||||
#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
|
||||
#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
|
||||
|
||||
#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
|
||||
#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
|
||||
#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
|
||||
|
||||
#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
|
||||
#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
|
||||
#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
|
||||
/* PORT_MUX deleted in VisualDSP++ 5.0 Update 3 */
|
||||
|
||||
|
||||
/* ****************** HANDSHAKE DMA (HMDMA) MASKS *********************/
|
||||
@@ -1903,46 +1976,6 @@
|
||||
|
||||
#define DPRESCALE 0xf /* Load Counter Register */
|
||||
|
||||
/* Bit masks for OTP_CONTROL */
|
||||
|
||||
#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
|
||||
#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
|
||||
#define nFIEN 0x0
|
||||
#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
|
||||
#define nFTESTDEC 0x0
|
||||
#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
|
||||
#define nFWRTEST 0x0
|
||||
#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
|
||||
#define nFRDEN 0x0
|
||||
#define FWREN 0x8000 /* OTP/Fuse Write Enable */
|
||||
#define nFWREN 0x0
|
||||
|
||||
/* Bit masks for OTP_BEN */
|
||||
|
||||
#define FBEN 0xffff /* OTP/Fuse Byte Enable */
|
||||
|
||||
/* Bit masks for OTP_STATUS */
|
||||
|
||||
#define FCOMP 0x1 /* OTP/Fuse Access Complete */
|
||||
#define nFCOMP 0x0
|
||||
#define FERROR 0x2 /* OTP/Fuse Access Error */
|
||||
#define nFERROR 0x0
|
||||
#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
|
||||
#define nMMRGLOAD 0x0
|
||||
#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
|
||||
#define nMMRGLOCK 0x0
|
||||
#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
|
||||
#define nFPGMEN 0x0
|
||||
|
||||
/* Bit masks for OTP_TIMING */
|
||||
|
||||
#define USECDIV 0xff /* Micro Second Divider */
|
||||
#define READACC 0x7f00 /* Read Access Time */
|
||||
#define CPUMPRL 0x38000 /* Charge Pump Release Time */
|
||||
#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
|
||||
#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
|
||||
#define PGMTIME 0xff000000 /* Program Time */
|
||||
|
||||
/* Bit masks for SECURE_SYSSWT */
|
||||
|
||||
#define EMUDABL 0x1 /* Emulation Disable. */
|
||||
@@ -1960,7 +1993,6 @@
|
||||
#define nEMUOVR 0x0
|
||||
#define OTPSEN 0x8000 /* OTP Secrets Enable. */
|
||||
#define nOTPSEN 0x0
|
||||
#define L2DABL 0x70000 /* L2 Memory Disable. */
|
||||
|
||||
/* Bit masks for SECURE_CONTROL */
|
||||
|
||||
|
||||
Reference in New Issue
Block a user