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* archures.c (bfd_mach_mips_loongson_2e): New.
	(bfd_mach_mips_loongson_2f): New.
	* bfd-in2.h (bfd_mach_mips_loongson_2e): New.
	(bfd_mach_mips_loongson_2f): New.
	* cpu-mips.c: Add I_loongson_2e and I_loongson_2f to
	anonymous enum.
	(arch_info_struct): Add Loongson-2E and Loongson-2F entries.
	* elfxx-mips.c (_bfd_elf_mips_mach): Handle Loongson-2E
	and Loongson-2F flags.
	(mips_set_isa_flags): Likewise.
	(mips_mach_extensions): Add Loongson-2E and Loongson-2F
	entries.

	binutils/
	* readelf.c (get_machine_flags): Handle Loongson-2E and -2F
	flags.

	gas/
	* config/tc-mips.c (mips_cpu_info_table): Add loongson2e
	and loongson2f entries.
	* doc/c-mips.texi: Document -march=loongson{2e,2f} options.

	gas/testsuite/
	* gas/mips/mips.exp: Add loongson-2e and -2f tests.
	* gas/mips/loongson-2e.d: New.
	* gas/mips/loongson-2e.s: New.
	* gas/mips/loongson-2f.d: New.
	* gas/mips/loongson-2f.s: New.

	include/elf/
	* mips.h (E_MIPS_MACH_LS2E): New.
	(E_MIPS_MACH_LS2F): New.

	include/opcode/
	* mips.h (INSN_LOONGSON_2E): New.
	(INSN_LOONGSON_2F): New.
	(CPU_LOONGSON_2E): New.
	(CPU_LOONGSON_2F): New.
	(OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.

	opcodes/
	* mips-dis.c (mips_arch_choices): Add Loongson-2E and -2F
	entries.
	* mips-opc.c (IL2E): New.
	(IL2F): New.
	(mips_builtin_opcodes): Add Loongson-2E and -2F instructions.
	Allow movz and movn for Loongson-2E and -2F.  Add movnz entry.
	Move coprocessor encodings to the end of the table.  Allow
	certain MIPS V .ps instructions on the Loongson-2E and -2F.
This commit is contained in:
Mark Shinwell 2007-11-29 12:23:44 +00:00
parent 35e137475d
commit 47c9864a0a
4 changed files with 25 additions and 0 deletions
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5
include/elf/ChangeLog
View File

@ -1,3 +1,8 @@
2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
* mips.h (E_MIPS_MACH_LS2E): New.
(E_MIPS_MACH_LS2F): New.
2007-11-28 Nathan Sidwell <nathan@codesourcery.com> 2007-11-28 Nathan Sidwell <nathan@codesourcery.com>
* internal.h (ELF_IS_SECTION_IN_SEGMENT): Adjust to cope with * internal.h (ELF_IS_SECTION_IN_SEGMENT): Adjust to cope with

2
include/elf/mips.h
View File

@ -216,6 +216,8 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
#define E_MIPS_MACH_5400 0x00910000 #define E_MIPS_MACH_5400 0x00910000
#define E_MIPS_MACH_5500 0x00980000 #define E_MIPS_MACH_5500 0x00980000
#define E_MIPS_MACH_9000 0x00990000 #define E_MIPS_MACH_9000 0x00990000
#define E_MIPS_MACH_LS2E 0x00A00000
#define E_MIPS_MACH_LS2F 0x00A10000
/* Processor specific section indices. These sections do not actually /* Processor specific section indices. These sections do not actually
exist. Symbols with a st_shndx field corresponding to one of these exist. Symbols with a st_shndx field corresponding to one of these

8
include/opcode/ChangeLog
View File

@ -1,3 +1,11 @@
2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
* mips.h (INSN_LOONGSON_2E): New.
(INSN_LOONGSON_2F): New.
(CPU_LOONGSON_2E): New.
(CPU_LOONGSON_2F): New.
(OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
2007-11-29 Mark Shinwell <shinwell@codesourcery.com> 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
* mips.h (INSN_ISA*): Redefine certain values as an * mips.h (INSN_ISA*): Redefine certain values as an

10
include/opcode/mips.h
View File

@ -552,6 +552,10 @@ static const unsigned int mips_isa_table[] =
#define INSN_SMARTMIPS 0x10000000 #define INSN_SMARTMIPS 0x10000000
/* DSP R2 ASE */ /* DSP R2 ASE */
#define INSN_DSPR2 0x20000000 #define INSN_DSPR2 0x20000000
/* ST Microelectronics Loongson 2E. */
#define INSN_LOONGSON_2E 0x40000000
/* ST Microelectronics Loongson 2F. */
#define INSN_LOONGSON_2F 0x80000000
/* MIPS ISA defines, use instead of hardcoding ISA level. */ /* MIPS ISA defines, use instead of hardcoding ISA level. */
@ -599,6 +603,8 @@ static const unsigned int mips_isa_table[] =
#define CPU_MIPS64 64 #define CPU_MIPS64 64
#define CPU_MIPS64R2 65 #define CPU_MIPS64R2 65
#define CPU_SB1 12310201 /* octal 'SB', 01. */ #define CPU_SB1 12310201 /* octal 'SB', 01. */
#define CPU_LOONGSON_2E 3001
#define CPU_LOONGSON_2F 3002
/* Test for membership in an ISA including chip specific ISAs. INSN /* Test for membership in an ISA including chip specific ISAs. INSN
is pointer to an element of the opcode table; ISA is the specified is pointer to an element of the opcode table; ISA is the specified
@ -625,6 +631,10 @@ static const unsigned int mips_isa_table[] =
|| (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
|| (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
|| (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
|| (cpu == CPU_LOONGSON_2E \
&& ((insn)->membership & INSN_LOONGSON_2E) != 0) \
|| (cpu == CPU_LOONGSON_2F \
&& ((insn)->membership & INSN_LOONGSON_2F) != 0) \
|| 0) /* Please keep this term for easier source merging. */ || 0) /* Please keep this term for easier source merging. */
/* This is a list of macro expanded instructions. /* This is a list of macro expanded instructions.