Add MIPS32 as a seperate MIPS architecture
This commit is contained in:
Nick Clifton
14
config.sub
vendored
14
config.sub
vendored
@@ -211,10 +211,11 @@ esac
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case $basic_machine in
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case $basic_machine in
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# Recognize the basic CPU types without company name.
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# Recognize the basic CPU types without company name.
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# Some are omitted here because they have special meanings below.
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# Some are omitted here because they have special meanings below.
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tahoe | i860 | ia64 | m32r | m68k | m68000 | m88k | ns32k | arc | arm \
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tahoe | i860 | ia64 | m32r | m68k | m68000 | m88k | ns32k | arc \
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| arme[lb] | armv[2345] | armv[345][lb] | pyramid | mn10200 | mn10300 | tron | a29k \
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| arm | arme[lb] | arm[bl]e | armv[2345] | armv[345][lb] | strongarm | xscale \
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| pyramid | mn10200 | mn10300 | tron | a29k \
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| 580 | i960 | h8300 \
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| 580 | i960 | h8300 \
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| x86 | ppcbe | mipsbe | mipsle | shbe | shle | armbe | armle \
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| x86 | ppcbe | mipsbe | mipsle | shbe | shle \
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| hppa | hppa1.0 | hppa1.1 | hppa2.0 | hppa2.0w | hppa2.0n \
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| hppa | hppa1.0 | hppa1.1 | hppa2.0 | hppa2.0w | hppa2.0n \
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| hppa64 \
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| hppa64 \
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| alpha | alphaev[4-8] | alphaev56 | alphapca5[67] \
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| alpha | alphaev[4-8] | alphaev56 | alphapca5[67] \
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@@ -251,11 +252,12 @@ case $basic_machine in
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# Recognize the basic CPU types with company name.
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# Recognize the basic CPU types with company name.
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# FIXME: clean up the formatting here.
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# FIXME: clean up the formatting here.
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vax-* | tahoe-* | i[234567]86-* | i860-* | ia64-* | m32r-* | m68k-* | m68000-* \
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vax-* | tahoe-* | i[234567]86-* | i860-* | ia64-* | m32r-* | m68k-* | m68000-* \
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| m88k-* | sparc-* | ns32k-* | fx80-* | arc-* | arm-* | c[123]* \
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| m88k-* | sparc-* | ns32k-* | fx80-* | arc-* | c[123]* \
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| arm-* | armbe-* | armle-* | armv*-* | strongarm-* | xscale-* \
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| mips-* | pyramid-* | tron-* | a29k-* | romp-* | rs6000-* \
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| mips-* | pyramid-* | tron-* | a29k-* | romp-* | rs6000-* \
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| power-* | none-* | 580-* | cray2-* | h8300-* | h8500-* | i960-* \
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| power-* | none-* | 580-* | cray2-* | h8300-* | h8500-* | i960-* \
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| xmp-* | ymp-* \
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| xmp-* | ymp-* \
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| x86-* | ppcbe-* | mipsbe-* | mipsle-* | shbe-* | shle-* | armbe-* | armle-* \
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| x86-* | ppcbe-* | mipsbe-* | mipsle-* | shbe-* | shle-* \
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| hppa-* | hppa1.0-* | hppa1.1-* | hppa2.0-* | hppa2.0w-* \
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| hppa-* | hppa1.0-* | hppa1.1-* | hppa2.0-* | hppa2.0w-* \
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| hppa2.0n-* | hppa64-* \
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| hppa2.0n-* | hppa64-* \
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| alpha-* | alphaev[4-8]-* | alphaev56-* | alphapca5[67]-* \
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| alpha-* | alphaev[4-8]-* | alphaev56-* | alphapca5[67]-* \
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@@ -267,7 +269,7 @@ case $basic_machine in
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| mips64el-* | mips64orion-* | mips64orionel-* \
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| mips64el-* | mips64orion-* | mips64orionel-* \
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| mips64vr4100-* | mips64vr4100el-* | mips64vr4300-* | mips64vr4300el-* \
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| mips64vr4100-* | mips64vr4100el-* | mips64vr4300-* | mips64vr4300el-* \
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| mipstx39-* | mipstx39el-* | mcore-* \
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| mipstx39-* | mipstx39el-* | mcore-* \
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| f301-* | armv*-* | s390-* | sv1-* | t3e-* \
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| f301-* | s390-* | sv1-* | t3e-* \
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| m88110-* | m680[01234]0-* | m683?2-* | m68360-* | z8k-* | d10v-* \
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| m88110-* | m680[01234]0-* | m683?2-* | m68360-* | z8k-* | d10v-* \
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| thumb-* | v850-* | d30v-* | tic30-* | c30-* | fr30-* \
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| thumb-* | v850-* | d30v-* | tic30-* | c30-* | fr30-* \
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| bs2000-* | tic54x-* | c54x-* | x86_64-*)
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| bs2000-* | tic54x-* | c54x-* | x86_64-*)
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@@ -1,3 +1,9 @@
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2000-10-16 Chris Demetriou <cgd@sibyte.com>
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* mips.h (E_MIPS_ARCH_32): New constant.
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(E_MIPS_MACH_MIPS32, E_MIPS_MACH_MIPS32_4K): Replace the
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former with the latter.
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2000-11-30 Jan Hubicka <jh@suse.cz>
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2000-11-30 Jan Hubicka <jh@suse.cz>
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* common.h (EM_X86_64): New macro.
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* common.h (EM_X86_64): New macro.
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@@ -121,6 +121,9 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
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/* -mips4 code. */
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/* -mips4 code. */
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#define E_MIPS_ARCH_4 0x30000000
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#define E_MIPS_ARCH_4 0x30000000
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/* -mips32 code. */
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#define E_MIPS_ARCH_32 0x50000000
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/* The ABI of the file. Also see EF_MIPS_ABI2 above. */
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/* The ABI of the file. Also see EF_MIPS_ABI2 above. */
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#define EF_MIPS_ABI 0x0000F000
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#define EF_MIPS_ABI 0x0000F000
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@@ -153,9 +156,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
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#define E_MIPS_MACH_4100 0x00830000
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#define E_MIPS_MACH_4100 0x00830000
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#define E_MIPS_MACH_4650 0x00850000
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#define E_MIPS_MACH_4650 0x00850000
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#define E_MIPS_MACH_4111 0x00880000
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#define E_MIPS_MACH_4111 0x00880000
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/* -mips32 code.
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#define E_MIPS_MACH_MIPS32_4K 0x00890000
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It is easier to treat MIPS32 as a machine rather than an architecture. */
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#define E_MIPS_MACH_MIPS32 0x00890000
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/* Processor specific section indices. These sections do not actually
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/* Processor specific section indices. These sections do not actually
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exist. Symbols with a st_shndx field corresponding to one of these
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exist. Symbols with a st_shndx field corresponding to one of these
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@@ -8,6 +8,23 @@
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(MIPS operand specifier comments): Remove 'm', add 'U' and
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(MIPS operand specifier comments): Remove 'm', add 'U' and
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'J', and update the meaning of 'B' so that it's more general.
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'J', and update the meaning of 'B' so that it's more general.
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* mips.h (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4,
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INSN_ISA5): Renumber, redefine to mean the ISA at which the
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instruction was added.
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(INSN_ISA32): New constant.
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(INSN_4650, INSN_4010, INSN_4100, INSN_3900, INSN_GP32):
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Renumber to avoid new and/or renumbered INSN_* constants.
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(INSN_MIPS32): Delete.
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(ISA_UNKNOWN): New constant to indicate unknown ISA.
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(ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5,
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ISA_MIPS32): New constants, defined to be the mask of INSN_*
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constants available at that ISA level.
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(CPU_UNKNOWN): New constant to indicate unknown CPU.
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(CPU_4K, CPU_MIPS32_4K): Rename the former to the latter,
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define it with a unique value.
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(OPCODE_IS_MEMBER): Update for new ISA membership-related
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constant meanings.
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2000-10-20 Jakub Jelinek <jakub@redhat.com>
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2000-10-20 Jakub Jelinek <jakub@redhat.com>
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* sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.
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* sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.
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@@ -302,41 +302,43 @@ struct mips_opcode
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disassembler, and requires special treatment by the assembler. */
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disassembler, and requires special treatment by the assembler. */
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#define INSN_MACRO 0xffffffff
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#define INSN_MACRO 0xffffffff
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/* Masks used to mark instructions to indicate which MIPS ISA level
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they were introduced in. ISAs, as defined below, are logical
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ORs of these bits, indicatingthat they support the instructions
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defined at the given level. */
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#define INSN_ISA1 0x00000010
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#define INSN_ISA2 0x00000020
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#define INSN_ISA3 0x00000040
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/* MIPS ISA field--CPU level at which insn is supported. */
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#define INSN_ISA4 0x00000080
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#define INSN_ISA 0x0000000F
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#define INSN_ISA5 0x00000100
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/* An instruction which is not part of any basic MIPS ISA.
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#define INSN_ISA32 0x00000200
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(ie it is a chip specific instruction) */
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#define INSN_NO_ISA 0x00000000
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/* MIPS ISA 1 instruction. */
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#define INSN_ISA1 0x00000001
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/* MIPS ISA 2 instruction (R6000 or R4000). */
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#define INSN_ISA2 0x00000002
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/* MIPS ISA 3 instruction (R4000). */
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#define INSN_ISA3 0x00000003
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/* MIPS ISA 4 instruction (R8000). */
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#define INSN_ISA4 0x00000004
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#define INSN_ISA5 0x00000005
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/* Chip specific instructions. These are bitmasks. */
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/* Chip specific instructions. These are bitmasks. */
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/* MIPS R4650 instruction. */
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/* MIPS R4650 instruction. */
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#define INSN_4650 0x00000010
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#define INSN_4650 0x00010000
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/* LSI R4010 instruction. */
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/* LSI R4010 instruction. */
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#define INSN_4010 0x00000020
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#define INSN_4010 0x00020000
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/* NEC VR4100 instruction. */
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/* NEC VR4100 instruction. */
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#define INSN_4100 0x00000040
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#define INSN_4100 0x00040000
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/* Toshiba R3900 instruction. */
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/* Toshiba R3900 instruction. */
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#define INSN_3900 0x00000080
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#define INSN_3900 0x00080000
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/* MIPS32 instruction (4Kc, 4Km, 4Kp). */
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/* 32-bit code running on a ISA3+ CPU. */
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#define INSN_MIPS32 0x00000100
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#define INSN_GP32 0x00100000
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/* 32-bit code running on a ISA3+ CPU. */
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#define INSN_GP32 0x00001000
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/* MIPS ISA defines, use instead of hardcoding ISA level. */
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#define ISA_UNKNOWN 0 /* Gas internal use. */
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#define ISA_MIPS1 (INSN_ISA1)
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#define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
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#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
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#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
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#define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
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/* CPU defines, use instead of hardcoding processor number. Keep this
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/* CPU defines, use instead of hardcoding processor number. Keep this
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in sync with bfd/archures.c in order for machine selection to work. */
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in sync with bfd/archures.c in order for machine selection to work. */
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#define CPU_UNKNOWN 0 /* Gas internal use. */
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#define CPU_R2000 2000
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#define CPU_R2000 2000
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#define CPU_R3000 3000
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#define CPU_R3000 3000
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#define CPU_R3900 3900
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#define CPU_R3900 3900
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@@ -354,7 +356,7 @@ struct mips_opcode
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#define CPU_R10000 10000
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#define CPU_R10000 10000
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#define CPU_MIPS16 16
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#define CPU_MIPS16 16
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#define CPU_MIPS32 32
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#define CPU_MIPS32 32
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#define CPU_4K CPU_MIPS32
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#define CPU_MIPS32_4K 3204113 /* 32, 04, octal 'K' */
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/* Test for membership in an ISA including chip specific ISAs.
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/* Test for membership in an ISA including chip specific ISAs.
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INSN is pointer to an element of the opcode table; ISA is the
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INSN is pointer to an element of the opcode table; ISA is the
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@@ -365,236 +367,235 @@ struct mips_opcode
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in the MIPS gas docs. */
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in the MIPS gas docs. */
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#define OPCODE_IS_MEMBER(insn, isa, cpu, gp32) \
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#define OPCODE_IS_MEMBER(insn, isa, cpu, gp32) \
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((((insn)->membership & INSN_ISA) != 0 \
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((((insn)->membership & isa) != 0 \
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&& ((insn)->membership & INSN_ISA) <= (unsigned) isa \
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&& ((insn)->membership & INSN_GP32 ? gp32 : 1)) \
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&& ((insn)->membership & INSN_GP32 ? gp32 : 1)) \
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|| (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
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|| (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
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|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
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|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
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|| ((cpu == CPU_VR4100 || cpu == CPU_R4111) \
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|| ((cpu == CPU_VR4100 || cpu == CPU_R4111) \
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&& ((insn)->membership & INSN_4100) != 0) \
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&& ((insn)->membership & INSN_4100) != 0) \
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|| (cpu == CPU_MIPS32 && ((insn)->membership & INSN_MIPS32) != 0) \
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|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0))
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|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0))
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/* This is a list of macro expanded instructions.
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/* This is a list of macro expanded instructions.
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*
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* _I appended means immediate
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_I appended means immediate
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* _A appended means address
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_A appended means address
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* _AB appended means address with base register
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_AB appended means address with base register
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* _D appended means 64 bit floating point constant
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_D appended means 64 bit floating point constant
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* _S appended means 32 bit floating point constant
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_S appended means 32 bit floating point constant. */
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*/
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enum {
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enum
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M_ABS,
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{
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M_ADD_I,
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M_ABS,
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M_ADDU_I,
|
M_ADD_I,
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M_AND_I,
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M_ADDU_I,
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M_BEQ,
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M_AND_I,
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M_BEQ_I,
|
M_BEQ,
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M_BEQL_I,
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M_BEQ_I,
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M_BGE,
|
M_BEQL_I,
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M_BGEL,
|
M_BGE,
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||||||
M_BGE_I,
|
M_BGEL,
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M_BGEL_I,
|
M_BGE_I,
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||||||
M_BGEU,
|
M_BGEL_I,
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M_BGEUL,
|
M_BGEU,
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||||||
M_BGEU_I,
|
M_BGEUL,
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||||||
M_BGEUL_I,
|
M_BGEU_I,
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||||||
M_BGT,
|
M_BGEUL_I,
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||||||
M_BGTL,
|
M_BGT,
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M_BGT_I,
|
M_BGTL,
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||||||
M_BGTL_I,
|
M_BGT_I,
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||||||
M_BGTU,
|
M_BGTL_I,
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||||||
M_BGTUL,
|
M_BGTU,
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||||||
M_BGTU_I,
|
M_BGTUL,
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||||||
M_BGTUL_I,
|
M_BGTU_I,
|
||||||
M_BLE,
|
M_BGTUL_I,
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||||||
M_BLEL,
|
M_BLE,
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||||||
M_BLE_I,
|
M_BLEL,
|
||||||
M_BLEL_I,
|
M_BLE_I,
|
||||||
M_BLEU,
|
M_BLEL_I,
|
||||||
M_BLEUL,
|
M_BLEU,
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||||||
M_BLEU_I,
|
M_BLEUL,
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||||||
M_BLEUL_I,
|
M_BLEU_I,
|
||||||
M_BLT,
|
M_BLEUL_I,
|
||||||
M_BLTL,
|
M_BLT,
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||||||
M_BLT_I,
|
M_BLTL,
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||||||
M_BLTL_I,
|
M_BLT_I,
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||||||
M_BLTU,
|
M_BLTL_I,
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||||||
M_BLTUL,
|
M_BLTU,
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||||||
M_BLTU_I,
|
M_BLTUL,
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||||||
M_BLTUL_I,
|
M_BLTU_I,
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||||||
M_BNE,
|
M_BLTUL_I,
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||||||
M_BNE_I,
|
M_BNE,
|
||||||
M_BNEL_I,
|
M_BNE_I,
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||||||
M_DABS,
|
M_BNEL_I,
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||||||
M_DADD_I,
|
M_DABS,
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||||||
M_DADDU_I,
|
M_DADD_I,
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||||||
M_DDIV_3,
|
M_DADDU_I,
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||||||
M_DDIV_3I,
|
M_DDIV_3,
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||||||
M_DDIVU_3,
|
M_DDIV_3I,
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||||||
M_DDIVU_3I,
|
M_DDIVU_3,
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||||||
M_DIV_3,
|
M_DDIVU_3I,
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||||||
M_DIV_3I,
|
M_DIV_3,
|
||||||
M_DIVU_3,
|
M_DIV_3I,
|
||||||
M_DIVU_3I,
|
M_DIVU_3,
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||||||
M_DLA_AB,
|
M_DIVU_3I,
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||||||
M_DLI,
|
M_DLA_AB,
|
||||||
M_DMUL,
|
M_DLI,
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||||||
M_DMUL_I,
|
M_DMUL,
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M_DMULO,
|
M_DMUL_I,
|
||||||
M_DMULO_I,
|
M_DMULO,
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||||||
M_DMULOU,
|
M_DMULO_I,
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||||||
M_DMULOU_I,
|
M_DMULOU,
|
||||||
M_DREM_3,
|
M_DMULOU_I,
|
||||||
M_DREM_3I,
|
M_DREM_3,
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||||||
M_DREMU_3,
|
M_DREM_3I,
|
||||||
M_DREMU_3I,
|
M_DREMU_3,
|
||||||
M_DSUB_I,
|
M_DREMU_3I,
|
||||||
M_DSUBU_I,
|
M_DSUB_I,
|
||||||
M_DSUBU_I_2,
|
M_DSUBU_I,
|
||||||
M_J_A,
|
M_DSUBU_I_2,
|
||||||
M_JAL_1,
|
M_J_A,
|
||||||
M_JAL_2,
|
M_JAL_1,
|
||||||
M_JAL_A,
|
M_JAL_2,
|
||||||
M_L_DOB,
|
M_JAL_A,
|
||||||
M_L_DAB,
|
M_L_DOB,
|
||||||
M_LA_AB,
|
M_L_DAB,
|
||||||
M_LB_A,
|
M_LA_AB,
|
||||||
M_LB_AB,
|
M_LB_A,
|
||||||
M_LBU_A,
|
M_LB_AB,
|
||||||
M_LBU_AB,
|
M_LBU_A,
|
||||||
M_LD_A,
|
M_LBU_AB,
|
||||||
M_LD_OB,
|
M_LD_A,
|
||||||
M_LD_AB,
|
M_LD_OB,
|
||||||
M_LDC1_AB,
|
M_LD_AB,
|
||||||
M_LDC2_AB,
|
M_LDC1_AB,
|
||||||
M_LDC3_AB,
|
M_LDC2_AB,
|
||||||
M_LDL_AB,
|
M_LDC3_AB,
|
||||||
M_LDR_AB,
|
M_LDL_AB,
|
||||||
M_LH_A,
|
M_LDR_AB,
|
||||||
M_LH_AB,
|
M_LH_A,
|
||||||
M_LHU_A,
|
M_LH_AB,
|
||||||
M_LHU_AB,
|
M_LHU_A,
|
||||||
M_LI,
|
M_LHU_AB,
|
||||||
M_LI_D,
|
M_LI,
|
||||||
M_LI_DD,
|
M_LI_D,
|
||||||
M_LI_S,
|
M_LI_DD,
|
||||||
M_LI_SS,
|
M_LI_S,
|
||||||
M_LL_AB,
|
M_LI_SS,
|
||||||
M_LLD_AB,
|
M_LL_AB,
|
||||||
M_LS_A,
|
M_LLD_AB,
|
||||||
M_LW_A,
|
M_LS_A,
|
||||||
M_LW_AB,
|
M_LW_A,
|
||||||
M_LWC0_A,
|
M_LW_AB,
|
||||||
M_LWC0_AB,
|
M_LWC0_A,
|
||||||
M_LWC1_A,
|
M_LWC0_AB,
|
||||||
M_LWC1_AB,
|
M_LWC1_A,
|
||||||
M_LWC2_A,
|
M_LWC1_AB,
|
||||||
M_LWC2_AB,
|
M_LWC2_A,
|
||||||
M_LWC3_A,
|
M_LWC2_AB,
|
||||||
M_LWC3_AB,
|
M_LWC3_A,
|
||||||
M_LWL_A,
|
M_LWC3_AB,
|
||||||
M_LWL_AB,
|
M_LWL_A,
|
||||||
M_LWR_A,
|
M_LWL_AB,
|
||||||
M_LWR_AB,
|
M_LWR_A,
|
||||||
M_LWU_AB,
|
M_LWR_AB,
|
||||||
M_MUL,
|
M_LWU_AB,
|
||||||
M_MUL_I,
|
M_MUL,
|
||||||
M_MULO,
|
M_MUL_I,
|
||||||
M_MULO_I,
|
M_MULO,
|
||||||
M_MULOU,
|
M_MULO_I,
|
||||||
M_MULOU_I,
|
M_MULOU,
|
||||||
M_NOR_I,
|
M_MULOU_I,
|
||||||
M_OR_I,
|
M_NOR_I,
|
||||||
M_REM_3,
|
M_OR_I,
|
||||||
M_REM_3I,
|
M_REM_3,
|
||||||
M_REMU_3,
|
M_REM_3I,
|
||||||
M_REMU_3I,
|
M_REMU_3,
|
||||||
M_ROL,
|
M_REMU_3I,
|
||||||
M_ROL_I,
|
M_ROL,
|
||||||
M_ROR,
|
M_ROL_I,
|
||||||
M_ROR_I,
|
M_ROR,
|
||||||
M_S_DA,
|
M_ROR_I,
|
||||||
M_S_DOB,
|
M_S_DA,
|
||||||
M_S_DAB,
|
M_S_DOB,
|
||||||
M_S_S,
|
M_S_DAB,
|
||||||
M_SC_AB,
|
M_S_S,
|
||||||
M_SCD_AB,
|
M_SC_AB,
|
||||||
M_SD_A,
|
M_SCD_AB,
|
||||||
M_SD_OB,
|
M_SD_A,
|
||||||
M_SD_AB,
|
M_SD_OB,
|
||||||
M_SDC1_AB,
|
M_SD_AB,
|
||||||
M_SDC2_AB,
|
M_SDC1_AB,
|
||||||
M_SDC3_AB,
|
M_SDC2_AB,
|
||||||
M_SDL_AB,
|
M_SDC3_AB,
|
||||||
M_SDR_AB,
|
M_SDL_AB,
|
||||||
M_SEQ,
|
M_SDR_AB,
|
||||||
M_SEQ_I,
|
M_SEQ,
|
||||||
M_SGE,
|
M_SEQ_I,
|
||||||
M_SGE_I,
|
M_SGE,
|
||||||
M_SGEU,
|
M_SGE_I,
|
||||||
M_SGEU_I,
|
M_SGEU,
|
||||||
M_SGT,
|
M_SGEU_I,
|
||||||
M_SGT_I,
|
M_SGT,
|
||||||
M_SGTU,
|
M_SGT_I,
|
||||||
M_SGTU_I,
|
M_SGTU,
|
||||||
M_SLE,
|
M_SGTU_I,
|
||||||
M_SLE_I,
|
M_SLE,
|
||||||
M_SLEU,
|
M_SLE_I,
|
||||||
M_SLEU_I,
|
M_SLEU,
|
||||||
M_SLT_I,
|
M_SLEU_I,
|
||||||
M_SLTU_I,
|
M_SLT_I,
|
||||||
M_SNE,
|
M_SLTU_I,
|
||||||
M_SNE_I,
|
M_SNE,
|
||||||
M_SB_A,
|
M_SNE_I,
|
||||||
M_SB_AB,
|
M_SB_A,
|
||||||
M_SH_A,
|
M_SB_AB,
|
||||||
M_SH_AB,
|
M_SH_A,
|
||||||
M_SW_A,
|
M_SH_AB,
|
||||||
M_SW_AB,
|
M_SW_A,
|
||||||
M_SWC0_A,
|
M_SW_AB,
|
||||||
M_SWC0_AB,
|
M_SWC0_A,
|
||||||
M_SWC1_A,
|
M_SWC0_AB,
|
||||||
M_SWC1_AB,
|
M_SWC1_A,
|
||||||
M_SWC2_A,
|
M_SWC1_AB,
|
||||||
M_SWC2_AB,
|
M_SWC2_A,
|
||||||
M_SWC3_A,
|
M_SWC2_AB,
|
||||||
M_SWC3_AB,
|
M_SWC3_A,
|
||||||
M_SWL_A,
|
M_SWC3_AB,
|
||||||
M_SWL_AB,
|
M_SWL_A,
|
||||||
M_SWR_A,
|
M_SWL_AB,
|
||||||
M_SWR_AB,
|
M_SWR_A,
|
||||||
M_SUB_I,
|
M_SWR_AB,
|
||||||
M_SUBU_I,
|
M_SUB_I,
|
||||||
M_SUBU_I_2,
|
M_SUBU_I,
|
||||||
M_TEQ_I,
|
M_SUBU_I_2,
|
||||||
M_TGE_I,
|
M_TEQ_I,
|
||||||
M_TGEU_I,
|
M_TGE_I,
|
||||||
M_TLT_I,
|
M_TGEU_I,
|
||||||
M_TLTU_I,
|
M_TLT_I,
|
||||||
M_TNE_I,
|
M_TLTU_I,
|
||||||
M_TRUNCWD,
|
M_TNE_I,
|
||||||
M_TRUNCWS,
|
M_TRUNCWD,
|
||||||
M_ULD,
|
M_TRUNCWS,
|
||||||
M_ULD_A,
|
M_ULD,
|
||||||
M_ULH,
|
M_ULD_A,
|
||||||
M_ULH_A,
|
M_ULH,
|
||||||
M_ULHU,
|
M_ULH_A,
|
||||||
M_ULHU_A,
|
M_ULHU,
|
||||||
M_ULW,
|
M_ULHU_A,
|
||||||
M_ULW_A,
|
M_ULW,
|
||||||
M_USH,
|
M_ULW_A,
|
||||||
M_USH_A,
|
M_USH,
|
||||||
M_USW,
|
M_USH_A,
|
||||||
M_USW_A,
|
M_USW,
|
||||||
M_USD,
|
M_USW_A,
|
||||||
M_USD_A,
|
M_USD,
|
||||||
M_XOR_I,
|
M_USD_A,
|
||||||
M_COP0,
|
M_XOR_I,
|
||||||
M_COP1,
|
M_COP0,
|
||||||
M_COP2,
|
M_COP1,
|
||||||
M_COP3,
|
M_COP2,
|
||||||
M_NUM_MACROS
|
M_COP3,
|
||||||
|
M_NUM_MACROS
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
Reference in New Issue
Block a user