JehanneOS/newlib
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

RISC-V: Updated syscall to take 6 arguments

Browse Source
This commit is contained in:
Jim Wilson
2017-12-26 12:26:19 -08:00
parent a6633677b9
commit 347b083911
2 changed files with 26 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
libgloss/riscv/machine/syscall.h
View File

@@ -57,12 +57,14 @@
extern long __syscall_error(long);
static inline long
__internal_syscall(long n, long _a0, long _a1, long _a2, long _a3)
__internal_syscall(long n, long _a0, long _a1, long _a2, long _a3, long _a4, long _a5)
{
register long a0 asm("a0") = _a0;
register long a1 asm("a1") = _a1;
register long a2 asm("a2") = _a2;
register long a3 asm("a3") = _a3;
register long a4 asm("a4") = _a4;
register long a5 asm("a5") = _a5;
#ifdef __riscv_32e
register long syscall_id asm("t0") = n;
@@ -71,7 +73,7 @@ __internal_syscall(long n, long _a0, long _a1, long _a2, long _a3)
#endif
asm volatile ("scall"
: "+r"(a0) : "r"(a1), "r"(a2), "r"(a3), "r"(syscall_id));
: "+r"(a0) : "r"(a1), "r"(a2), "r"(a3), "r"(a4), "r"(a5), "r"(syscall_id));
if (a0 < 0)
return __syscall_error (a0);