fenv.h: Change fexcept_t to integral type for compatibility
On Linux and in Mingw-w64, fexcept_t is defined as type unsigned short. There are packages in the wild which rely on the fact that fexcept_t is an integral type. We're changing the internal handling to use the bits just as in GLibc, so only the 6 lowest bits are used to reflect the hw bits. We even change the header file guard to reflect GLibc for compatibility. * include/fenv.h (_FENV_H): Rename from _FENV_H_ and set to 1 as in GLibc's header. (fexcept_t): Change to __uint16_t to be an integral type as in GLibc. * fenv.cc (fegetexceptflag): Align to the *flagp's type change. (fesetexceptflag): Ditto. Signed-off-by: Corinna Vinschen <corinna@vinschen.de>
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@@ -295,9 +295,8 @@ fegetexceptflag (fexcept_t *flagp, int excepts)
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if (use_sse)
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__asm__ volatile ("stmxcsr %0" : "=m" (mxcsr) : );
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/* Mask undesired bits out and set result struct. */
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flagp->_fpu_exceptions = (sw & excepts);
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flagp->_sse_exceptions = (mxcsr & excepts);
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/* Mask undesired bits out and set result. */
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*flagp = (sw | mxcsr) & excepts;
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return 0;
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}
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@@ -317,9 +316,9 @@ fesetexceptflag (const fexcept_t *flagp, int excepts)
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/* Set/Clear desired exception bits. */
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fenv._fpu._fpu_sw &= ~excepts;
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fenv._fpu._fpu_sw |= (excepts & flagp->_fpu_exceptions);
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fenv._fpu._fpu_sw |= excepts & *flagp;
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fenv._sse_mxcsr &= ~excepts;
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fenv._sse_mxcsr |= (excepts & flagp->_sse_exceptions);
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fenv._sse_mxcsr |= excepts & *flagp;
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/* Set back into FPU state. */
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return fesetenv (&fenv);
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