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2012-12-17 Stuart Henderson <shenders@gcc.gnu.org>

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* bfin/Makefile.in: Add BF60x support.
	* bfin/basiccrt.S: Add core1 support.
	* bfin/bf606.ld: New file.
	* bfin/bf606c0.ld: New file.
	* bfin/bf606c1.ld: New file.
	* bfin/bf606m.ld: New file.
	* bfin/bf607.ld: New file.
	* bfin/bf607c0.ld: New file.
	* bfin/bf607c1.ld: New file.
	* bfin/bf607m.ld: New file.
	* bfin/bf608.ld: New file.
	* bfin/bf608c0.ld: New file.
	* bfin/bf608c1.ld: New file.
	* bfin/bf608m.ld: New file.
	* bfin/bf609.ld: New file.
	* bfin/bf609c0.ld: New file.
	* bfin/bf609c1.ld: New file.
	* bfin/bf609m.ld: New file.
	* bfin/bfin-common-mc0.ld: New file.
	* bfin/include/cdefBF606.h : New file.
	* bfin/include/cdefBF607.h : New file.
	* bfin/include/cdefBF608.h : New file.
	* bfin/include/cdefBF609.h : New file.
	* bfin/include/defBF606.h : New file.
	* bfin/include/defBF607.h : New file.
	* bfin/include/defBF608.h : New file.
	* bfin/include/defBF609.h : New file.
	* bfin/include/sys/_adi_platform.h: Add BF60x support.
	* bfin/include/sys/anomaly_macros_rtl.h : Clean up.
This commit is contained in:
Jeff Johnston 2012-12-17 17:44:38 +00:00
parent 301264066b
commit 24fb7750f3
30 changed files with 92380 additions and 454 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
libgloss/ChangeLog
View File

@ -1,3 +1,35 @@
2012-12-17 Stuart Henderson <shenders@gcc.gnu.org>
* bfin/Makefile.in: Add BF60x support.
* bfin/basiccrt.S: Add core1 support.
* bfin/bf606.ld: New file.
* bfin/bf606c0.ld: New file.
* bfin/bf606c1.ld: New file.
* bfin/bf606m.ld: New file.
* bfin/bf607.ld: New file.
* bfin/bf607c0.ld: New file.
* bfin/bf607c1.ld: New file.
* bfin/bf607m.ld: New file.
* bfin/bf608.ld: New file.
* bfin/bf608c0.ld: New file.
* bfin/bf608c1.ld: New file.
* bfin/bf608m.ld: New file.
* bfin/bf609.ld: New file.
* bfin/bf609c0.ld: New file.
* bfin/bf609c1.ld: New file.
* bfin/bf609m.ld: New file.
* bfin/bfin-common-mc0.ld: New file.
* bfin/include/cdefBF606.h : New file.
* bfin/include/cdefBF607.h : New file.
* bfin/include/cdefBF608.h : New file.
* bfin/include/cdefBF609.h : New file.
* bfin/include/defBF606.h : New file.
* bfin/include/defBF607.h : New file.
* bfin/include/defBF608.h : New file.
* bfin/include/defBF609.h : New file.
* bfin/include/sys/_adi_platform.h: Add BF60x support.
* bfin/include/sys/anomaly_macros_rtl.h : Clean up.
2012-11-23 Yufeng Zhang <yufeng.zhang@arm.com> 2012-11-23 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64/configure.in: Replace the direct generation of * aarch64/configure.in: Replace the direct generation of

28
libgloss/bfin/Makefile.in
View File

@ -60,7 +60,7 @@ SIM_TEST = sim-test
SIM_INSTALL = install-sim SIM_INSTALL = install-sim
# Here is all of the development board stuff # Here is all of the development board stuff
BOARD_SCRIPTS = bfin-common-sc.ld bfin-common-mc.ld \ BOARD_SCRIPTS = bfin-common-sc.ld bfin-common-mc.ld bfin-common-mc0.ld \
bf504.ld bf506.ld \ bf504.ld bf506.ld \
bf512.ld bf514.ld bf516.ld bf518.ld \ bf512.ld bf514.ld bf516.ld bf518.ld \
bf522.ld bf523.ld bf524.ld bf525.ld bf526.ld bf527.ld \ bf522.ld bf523.ld bf524.ld bf525.ld bf526.ld bf527.ld \
@ -69,11 +69,16 @@ BOARD_SCRIPTS = bfin-common-sc.ld bfin-common-mc.ld \
bf538.ld bf539.ld \ bf538.ld bf539.ld \
bf542.ld bf544.ld bf547.ld bf548.ld bf549.ld \ bf542.ld bf544.ld bf547.ld bf548.ld bf549.ld \
bf561.ld bf561a.ld bf561b.ld bf561m.ld \ bf561.ld bf561a.ld bf561b.ld bf561m.ld \
bf606.ld bf606c0.ld bf606c1.ld bf606m.ld \
bf607.ld bf607c0.ld bf607c1.ld bf607m.ld \
bf608.ld bf608c0.ld bf608c1.ld bf608m.ld \
bf609.ld bf609c0.ld bf609c1.ld bf609m.ld \
bf592.ld bf592.ld
BOARD_LDFLAGS = BOARD_LDFLAGS =
BOARD_BSP = libbfinbsp.a BOARD_BSP = libbfinbsp.a
BOARD_CRT0S = basiccrt.o basiccrts.o BOARD_CRT0S = basiccrt.o basiccrts.o
BOARD_CRT0S += basiccrt561.o basiccrt561s.o basiccrt561b.o BOARD_CRT0S += basiccrt561.o basiccrt561s.o basiccrt561b.o
BOARD_CRT0S += basiccrt60x.o basiccrt60xs.o basiccrt60xc1.o
BOARD_OBJS = clear_cache_range.o _exit.o BOARD_OBJS = clear_cache_range.o _exit.o
BOARD_TEST = BOARD_TEST =
BOARD_INSTALL = install-board BOARD_INSTALL = install-board
@ -139,6 +144,27 @@ else
$(CC) -D__ADSPBF561_COREB__ $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -mcpu=bf561-any -o $@ -c $< $(CC) -D__ADSPBF561_COREB__ $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -mcpu=bf561-any -o $@ -c $<
endif endif
basiccrt60x.o: basiccrt.S
ifneq (,$(findstring mcpu=bf532-none,$(CFLAGS)))
$(CC) $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -mcpu=bf608-none -o $@ -c $<
else
$(CC) $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -mcpu=bf608-any -o $@ -c $<
endif
basiccrt60xs.o: basiccrt.S
ifneq (,$(findstring mcpu=bf532-none,$(CFLAGS)))
$(CC) -D__BFIN_SDRAM $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -mcpu=bf608-none -o $@ -c $<
else
$(CC) -D__BFIN_SDRAM $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -mcpu=bf608-any -o $@ -c $<
endif
basiccrt60xc1.o: basiccrt.S
ifneq (,$(findstring mcpu=bf532-none,$(CFLAGS)))
$(CC) -D__ADSPBF60x_CORE1__ $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -mcpu=bf608-none -o $@ -c $<
else
$(CC) -D__ADSPBF60x_CORE1__ $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -mcpu=bf608-any -o $@ -c $<
endif
clean mostlyclean: clean mostlyclean:
rm -f a.out core *.i *.o ${SIM_BSP} ${BOARD_BSP} rm -f a.out core *.i *.o ${SIM_BSP} ${BOARD_BSP}

47
libgloss/bfin/basiccrt.S
View File

@ -66,6 +66,12 @@
.global __coreb_start; .global __coreb_start;
.type __coreb_start, STT_FUNC; .type __coreb_start, STT_FUNC;
__coreb_start: __coreb_start:
#elif defined(__ADSPBF60x_CORE1__)
.section .1.text,"ax",@progbits
.align 2;
.global __core1_start;
.type __core1_start, STT_FUNC;
__core1_start:
#else #else
.text; .text;
.align 2; .align 2;
@ -160,6 +166,9 @@ L$ivt: [P0++] = R1;
#ifdef __ADSPBF561_COREB__ #ifdef __ADSPBF561_COREB__
SP.L=__coreb_stack_end - 12; SP.L=__coreb_stack_end - 12;
SP.H=__coreb_stack_end - 12; SP.H=__coreb_stack_end - 12;
#elif defined(__ADSPBF60x_CORE1__)
SP.L=__core1_stack_end - 12;
SP.H=__core1_stack_end - 12;
#else #else
SP.L=__stack_end - 12; SP.L=__stack_end - 12;
SP.H=__stack_end - 12; SP.H=__stack_end - 12;
@ -187,6 +196,11 @@ L$ivt: [P0++] = R1;
R0.H = __coreb_bss_start; R0.H = __coreb_bss_start;
R1.L = __coreb_bss_end; R1.L = __coreb_bss_end;
R1.H = __coreb_bss_end; R1.H = __coreb_bss_end;
#elif defined(__ADSPBF60x_CORE1__)
R0.L = __core1_bss_start;
R0.H = __core1_bss_start;
R1.L = __core1_bss_end;
R1.H = __core1_bss_end;
#else #else
R0.L = __bss_start; R0.L = __bss_start;
R0.H = __bss_start; R0.H = __bss_start;
@ -198,6 +212,8 @@ L$ivt: [P0++] = R1;
R1 = 0; R1 = 0;
#ifdef __ADSPBF561_COREB__ #ifdef __ADSPBF561_COREB__
CALL.X __coreb_memset; CALL.X __coreb_memset;
#elif defined(__ADSPBF60x_CORE1__)
CALL.X __core1_memset;
#else #else
CALL.X _memset; CALL.X _memset;
#endif #endif
@ -269,7 +285,8 @@ L$clock_is_set:
#endif #endif
#endif /* ADSPLPBLACKFIN */ #endif /* ADSPLPBLACKFIN */
#if defined(__ADSPBF561__) || defined(__ADSPBF566__) #if defined(__ADSPBF561__) || defined(__ADSPBF566__) || defined(__ADSPBF606__) || defined(__ADSPBF607__) || defined(__ADSPBF608__) || defined(__ADSPBF609__)
// Initialise the multi-core data tables. // Initialise the multi-core data tables.
// A dummy function will be called if we are not linking with // A dummy function will be called if we are not linking with
// -multicore // -multicore
@ -354,7 +371,7 @@ L$supervisor_mode:
CALL.X monstartup; // initialise profiling routines CALL.X monstartup; // initialise profiling routines
#endif /* PROFCRT */ #endif /* PROFCRT */
#ifndef __ADSPBF561_COREB__ #if !defined(__ADSPBF561_COREB__) && !defined(__ADSPBF60x_CORE1__)
CALL.X __init; CALL.X __init;
R0.L = __fini; R0.L = __fini;
@ -374,6 +391,9 @@ L$supervisor_mode:
#ifdef __ADSPBF561_COREB__ #ifdef __ADSPBF561_COREB__
R1.L=L$argv_coreb; R1.L=L$argv_coreb;
R1.H=L$argv_coreb; R1.H=L$argv_coreb;
#elif defined(__ADSPBF60x_CORE1__)
R1.L=L$argv_core1;
R1.H=L$argv_core1;
#else #else
R1.L=L$argv; R1.L=L$argv;
R1.H=L$argv; R1.H=L$argv;
@ -384,18 +404,22 @@ L$supervisor_mode:
// At long last, call the application program. // At long last, call the application program.
#ifdef __ADSPBF561_COREB__ #ifdef __ADSPBF561_COREB__
CALL.X _coreb_main; CALL.X _coreb_main;
#elif defined(__ADSPBF60x_CORE1__)
CALL.X _core1_main;
#else #else
CALL.X _main; CALL.X _main;
#endif #endif
#if !defined(_ADI_THREADS) #if !defined(_ADI_THREADS)
#ifndef __ADSPBF561_COREB__ #if !defined(__ADSPBF561_COREB__) && !defined(__ADSPBF60x_CORE1__)
CALL.X _exit; // passing in main's return value CALL.X _exit; // passing in main's return value
#endif #endif
#endif #endif
#ifdef __ADSPBF561_COREB__ #ifdef __ADSPBF561_COREB__
.size __coreb_start, .-__coreb_start .size __coreb_start, .-__coreb_start
#elif defined(__ADSPBF60x_CORE1__)
.size __core1_start, .-__core1_start
#else #else
.size __start, .-__start .size __start, .-__start
#endif #endif
@ -506,10 +530,16 @@ L$done:
#endif #endif
#endif /* ADSPLPBLACKFIN */ #endif /* ADSPLPBLACKFIN */
#if defined(__ADSPBF561_COREB__) || defined(__ADSPBF60x_CORE1__)
#ifdef __ADSPBF561_COREB__ #ifdef __ADSPBF561_COREB__
.section .b.text,"ax",@progbits .section .b.text,"ax",@progbits
.type __coreb_memset, STT_FUNC .type __coreb_memset, STT_FUNC
__coreb_memset: __coreb_memset:
#else
.section .1.text,"ax",@progbits
.type __core1_memset, STT_FUNC
__core1_memset:
#endif
P0 = R0 ; /* P0 = address */ P0 = R0 ; /* P0 = address */
P2 = R2 ; /* P2 = count */ P2 = R2 ; /* P2 = count */
R3 = R0 + R2; /* end */ R3 = R0 + R2; /* end */
@ -569,7 +599,11 @@ __coreb_memset:
B[P0++] = R1; B[P0++] = R1;
B[P0++] = R1; B[P0++] = R1;
JUMP .Laligned; JUMP .Laligned;
#ifdef __ADSPBF561_COREB__
.size __coreb_memset,.-__coreb_memset .size __coreb_memset,.-__coreb_memset
#else
.size __core1_memset,.-__core1_memset
#endif
#endif #endif
#ifdef __ADSPBF561_COREB__ #ifdef __ADSPBF561_COREB__
@ -579,6 +613,13 @@ __coreb_memset:
.size L$argv_coreb, 4 .size L$argv_coreb, 4
L$argv_coreb: L$argv_coreb:
.zero 4 .zero 4
#elif defined(__ADSPBF60x_CORE1__)
.section .1.bss,"aw",@progbits
.align 4
.type L$argv_core1, @object
.size L$argv_core1, 4
L$argv_core1:
.zero 4
#else #else
.local L$argv .local L$argv
.comm L$argv,4,4 .comm L$argv,4,4

27
libgloss/bfin/bf606.ld Normal file
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@ -0,0 +1,27 @@
/*
* The default linker script for standalone executables running on
* ADSP-BF606 processor (single core).
*
* Copyright (C) 2011 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x10000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xC8080000, LENGTH = 0x40000
}

34
libgloss/bfin/bf606c0.ld Normal file
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@ -0,0 +1,34 @@
/*
* The default linker script for standalone executables running on
* Core 0 of ADSP-BF606 processor (dual core).
*
* Copyright (C) 2011 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x10000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_C1_L1_CODE : ORIGIN = 0xFF600000, LENGTH = 0x0
MEM_C1_L1_CODE_CACHE : ORIGIN = 0xFF610000, LENGTH = 0x0
MEM_C1_L1_SCRATCH : ORIGIN = 0xFF700000, LENGTH = 0x0
MEM_C1_L1_DATA_B : ORIGIN = 0xFF500000, LENGTH = 0x0
MEM_C1_L1_DATA_A : ORIGIN = 0xFF400000, LENGTH = 0x0
MEM_L2 : ORIGIN = 0xC8090000, LENGTH = 0x10000
MEM_L2_SHARED : ORIGIN = 0xC80A0000, LENGTH = 0x20000
}

36
libgloss/bfin/bf606c1.ld Normal file
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@ -0,0 +1,36 @@
/*
* The default linker script for standalone executables running on
* Core 1 of ADSP-BF606 processor (dual core).
*
* Copyright (C) 2011 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
/* These MEM_C1_* are Core A memory region with zero length.
They just provide dummy memory region to satisfy bfin-common-mc.ld. */
MEM_C1_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x0
MEM_C1_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x0
MEM_C1_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x0
MEM_C1_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x0
MEM_C1_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x0
MEM_L1_CODE : ORIGIN = 0xFF600000, LENGTH = 0x10000
MEM_L1_CODE_CACHE : ORIGIN = 0xFF610000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFF700000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF500000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF400000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xC8080000, LENGTH = 0x10000
MEM_L2_SHARED : ORIGIN = 0xC80A0000, LENGTH = 0x20000
}

34
libgloss/bfin/bf606m.ld Normal file
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@ -0,0 +1,34 @@
/*
* The default linker script for standalone executables running on
* ADSP-BF606 processor (dual core).
*
* Copyright (C) 2011 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x10000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_C1_L1_CODE : ORIGIN = 0xFF600000, LENGTH = 0x10000
MEM_C1_L1_CODE_CACHE : ORIGIN = 0xFF610000, LENGTH = 0x4000
MEM_C1_L1_SCRATCH : ORIGIN = 0xFF700000, LENGTH = 0x1000
MEM_C1_L1_DATA_B : ORIGIN = 0xFF500000, LENGTH = 0x8000
MEM_C1_L1_DATA_A : ORIGIN = 0xFF400000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xC8080000, LENGTH = 0x40000
MEM_L2_SHARED : ORIGIN = 0xC80C0000, LENGTH = 0x0
}

27
libgloss/bfin/bf607.ld Normal file
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@ -0,0 +1,27 @@
/*
* The default linker script for standalone executables running on
* ADSP-BF607 processor (single core).
*
* Copyright (C) 2011 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x10000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xC8080000, LENGTH = 0x40000
}

34
libgloss/bfin/bf607c0.ld Normal file
View File

@ -0,0 +1,34 @@
/*
* The default linker script for standalone executables running on
* Core 0 of ADSP-BF607 processor (dual core).
*
* Copyright (C) 2011 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x10000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_C1_L1_CODE : ORIGIN = 0xFF600000, LENGTH = 0x0
MEM_C1_L1_CODE_CACHE : ORIGIN = 0xFF610000, LENGTH = 0x0
MEM_C1_L1_SCRATCH : ORIGIN = 0xFF700000, LENGTH = 0x0
MEM_C1_L1_DATA_B : ORIGIN = 0xFF500000, LENGTH = 0x0
MEM_C1_L1_DATA_A : ORIGIN = 0xFF400000, LENGTH = 0x0
MEM_L2 : ORIGIN = 0xC8090000, LENGTH = 0x10000
MEM_L2_SHARED : ORIGIN = 0xC80A0000, LENGTH = 0x20000
}

36
libgloss/bfin/bf607c1.ld Normal file
View File

@ -0,0 +1,36 @@
/*
* The default linker script for standalone executables running on
* Core 1 of ADSP-BF607 processor (dual core).
*
* Copyright (C) 2011 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
/* These MEM_C1_* are Core A memory region with zero length.
They just provide dummy memory region to satisfy bfin-common-mc.ld. */
MEM_C1_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x0
MEM_C1_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x0
MEM_C1_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x0
MEM_C1_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x0
MEM_C1_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x0
MEM_L1_CODE : ORIGIN = 0xFF600000, LENGTH = 0x10000
MEM_L1_CODE_CACHE : ORIGIN = 0xFF610000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFF700000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF500000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF400000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xC8080000, LENGTH = 0x10000
MEM_L2_SHARED : ORIGIN = 0xC80A0000, LENGTH = 0x20000
}

34
libgloss/bfin/bf607m.ld Normal file
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@ -0,0 +1,34 @@
/*
* The default linker script for standalone executables running on
* ADSP-BF607 processor (dual core).
*
* Copyright (C) 2011 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x10000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_C1_L1_CODE : ORIGIN = 0xFF600000, LENGTH = 0x10000
MEM_C1_L1_CODE_CACHE : ORIGIN = 0xFF610000, LENGTH = 0x4000
MEM_C1_L1_SCRATCH : ORIGIN = 0xFF700000, LENGTH = 0x1000
MEM_C1_L1_DATA_B : ORIGIN = 0xFF500000, LENGTH = 0x8000
MEM_C1_L1_DATA_A : ORIGIN = 0xFF400000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xC8080000, LENGTH = 0x40000
MEM_L2_SHARED : ORIGIN = 0xC80C0000, LENGTH = 0x0
}

27
libgloss/bfin/bf608.ld Normal file
View File

@ -0,0 +1,27 @@
/*
* The default linker script for standalone executables running on
* ADSP-BF608 processor (single core).
*
* Copyright (C) 2011 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x10000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xC8080000, LENGTH = 0x40000
}

34
libgloss/bfin/bf608c0.ld Normal file
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@ -0,0 +1,34 @@
/*
* The default linker script for standalone executables running on
* Core 0 of ADSP-BF608 processor (dual core).
*
* Copyright (C) 2011 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x10000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_C1_L1_CODE : ORIGIN = 0xFF600000, LENGTH = 0x0
MEM_C1_L1_CODE_CACHE : ORIGIN = 0xFF610000, LENGTH = 0x0
MEM_C1_L1_SCRATCH : ORIGIN = 0xFF700000, LENGTH = 0x0
MEM_C1_L1_DATA_B : ORIGIN = 0xFF500000, LENGTH = 0x0
MEM_C1_L1_DATA_A : ORIGIN = 0xFF400000, LENGTH = 0x0
MEM_L2 : ORIGIN = 0xC8090000, LENGTH = 0x10000
MEM_L2_SHARED : ORIGIN = 0xC80A0000, LENGTH = 0x20000
}

36
libgloss/bfin/bf608c1.ld Normal file
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@ -0,0 +1,36 @@
/*
* The default linker script for standalone executables running on
* Core 1 of ADSP-BF608 processor (dual core).
*
* Copyright (C) 2011 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
/* These MEM_C1_* are Core A memory region with zero length.
They just provide dummy memory region to satisfy bfin-common-mc.ld. */
MEM_C1_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x0
MEM_C1_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x0
MEM_C1_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x0
MEM_C1_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x0
MEM_C1_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x0
MEM_L1_CODE : ORIGIN = 0xFF600000, LENGTH = 0x10000
MEM_L1_CODE_CACHE : ORIGIN = 0xFF610000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFF700000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF500000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF400000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xC8080000, LENGTH = 0x10000
MEM_L2_SHARED : ORIGIN = 0xC80A0000, LENGTH = 0x20000
}

34
libgloss/bfin/bf608m.ld Normal file
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@ -0,0 +1,34 @@
/*
* The default linker script for standalone executables running on
* ADSP-BF608 processor (dual core).
*
* Copyright (C) 2011 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x10000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_C1_L1_CODE : ORIGIN = 0xFF600000, LENGTH = 0x10000
MEM_C1_L1_CODE_CACHE : ORIGIN = 0xFF610000, LENGTH = 0x4000
MEM_C1_L1_SCRATCH : ORIGIN = 0xFF700000, LENGTH = 0x1000
MEM_C1_L1_DATA_B : ORIGIN = 0xFF500000, LENGTH = 0x8000
MEM_C1_L1_DATA_A : ORIGIN = 0xFF400000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xC8080000, LENGTH = 0x40000
MEM_L2_SHARED : ORIGIN = 0xC80C0000, LENGTH = 0x0
}

27
libgloss/bfin/bf609.ld Normal file
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@ -0,0 +1,27 @@
/*
* The default linker script for standalone executables running on
* ADSP-BF609 processor (single core).
*
* Copyright (C) 2011 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x10000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xC8080000, LENGTH = 0x40000
}

34
libgloss/bfin/bf609c0.ld Normal file
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@ -0,0 +1,34 @@
/*
* The default linker script for standalone executables running on
* Core 0 of ADSP-BF609 processor (dual core).
*
* Copyright (C) 2011 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x10000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_C1_L1_CODE : ORIGIN = 0xFF600000, LENGTH = 0x0
MEM_C1_L1_CODE_CACHE : ORIGIN = 0xFF610000, LENGTH = 0x0
MEM_C1_L1_SCRATCH : ORIGIN = 0xFF700000, LENGTH = 0x0
MEM_C1_L1_DATA_B : ORIGIN = 0xFF500000, LENGTH = 0x0
MEM_C1_L1_DATA_A : ORIGIN = 0xFF400000, LENGTH = 0x0
MEM_L2 : ORIGIN = 0xC8090000, LENGTH = 0x10000
MEM_L2_SHARED : ORIGIN = 0xC80A0000, LENGTH = 0x20000
}

36
libgloss/bfin/bf609c1.ld Normal file
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@ -0,0 +1,36 @@
/*
* The default linker script for standalone executables running on
* Core 1 of ADSP-BF609 processor (dual core).
*
* Copyright (C) 2011 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
/* These MEM_C1_* are Core A memory region with zero length.
They just provide dummy memory region to satisfy bfin-common-mc.ld. */
MEM_C1_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x0
MEM_C1_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x0
MEM_C1_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x0
MEM_C1_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x0
MEM_C1_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x0
MEM_L1_CODE : ORIGIN = 0xFF600000, LENGTH = 0x10000
MEM_L1_CODE_CACHE : ORIGIN = 0xFF610000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFF700000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF500000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF400000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xC8080000, LENGTH = 0x10000
MEM_L2_SHARED : ORIGIN = 0xC80A0000, LENGTH = 0x20000
}

34
libgloss/bfin/bf609m.ld Normal file
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@ -0,0 +1,34 @@
/*
* The default linker script for standalone executables running on
* ADSP-BF609 processor (dual core).
*
* Copyright (C) 2011 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x10000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_C1_L1_CODE : ORIGIN = 0xFF600000, LENGTH = 0x10000
MEM_C1_L1_CODE_CACHE : ORIGIN = 0xFF610000, LENGTH = 0x4000
MEM_C1_L1_SCRATCH : ORIGIN = 0xFF700000, LENGTH = 0x1000
MEM_C1_L1_DATA_B : ORIGIN = 0xFF500000, LENGTH = 0x8000
MEM_C1_L1_DATA_A : ORIGIN = 0xFF400000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xC8080000, LENGTH = 0x40000
MEM_L2_SHARED : ORIGIN = 0xC80C0000, LENGTH = 0x0
}

260
libgloss/bfin/bfin-common-mc0.ld Normal file
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@ -0,0 +1,260 @@
/*
* The common part of the default linker scripts for standalone executables
* running on single core Blackfin processors.
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/* The default linker script, for single core blackfin standalone executables */
OUTPUT_FORMAT("elf32-bfin", "elf32-bfin",
"elf32-bfin")
OUTPUT_ARCH(bfin)
ENTRY(__start)
SECTIONS
{
/* Read-only sections, merged into text segment: */
PROVIDE (__executable_start = 0x0); . = 0x0;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.gnu.version : { *(.gnu.version) }
.gnu.version_d : { *(.gnu.version_d) }
.gnu.version_r : { *(.gnu.version_r) }
.rel.init : { *(.rel.init) }
.rela.init : { *(.rela.init) }
.rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) }
.rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
.rel.fini : { *(.rel.fini) }
.rela.fini : { *(.rela.fini) }
.rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) }
.rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) }
.rel.data.rel.ro : { *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*) }
.rela.data.rel.ro : { *(.rela.data.rel.ro* .rela.gnu.linkonce.d.rel.ro.*) }
.rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) }
.rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) }
.rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) }
.rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) }
.rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) }
.rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.sdata : { *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) }
.rela.sdata : { *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) }
.rel.sbss : { *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) }
.rela.sbss : { *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) }
.rel.sdata2 : { *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) }
.rela.sdata2 : { *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) }
.rel.sbss2 : { *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) }
.rela.sbss2 : { *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) }
.rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) }
.rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.l2 :
{
*(.l2 .l2.*)
} >MEM_L2 =0
.l2_shared :
{
*(.l2_shared .l2_shared.*)
} >MEM_L2_SHARED =0
.1.text :
{
*(.1.text .1.text.* .1.l1.text .1.l1.text.*)
} >MEM_C1_L1_CODE =0
.text :
{
*(.text .stub .text.* .gnu.linkonce.t.* .l1.text .l1.text.*)
KEEP (*(.text.*personality*))
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
} >MEM_L1_CODE =0
.init :
{
KEEP (*(.init))
} >MEM_L1_CODE =0
.plt : { *(.plt) } >MEM_L1_CODE
.fini :
{
KEEP (*(.fini))
} >MEM_L1_CODE =0
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.1.rodata : { *(.1.rodata .1.rodata.*) } >MEM_C1_L1_DATA_A
.rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >MEM_L1_DATA_A
.rodata1 : { *(.rodata1) } >MEM_L1_DATA_A
.sdata2 :
{
*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
} >MEM_L1_DATA_A
.sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) } >MEM_L1_DATA_A
.eh_frame_hdr : { *(.eh_frame_hdr) } >MEM_L1_DATA_A
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >MEM_L1_DATA_A
.gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } >MEM_L1_DATA_A
/* Adjust the address for the data segment. We want to adjust up to
the same address within the page on the next page up. */
. = ALIGN(0x1000) + (. & (0x1000 - 1));
/* Exception handling */
.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >MEM_L1_DATA_A
.gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } >MEM_L1_DATA_A
/* Thread Local Storage sections */
.tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >MEM_L1_DATA_A
.tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >MEM_L1_DATA_A
.preinit_array :
{
PROVIDE_HIDDEN (___preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (___preinit_array_end = .);
} >MEM_L1_DATA_A
.init_array :
{
PROVIDE_HIDDEN (___init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE_HIDDEN (___init_array_end = .);
} >MEM_L1_DATA_A
.fini_array :
{
PROVIDE_HIDDEN (___fini_array_start = .);
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
PROVIDE_HIDDEN (___fini_array_end = .);
} >MEM_L1_DATA_A
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin*.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >MEM_L1_DATA_A
.dtors :
{
KEEP (*crtbegin*.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >MEM_L1_DATA_A
.jcr : { KEEP (*(.jcr)) } >MEM_L1_DATA_A
.data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*) } >MEM_L1_DATA_A
.dynamic : { *(.dynamic) } >MEM_L1_DATA_A
.1.data :
{
*(.1.data .1.data.* .1.l1.data .1.l1.data.*)
} >MEM_C1_L1_DATA_A
.data :
{
*(.data .data.* .gnu.linkonce.d.* .l1.data .l1.data.*)
KEEP (*(.gnu.linkonce.d.*personality*))
SORT(CONSTRUCTORS)
} >MEM_L1_DATA_A
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can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
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{
*(.sdata .sdata.* .gnu.linkonce.s.*)
} >MEM_L1_DATA_A
__edata = .; PROVIDE (_edata = .);
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} >MEM_C1_L1_DATA_A
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*(.1.bss .1.bss.*)
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} >MEM_C1_L1_DATA_A
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{
__bss_start = .;
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
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_end. Align after .bss to ensure correct alignment even if the
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FIXME: Why do we need it? When there is no .bss section, we don't
pad the .data section. */
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__bss_end = .;
} >MEM_L1_DATA_A
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. = ALIGN(32 / 8);
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Symbols in the DWARF debugging sections are relative to the beginning
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}

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16
libgloss/bfin/include/sys/_adi_platform.h
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@ -108,6 +108,14 @@
#include <cdefBF549M.h> #include <cdefBF549M.h>
#elif defined (__ADSPBF592A__) #elif defined (__ADSPBF592A__)
#include <cdefBF592-A.h> #include <cdefBF592-A.h>
#elif defined (__ADSPBF606__)
#include <cdefBF606.h>
#elif defined (__ADSPBF607__)
#include <cdefBF607.h>
#elif defined (__ADSPBF608__)
#include <cdefBF608.h>
#elif defined (__ADSPBF609__)
#include <cdefBF609.h>
#else #else
#error Processor Type Not Supported #error Processor Type Not Supported
#endif #endif
@ -203,6 +211,14 @@
#include <defBF549M.h> #include <defBF549M.h>
#elif defined (__ADSPBF592A__) #elif defined (__ADSPBF592A__)
#include <defBF592-A.h> #include <defBF592-A.h>
#elif defined (__ADSPBF606__)
#include <defBF606.h>
#elif defined (__ADSPBF607__)
#include <defBF607.h>
#elif defined (__ADSPBF608__)
#include <defBF608.h>
#elif defined (__ADSPBF609__)
#include <defBF609.h>
#else #else
#error Processor Type Not Supported #error Processor Type Not Supported

483
libgloss/bfin/include/sys/anomaly_macros_rtl.h
View File

@ -14,7 +14,7 @@
* *
* anomaly_macros_rtl.h : $Revision$ * anomaly_macros_rtl.h : $Revision$
* *
* (c) Copyright 2005-2009 Analog Devices, Inc. All rights reserved. * (c) Copyright 2005-2011 Analog Devices, Inc. All rights reserved.
* *
* This file defines macros used within the run-time libraries to enable * This file defines macros used within the run-time libraries to enable
* certain anomaly workarounds for the appropriate chips and silicon * certain anomaly workarounds for the appropriate chips and silicon
@ -33,7 +33,6 @@
#ifdef _MISRA_RULES #ifdef _MISRA_RULES
#pragma diag(push) #pragma diag(push)
#pragma diag(suppress:misra_rule_2_4:"Assembly code in comment used to illustrate anomalous behaviour") #pragma diag(suppress:misra_rule_2_4:"Assembly code in comment used to illustrate anomalous behaviour")
#pragma diag(suppress:misra_rule_19_4:"The definition of WA_05000204_CHECK_AVOID_FOR_REV cannot be parenthasised as it would fail when used in assembly library code.")
#endif /* _MISRA_RULES */ #endif /* _MISRA_RULES */
#if !defined(__SILICON_REVISION__) #if !defined(__SILICON_REVISION__)
@ -41,308 +40,6 @@
#endif #endif
/* 05-00-0096 - PREFETCH, FLUSH, and FLUSHINV must be followed by a CSYNC
**
** ADSP-BF531/2/3 - revs 0.0-0.1,
** ADSP-BF561 - revs 0.0-0.1 (not supported in VDSP++ 4.0)
**
*/
#define WA_05000096 \
((defined(__ADSPBF531__) || \
defined(__ADSPBF532__) || \
defined(__ADSPBF533__) || \
defined(__ADSPBF561__)) && \
((defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x1)) || \
defined(__FORCE_LEGACY_WORKAROUNDS__)))
/* 05-00-0109 - Reserved bits in SYSCFG register not set at power on
**
** ADSP-BF531/2/3 - revs 0.0-0.2 (fixed 0.3)
** ADSP-BF561 - revs 0.0-0.2 (fixed 0.3. 0.0, 0.1 not supported in VDSP++ 4.0)
**
** Changes to start code.
*/
#define WA_05000109 \
((defined(__ADSPBF531__) || \
defined(__ADSPBF532__) || \
defined(__ADSPBF533__) || \
defined(__ADSPBF561__)) && \
((defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \
defined(__FORCE_LEGACY_WORKAROUNDS__)))
/* 05-00-0123 - DTEST_COMMAND initiated memory access may be incorrect if
** data cache or DMA is active.
**
** ADSP-BF531/2/3 - revs 0.1-0.2 (fixed 0.3)
** ADSP-BF561 - revs 0.0-0.2 (0.0 and 0.1 not supported in VDSP++ 4.0)
*/
#define WA_05000123 \
((defined(__ADSPBF531__) || \
defined(__ADSPBF532__) || \
defined(__ADSPBF533__) || \
defined(__ADSPBF561__)) && \
((defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \
defined(__FORCE_LEGACY_WORKAROUNDS__)))
/* 05-00-0125 - Erroneous exception when enabling cache
**
** ADSP-BF531/2/3 - revs 0.1-0.2 (fixed 0.3)
** ADSP-BF561 - revs 0.0-0.2 (0.0 and 0.1 not supported in VDSP++ 4.0)
**
*/
#define WA_05000125 \
((defined(__ADSPBF531__) || \
defined(__ADSPBF532__) || \
defined(__ADSPBF533__) || \
defined(__ADSPBF561__)) && \
((defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \
defined(__FORCE_LEGACY_WORKAROUNDS__)))
/* 05-00-0127 - Signbits instruction not functional under certain conditions
**
** ADSP-BF561 - from rev 0.0 (not yet fixed)
**
** The SIGNBITS instruction requires a NOP before it if one of its operands
** is defined in the preceding instruction.
**
*/
#define WA_05000127 \
(defined(__SILICON_REVISION__) && defined(__ADSPBF561__))
/* 05-00-0137 - DMEM_CONTROL<12> is not set on Reset
**
** ADSP-BF531/2/3 - revs 0.0-0.2 (fixed 0.3)
**
** Changes to start code.
**
*/
#define WA_05000137 \
((defined(__ADSPBF531__) || \
defined(__ADSPBF532__) || \
defined(__ADSPBF533__)) && \
((defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \
defined(__FORCE_LEGACY_WORKAROUNDS__)))
/* 05-00-0158 - "Boot fails when data cache enabled: Data from a Data Cache
** fill can be corrupted after or during instruction DMA if certain core
** stalls exist"
**
** Impacted:
** BF533/3/1 : 0.0-0.4 (fixed 0.5)
**
** The workaround we have only works for si-revisions >= 0.3. No workaround for
** ealier revisions.
*/
#define WA_05000158 \
((defined(__ADSPBF531__) || \
defined(__ADSPBF532__) || \
defined(__ADSPBF533__)) && \
((defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ == 0xffff || \
(__SILICON_REVISION__ >= 0x3 && \
__SILICON_REVISION__ < 0x5))) || \
defined(__FORCE_LEGACY_WORKAROUNDS__)))
/* 05-00-0162 - DMEM_CONTROL<12> is not set on Reset
**
** ADSP-BF561 - revs 0.0-0.2 (fixed 0.3)
**
** Changes to start code.
**
*/
#define WA_05000162 \
(defined(__ADSPBF561__) && \
((defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \
defined(__FORCE_LEGACY_WORKAROUNDS__)))
/* 05-00-0198 - System MMR accesses may fail when stalled by preceding memory
** read.
**
** Impacted:
** ADSP-BF531 - rev 0.1-0.4 (fixed 0.5)
** ADSP-BF532 - rev 0.1-0.4 (fixed 0.5)
** ADSP-BF533 - rev 0.1-0.4 (fixed 0.5)
** ADSP-BF534 - rev 0.0 (fixed 0.1)
** ADSP-BF536 - rev 0.0 (fixed 0.1)
** ADSP-BF537 - rev 0.0 (fixed 0.1)
** ADSP-BF561 - rev 0.2-0.3 (fixed 0.4)
**
*/
#define WA_05000198 \
(((defined(__ADSPBF531__) || \
defined(__ADSPBF532__) || \
defined(__ADSPBF533__)) && \
(defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ <= 0x4 || __SILICON_REVISION__ == 0xffff))) || \
((defined(__ADSPBF534__) || \
defined(__ADSPBF536__) || \
defined(__ADSPBF537__) || \
defined(__ADSPBF539__)) && \
(defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ == 0x0 || __SILICON_REVISION__ == 0xffff))) || \
(defined(__ADSPBF561__) && \
(defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff))))
/* 05-00-0199 - Current DMA Address Shows Wrong Value During Carry Fix
**
** Impacted:
** ADSP-BF53[123] - rev 0.0-0.3 (fixed 0.4)
** ADSP-BF53[89] - rev 0.0-0.3 (fixed 0.4)
** ADSP-BF561 - rev 0.0-0.3 (fixed 0.4)
**
** Use by System Services/Device Drivers.
*/
#define WA_05000199 \
((defined(__ADSPBF533_FAMILY__) && \
(defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff))) || \
(defined(__ADSPBF538_FAMILY__) && \
(defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff))) || \
(defined(__ADSPBF561__) && \
(defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff))))
/* 05-00-0204 - "Incorrect data read with write-through cache and
** allocate cache lines on reads only mode.
**
** This problem is cache related with high speed clocks. It apparently does
** not impact BF531 and BF532 because they cannot run at high enough clock
** to cause the anomaly. We build libs for BF532 though so that means we will
** need to do the workaround for BF532 and BF531 also.
**
** Also the 0.3 to 0.4 revision is not an inflexion for libs BF532 and BF561.
** This means a RT check may be required to avoid doing the WA for 0.4.
**
** Impacted:
** BF533 - 0.0-0.3 (fixed 0.4)
** BF534 - 0.0 (fixed 0.1)
** BF536 - 0.0 (fixed 0.1)
** BF537 - 0.0 (fixed 0.1)
** BF538 - 0.0 (fixed 0.1)
** BF539 - 0.0 (fixed 0.1)
** BF561 - 0.0-0.3 (fixed 0.4)
*/
#if defined(__ADI_LIB_BUILD__)
# define __BUILDBF53123 1 /* building one single library for BF531/2/3 */
#else
# define __BUILDBF53123 0
#endif
#define WA_05000204 \
((((__BUILDBF53123==1 && \
(defined(__ADSPBF531__) || defined(__ADSPBF532__))) || \
(defined(__ADSPBF533__) || defined(__ADSPBF561__))) && \
(defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x3))) || \
((defined(__ADSPBF534__) || defined(__ADSPBF536__) || \
defined(__ADSPBF537__) || defined(__ADSPBF538__) || \
defined(__ADSPBF539__)) && \
(defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ == 0x0))))
#if ((defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
defined(__ADSPBF533__) || defined(__ADSPBF561__)) && \
(defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ == 0x3)))
/* check at RT for 0.4 revs when doing 204 workaround */
# define WA_05000204_CHECK_AVOID_FOR_REV <=3
#elif ((defined(__ADSPBF534__) || defined(__ADSPBF536__) || \
defined(__ADSPBF537__) || defined(__ADSPBF538__) || \
defined(__ADSPBF539__)) && \
(defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ == 0x0)))
/* check at RT for 0.4 revs when doing 204 workaround */
# define WA_05000204_CHECK_AVOID_FOR_REV <1
#else
/* do not check at RT for 0.4 revs when doing 204 workaround */
#endif
/* 05-00-0209 - Speed Path in Computational Unit Affects Certain Instructions
**
** ADSP-BF531/2/3 - revs 0.0 - 0.3 (fixed in 0.4)
** ADSP-BF534/6/7 - rev 0.0 (fixed in 0.1)
** ADSP-BF538/9 - rev 0.0 (fixed in 0.1)
** ADSP-BF561 - revs 0.0 - 0.3 (fixed in 0.4)
**
** SIGNBITS, EXTRACT, DEPOSIT, EXPADJ require a NOP before them if
** one of their operands is defined in the preceding instruction.
*/
#define WA_05000209 \
(defined(__SILICON_REVISION__) && \
(((defined(__ADSPBF531__) || \
defined(__ADSPBF532__) || \
defined(__ADSPBF533__)) && \
(__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff)) || \
((defined(__ADSPBF534__) || \
defined(__ADSPBF536__) || \
defined(__ADSPBF537__) || \
defined(__ADSPBF538__) || \
defined(__ADSPBF539__)) && \
(__SILICON_REVISION__ == 0x0 || __SILICON_REVISION__ == 0xffff)) || \
((defined(__ADSPBF561__)) && \
(__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff))))
/* 05-00-0212 - PORTx_FER, PORT_MUX Registers Do Not accept "writes" correctly
**
** Impacted:
** ADSP-BF53[467] - rev 0.0 (fixed 0.1)
**
** Use by System Services/Device Drivers.
*/
#define WA_05000212 \
(defined(__ADSPBF537_FAMILY__) && \
(defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ == 0x0 || __SILICON_REVISION__ == 0xffff)))
/* 050000244 - "If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control
** Causes Failures"
**
** When instruction cache is enabled, a CSYNC/SSYNC/IDLE around a
** change of control (including asynchronous exceptions/interrupts)
** can cause unpredictable results.
**
** This macro is used by System Services/Device Drivers.
**
** Impacted:
**
** BF531/2/3 - 0.0-0.4 (fixed 0.5)
** BF534/6/7 - 0.0-0.2 (fixed 0.3)
** BF534/8/9 - 0.0-0.1 (fixed 0.2)
** BF561 - 0.0-0.3 (fixed 0.5)
*/
#define WA_05000244 \
(defined(__SILICON_REVISION__) && \
((defined(__ADSPBF533_FAMILY__) && \
(__SILICON_REVISION__ <= 0x4 || __SILICON_REVISION__ == 0xffff)) || \
(defined(__ADSPBF537_FAMILY__) && \
(__SILICON_REVISION__ <= 0x2 || __SILICON_REVISION__ == 0xffff)) || \
(defined(__ADSPBF538_FAMILY__) && \
(__SILICON_REVISION__ <= 0x1 || __SILICON_REVISION__ == 0xffff)) || \
(defined(__ADSPBF561_FAMILY__) && \
(__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff))))
/* 050000245 - "False Hardware Error from an Access in the Shadow of a /* 050000245 - "False Hardware Error from an Access in the Shadow of a
** Conditional Branch" ** Conditional Branch"
** **
@ -354,118 +51,10 @@
** **
** This is for all Blackfin LP parts. ** This is for all Blackfin LP parts.
*/ */
#define WA_05000245 \ #define WA_05000245 \
(defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__)) (defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__))
/* 050000248 - "TESTSET Operation Forces Stall on the Other Core "
**
** Use by System Services/Device Drivers.
**
** Succeed any testset to L2 with a write to L2 to avoid the other core
** stalling. This must be atomic, as an interrupt between the two would
** cause the lockout to occur until the interrupt is fully serviced.
**
** This macro is used by System Services/Device Drivers.
**
** Impacted:
**
** BF561 - 0.0-0.3 (fixed 0.5)
**
*/
#define WA_05000248 \
(defined (__SILICON_REVISION__) && defined(__ADSPBF561_FAMILY__) && \
(__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff))
/* 05-00-0258 - "Instruction Cache is corrupted when bit 9 and 12 of
* the ICPLB Data registers differ"
*
* When bit 9 and bit 12 of the ICPLB Data MMR differ, the cache may
* not update properly. For example, for a particular cache line,
* the cache tag may be valid while the contents of that cache line
* are not present in the cache.
*
* Impacted:
*
* BF531/2/3 - 0.0-0.4 (fixed 0.5)
* BF534/6/7/8/9 - 0.0-0.2 (fixed 0.3)
* BF561 - 0.0-0.4 (fixed 0.5)
* BF566 - 0.0-0.1 (fixed 0.2)
* BF535/AD6532/AD6900 - all revs
*/
#define WA_05000258 \
(((defined(__ADSPBF531__) || \
defined(__ADSPBF532__) || \
defined(__ADSPBF533__)) && \
(defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ <= 0x4 || \
__SILICON_REVISION__ == 0xffff))) || \
((defined(__ADSPBF534__) || \
defined(__ADSPBF536__) || \
defined(__ADSPBF537__) || \
defined(__ADSPBF538__) || \
defined(__ADSPBF539__)) && \
(defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ <= 0x2 || \
__SILICON_REVISION__ == 0xffff))) || \
(defined(__ADSPBF561__) && \
(defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ <= 0x4 || \
__SILICON_REVISION__ == 0xffff))) || \
(defined(__ADSPBF566__) && \
(defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ <= 0x1 || \
__SILICON_REVISION__ == 0xffff))) || \
(!defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__)))
/* 05-00-0261 - "DCPLB_FAULT_ADDR MMR may be corrupted".
* The DCPLB_FAULT_ADDR MMR may contain the fault address of a
* aborted memory access which generated both a protection exception
* and a stall.
*
* We work around this by initially ignoring a DCPLB miss exception
* on the assumption that the faulting address might be invalid.
* We return without servicing. The exception will be raised
* again when the faulting instruction is re-executed. The fault
* address is correct this time round so the miss exception can
* be serviced as normal. The only complication is we have to
* ensure that we are about to service the same miss rather than
* a miss raised within a higher-priority interrupt handler, where
* the fault address could again be invalid. We therefore record
* the last seen RETX and only service an exception when RETX and
* the last seen RETX are equal.
*
* This problem impacts:
* BF531/2/3 - rev 0.0-0.4 (fixed 0.5)
* BF534/6/7/8/9 - rev 0.0-0.2 (fixed 0.3)
* BF561 - rev 0.0-0.4 (fixed 0.5)
*
*/
#define WA_05000261 \
(((defined(__ADSPBF531__) || \
defined(__ADSPBF532__) || \
defined(__ADSPBF533__)) && \
(defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ <= 0x4 || \
__SILICON_REVISION__ == 0xffff))) || \
((defined(__ADSPBF534__) || \
defined(__ADSPBF536__) || \
defined(__ADSPBF537__) || \
defined(__ADSPBF538__) || \
defined(__ADSPBF539__)) && \
(defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ <= 0x2 || \
__SILICON_REVISION__ == 0xffff))) || \
(defined(__ADSPBF561__) && \
(defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ <= 0x4 || \
__SILICON_REVISION__ == 0xffff))))
/* 05-00-0229 - "SPI Slave Boot Mode Modifies Registers". /* 05-00-0229 - "SPI Slave Boot Mode Modifies Registers".
* When the SPI slave boot completes, the final DMA IRQ is cleared * When the SPI slave boot completes, the final DMA IRQ is cleared
* but the DMA5_CONFIG and SPI_CTL registers are not reset to their * but the DMA5_CONFIG and SPI_CTL registers are not reset to their
@ -478,13 +67,13 @@
* *
* This problem impacts all revisions of ADSP-BF531/2/3/8/9 * This problem impacts all revisions of ADSP-BF531/2/3/8/9
*/ */
#define WA_05000229 \ #define WA_05000229 \
(defined(__ADSPBLACKFIN__) && defined (__SILICON_REVISION__) && \ (defined(__ADSPBLACKFIN__) && defined (__SILICON_REVISION__) && \
(defined(__ADSPBF531__) || defined(__ADSPBF532__) || \ (defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
defined(__ADSPBF533__) || defined(__ADSPBF538__) || \ defined(__ADSPBF533__) || defined(__ADSPBF538__) || \
defined(__ADSPBF539__))) defined(__ADSPBF539__)))
/* 05-00-0283 - "A system MMR write is stalled indefinitely when killed in a /* 05-00-0283 - "A system MMR write is stalled indefinitely when killed in a
* particular stage". * particular stage".
* *
@ -505,7 +94,6 @@
* we have to enable this workaround for the 534 0.3 libraries (see bottom * we have to enable this workaround for the 534 0.3 libraries (see bottom
* two lines). * two lines).
*/ */
#define WA_05000283 \ #define WA_05000283 \
(defined (__SILICON_REVISION__) && \ (defined (__SILICON_REVISION__) && \
(((defined(__ADSPBF531__) || \ (((defined(__ADSPBF531__) || \
@ -541,7 +129,6 @@
/* 05-00-0312 - Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers /* 05-00-0312 - Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers
** Are Interrupted ** Are Interrupted
** **
** Impacted: ** Impacted:
@ -555,14 +142,14 @@
*/ */
#define WA_05000312 \ #define WA_05000312 \
(defined(__SILICON_REVISION__) && \ (defined(__SILICON_REVISION__) && \
(defined(__ADSPBF533_FAMILY__) && \ ((defined(__ADSPBF533_FAMILY__) && \
(__SILICON_REVISION__ <= 0x5 || __SILICON_REVISION__ == 0xffff)) || \ (__SILICON_REVISION__ <= 0x5 || __SILICON_REVISION__ == 0xffff)) || \
(defined(__ADSPBF537_FAMILY__)) || \ (defined(__ADSPBF537_FAMILY__)) || \
(defined(__ADSPBF538_FAMILY__) && \ (defined(__ADSPBF538_FAMILY__) && \
(__SILICON_REVISION__ <= 0x4 || __SILICON_REVISION__ == 0xffff)) || \ (__SILICON_REVISION__ <= 0x4 || __SILICON_REVISION__ == 0xffff)) || \
(defined(__ADSPBF548_FAMILY__) && \ (defined(__ADSPBF548_FAMILY__) && \
(__SILICON_REVISION__ == 0x0 || __SILICON_REVISION__ == 0xffff)) || \ (__SILICON_REVISION__ == 0x0 || __SILICON_REVISION__ == 0xffff)) || \
(defined(__ADSPBF561_FAMILY__))) (defined(__ADSPBF561_FAMILY__))))
/* 05-00-0323 - Erroneous Flag (GPIO) Pin Operations under Specific Sequences /* 05-00-0323 - Erroneous Flag (GPIO) Pin Operations under Specific Sequences
@ -602,33 +189,19 @@
** BF523/5/7 - 0.0-0.1 (fixed in 0.2) ** BF523/5/7 - 0.0-0.1 (fixed in 0.2)
** **
*/ */
#define WA_05000371 \ #define WA_05000371 \
(defined(__SILICON_REVISION__) && \ (defined(__SILICON_REVISION__) && \
(defined(__ADSPBF533_FAMILY__) && \ ((defined(__ADSPBF533_FAMILY__) && \
(__SILICON_REVISION__ <= 0x5 || __SILICON_REVISION__ == 0xffff)) || \ (__SILICON_REVISION__ <= 0x5 || __SILICON_REVISION__ == 0xffff)) || \
(defined(__ADSPBF537_FAMILY__) && \ (defined(__ADSPBF537_FAMILY__) && \
(__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff)) || \ (__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff)) || \
(defined(__ADSPBF538_FAMILY__) && \ (defined(__ADSPBF538_FAMILY__) && \
(__SILICON_REVISION__ <= 0x4 || __SILICON_REVISION__ == 0xffff)) || \ (__SILICON_REVISION__ <= 0x4 || __SILICON_REVISION__ == 0xffff)) || \
(defined(__ADSPBF548_FAMILY__) && \ (defined(__ADSPBF548_FAMILY__) && \
(__SILICON_REVISION__ <= 0x1 || __SILICON_REVISION__ == 0xffff)) || \ (__SILICON_REVISION__ <= 0x1 || __SILICON_REVISION__ == 0xffff)) || \
(defined(__ADSPBF527_FAMILY__) && \ (defined(__ADSPBF527_FAMILY__) && \
(__SILICON_REVISION__ <= 0x1 || __SILICON_REVISION__ == 0xffff)) || \ (__SILICON_REVISION__ <= 0x1 || __SILICON_REVISION__ == 0xffff)) || \
(defined(__ADSPBF561__) || defined(__ADSPBF566__))) (defined(__ADSPBF561__) || defined(__ADSPBF566__))))
/* 05-00-0380 - Data Read From L3 Memory by USB DMA May be Corrupted
**
** Impacted:
** ADSP-BF52[357] - rev 0.0-0.1 (fixed 0.2)
**
** Use by System Services/Device Drivers.
*/
#define WA_05000380 \
(defined(__ADSPBF527_FAMILY__) && \
(defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ <= 0x1 || __SILICON_REVISION__ == 0xffff)))
/* 05-00-0412 - "TESTSET Instruction Causes Data Corruption with Writeback Data /* 05-00-0412 - "TESTSET Instruction Causes Data Corruption with Writeback Data
@ -654,7 +227,6 @@
* BF561/6 - rev 0.0-0.5 * BF561/6 - rev 0.0-0.5
* *
*/ */
#define WA_05000412 \ #define WA_05000412 \
(defined (__SILICON_REVISION__) && defined(__ADSPBF561__)) (defined (__SILICON_REVISION__) && defined(__ADSPBF561__))
@ -731,7 +303,6 @@
* BF561 - rev 0.4,0.5 * BF561 - rev 0.4,0.5
* *
*/ */
#define WA_05000428 \ #define WA_05000428 \
(defined(__SILICON_REVISION__) && \ (defined(__SILICON_REVISION__) && \
defined(__ADSPBF561__) && \ defined(__ADSPBF561__) && \
@ -750,6 +321,18 @@
#define WA_05000443 \ #define WA_05000443 \
(defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__)) (defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__))
/* 16-00-0005 - "Using L1 Instruction Cache with Parity Enabled is Unreliable."
**
** Using L1 instruction cache with parity enabled is unreliable and may cause
** unpredictable results.
**
** Impacted:
** BF6xx.
*/
#define WA_16000005 \
(defined(__ADSPBF60x__) && defined(__SILICON_REVISION__))
#ifdef _MISRA_RULES #ifdef _MISRA_RULES
#pragma diag(pop) #pragma diag(pop)
#endif /* _MISRA_RULES */ #endif /* _MISRA_RULES */