libgloss: bfin: sync headers to VDSP 5.0 Update 8
A new release of VDSP means syncing random updates to the libgloss headers. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Michael Frysinger
@ -14,7 +14,7 @@
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*
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* anomaly_macros_rtl.h : $Revision$
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*
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* Copyright (C) 2008, 2009 Analog Devices, Inc.
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* (c) Copyright 2005-2009 Analog Devices, Inc. All rights reserved.
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*
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* This file defines macros used within the run-time libraries to enable
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* certain anomaly workarounds for the appropriate chips and silicon
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@ -314,6 +314,72 @@
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(__SILICON_REVISION__ == 0x0 || __SILICON_REVISION__ == 0xffff)))
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/* 050000244 - "If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control
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** Causes Failures"
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**
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** When instruction cache is enabled, a CSYNC/SSYNC/IDLE around a
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** change of control (including asynchronous exceptions/interrupts)
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** can cause unpredictable results.
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**
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** This macro is used by System Services/Device Drivers.
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**
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** Impacted:
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**
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** BF531/2/3 - 0.0-0.4 (fixed 0.5)
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** BF534/6/7 - 0.0-0.2 (fixed 0.3)
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** BF534/8/9 - 0.0-0.1 (fixed 0.2)
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** BF561 - 0.0-0.3 (fixed 0.5)
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*/
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#define WA_05000244 \
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(defined(__SILICON_REVISION__) && \
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((defined(__ADSPBF533_FAMILY__) && \
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(__SILICON_REVISION__ <= 0x4 || __SILICON_REVISION__ == 0xffff)) || \
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(defined(__ADSPBF537_FAMILY__) && \
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(__SILICON_REVISION__ <= 0x2 || __SILICON_REVISION__ == 0xffff)) || \
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(defined(__ADSPBF538_FAMILY__) && \
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(__SILICON_REVISION__ <= 0x1 || __SILICON_REVISION__ == 0xffff)) || \
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(defined(__ADSPBF561_FAMILY__) && \
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(__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff))))
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/* 050000245 - "False Hardware Error from an Access in the Shadow of a
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** Conditional Branch"
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**
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** If a load accesses reserved or illegal memory on the opposite control
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** flow of a conditional jump to the taken path, a false hardware error
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** will occur.
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**
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** This macro is used by System Services/Device Drivers.
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**
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** This is for all Blackfin LP parts.
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*/
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#define WA_05000245 \
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(defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__))
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/* 050000248 - "TESTSET Operation Forces Stall on the Other Core "
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**
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** Use by System Services/Device Drivers.
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**
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** Succeed any testset to L2 with a write to L2 to avoid the other core
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** stalling. This must be atomic, as an interrupt between the two would
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** cause the lockout to occur until the interrupt is fully serviced.
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**
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** This macro is used by System Services/Device Drivers.
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**
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** Impacted:
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**
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** BF561 - 0.0-0.3 (fixed 0.5)
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**
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*/
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#define WA_05000248 \
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(defined (__SILICON_REVISION__) && defined(__ADSPBF561_FAMILY__) && \
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(__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff))
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/* 05-00-0258 - "Instruction Cache is corrupted when bit 9 and 12 of
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* the ICPLB Data registers differ"
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*
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@ -356,18 +422,6 @@
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(!defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__)))
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/* 05-00-0259 - "Non-deterministic ICPLB descriptors delivered to
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* hardware". Whenever ICPLBs are disabled via an MMR write, immediately
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* follow this write with a CSYNC, and locate the MMR write and CSYNC
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* within the same aligned 64 bit word.
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*
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* This problem impacts all revisions of Blackfins.
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*/
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#define WA_05000259 \
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(defined(__ADSPBLACKFIN__) && defined(__SILICON_REVISION__))
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/* 05-00-0261 - "DCPLB_FAULT_ADDR MMR may be corrupted".
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* The DCPLB_FAULT_ADDR MMR may contain the fault address of a
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* aborted memory access which generated both a protection exception
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@ -486,6 +540,31 @@
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(__SILICON_REVISION__ <= 0x5 || __SILICON_REVISION__ == 0xffff)))
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/* 05-00-0312 - Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers
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** Are Interrupted
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**
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** Impacted:
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** ADSP-BF53[123] - 0.0-0.5 (fixed in 0.6)
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** ADSP-BF53[467] - all supported revisions
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** ADSP-BF53[89] - 0.0-0.4 (fixed in 0.5)
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** ADSP-BF561 - all supported revisions
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** ADSP-BF54[24789] - 0.0 (fixed in 0.1)
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**
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** Used by VDK
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*/
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#define WA_05000312 \
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(defined(__SILICON_REVISION__) && \
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(defined(__ADSPBF533_FAMILY__) && \
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(__SILICON_REVISION__ <= 0x5 || __SILICON_REVISION__ == 0xffff)) || \
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(defined(__ADSPBF537_FAMILY__)) || \
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(defined(__ADSPBF538_FAMILY__) && \
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(__SILICON_REVISION__ <= 0x4 || __SILICON_REVISION__ == 0xffff)) || \
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(defined(__ADSPBF548_FAMILY__) && \
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(__SILICON_REVISION__ == 0x0 || __SILICON_REVISION__ == 0xffff)) || \
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(defined(__ADSPBF561_FAMILY__)))
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/* 05-00-0323 - Erroneous Flag (GPIO) Pin Operations under Specific Sequences
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**
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** Impacted:
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@ -511,6 +590,34 @@
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defined(__SILICON_REVISION__))
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/* 05-00-0371 - Possible RETS Register Corruption when Subroutine Is under
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** 5 Cycles in Duration
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**
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** This problem impacts:
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** BF531/2/3 - 0.0-0.5 (fixed in 0.6)
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** BF534/6/7 - 0.0-0.3
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** BF538/9 - 0.0-0.4 (fixed in 0.5)
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** BF561 - 0.0-0.5
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** BF542/4/7/8/9 - 0.0-0.1 (fixed in 0.2)
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** BF523/5/7 - 0.0-0.1 (fixed in 0.2)
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**
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*/
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#define WA_05000371 \
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(defined(__SILICON_REVISION__) && \
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(defined(__ADSPBF533_FAMILY__) && \
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(__SILICON_REVISION__ <= 0x5 || __SILICON_REVISION__ == 0xffff)) || \
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(defined(__ADSPBF537_FAMILY__) && \
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(__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff)) || \
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(defined(__ADSPBF538_FAMILY__) && \
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(__SILICON_REVISION__ <= 0x4 || __SILICON_REVISION__ == 0xffff)) || \
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(defined(__ADSPBF548_FAMILY__) && \
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(__SILICON_REVISION__ <= 0x1 || __SILICON_REVISION__ == 0xffff)) || \
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(defined(__ADSPBF527_FAMILY__) && \
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(__SILICON_REVISION__ <= 0x1 || __SILICON_REVISION__ == 0xffff)) || \
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(defined(__ADSPBF561__) || defined(__ADSPBF566__)))
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/* 05-00-0380 - Data Read From L3 Memory by USB DMA May be Corrupted
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**
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** Impacted:
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@ -552,6 +659,31 @@
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(defined (__SILICON_REVISION__) && defined(__ADSPBF561__))
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/* 05-00-0426 - Speculative Fetches of Indirect-Pointer Instructions Can
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** Cause False Hardware Errors
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**
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**
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** A false hardware error is generated if there is an indirect jump or
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** call through a pointer which may point to reserved or illegal memory
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** on the opposite control flow of a conditional jump to the taken path.
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** This commonly occurs when using function pointers, which can be
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** invalid (e.g., set to -1).
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**
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** Workaround: If instruction cache is on or the ICPLBs are enabled,
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** this anomaly does not apply. If instruction cache is off and ICPLBs
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** are disabled, the indirect pointer instructions must be 2 instructions
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** away from the branch instruction, which can be implemented using NOPs:
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**
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**
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** Impacted:
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** All parts and revisions other than BF535 based parts.
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**
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** Used by System Services/Device Drivers.
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*/
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#define WA_05000426 \
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(defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__))
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/* 05-00-0428 - "Lost/Corrupted Write to L2 Memory Following Speculative Read
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* by Core B from L2 Memory"
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*
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@ -608,6 +740,16 @@
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(__SILICON_REVISION__ == 0x5)))
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/* 05-00-0443 - IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall
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**
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** Impacted:
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** All parts and revisions other than BF535 based parts.
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**
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** Used by System Services/Device Drivers.
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*/
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#define WA_05000443 \
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(defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__))
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#ifdef _MISRA_RULES
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#pragma diag(pop)
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#endif /* _MISRA_RULES */
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