libgloss: bfin: sync headers to VDSP 5.0 Update 8
A new release of VDSP means syncing random updates to the libgloss headers. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Michael Frysinger
@@ -13,7 +13,7 @@
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/*
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** defBF51x_base.h
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**
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** Copyright (C) 2009 Analog Devices, Inc.
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** Copyright (C) 2007-2009 Analog Devices Inc., All Rights Reserved.
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**
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************************************************************************************
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**
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@@ -31,6 +31,7 @@
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#pragma diag(push)
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#pragma diag(suppress:misra_rule_19_4)
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#pragma diag(suppress:misra_rule_19_7)
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#include <stdint.h>
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#endif /* _MISRA_RULES */
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@@ -101,7 +102,6 @@
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#define UART0_LCR 0xFFC0040C /* Line Control Register */
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#define UART0_MCR 0xFFC00410 /* Modem Control Register */
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#define UART0_LSR 0xFFC00414 /* Line Status Register */
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#define UART0_MSR 0xFFC00418 /* Modem Status Register */
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#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
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#define UART0_GCTL 0xFFC00424 /* Global Control Register */
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@@ -567,7 +567,6 @@
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#define UART1_LCR 0xFFC0200C /* Line Control Register */
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#define UART1_MCR 0xFFC02010 /* Modem Control Register */
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#define UART1_LSR 0xFFC02014 /* Line Status Register */
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#define UART1_MSR 0xFFC02018 /* Modem Status Register */
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#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
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#define UART1_GCTL 0xFFC02024 /* Global Control Register */
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@@ -750,19 +749,15 @@
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#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
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/* SYSCR Masks */
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#define BMODE_BYPASS 0x0000 /* Bypass boot ROM, execute from 16-bit external memory */
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#define BMODE_FLASH 0x0001 /* Use Boot ROM to load from 8-bit or 16-bit flash */
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#define BMODE_SPIMEM 0x0003 /* Boot from serial SPI memory */
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#define BMODE_SPIHOST 0x0004 /* Boot from SPI0 host (slave mode) */
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#define BMODE_TWIMEM 0x0005 /* Boot from serial TWI memory */
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#define BMODE_TWIHOST 0x0006 /* Boot from TWI0 host (slave mode) */
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#define BMODE_UART0HOST 0x0007 /* Boot from UART0 host */
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#define BMODE_UART1HOST 0x0008 /* Boot from UART1 host */
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#define BMODE_SDRAMMEM 0x000A /* Boot from SDRAM memory (warm boot) */
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#define BMODE_OTPMEM 0x000B /* Boot from OTP memory */
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#define BMODE_HOSTDMA_ACK 0x000E /* Boot from 16-bit host DMA (ACK mode) */
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#define BMODE_HOSTDMA_INT 0x000F /* Boot from 8-bit host DMA (INT mode) */
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#define BMODE 0x000F /* Boot Mode. Mirror of BMODE Mode Pins */
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#define BMODE_BYPASS 0x0000 /* No boot mode */
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#define BMODE_FLASH 0x0001 /* Use Boot ROM to load from 8-bit or 16-bit flash */
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#define BMODE_SPI0MEM_INT 0x0002 /* Boot from internal SPI0 memory */
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#define BMODE_SPI0MEM_EXT 0x0003 /* Boot from external SPI0 memory */
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#define BMODE_SPI0HOST 0x0004 /* Boot from SPI0 host (slave mode) */
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#define BMODE_OTPMEM 0x0005 /* Boot from OTP memory */
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#define BMODE_SDRAMMEM 0x0006 /* Boot from SDRAM memory (warm boot) */
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#define BMODE_UART0HOST 0x0007 /* Boot from UART0 host */
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#define BMODE 0x0007 /* Boot Mode. Mirror of BMODE Mode Pins */
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#define BCODE 0x00F0
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#define BCODE_NORMAL 0x0000 /* normal boot, update PLL/VR, quickboot as by WURESET */
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@@ -771,11 +766,6 @@
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#define BCODE_ALLBOOT 0x0040 /* no quick boot, overrule WURESET, don't update PLL/VR */
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#define BCODE_FULLBOOT 0x0060 /* no quick boot, overrule WURESET, update PLL/VR */
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#define DCB1_PRIO 0x0100 /* DCB1 requests are urgent */
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#define DCB_ROT_PRIO 0x0200 /* enable rotating DCB priority */
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#define DEB1_PRIO 0x0400 /* DEB1 requests are urgent */
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#define DEB_ROT_PRIO 0x0800 /* enable rotating DEB priority */
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#define WURESET 0x1000 /* wakeup event since last hardware reset */
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#define DFRESET 0x2000 /* recent reset was due to a double fault event */
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#define WDRESET 0x4000 /* recent reset was due to a watchdog event */
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@@ -861,129 +851,130 @@
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#define _MF7 7
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#endif /* _MISRA_RULES */
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/* SIC_IAR0 Macros */
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#define P0_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #0 assigned IVG #x */
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#define P1_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #1 assigned IVG #x */
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#define P2_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #2 assigned IVG #x */
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#define P3_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #3 assigned IVG #x */
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#define P4_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #4 assigned IVG #x */
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#define P5_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #5 assigned IVG #x */
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#define P6_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #6 assigned IVG #x */
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#define P7_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #7 assigned IVG #x */
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/* SIC_IAR0 Macros*/
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#define P0_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #0 assigned IVG #x */
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#define P1_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #1 assigned IVG #x */
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#define P2_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #2 assigned IVG #x */
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#define P3_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #3 assigned IVG #x */
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#define P4_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #4 assigned IVG #x */
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#define P5_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #5 assigned IVG #x */
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#define P6_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #6 assigned IVG #x */
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#define P7_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #7 assigned IVG #x */
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/* SIC_IAR1 Macros */
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#define P8_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #8 assigned IVG #x */
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#define P9_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #9 assigned IVG #x */
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#define P10_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #10 assigned IVG #x */
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#define P11_IVG(x) /* Reserved */
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#define P12_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #12 assigned IVG #x */
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#define P13_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #13 assigned IVG #x */
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#define P14_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #14 assigned IVG #x */
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#define P15_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #15 assigned IVG #x */
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/* SIC_IAR1 Macros*/
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#define P8_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #8 assigned IVG #x */
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#define P9_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #9 assigned IVG #x */
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#define P10_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #10 assigned IVG #x */
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#define P11_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #11 assigned IVG #x */
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#define P12_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #12 assigned IVG #x */
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#define P13_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #13 assigned IVG #x */
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/* SIC_IAR2 Macros */
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#define P16_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #16 assigned IVG #x */
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#define P17_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #17 assigned IVG #x */
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#define P18_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #18 assigned IVG #x */
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#define P19_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #19 assigned IVG #x */
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#define P20_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #20 assigned IVG #x */
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#define P21_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #21 assigned IVG #x */
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#define P22_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #22 assigned IVG #x */
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#define P23_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #23 assigned IVG #x */
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/* SIC_IAR2 Macros*/
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#define P14_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #14 assigned IVG #x */
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#define P15_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #15 assigned IVG #x */
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#define P16_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #16 assigned IVG #x */
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#define P17_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #17 assigned IVG #x */
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#define P18_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #18 assigned IVG #x */
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#define P19_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #19 assigned IVG #x */
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#define P20_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #20 assigned IVG #x */
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#define P21_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #21 assigned IVG #x */
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/* SIC_IAR3 Macros */
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#define P24_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #24 assigned IVG #x */
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#define P25_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #25 assigned IVG #x */
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#define P26_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #26 assigned IVG #x */
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#define P27_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #27 assigned IVG #x */
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#define P28_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #28 assigned IVG #x */
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#define P29_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #29 assigned IVG #x */
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#define P30_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #30 assigned IVG #x */
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#define P31_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #31 assigned IVG #x */
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/* SIC_IAR3 Macros*/
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#define P22_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #22 assigned IVG #x */
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#define P23_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #23 assigned IVG #x */
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#define P24_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #24 assigned IVG #x */
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#define P25_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #25 assigned IVG #x */
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#define P26_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #26 assigned IVG #x */
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#define P27_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #27 assigned IVG #x */
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#define P28_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #28 assigned IVG #x */
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#define P29_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #29 assigned IVG #x */
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/* SIC_IAR4 Macros */
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#define P32_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #32 assigned IVG #x */
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#define P33_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #33 assigned IVG #x */
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#define P34_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #34 assigned IVG #x */
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#define P35_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #35 assigned IVG #x */
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#define P36_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #36 assigned IVG #x */
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#define P37_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #37 assigned IVG #x */
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#define P38_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #38 assigned IVG #x */
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#define P39_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #39 assigned IVG #x */
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/* SIC_IAR4 Macros*/
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#define P30_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #30 assigned IVG #x */
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#define P31_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #31 assigned IVG #x */
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#define P32_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #32 assigned IVG #x */
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#define P33_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #33 assigned IVG #x */
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#define P34_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #34 assigned IVG #x */
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#define P35_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #35 assigned IVG #x */
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#define P36_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #36 assigned IVG #x */
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#define P37_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #37 assigned IVG #x */
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/* SIC_IAR5 Macros */
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#define P40_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #40 assigned IVG #x */
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#define P41_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #41 assigned IVG #x */
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#define P42_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #42 assigned IVG #x */
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#define P43_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #43 assigned IVG #x */
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#define P44_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #44 assigned IVG #x */
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#define P45_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #45 assigned IVG #x */
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#define P46_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #46 assigned IVG #x */
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#define P47_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #47 assigned IVG #x */
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/* SIC_IAR5 Macros*/
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#define P38_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #38 assigned IVG #x */
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#define P39_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #39 assigned IVG #x */
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#define P40_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #40 assigned IVG #x */
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#define P41_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #41 assigned IVG #x */
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#define P42_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #42 assigned IVG #x */
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#define P43_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #43 assigned IVG #x */
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#define P44_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #44 assigned IVG #x */
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#define P45_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #45 assigned IVG #x */
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/* SIC_IAR6 Macros */
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#define P48_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #48 assigned IVG #x */
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#define P49_IVG(x) /* Reserved */
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#define P50_IVG(x) /* Reserved */
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#define P51_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #51 assigned IVG #x */
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#define P52_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #52 assigned IVG #x */
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#define P53_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #53 assigned IVG #x */
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#define P54_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #54 assigned IVG #x */
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#define P55_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #55 assigned IVG #x */
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/* SIC_IAR6 Macros*/
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#define P46_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #46 assigned IVG #x */
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#define P47_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #47 assigned IVG #x */
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#define P48_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #48 assigned IVG #x */
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#define P49_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #49 assigned IVG #x */
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#define P50_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #50 assigned IVG #x */
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#define P51_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #51 assigned IVG #x */
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#define P52_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #52 assigned IVG #x */
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#define P53_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #53 assigned IVG #x */
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/* SIC_IAR7 Macros*/
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#define P54_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #54 assigned IVG #x */
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#define P55_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #55 assigned IVG #x */
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#define P56_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #56 assigned IVG #x */
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#define P57_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #57 assigned IVG #x */
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#define P58_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #58 assigned IVG #x */
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#define P59_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #59 assigned IVG #x */
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#define P60_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #60 assigned IVG #x */
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#define P61_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #61 assigned IVG #x */
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/* SIC_IAR7 Macros */
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#define P56_IVG(x) /* Reserved */
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#define P57_IVG(x) /* Reserved */
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#define P58_IVG(x) /* Reserved */
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#define P59_IVG(x) /* Reserved */
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#define P60_IVG(x) /* Reserved */
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#define P61_IVG(x) /* Reserved */
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#define P62_IVG(x) /* Reserved */
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#define P63_IVG(x) /* Reserved */
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/* SIC_IMASK0 Masks*/
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#define SIC_UNMASK0_ALL 0x00000000 /* Unmask all peripheral interrupts */
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#define SIC_MASK0_ALL 0xFFFFF3FF /* Mask all peripheral interrupts */
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#define SIC_UNMASK0_ALL 0x00000000 /* Unmask all peripheral interrupts */
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#define SIC_MASK0_ALL 0xFFFFF3FF /* Mask all peripheral interrupts */
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#ifdef _MISRA_RULES
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#define SIC_MASK0(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
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#define SIC_UNMASK0(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))/*Unmask Peripheral #x interrupt*/
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#define SIC_MASK0(x) ((int32_t)1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
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#define SIC_UNMASK0(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /*Unmask Peripheral #x interrupt*/
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#else
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#define SIC_MASK0(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
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#define SIC_UNMASK0(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Unmask Peripheral #x interrupt */
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#define SIC_MASK0(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
|
||||
#define SIC_UNMASK0(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
|
||||
#endif /* _MISRA_RULES */
|
||||
|
||||
/* SIC_IMASK1 Masks*/
|
||||
#define SIC_UNMASK1_ALL 0x00000000 /* Unmask all peripheral interrupts */
|
||||
#define SIC_MASK1_ALL 0xFFFFFF /* Mask all peripheral interrupts */
|
||||
#define SIC_UNMASK1_ALL 0x00000000 /* Unmask all peripheral interrupts */
|
||||
#define SIC_MASK1_ALL 0xFFFFFF /* Mask all peripheral interrupts */
|
||||
#ifdef _MISRA_RULES
|
||||
#define SIC_MASK1(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
|
||||
#define SIC_UNMASK1(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))/*Unmask Peripheral #x interrupt*/
|
||||
#define SIC_MASK1(x) ((int32_t)1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
|
||||
#define SIC_UNMASK1(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /*Unmask Peripheral #x interrupt*/
|
||||
#else
|
||||
#define SIC_MASK1(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
|
||||
#define SIC_UNMASK1(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Unmask Peripheral #x interrupt */
|
||||
#define SIC_MASK1(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
|
||||
#define SIC_UNMASK1(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
|
||||
#endif /* _MISRA_RULES */
|
||||
|
||||
|
||||
/* SIC_IWR0 Masks*/
|
||||
#define IWR0_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
|
||||
#define IWR0_ENABLE_ALL 0xFFFFF3FF /* Wakeup Enable all peripherals */
|
||||
#define IWR0_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
|
||||
#define IWR0_ENABLE_ALL 0xFFFFF3FF /* Wakeup Enable all peripherals */
|
||||
#ifdef _MISRA_RULES
|
||||
#define IWR0_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
|
||||
#define IWR0_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))/*Wakeup Disable Peripheral #x */
|
||||
#define IWR0_ENABLE(x) ((int32_t)1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
|
||||
#define IWR0_DISABLE(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /*Wakeup Disable Peripheral #x */
|
||||
#else
|
||||
#define IWR0_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
|
||||
#define IWR0_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Wakeup Disable Peripheral #x */
|
||||
#define IWR0_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
|
||||
#define IWR0_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
|
||||
#endif /* _MISRA_RULES */
|
||||
|
||||
/* SIC_IWR1 Masks*/
|
||||
#define IWR1_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
|
||||
#define IWR1_ENABLE_ALL 0xFFFFFF /* Wakeup Enable all peripherals */
|
||||
#define IWR1_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
|
||||
#define IWR1_ENABLE_ALL 0xFFFFFF /* Wakeup Enable all peripherals */
|
||||
#ifdef _MISRA_RULES
|
||||
#define IWR1_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
|
||||
#define IWR1_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))/* Wakeup Disable Peripheral #x*/
|
||||
#define IWR1_ENABLE(x) ((int32_t)1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
|
||||
#define IWR1_DISABLE(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x*/
|
||||
#else
|
||||
#define IWR1_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
|
||||
#define IWR1_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Wakeup Disable Peripheral #x */
|
||||
#define IWR1_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
|
||||
#define IWR1_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Wakeup Disable Peripheral #x */
|
||||
#endif /* _MISRA_RULES */
|
||||
|
||||
|
||||
@@ -1844,8 +1835,6 @@
|
||||
#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
|
||||
|
||||
/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
|
||||
#define PGDE_UART PFDE_UART
|
||||
#define PGDE_DMA PFDE_DMA
|
||||
#define CKELOW SCKELOW
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user