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Fix support ARC processors without barrel-shifter

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crt0.S for ARC used to use instruction "asr.f lp_count, r3, 2" for all cores
except ARC601. However instructions which shift more than 1 bit are
optional, so this crt0.S didn't worked for all ARC cores.

Luckily this is a shift just by 2 bits on all occassions, so fix is trivial
- use two single-bit shifts.

libgloss/ChangeLog

2016-04-29  Anton Kolesov  <anton.kolesov@synopsys.com>

        * arc/crt0.S: Fix support for processors without barrel-shifter.

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
This commit is contained in:
Jeff Johnston
2016-05-02 12:04:40 -04:00
parent cd494f7038
commit 11afe8f6b6
1 changed files with 6 additions and 1 deletions
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5
libgloss/arc/crt0.S
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@@ -135,7 +135,12 @@ __start:
mov_s r2, @__sbss_start ; r2 = start of the bss section
sub r3, @_end, r2 ; r3 = size of the bss section in bytes
; set up the loop counter register to the size (in words) of the bss section
#if defined (__ARC_BARREL_SHIFTER__)
asr.f lp_count, r3, 2
#else
asr_s r13, r3
asr.f lp_count, r13
#endif
#if defined (__ARC600__)
; loop to zero out the bss. Enter loop only if lp_count != 0
lpnz @.Lend_zbss