For include/opcode:
* mips.h (INSN_ISA5): New. For opcodes: * mips-opc.c (I5): New. (abs.ps,add.ps,alnv.ps,c.COND.ps,cvt.s.pl,cvt.s.pu,cvt.ps.s madd.ps,movf.ps,movt.ps,mul.ps,net.ps,nmadd.ps,nmsub.ps, pll.ps,plu.ps,pul.ps,puu.ps,sub.ps,suxc1,luxc1): New.
This commit is contained in:
		| @@ -1,3 +1,7 @@ | |||||||
|  | 1999-11-18  Gavin Romig-Koch  <gavin@cygnus.com> | ||||||
|  |  | ||||||
|  | 	* mips.h (INSN_ISA5): New. | ||||||
|  |  | ||||||
| 1999-11-01  Gavin Romig-Koch  <gavin@cygnus.com> | 1999-11-01  Gavin Romig-Koch  <gavin@cygnus.com> | ||||||
|  |  | ||||||
| 	* mips.h (OPCODE_IS_MEMBER): New. | 	* mips.h (OPCODE_IS_MEMBER): New. | ||||||
|   | |||||||
| @@ -308,6 +308,7 @@ struct mips_opcode | |||||||
| #define INSN_ISA3		    0x00000003 | #define INSN_ISA3		    0x00000003 | ||||||
| /* MIPS ISA 4 instruction (R8000).  */ | /* MIPS ISA 4 instruction (R8000).  */ | ||||||
| #define INSN_ISA4		    0x00000004 | #define INSN_ISA4		    0x00000004 | ||||||
|  | #define INSN_ISA5		    0x00000005 | ||||||
|  |  | ||||||
| /* Chip specific instructions.  These are bitmasks.  */ | /* Chip specific instructions.  These are bitmasks.  */ | ||||||
| /* MIPS R4650 instruction.  */ | /* MIPS R4650 instruction.  */ | ||||||
|   | |||||||
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