309 lines
6.3 KiB
C
309 lines
6.3 KiB
C
/* Copyright (C) Charles Forsyth
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* See /doc/license/NOTICE.Plan9-9k.txt for details about the licensing.
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*/
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/* Portions of this file are Copyright (C) 2015-2018 Giacomo Tesio <giacomo@tesio.it>
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* See /doc/license/gpl-2.0.txt for details about the licensing.
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*/
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/* Portions of this file are Copyright (C) 9front's team.
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* See /doc/license/9front-mit for details about the licensing.
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* See http://code.9front.org/hg/plan9front/ for a list of authors.
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*/
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/*
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* PC-specific code for
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* USB Enhanced Host Controller Interface (EHCI) driver
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* High speed USB 2.0.
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "../port/error.h"
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#include "../port/usb.h"
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#include "../port/portusbehci.h"
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#include "usbehci.h"
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static Ctlr* ctlrs[Nhcis];
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static int maxehci = Nhcis;
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static int
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ehciecap(Ctlr *ctlr, int cap)
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{
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int i, off;
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off = (ctlr->capio->capparms >> Ceecpshift) & Ceecpmask;
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for(i=0; i<48; i++){
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if(off < 0x40 || (off & 3) != 0)
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break;
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if(pcicfgr8(ctlr->pcidev, off) == cap)
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return off;
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off = pcicfgr8(ctlr->pcidev, off+1);
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}
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return -1;
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}
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static void
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getehci(Ctlr* ctlr)
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{
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int i, off;
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off = ehciecap(ctlr, Clegacy);
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if(off == -1)
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return;
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if(pcicfgr8(ctlr->pcidev, off+CLbiossem) != 0){
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dprint("ehci %#p: bios active, taking over...\n", ctlr->capio);
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pcicfgw8(ctlr->pcidev, off+CLossem, 1);
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for(i = 0; i < 100; i++){
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if(pcicfgr8(ctlr->pcidev, off+CLbiossem) == 0)
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break;
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delay(10);
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}
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if(i == 100)
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jehanne_print("ehci %#p: bios timed out\n", ctlr->capio);
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}
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pcicfgw32(ctlr->pcidev, off+CLcontrol, 0); /* no SMIs */
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}
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static void
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ehcireset(Ctlr *ctlr)
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{
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Eopio *opio;
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int i;
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ilock(&ctlr->l);
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dprint("ehci %#p reset\n", ctlr->capio);
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opio = ctlr->opio;
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/*
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* reclaim from bios
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*/
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getehci(ctlr);
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/*
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* halt and route ports to companion controllers
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* until we are setup
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*/
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ehcirun(ctlr, 0);
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opio->config = 0;
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coherence();
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/* clear high 32 bits of address signals if it's 64 bits capable.
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* This is probably not needed but it does not hurt and others do it.
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*/
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if((ctlr->capio->capparms & C64) != 0){
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dprint("ehci: 64 bits\n");
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opio->seg = 0;
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coherence();
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}
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if(ehcidebugcapio != ctlr->capio){
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opio->cmd |= Chcreset; /* controller reset */
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coherence();
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for(i = 0; i < 100; i++){
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if((opio->cmd & Chcreset) == 0)
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break;
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delay(1);
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}
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if(i == 100)
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jehanne_print("ehci %#p controller reset timed out\n", ctlr->capio);
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}
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opio->cmd |= Citc1; /* 1 intr. per µframe */
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coherence();
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switch(opio->cmd & Cflsmask){
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case Cfls1024:
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ctlr->nframes = 1024;
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break;
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case Cfls512:
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ctlr->nframes = 512;
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break;
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case Cfls256:
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ctlr->nframes = 256;
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break;
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default:
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panic("ehci: unknown fls %ld", opio->cmd & Cflsmask);
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}
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dprint("ehci: %d frames\n", ctlr->nframes);
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iunlock(&ctlr->l);
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}
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static void
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setdebug(Hci* _, int d)
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{
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ehcidebug = d;
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}
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static void
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shutdown(Hci *hp)
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{
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int i;
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Ctlr *ctlr;
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Eopio *opio;
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ctlr = hp->aux;
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ilock(&ctlr->l);
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opio = ctlr->opio;
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opio->cmd |= Chcreset; /* controller reset */
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coherence();
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for(i = 0; i < 100; i++){
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if((opio->cmd & Chcreset) == 0)
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break;
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delay(1);
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}
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if(i >= 100)
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jehanne_print("ehci %#p controller reset timed out\n", ctlr->capio);
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delay(100);
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ehcirun(ctlr, 0);
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opio->frbase = 0;
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iunlock(&ctlr->l);
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}
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static void
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scanpci(void)
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{
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static int already = 0;
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int i;
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uintptr_t io;
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Ctlr *ctlr;
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Pcidev *p;
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Ecapio *capio;
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if(already)
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return;
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already = 1;
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p = nil;
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while ((p = pcimatch(p, 0, 0)) != nil) {
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/*
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* Find EHCI controllers (Programming Interface = 0x20).
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*/
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if(p->ccrb != Pcibcserial || p->ccru != Pciscusb)
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continue;
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switch(p->ccrp){
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case 0x20:
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io = p->mem[0].bar & ~0x0f;
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break;
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default:
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continue;
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}
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if(io == 0){
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jehanne_print("usbehci: %x %x: failed to map registers\n",
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p->vid, p->did);
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continue;
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}
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dprint("usbehci: %#x %#x: port %#p size %#x irq %d\n",
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p->vid, p->did, io, p->mem[0].size, p->intl);
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ctlr = jehanne_malloc(sizeof(Ctlr));
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if(ctlr == nil){
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jehanne_print("usbehci: no memory\n");
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continue;
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}
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ctlr->pcidev = p;
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capio = ctlr->capio = vmap(io, p->mem[0].size);
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ctlr->opio = (Eopio*)((uintptr_t)capio + (capio->cap & 0xff));
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pcisetbme(p);
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pcisetpms(p, 0);
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for(i = 0; i < Nhcis; i++)
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if(ctlrs[i] == nil){
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ctlrs[i] = ctlr;
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break;
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}
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if(i >= Nhcis)
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jehanne_print("ehci: bug: more than %d controllers\n", Nhcis);
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/*
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* currently, if we enable a second ehci controller,
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* we'll wedge solid after iunlock in init for the second one.
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*/
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if (i >= maxehci) {
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iprint("usbehci: ignoring controllers after first %d, "
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"at %#p\n", maxehci, io);
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if(i < Nhcis)
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ctlrs[i] = nil;
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}
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}
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}
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static int
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reset(Hci *hp)
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{
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int i;
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char *s;
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Ctlr *ctlr;
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Ecapio *capio;
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Pcidev *p;
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static Lock resetlck;
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s = getconf("*maxehci");
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if (s != nil && s[0] >= '0' && s[0] <= '9')
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maxehci = jehanne_atoi(s);
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if(maxehci == 0 || getconf("*nousbehci"))
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return -1;
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ilock(&resetlck);
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scanpci();
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/*
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* Any adapter matches if no hp->port is supplied,
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* otherwise the ports must match.
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*/
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ctlr = nil;
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for(i = 0; i < Nhcis && ctlrs[i] != nil; i++){
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ctlr = ctlrs[i];
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if(ctlr->active == 0)
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if(hp->port == 0 || hp->port == (uintptr_t)ctlr->capio){
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ctlr->active = 1;
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break;
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}
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}
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iunlock(&resetlck);
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if(i >= Nhcis || ctlrs[i] == nil)
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return -1;
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p = ctlr->pcidev;
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hp->aux = ctlr;
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hp->port = (uintptr_t)ctlr->capio;
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hp->irq = p->intl;
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hp->tbdf = p->tbdf;
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capio = ctlr->capio;
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hp->nports = capio->parms & Cnports;
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ddprint("echi: %s, ncc %lud npcc %lud\n",
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capio->parms & 0x10000 ? "leds" : "no leds",
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(capio->parms >> 12) & 0xf, (capio->parms >> 8) & 0xf);
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ddprint("ehci: routing %s, %sport power ctl, %d ports\n",
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capio->parms & 0x40 ? "explicit" : "automatic",
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capio->parms & 0x10 ? "" : "no ", hp->nports);
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ehcireset(ctlr);
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ehcimeminit(ctlr);
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/*
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* Linkage to the generic HCI driver.
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*/
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ehcilinkage(hp);
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hp->shutdown = shutdown;
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hp->debug = setdebug;
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if(hp->interrupt == nil)
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return 0;
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/*
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* IRQ2 doesn't really exist, it's used to gang the interrupt
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* controllers together. A device set to IRQ2 will appear on
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* the second interrupt controller as IRQ9.
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*/
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if(hp->irq == 2)
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hp->irq = 9;
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intrenable(hp->irq, hp->interrupt, hp, hp->tbdf, hp->type);
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return 0;
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}
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void
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usbehcilink(void)
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{
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addhcitype("ehci", reset);
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}
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