738 lines
14 KiB
C
738 lines
14 KiB
C
/* Copyright (C) Charles Forsyth
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* See /doc/license/NOTICE.Plan9-9k.txt for details about the licensing.
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*/
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/* Portions of this file are Copyright (C) 9front's team.
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* See /doc/license/9front-mit for details about the licensing.
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* See http://code.9front.org/hg/plan9front/ for a list of authors.
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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/*
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* 8250 UART and compatibles.
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*/
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enum {
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Uart0 = 0x3F8, /* COM1 */
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Uart0IRQ = 4,
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Uart1 = 0x2F8, /* COM2 */
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Uart1IRQ = 3,
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UartFREQ = 1843200,
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};
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enum { /* registers */
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Rbr = 0, /* Receiver Buffer (RO) */
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Thr = 0, /* Transmitter Holding (WO) */
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Ier = 1, /* Interrupt Enable */
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Iir = 2, /* Interrupt Identification (RO) */
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Fcr = 2, /* FIFO Control (WO) */
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Lcr = 3, /* Line Control */
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Mcr = 4, /* Modem Control */
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Lsr = 5, /* Line Status */
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Msr = 6, /* Modem Status */
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Scr = 7, /* Scratch Pad */
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Dll = 0, /* Divisor Latch LSB */
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Dlm = 1, /* Divisor Latch MSB */
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};
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enum { /* Ier */
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Erda = 0x01, /* Enable Received Data Available */
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Ethre = 0x02, /* Enable Thr Empty */
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Erls = 0x04, /* Enable Receiver Line Status */
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Ems = 0x08, /* Enable Modem Status */
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};
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enum { /* Iir */
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Ims = 0x00, /* Ms interrupt */
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Ip = 0x01, /* Interrupt Pending (not) */
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Ithre = 0x02, /* Thr Empty */
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Irda = 0x04, /* Received Data Available */
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Irls = 0x06, /* Receiver Line Status */
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Ictoi = 0x0C, /* Character Time-out Indication */
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IirMASK = 0x3F,
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Ifena = 0xC0, /* FIFOs enabled */
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};
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enum { /* Fcr */
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FIFOena = 0x01, /* FIFO enable */
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FIFOrclr = 0x02, /* clear Rx FIFO */
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FIFOtclr = 0x04, /* clear Tx FIFO */
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FIFO1 = 0x00, /* Rx FIFO trigger level 1 byte */
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FIFO4 = 0x40, /* 4 bytes */
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FIFO8 = 0x80, /* 8 bytes */
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FIFO14 = 0xC0, /* 14 bytes */
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};
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enum { /* Lcr */
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Wls5 = 0x00, /* Word Length Select 5 bits/byte */
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Wls6 = 0x01, /* 6 bits/byte */
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Wls7 = 0x02, /* 7 bits/byte */
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Wls8 = 0x03, /* 8 bits/byte */
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WlsMASK = 0x03,
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Stb = 0x04, /* 2 stop bits */
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Pen = 0x08, /* Parity Enable */
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Eps = 0x10, /* Even Parity Select */
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Stp = 0x20, /* Stick Parity */
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Brk = 0x40, /* Break */
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Dlab = 0x80, /* Divisor Latch Access Bit */
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};
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enum { /* Mcr */
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Dtr = 0x01, /* Data Terminal Ready */
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Rts = 0x02, /* Ready To Send */
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Out1 = 0x04, /* no longer in use */
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Ie = 0x08, /* IRQ Enable */
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Dm = 0x10, /* Diagnostic Mode loopback */
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};
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enum { /* Lsr */
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Dr = 0x01, /* Data Ready */
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Oe = 0x02, /* Overrun Error */
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Pe = 0x04, /* Parity Error */
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Fe = 0x08, /* Framing Error */
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Bi = 0x10, /* Break Interrupt */
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Thre = 0x20, /* Thr Empty */
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Temt = 0x40, /* Tramsmitter Empty */
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FIFOerr = 0x80, /* error in receiver FIFO */
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};
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enum { /* Msr */
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Dcts = 0x01, /* Delta Cts */
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Ddsr = 0x02, /* Delta Dsr */
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Teri = 0x04, /* Trailing Edge of Ri */
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Ddcd = 0x08, /* Delta Dcd */
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Cts = 0x10, /* Clear To Send */
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Dsr = 0x20, /* Data Set Ready */
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Ri = 0x40, /* Ring Indicator */
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Dcd = 0x80, /* Data Set Ready */
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};
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typedef struct Ctlr {
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int io;
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int irq;
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int tbdf;
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int iena;
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void* vector;
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int poll;
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uint8_t sticky[8];
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Lock;
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int hasfifo;
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int checkfifo;
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int fena;
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} Ctlr;
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extern PhysUart i8250physuart;
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static Ctlr i8250ctlr[2] = {
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{ .io = Uart0,
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.irq = Uart0IRQ,
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.tbdf = -1, },
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{ .io = Uart1,
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.irq = Uart1IRQ,
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.tbdf = -1, },
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};
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static Uart i8250uart[2] = {
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{ .regs = &i8250ctlr[0],
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.name = "COM1",
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.freq = UartFREQ,
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.phys = &i8250physuart,
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.special= 0,
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.next = &i8250uart[1], },
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{ .regs = &i8250ctlr[1],
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.name = "COM2",
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.freq = UartFREQ,
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.phys = &i8250physuart,
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.special= 0,
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.next = nil, },
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};
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#define csr8r(c, r) inb((c)->io+(r))
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#define csr8w(c, r, v) outb((c)->io+(r), (c)->sticky[(r)]|(v))
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#define csr8o(c, r, v) outb((c)->io+(r), (v))
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static long
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i8250status(Uart* uart, void* buf, long n, long offset)
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{
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char *p;
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Ctlr *ctlr;
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uint8_t ier, lcr, mcr, msr;
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ctlr = uart->regs;
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p = smalloc(READSTR);
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mcr = ctlr->sticky[Mcr];
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msr = csr8r(ctlr, Msr);
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ier = ctlr->sticky[Ier];
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lcr = ctlr->sticky[Lcr];
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jehanne_snprint(p, READSTR,
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"b%d c%d d%d e%d l%d m%d p%c r%d s%d i%d\n"
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"dev(%d) type(%d) framing(%d) overruns(%d) "
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"berr(%d) serr(%d)%s%s%s%s\n",
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uart->baud,
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uart->hup_dcd,
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(msr & Dsr) != 0,
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uart->hup_dsr,
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(lcr & WlsMASK) + 5,
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(ier & Ems) != 0,
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(lcr & Pen) ? ((lcr & Eps) ? 'e': 'o'): 'n',
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(mcr & Rts) != 0,
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(lcr & Stb) ? 2: 1,
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ctlr->fena,
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uart->dev,
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uart->type,
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uart->ferr,
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uart->oerr,
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uart->berr,
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uart->serr,
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(msr & Cts) ? " cts": "",
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(msr & Dsr) ? " dsr": "",
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(msr & Dcd) ? " dcd": "",
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(msr & Ri) ? " ring": ""
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);
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n = readstr(offset, buf, n, p);
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jehanne_free(p);
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return n;
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}
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static void
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i8250fifo(Uart* uart, int level)
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{
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Ctlr *ctlr;
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ctlr = uart->regs;
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if(ctlr->hasfifo == 0)
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return;
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/*
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* Changing the FIFOena bit in Fcr flushes data
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* from both receive and transmit FIFOs; there's
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* no easy way to guarantee not losing data on
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* the receive side, but it's possible to wait until
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* the transmitter is really empty.
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*/
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ilock(ctlr);
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while(!(csr8r(ctlr, Lsr) & Temt))
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;
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/*
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* Set the trigger level, default is the max.
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* value.
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* Some UARTs require FIFOena to be set before
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* other bits can take effect, so set it twice.
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*/
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ctlr->fena = level;
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switch(level){
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case 0:
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break;
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case 1:
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level = FIFO1|FIFOena;
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break;
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case 4:
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level = FIFO4|FIFOena;
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break;
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case 8:
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level = FIFO8|FIFOena;
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break;
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default:
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level = FIFO14|FIFOena;
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break;
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}
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csr8w(ctlr, Fcr, level);
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csr8w(ctlr, Fcr, level);
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iunlock(ctlr);
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}
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static void
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i8250dtr(Uart* uart, int on)
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{
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Ctlr *ctlr;
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/*
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* Toggle DTR.
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*/
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ctlr = uart->regs;
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if(on)
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ctlr->sticky[Mcr] |= Dtr;
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else
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ctlr->sticky[Mcr] &= ~Dtr;
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csr8w(ctlr, Mcr, 0);
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}
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static void
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i8250rts(Uart* uart, int on)
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{
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Ctlr *ctlr;
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/*
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* Toggle RTS.
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*/
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ctlr = uart->regs;
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if(on)
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ctlr->sticky[Mcr] |= Rts;
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else
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ctlr->sticky[Mcr] &= ~Rts;
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csr8w(ctlr, Mcr, 0);
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}
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static void
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i8250modemctl(Uart* uart, int on)
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{
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Ctlr *ctlr;
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ctlr = uart->regs;
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ilock(&uart->tlock);
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if(on){
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ctlr->sticky[Ier] |= Ems;
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csr8w(ctlr, Ier, ctlr->sticky[Ier]);
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uart->modem = 1;
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uart->cts = csr8r(ctlr, Msr) & Cts;
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}
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else{
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ctlr->sticky[Ier] &= ~Ems;
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csr8w(ctlr, Ier, ctlr->sticky[Ier]);
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uart->modem = 0;
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uart->cts = 1;
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}
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iunlock(&uart->tlock);
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/* modem needs fifo */
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(*uart->phys->fifo)(uart, on);
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}
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static int
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i8250parity(Uart* uart, int parity)
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{
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int lcr;
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Ctlr *ctlr;
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ctlr = uart->regs;
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lcr = ctlr->sticky[Lcr] & ~(Eps|Pen);
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switch(parity){
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case 'e':
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lcr |= Eps|Pen;
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break;
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case 'o':
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lcr |= Pen;
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break;
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case 'n':
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break;
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default:
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return -1;
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}
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ctlr->sticky[Lcr] = lcr;
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csr8w(ctlr, Lcr, 0);
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uart->parity = parity;
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return 0;
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}
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static int
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i8250stop(Uart* uart, int stop)
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{
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int lcr;
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Ctlr *ctlr;
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ctlr = uart->regs;
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lcr = ctlr->sticky[Lcr] & ~Stb;
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switch(stop){
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case 1:
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break;
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case 2:
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lcr |= Stb;
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break;
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default:
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return -1;
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}
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ctlr->sticky[Lcr] = lcr;
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csr8w(ctlr, Lcr, 0);
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uart->stop = stop;
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return 0;
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}
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static int
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i8250bits(Uart* uart, int bits)
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{
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int lcr;
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Ctlr *ctlr;
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ctlr = uart->regs;
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lcr = ctlr->sticky[Lcr] & ~WlsMASK;
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switch(bits){
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case 5:
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lcr |= Wls5;
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break;
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case 6:
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lcr |= Wls6;
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break;
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case 7:
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lcr |= Wls7;
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break;
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case 8:
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lcr |= Wls8;
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break;
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default:
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return -1;
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}
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ctlr->sticky[Lcr] = lcr;
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csr8w(ctlr, Lcr, 0);
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uart->bits = bits;
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return 0;
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}
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static int
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i8250baud(Uart* uart, int baud)
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{
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uint32_t bgc;
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Ctlr *ctlr;
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/*
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* Set the Baud rate by calculating and setting the Baud rate
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* Generator Constant. This will work with fairly non-standard
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* Baud rates.
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*/
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if(uart->freq == 0 || baud <= 0)
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return -1;
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bgc = (uart->freq+8*baud-1)/(16*baud);
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ctlr = uart->regs;
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csr8w(ctlr, Lcr, Dlab);
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csr8o(ctlr, Dlm, bgc>>8);
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csr8o(ctlr, Dll, bgc);
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csr8w(ctlr, Lcr, 0);
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uart->baud = baud;
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return 0;
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}
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static void
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i8250break(Uart* uart, int ms)
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{
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Ctlr *ctlr;
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/*
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* Send a break.
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*/
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if(ms <= 0)
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ms = 200;
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ctlr = uart->regs;
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csr8w(ctlr, Lcr, Brk);
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tsleep(&up->sleep, return0, 0, ms);
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csr8w(ctlr, Lcr, 0);
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}
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static void
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i8250kick(Uart* uart)
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{
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int i;
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Ctlr *ctlr;
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if(uart->cts == 0 || uart->blocked)
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return;
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/*
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* 128 here is an arbitrary limit to make sure
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* we don't stay in this loop too long. If the
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* chip's output queue is longer than 128, too
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* bad -- presotto
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*/
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ctlr = uart->regs;
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for(i = 0; i < 128; i++){
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if(!(csr8r(ctlr, Lsr) & Thre))
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break;
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if(uart->op >= uart->oe && uartstageoutput(uart) == 0)
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break;
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csr8o(ctlr, Thr, *(uart->op++));
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}
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}
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static void
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i8250interrupt(Ureg* _1, void* arg)
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{
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Ctlr *ctlr;
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Uart *uart;
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int iir, lsr, old, r;
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uart = arg;
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ctlr = uart->regs;
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for(iir = csr8r(ctlr, Iir); !(iir & Ip); iir = csr8r(ctlr, Iir)){
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switch(iir & IirMASK){
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case Ims: /* Ms interrupt */
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r = csr8r(ctlr, Msr);
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if(r & Dcts){
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ilock(&uart->tlock);
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old = uart->cts;
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uart->cts = r & Cts;
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if(old == 0 && uart->cts)
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uart->ctsbackoff = 2;
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iunlock(&uart->tlock);
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}
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if(r & Ddsr){
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old = r & Dsr;
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if(uart->hup_dsr && uart->dsr && !old)
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uart->dohup = 1;
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uart->dsr = old;
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}
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if(r & Ddcd){
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old = r & Dcd;
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if(uart->hup_dcd && uart->dcd && !old)
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uart->dohup = 1;
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uart->dcd = old;
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}
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break;
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case Ithre: /* Thr Empty */
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uartkick(uart);
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break;
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case Irda: /* Received Data Available */
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case Irls: /* Receiver Line Status */
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case Ictoi: /* Character Time-out Indication */
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/*
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* Consume any received data.
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* If the received byte came in with a break,
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* parity or framing error, throw it away;
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* overrun is an indication that something has
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* already been tossed.
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*/
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while((lsr = csr8r(ctlr, Lsr)) & Dr){
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if(lsr & (FIFOerr|Oe))
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uart->oerr++;
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if(lsr & Pe)
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uart->perr++;
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if(lsr & Fe)
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uart->ferr++;
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r = csr8r(ctlr, Rbr);
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if(!(lsr & (Bi|Fe|Pe)))
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uartrecv(uart, r);
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}
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break;
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default:
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iprint("weird uart interrupt %#2.2ux\n", iir);
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break;
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}
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}
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}
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|
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static void
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i8250disable(Uart* uart)
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{
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Ctlr *ctlr;
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|
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/*
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* Turn off DTR and RTS, disable interrupts and fifos.
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*/
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(*uart->phys->dtr)(uart, 0);
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(*uart->phys->rts)(uart, 0);
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(*uart->phys->fifo)(uart, 0);
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ctlr = uart->regs;
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ctlr->sticky[Ier] = 0;
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csr8w(ctlr, Ier, ctlr->sticky[Ier]);
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|
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if(ctlr->iena != 0){
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ctlr->iena = 0;
|
|
intrdisable(ctlr->irq, i8250interrupt, uart, ctlr->tbdf, uart->name);
|
|
}
|
|
}
|
|
|
|
static void
|
|
i8250enable(Uart* uart, int ie)
|
|
{
|
|
Ctlr *ctlr;
|
|
|
|
ctlr = uart->regs;
|
|
|
|
/*
|
|
* Check if there is a FIFO.
|
|
* Changing the FIFOena bit in Fcr flushes data
|
|
* from both receive and transmit FIFOs; there's
|
|
* no easy way to guarantee not losing data on
|
|
* the receive side, but it's possible to wait until
|
|
* the transmitter is really empty.
|
|
* Also, reading the Iir outwith i8250interrupt()
|
|
* can be dangerous, but this should only happen
|
|
* once, before interrupts are enabled.
|
|
*/
|
|
ilock(ctlr);
|
|
if(!ctlr->checkfifo){
|
|
/*
|
|
* Wait until the transmitter is really empty.
|
|
*/
|
|
while(!(csr8r(ctlr, Lsr) & Temt))
|
|
;
|
|
csr8w(ctlr, Fcr, FIFOena);
|
|
if(csr8r(ctlr, Iir) & Ifena)
|
|
ctlr->hasfifo = 1;
|
|
csr8w(ctlr, Fcr, 0);
|
|
ctlr->checkfifo = 1;
|
|
}
|
|
iunlock(ctlr);
|
|
|
|
/*
|
|
* Enable interrupts and turn on DTR and RTS.
|
|
* Be careful if this is called to set up a polled serial line
|
|
* early on not to try to enable interrupts as interrupt-
|
|
* -enabling mechanisms might not be set up yet.
|
|
*/
|
|
if(ie){
|
|
if(ctlr->iena == 0 && !ctlr->poll){
|
|
ctlr->vector = intrenable(ctlr->irq, i8250interrupt, uart, ctlr->tbdf, uart->name);
|
|
ctlr->iena = 1;
|
|
}
|
|
ctlr->sticky[Ier] = Ethre|Erda;
|
|
ctlr->sticky[Mcr] |= Ie;
|
|
}
|
|
else{
|
|
ctlr->sticky[Ier] = 0;
|
|
ctlr->sticky[Mcr] = 0;
|
|
}
|
|
csr8w(ctlr, Ier, ctlr->sticky[Ier]);
|
|
csr8w(ctlr, Mcr, ctlr->sticky[Mcr]);
|
|
|
|
(*uart->phys->dtr)(uart, 1);
|
|
(*uart->phys->rts)(uart, 1);
|
|
|
|
/*
|
|
* During startup, the i8259 interrupt controller is reset.
|
|
* This may result in a lost interrupt from the i8250 uart.
|
|
* The i8250 thinks the interrupt is still outstanding and does not
|
|
* generate any further interrupts. The workaround is to call the
|
|
* interrupt handler to clear any pending interrupt events.
|
|
* Note: this must be done after setting Ier.
|
|
*/
|
|
if(ie)
|
|
i8250interrupt(nil, uart);
|
|
}
|
|
|
|
void*
|
|
i8250alloc(int io, int irq, int tbdf)
|
|
{
|
|
Ctlr *ctlr;
|
|
|
|
if((ctlr = jehanne_malloc(sizeof(Ctlr))) != nil){
|
|
ctlr->io = io;
|
|
ctlr->irq = irq;
|
|
ctlr->tbdf = tbdf;
|
|
}
|
|
|
|
return ctlr;
|
|
}
|
|
|
|
static Uart*
|
|
i8250pnp(void)
|
|
{
|
|
int i;
|
|
Ctlr *ctlr;
|
|
Uart *head, *uart;
|
|
|
|
head = i8250uart;
|
|
for(i = 0; i < nelem(i8250uart); i++){
|
|
/*
|
|
* Does it exist?
|
|
* Should be able to write/read the Scratch Pad
|
|
* and reserve the I/O space.
|
|
*/
|
|
uart = &i8250uart[i];
|
|
ctlr = uart->regs;
|
|
csr8o(ctlr, Scr, 0x55);
|
|
if(csr8r(ctlr, Scr) == 0x55)
|
|
continue;
|
|
if(ioalloc(ctlr->io, 8, 0, uart->name) < 0)
|
|
continue;
|
|
if(uart == head)
|
|
head = uart->next;
|
|
else
|
|
(uart-1)->next = uart->next;
|
|
}
|
|
|
|
return head;
|
|
}
|
|
|
|
static int
|
|
i8250getc(Uart* uart)
|
|
{
|
|
Ctlr *ctlr;
|
|
|
|
ctlr = uart->regs;
|
|
while(!(csr8r(ctlr, Lsr) & Dr))
|
|
delay(1);
|
|
return csr8r(ctlr, Rbr);
|
|
}
|
|
|
|
static void
|
|
i8250putc(Uart* uart, int c)
|
|
{
|
|
int i;
|
|
Ctlr *ctlr;
|
|
|
|
ctlr = uart->regs;
|
|
for(i = 0; !(csr8r(ctlr, Lsr) & Thre) && i < 128; i++)
|
|
delay(1);
|
|
csr8o(ctlr, Thr, c);
|
|
for(i = 0; !(csr8r(ctlr, Lsr) & Thre) && i < 128; i++)
|
|
delay(1);
|
|
}
|
|
|
|
PhysUart i8250physuart = {
|
|
.name = "i8250",
|
|
.pnp = i8250pnp,
|
|
.enable = i8250enable,
|
|
.disable = i8250disable,
|
|
.kick = i8250kick,
|
|
.dobreak = i8250break,
|
|
.baud = i8250baud,
|
|
.bits = i8250bits,
|
|
.stop = i8250stop,
|
|
.parity = i8250parity,
|
|
.modemctl = i8250modemctl,
|
|
.rts = i8250rts,
|
|
.dtr = i8250dtr,
|
|
.status = i8250status,
|
|
.fifo = i8250fifo,
|
|
.getc = i8250getc,
|
|
.putc = i8250putc,
|
|
};
|
|
|
|
void
|
|
i8250console(void)
|
|
{
|
|
Uart *uart;
|
|
int n;
|
|
char *cmd, *p;
|
|
|
|
if((p = getconf("console")) == nil)
|
|
return;
|
|
n = strtoul(p, &cmd, 0);
|
|
if(p == cmd || n < 0 || n >= nelem(i8250uart))
|
|
return;
|
|
uart = &i8250uart[n];
|
|
|
|
(*uart->phys->enable)(uart, 0);
|
|
uartctl(uart, "b9600 l8 pn s1");
|
|
if(*cmd != '\0')
|
|
uartctl(uart, cmd);
|
|
|
|
consuart = uart;
|
|
uart->console = 1;
|
|
}
|