1568 lines
33 KiB
C
1568 lines
33 KiB
C
/* Copyright (C) Charles Forsyth
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* See /doc/license/NOTICE.Plan9-9k.txt for details about the licensing.
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*/
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/* Portions of this file are Copyright (C) 9front's team.
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* See /doc/license/9front-mit for details about the licensing.
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* See http://code.9front.org/hg/plan9front/ for a list of authors.
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*/
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/*
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* PCI support code.
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* Needs a massive rewrite.
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "../port/error.h"
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enum
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{ /* configuration mechanism #1 */
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PciADDR = 0xCF8, /* CONFIG_ADDRESS */
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PciDATA = 0xCFC, /* CONFIG_DATA */
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/* configuration mechanism #2 */
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PciCSE = 0xCF8, /* configuration space enable */
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PciFORWARD = 0xCFA, /* which bus */
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MaxFNO = 7,
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MaxUBN = 255,
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};
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enum
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{ /* command register */
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IOen = (1<<0),
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MEMen = (1<<1),
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MASen = (1<<2),
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MemWrInv = (1<<4),
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PErrEn = (1<<6),
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SErrEn = (1<<8),
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};
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static Lock pcicfglock;
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static Lock pcicfginitlock;
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static int pcicfgmode = -1;
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static int pcimaxbno = 255;
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static int pcimaxdno;
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static Pcidev* pciroot;
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static Pcidev* pcilist;
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static Pcidev* pcitail;
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static int nobios, nopcirouting;
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static BIOS32si* pcibiossi;
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static int pcicfgrw8raw(int, int, int, int);
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static int pcicfgrw16raw(int, int, int, int);
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static int pcicfgrw32raw(int, int, int, int);
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static int (*pcicfgrw8)(int, int, int, int) = pcicfgrw8raw;
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static int (*pcicfgrw16)(int, int, int, int) = pcicfgrw16raw;
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static int (*pcicfgrw32)(int, int, int, int) = pcicfgrw32raw;
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static char* bustypes[] = {
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"CBUSI",
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"CBUSII",
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"EISA",
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"FUTURE",
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"INTERN",
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"ISA",
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"MBI",
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"MBII",
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"MCA",
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"MPI",
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"MPSA",
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"NUBUS",
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"PCI",
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"PCMCIA",
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"TC",
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"VL",
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"VME",
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"XPRESS",
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};
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static int
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tbdffmt(Fmt* fmt)
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{
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char *p;
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int l, r;
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uint32_t type, tbdf;
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if((p = jehanne_malloc(READSTR)) == nil)
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return jehanne_fmtstrcpy(fmt, "(tbdfconv)");
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switch(fmt->r){
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case 'T':
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tbdf = va_arg(fmt->args, int);
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if(tbdf == BUSUNKNOWN)
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jehanne_snprint(p, READSTR, "unknown");
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else{
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type = BUSTYPE(tbdf);
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if(type < nelem(bustypes))
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l = jehanne_snprint(p, READSTR, bustypes[type]);
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else
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l = jehanne_snprint(p, READSTR, "%d", type);
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jehanne_snprint(p+l, READSTR-l, ".%d.%d.%d",
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BUSBNO(tbdf), BUSDNO(tbdf), BUSFNO(tbdf));
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}
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break;
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default:
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jehanne_snprint(p, READSTR, "(tbdfconv)");
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break;
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}
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r = jehanne_fmtstrcpy(fmt, p);
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jehanne_free(p);
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return r;
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}
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uint32_t
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pcibarsize(Pcidev *p, int rno)
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{
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uint32_t v, size;
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v = pcicfgrw32(p->tbdf, rno, 0, 1);
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pcicfgrw32(p->tbdf, rno, 0xFFFFFFF0, 0);
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size = pcicfgrw32(p->tbdf, rno, 0, 1);
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if(v & 1)
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size |= 0xFFFF0000;
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pcicfgrw32(p->tbdf, rno, v, 0);
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return -(size & ~0x0F);
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}
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static int
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pcisizcmp(void *a, void *b)
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{
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Pcisiz *aa, *bb;
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aa = a;
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bb = b;
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return aa->siz - bb->siz;
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}
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static uint32_t
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pcimask(uint32_t v)
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{
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uint32_t m;
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m = BI2BY*sizeof(v);
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for(m = 1<<(m-1); m != 0; m >>= 1) {
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if(m & v)
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break;
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}
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m--;
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if((v & m) == 0)
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return v;
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v |= m;
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return v+1;
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}
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static void
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pcibusmap(Pcidev *root, uint32_t *pmema, uint32_t *pioa, int wrreg)
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{
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Pcidev *p;
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int ntb, i, size, rno, hole;
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uint32_t v, mema, ioa, sioa, smema, base, limit;
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Pcisiz *table, *tptr, *mtb, *itb;
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if(!nobios)
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return;
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ioa = *pioa;
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mema = *pmema;
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DBG("pcibusmap wr=%d %T mem=%luX io=%luX\n",
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wrreg, root->tbdf, mema, ioa);
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ntb = 0;
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for(p = root; p != nil; p = p->link)
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ntb++;
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ntb *= (PciCIS-PciBAR0)/4;
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table = jehanne_malloc(2*ntb*sizeof(Pcisiz));
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if(table == nil)
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panic("pcibusmap: can't allocate memory");
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itb = table;
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mtb = table+ntb;
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/*
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* Build a table of sizes
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*/
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for(p = root; p != nil; p = p->link) {
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if(p->ccrb == 0x06) {
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if(p->ccru != 0x04 || p->bridge == nil) {
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DBG("pci: ignored bridge %T\n", p->tbdf);
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continue;
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}
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sioa = ioa;
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smema = mema;
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pcibusmap(p->bridge, &smema, &sioa, 0);
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hole = pcimask(smema-mema);
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if(hole < (1<<20))
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hole = 1<<20;
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p->mema.size = hole;
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hole = pcimask(sioa-ioa);
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if(hole < (1<<12))
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hole = 1<<12;
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p->ioa.size = hole;
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itb->dev = p;
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itb->bar = -1;
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itb->siz = p->ioa.size;
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itb++;
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mtb->dev = p;
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mtb->bar = -1;
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mtb->siz = p->mema.size;
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mtb++;
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continue;
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}
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for(i = 0; i <= 5; i++) {
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rno = PciBAR0 + i*4;
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v = pcicfgrw32(p->tbdf, rno, 0, 1);
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size = pcibarsize(p, rno);
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if(size == 0)
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continue;
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p->mem[i].size = size;
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if(v & 1) {
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itb->dev = p;
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itb->bar = i;
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itb->siz = size;
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itb++;
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}
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else {
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mtb->dev = p;
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mtb->bar = i;
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mtb->siz = size;
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mtb++;
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if((v & 7) == 4)
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i++;
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}
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}
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}
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/*
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* Sort both tables IO smallest first, Memory largest
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*/
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jehanne_qsort(table, itb-table, sizeof(Pcisiz), pcisizcmp);
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tptr = table+ntb;
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jehanne_qsort(tptr, mtb-tptr, sizeof(Pcisiz), pcisizcmp);
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/*
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* Allocate IO address space on this bus
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*/
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for(tptr = table; tptr < itb; tptr++) {
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hole = tptr->siz;
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if(tptr->bar == -1)
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hole = 1<<12;
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ioa = (ioa+hole-1) & ~(hole-1);
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p = tptr->dev;
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if(tptr->bar == -1)
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p->ioa.bar = ioa;
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else {
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p->pcr |= IOen;
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p->mem[tptr->bar].bar = ioa|1;
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if(wrreg)
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pcicfgrw32(p->tbdf, PciBAR0+(tptr->bar*4), ioa|1, 0);
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}
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ioa += tptr->siz;
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}
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/*
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* Allocate Memory address space on this bus
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*/
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for(tptr = table+ntb; tptr < mtb; tptr++) {
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hole = tptr->siz;
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if(tptr->bar == -1)
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hole = 1<<20;
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mema = (mema+hole-1) & ~(hole-1);
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p = tptr->dev;
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if(tptr->bar == -1)
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p->mema.bar = mema;
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else {
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p->pcr |= MEMen;
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p->mem[tptr->bar].bar = mema;
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if(wrreg)
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pcicfgrw32(p->tbdf, PciBAR0+(tptr->bar*4), mema, 0);
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}
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mema += tptr->siz;
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}
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*pmema = mema;
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*pioa = ioa;
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jehanne_free(table);
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if(wrreg == 0)
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return;
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/*
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* Finally set all the bridge addresses & registers
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*/
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for(p = root; p != nil; p = p->link) {
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if(p->bridge == nil) {
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pcicfgrw8(p->tbdf, PciLTR, 64, 0);
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p->pcr |= MASen;
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pcicfgrw16(p->tbdf, PciPCR, p->pcr, 0);
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continue;
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}
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base = p->ioa.bar;
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limit = base+p->ioa.size-1;
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v = pcicfgrw32(p->tbdf, PciIBR, 0, 1);
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v = (v&0xFFFF0000)|(limit & 0xF000)|((base & 0xF000)>>8);
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pcicfgrw32(p->tbdf, PciIBR, v, 0);
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v = (limit & 0xFFFF0000)|(base>>16);
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pcicfgrw32(p->tbdf, PciIUBR, v, 0);
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base = p->mema.bar;
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limit = base+p->mema.size-1;
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v = (limit & 0xFFF00000)|((base & 0xFFF00000)>>16);
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pcicfgrw32(p->tbdf, PciMBR, v, 0);
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/*
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* Disable memory prefetch
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*/
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pcicfgrw32(p->tbdf, PciPMBR, 0x0000FFFF, 0);
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pcicfgrw8(p->tbdf, PciLTR, 64, 0);
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/*
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* Enable the bridge
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*/
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p->pcr |= IOen|MEMen|MASen;
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pcicfgrw32(p->tbdf, PciPCR, 0xFFFF0000|p->pcr , 0);
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sioa = p->ioa.bar;
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smema = p->mema.bar;
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pcibusmap(p->bridge, &smema, &sioa, 1);
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}
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}
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static int
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pcilscan(int bno, Pcidev** list, Pcidev *parent)
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{
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Pcidev *p, *head, *tail;
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int dno, fno, i, hdt, l, maxfno, maxubn, rno, sbn, tbdf, ubn;
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maxubn = bno;
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head = nil;
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tail = nil;
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for(dno = 0; dno <= pcimaxdno; dno++){
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maxfno = 0;
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for(fno = 0; fno <= maxfno; fno++){
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/*
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* For this possible device, form the
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* bus+device+function triplet needed to address it
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* and try to read the vendor and device ID.
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* If successful, allocate a device struct and
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* start to fill it in with some useful information
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* from the device's configuration space.
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*/
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tbdf = MKBUS(BusPCI, bno, dno, fno);
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l = pcicfgrw32(tbdf, PciVID, 0, 1);
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if(l == 0xFFFFFFFF || l == 0)
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continue;
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p = jehanne_malloc(sizeof(*p));
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if(p == nil)
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panic("pcilscan: can't allocate memory");
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p->tbdf = tbdf;
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p->vid = l;
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p->did = l>>16;
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if(pcilist != nil)
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pcitail->list = p;
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else
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pcilist = p;
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pcitail = p;
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p->pcr = pcicfgr16(p, PciPCR);
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p->rid = pcicfgr8(p, PciRID);
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p->ccrp = pcicfgr8(p, PciCCRp);
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p->ccru = pcicfgr8(p, PciCCRu);
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p->ccrb = pcicfgr8(p, PciCCRb);
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p->cls = pcicfgr8(p, PciCLS);
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p->ltr = pcicfgr8(p, PciLTR);
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p->intl = pcicfgr8(p, PciINTL);
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/*
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* If the device is a multi-function device adjust the
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* loop count so all possible functions are checked.
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*/
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hdt = pcicfgr8(p, PciHDT);
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if(hdt & 0x80)
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maxfno = MaxFNO;
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/*
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* If appropriate, read the base address registers
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* and work out the sizes.
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*/
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switch(p->ccrb) {
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case 0x00: /* prehistoric */
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case 0x01: /* mass storage controller */
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case 0x02: /* network controller */
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case 0x03: /* display controller */
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case 0x04: /* multimedia device */
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case 0x07: /* simple comm. controllers */
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case 0x08: /* base system peripherals */
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case 0x09: /* input devices */
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case 0x0A: /* docking stations */
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case 0x0B: /* processors */
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case 0x0C: /* serial bus controllers */
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case 0x0D: /* wireless controllers */
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case 0x0E: /* intelligent I/O controllers */
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case 0x0F: /* sattelite communication controllers */
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case 0x10: /* encryption/decryption controllers */
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case 0x11: /* signal processing controllers */
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if((hdt & 0x7F) != 0)
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break;
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rno = PciBAR0;
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for(i = 0; i <= 5; i++) {
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p->mem[i].bar = pcicfgr32(p, rno);
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p->mem[i].size = pcibarsize(p, rno);
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if((p->mem[i].bar & 7) == 4 && i < 5){
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uint32_t hi;
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rno += 4;
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hi = pcicfgr32(p, rno);
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if(hi != 0){
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jehanne_print("ignoring 64-bit bar %d: %llux %d from %T\n",
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i, (uint64_t)hi<<32 | p->mem[i].bar, p->mem[i].size, p->tbdf);
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p->mem[i].bar = 0;
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p->mem[i].size = 0;
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}
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i++;
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}
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rno += 4;
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}
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break;
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case 0x05: /* memory controller */
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case 0x06: /* bridge device */
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default:
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break;
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}
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p->parent = parent;
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if(head != nil)
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tail->link = p;
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else
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head = p;
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tail = p;
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}
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}
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|
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*list = head;
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for(p = head; p != nil; p = p->link){
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/*
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* Find PCI-PCI bridges and recursively descend the tree.
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*/
|
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if(p->ccrb != 0x06 || p->ccru != 0x04)
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continue;
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|
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/*
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* If the secondary or subordinate bus number is not
|
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* initialised try to do what the PCI BIOS should have
|
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* done and fill in the numbers as the tree is descended.
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* On the way down the subordinate bus number is set to
|
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* the maximum as it's not known how many buses are behind
|
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* this one; the final value is set on the way back up.
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*/
|
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sbn = pcicfgr8(p, PciSBN);
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ubn = pcicfgr8(p, PciUBN);
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|
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if(sbn == 0 || ubn == 0 || nobios) {
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sbn = maxubn+1;
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/*
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* Make sure memory, I/O and master enables are
|
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* off, set the primary, secondary and subordinate
|
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* bus numbers and clear the secondary status before
|
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* attempting to scan the secondary bus.
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*
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* Initialisation of the bridge should be done here.
|
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*/
|
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pcicfgw32(p, PciPCR, 0xFFFF0000);
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l = (MaxUBN<<16)|(sbn<<8)|bno;
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pcicfgw32(p, PciPBN, l);
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pcicfgw16(p, PciSPSR, 0xFFFF);
|
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maxubn = pcilscan(sbn, &p->bridge, p);
|
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l = (maxubn<<16)|(sbn<<8)|bno;
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|
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pcicfgw32(p, PciPBN, l);
|
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}
|
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else {
|
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if(ubn > maxubn)
|
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maxubn = ubn;
|
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pcilscan(sbn, &p->bridge, p);
|
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}
|
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}
|
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|
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return maxubn;
|
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}
|
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|
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int
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pciscan(int bno, Pcidev **list)
|
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{
|
|
int ubn;
|
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|
|
lock(&pcicfginitlock);
|
|
ubn = pcilscan(bno, list, nil);
|
|
unlock(&pcicfginitlock);
|
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return ubn;
|
|
}
|
|
|
|
static uint8_t
|
|
pIIxget(Pcidev *router, uint8_t link)
|
|
{
|
|
uint8_t pirq;
|
|
|
|
/* link should be 0x60, 0x61, 0x62, 0x63 */
|
|
pirq = pcicfgr8(router, link);
|
|
return (pirq < 16)? pirq: 0;
|
|
}
|
|
|
|
static void
|
|
pIIxset(Pcidev *router, uint8_t link, uint8_t irq)
|
|
{
|
|
pcicfgw8(router, link, irq);
|
|
}
|
|
|
|
static uint8_t
|
|
viaget(Pcidev *router, uint8_t link)
|
|
{
|
|
uint8_t pirq;
|
|
|
|
/* link should be 1, 2, 3, 5 */
|
|
pirq = (link < 6)? pcicfgr8(router, 0x55 + (link>>1)): 0;
|
|
|
|
return (link & 1)? (pirq >> 4): (pirq & 15);
|
|
}
|
|
|
|
static void
|
|
viaset(Pcidev *router, uint8_t link, uint8_t irq)
|
|
{
|
|
uint8_t pirq;
|
|
|
|
pirq = pcicfgr8(router, 0x55 + (link >> 1));
|
|
pirq &= (link & 1)? 0x0f: 0xf0;
|
|
pirq |= (link & 1)? (irq << 4): (irq & 15);
|
|
pcicfgw8(router, 0x55 + (link>>1), pirq);
|
|
}
|
|
|
|
static uint8_t
|
|
optiget(Pcidev *router, uint8_t link)
|
|
{
|
|
uint8_t pirq = 0;
|
|
|
|
/* link should be 0x02, 0x12, 0x22, 0x32 */
|
|
if ((link & 0xcf) == 0x02)
|
|
pirq = pcicfgr8(router, 0xb8 + (link >> 5));
|
|
return (link & 0x10)? (pirq >> 4): (pirq & 15);
|
|
}
|
|
|
|
static void
|
|
optiset(Pcidev *router, uint8_t link, uint8_t irq)
|
|
{
|
|
uint8_t pirq;
|
|
|
|
pirq = pcicfgr8(router, 0xb8 + (link >> 5));
|
|
pirq &= (link & 0x10)? 0x0f : 0xf0;
|
|
pirq |= (link & 0x10)? (irq << 4): (irq & 15);
|
|
pcicfgw8(router, 0xb8 + (link >> 5), pirq);
|
|
}
|
|
|
|
static uint8_t
|
|
aliget(Pcidev *router, uint8_t link)
|
|
{
|
|
/* No, you're not dreaming */
|
|
static const uint8_t map[] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
|
|
uint8_t pirq;
|
|
|
|
/* link should be 0x01..0x08 */
|
|
pirq = pcicfgr8(router, 0x48 + ((link-1)>>1));
|
|
return (link & 1)? map[pirq&15]: map[pirq>>4];
|
|
}
|
|
|
|
static void
|
|
aliset(Pcidev *router, uint8_t link, uint8_t irq)
|
|
{
|
|
/* Inverse of map in aliget */
|
|
static const uint8_t map[] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
|
|
uint8_t pirq;
|
|
|
|
pirq = pcicfgr8(router, 0x48 + ((link-1)>>1));
|
|
pirq &= (link & 1)? 0x0f: 0xf0;
|
|
pirq |= (link & 1)? (map[irq] << 4): (map[irq] & 15);
|
|
pcicfgw8(router, 0x48 + ((link-1)>>1), pirq);
|
|
}
|
|
|
|
static uint8_t
|
|
cyrixget(Pcidev *router, uint8_t link)
|
|
{
|
|
uint8_t pirq;
|
|
|
|
/* link should be 1, 2, 3, 4 */
|
|
pirq = pcicfgr8(router, 0x5c + ((link-1)>>1));
|
|
return ((link & 1)? pirq >> 4: pirq & 15);
|
|
}
|
|
|
|
static void
|
|
cyrixset(Pcidev *router, uint8_t link, uint8_t irq)
|
|
{
|
|
uint8_t pirq;
|
|
|
|
pirq = pcicfgr8(router, 0x5c + (link>>1));
|
|
pirq &= (link & 1)? 0x0f: 0xf0;
|
|
pirq |= (link & 1)? (irq << 4): (irq & 15);
|
|
pcicfgw8(router, 0x5c + (link>>1), pirq);
|
|
}
|
|
|
|
typedef struct Bridge Bridge;
|
|
struct Bridge
|
|
{
|
|
uint16_t vid;
|
|
uint16_t did;
|
|
uint8_t (*get)(Pcidev *, uint8_t);
|
|
void (*set)(Pcidev *, uint8_t, uint8_t);
|
|
};
|
|
|
|
static Bridge southbridges[] = {
|
|
{ 0x8086, 0x122e, pIIxget, pIIxset }, /* Intel 82371FB */
|
|
{ 0x8086, 0x1234, pIIxget, pIIxset }, /* Intel 82371MX */
|
|
{ 0x8086, 0x7000, pIIxget, pIIxset }, /* Intel 82371SB */
|
|
{ 0x8086, 0x7110, pIIxget, pIIxset }, /* Intel 82371AB */
|
|
{ 0x8086, 0x7198, pIIxget, pIIxset }, /* Intel 82443MX (fn 1) */
|
|
{ 0x8086, 0x2410, pIIxget, pIIxset }, /* Intel 82801AA */
|
|
{ 0x8086, 0x2420, pIIxget, pIIxset }, /* Intel 82801AB */
|
|
{ 0x8086, 0x2440, pIIxget, pIIxset }, /* Intel 82801BA */
|
|
{ 0x8086, 0x2448, pIIxget, pIIxset }, /* Intel 82801BAM/CAM/DBM */
|
|
{ 0x8086, 0x244c, pIIxget, pIIxset }, /* Intel 82801BAM */
|
|
{ 0x8086, 0x244e, pIIxget, pIIxset }, /* Intel 82801 */
|
|
{ 0x8086, 0x2480, pIIxget, pIIxset }, /* Intel 82801CA */
|
|
{ 0x8086, 0x248c, pIIxget, pIIxset }, /* Intel 82801CAM */
|
|
{ 0x8086, 0x24c0, pIIxget, pIIxset }, /* Intel 82801DBL */
|
|
{ 0x8086, 0x24cc, pIIxget, pIIxset }, /* Intel 82801DBM */
|
|
{ 0x8086, 0x24d0, pIIxget, pIIxset }, /* Intel 82801EB */
|
|
{ 0x8086, 0x25a1, pIIxget, pIIxset }, /* Intel 6300ESB */
|
|
{ 0x8086, 0x2640, pIIxget, pIIxset }, /* Intel 82801FB */
|
|
{ 0x8086, 0x2641, pIIxget, pIIxset }, /* Intel 82801FBM */
|
|
{ 0x8086, 0x2670, pIIxget, pIIxset }, /* Intel 632xesb */
|
|
{ 0x8086, 0x27b8, pIIxget, pIIxset }, /* Intel 82801GB */
|
|
{ 0x8086, 0x27b9, pIIxget, pIIxset }, /* Intel 82801GBM */
|
|
{ 0x8086, 0x27bd, pIIxget, pIIxset }, /* Intel 82801GB/GR */
|
|
{ 0x8086, 0x3a16, pIIxget, pIIxset }, /* Intel 82801JIR */
|
|
{ 0x8086, 0x3a40, pIIxget, pIIxset }, /* Intel 82801JI */
|
|
{ 0x8086, 0x3a42, pIIxget, pIIxset }, /* Intel 82801JI */
|
|
{ 0x8086, 0x3a48, pIIxget, pIIxset }, /* Intel 82801JI */
|
|
{ 0x8086, 0x2916, pIIxget, pIIxset }, /* Intel 82801? */
|
|
{ 0x8086, 0x1c02, pIIxget, pIIxset }, /* Intel 6 Series/C200 */
|
|
{ 0x8086, 0x1e53, pIIxget, pIIxset }, /* Intel 7 Series/C216 */
|
|
{ 0x8086, 0x8c56, pIIxget, pIIxset }, /* Intel 8 Series/C226 */
|
|
{ 0x8086, 0x2810, pIIxget, pIIxset }, /* Intel 82801HB/HR (ich8/r) */
|
|
{ 0x8086, 0x2812, pIIxget, pIIxset }, /* Intel 82801HH (ich8dh) */
|
|
{ 0x8086, 0x2912, pIIxget, pIIxset }, /* Intel 82801ih ich9dh */
|
|
{ 0x8086, 0x2914, pIIxget, pIIxset }, /* Intel 82801io ich9do */
|
|
{ 0x8086, 0x2916, pIIxget, pIIxset }, /* Intel 82801ibr ich9r */
|
|
{ 0x8086, 0x2917, pIIxget, pIIxset }, /* Intel 82801iem ich9m-e */
|
|
{ 0x8086, 0x2918, pIIxget, pIIxset }, /* Intel 82801ib ich9 */
|
|
{ 0x8086, 0x2919, pIIxget, pIIxset }, /* Intel 82801? ich9m */
|
|
{ 0x8086, 0x3a16, pIIxget, pIIxset }, /* Intel 82801jir ich10r */
|
|
{ 0x8086, 0x3a18, pIIxget, pIIxset }, /* Intel 82801jib ich10 */
|
|
{ 0x8086, 0x3a40, pIIxget, pIIxset }, /* Intel 82801ji */
|
|
{ 0x8086, 0x3a42, pIIxget, pIIxset }, /* Intel 82801ji */
|
|
{ 0x8086, 0x3a48, pIIxget, pIIxset }, /* Intel 82801ji */
|
|
{ 0x8086, 0x3b06, pIIxget, pIIxset }, /* Intel 82801? ibex peak */
|
|
{ 0x8086, 0x3b14, pIIxget, pIIxset }, /* Intel 82801? 3420 */
|
|
{ 0x8086, 0x1c49, pIIxget, pIIxset }, /* Intel 82hm65 cougar point pch */
|
|
{ 0x8086, 0x1c4b, pIIxget, pIIxset }, /* Intel 82hm67 */
|
|
{ 0x8086, 0x1c4f, pIIxget, pIIxset }, /* Intel 82qm67 cougar point pch */
|
|
{ 0x8086, 0x1c52, pIIxget, pIIxset }, /* Intel 82q65 cougar point pch */
|
|
{ 0x8086, 0x1c54, pIIxget, pIIxset }, /* Intel 82q67 cougar point pch */
|
|
{ 0x8086, 0x1e55, pIIxget, pIIxset }, /* Intel QM77 panter point lpc */
|
|
|
|
{ 0x1106, 0x0586, viaget, viaset }, /* Viatech 82C586 */
|
|
{ 0x1106, 0x0596, viaget, viaset }, /* Viatech 82C596 */
|
|
{ 0x1106, 0x0686, viaget, viaset }, /* Viatech 82C686 */
|
|
{ 0x1106, 0x3177, viaget, viaset }, /* Viatech VT8235 */
|
|
{ 0x1106, 0x3227, viaget, viaset }, /* Viatech VT8237 */
|
|
{ 0x1106, 0x3287, viaget, viaset }, /* Viatech VT8251 */
|
|
{ 0x1106, 0x8410, viaget, viaset }, /* Viatech PV530 bridge */
|
|
{ 0x1045, 0xc700, optiget, optiset }, /* Opti 82C700 */
|
|
{ 0x10b9, 0x1533, aliget, aliset }, /* Al M1533 */
|
|
{ 0x1039, 0x0008, pIIxget, pIIxset }, /* SI 503 */
|
|
{ 0x1039, 0x0496, pIIxget, pIIxset }, /* SI 496 */
|
|
{ 0x1078, 0x0100, cyrixget, cyrixset }, /* Cyrix 5530 Legacy */
|
|
|
|
{ 0x1022, 0x746b, nil, nil }, /* AMD 8111 */
|
|
{ 0x10de, 0x00d1, nil, nil }, /* NVIDIA nForce 3 */
|
|
{ 0x10de, 0x00e0, nil, nil }, /* NVIDIA nForce 3 250 Series */
|
|
{ 0x10de, 0x00e1, nil, nil }, /* NVIDIA nForce 3 250 Series */
|
|
{ 0x1166, 0x0200, nil, nil }, /* ServerWorks ServerSet III LE */
|
|
{ 0x1002, 0x4377, nil, nil }, /* ATI Radeon Xpress 200M */
|
|
{ 0x1002, 0x4372, nil, nil }, /* ATI SB400 */
|
|
{ 0x1002, 0x9601, nil, nil }, /* AMD SB710 */
|
|
{ 0x1002, 0x438d, nil, nil }, /* AMD SB600 */
|
|
{ 0x1002, 0x439d, nil, nil }, /* AMD SB810 */
|
|
};
|
|
|
|
typedef struct Slot Slot;
|
|
struct Slot {
|
|
uint8_t bus; /* Pci bus number */
|
|
uint8_t dev; /* Pci device number */
|
|
uint8_t maps[12]; /* Avoid structs! Link and mask. */
|
|
uint8_t slot; /* Add-in/built-in slot */
|
|
uint8_t reserved;
|
|
};
|
|
|
|
typedef struct Router Router;
|
|
struct Router {
|
|
uint8_t signature[4]; /* Routing table signature */
|
|
uint8_t version[2]; /* Version number */
|
|
uint8_t size[2]; /* Total table size */
|
|
uint8_t bus; /* Interrupt router bus number */
|
|
uint8_t devfn; /* Router's devfunc */
|
|
uint8_t pciirqs[2]; /* Exclusive PCI irqs */
|
|
uint8_t compat[4]; /* Compatible PCI interrupt router */
|
|
uint8_t miniport[4]; /* Miniport data */
|
|
uint8_t reserved[11];
|
|
uint8_t checksum;
|
|
};
|
|
|
|
static uint16_t pciirqs; /* Exclusive PCI irqs */
|
|
static Bridge *southbridge; /* Which southbridge to use. */
|
|
|
|
static void
|
|
pcirouting(void)
|
|
{
|
|
Slot *e;
|
|
Router *r;
|
|
int i, size, tbdf;
|
|
Pcidev *sbpci, *pci;
|
|
uint8_t *p, pin, irq, link, *map;
|
|
|
|
if((p = sigsearch("$PIR")) == nil)
|
|
return;
|
|
|
|
r = (Router*)p;
|
|
size = (r->size[1] << 8)|r->size[0];
|
|
if(size < sizeof(Router) || checksum(r, size))
|
|
return;
|
|
|
|
if(0) jehanne_print("PCI interrupt routing table version %d.%d at %p\n",
|
|
r->version[0], r->version[1], r);
|
|
|
|
tbdf = MKBUS(BusPCI, r->bus, (r->devfn>>3)&0x1f, r->devfn&7);
|
|
sbpci = pcimatchtbdf(tbdf);
|
|
if(sbpci == nil) {
|
|
jehanne_print("pcirouting: Cannot find south bridge %T\n", tbdf);
|
|
return;
|
|
}
|
|
|
|
for(i = 0; i < nelem(southbridges); i++)
|
|
if(sbpci->vid == southbridges[i].vid && sbpci->did == southbridges[i].did)
|
|
break;
|
|
|
|
if(i == nelem(southbridges)) {
|
|
jehanne_print("pcirouting: ignoring south bridge %T %.4uX/%.4uX\n", tbdf, sbpci->vid, sbpci->did);
|
|
return;
|
|
}
|
|
southbridge = &southbridges[i];
|
|
if(southbridge->get == nil)
|
|
return;
|
|
|
|
pciirqs = (r->pciirqs[1] << 8)|r->pciirqs[0];
|
|
for(e = (Slot *)&r[1]; (uint8_t *)e < p + size; e++) {
|
|
if(0) {
|
|
jehanne_print("%.2uX/%.2uX %.2uX: ", e->bus, e->dev, e->slot);
|
|
for (i = 0; i < 4; i++) {
|
|
map = &e->maps[i * 3];
|
|
jehanne_print("[%d] %.2uX %.4uX ", i, map[0], (map[2] << 8)|map[1]);
|
|
}
|
|
jehanne_print("\n");
|
|
}
|
|
for(i = 0; i < 8; i++) {
|
|
tbdf = MKBUS(BusPCI, e->bus, (e->dev>>3)&0x1f, i);
|
|
pci = pcimatchtbdf(tbdf);
|
|
if(pci == nil)
|
|
continue;
|
|
pin = pcicfgr8(pci, PciINTP);
|
|
if(pin == 0 || pin == 0xff)
|
|
continue;
|
|
|
|
map = &e->maps[((pin - 1) % 4) * 3];
|
|
link = map[0];
|
|
irq = southbridge->get(sbpci, link);
|
|
if(irq == pci->intl)
|
|
continue;
|
|
if(irq == 0 || (irq & 0x80) != 0){
|
|
irq = pci->intl;
|
|
if(irq == 0 || irq == 0xff)
|
|
continue;
|
|
if(southbridge->set == nil)
|
|
continue;
|
|
southbridge->set(sbpci, link, irq);
|
|
}
|
|
jehanne_print("pcirouting: %T at pin %d link %.2uX irq %d -> %d\n", tbdf, pin, link, pci->intl, irq);
|
|
pcicfgw8(pci, PciINTL, irq);
|
|
pci->intl = irq;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void pcireservemem(void);
|
|
|
|
static int
|
|
pcicfgrw8bios(int tbdf, int rno, int data, int read)
|
|
{
|
|
BIOS32ci ci;
|
|
|
|
if(pcibiossi == nil)
|
|
return -1;
|
|
|
|
jehanne_memset(&ci, 0, sizeof(BIOS32ci));
|
|
ci.ebx = (BUSBNO(tbdf)<<8)|(BUSDNO(tbdf)<<3)|BUSFNO(tbdf);
|
|
ci.edi = rno;
|
|
if(read){
|
|
ci.eax = 0xB108;
|
|
if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
|
|
return ci.ecx & 0xFF;
|
|
}
|
|
else{
|
|
ci.eax = 0xB10B;
|
|
ci.ecx = data & 0xFF;
|
|
if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
|
|
return 0;
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
static int
|
|
pcicfgrw16bios(int tbdf, int rno, int data, int read)
|
|
{
|
|
BIOS32ci ci;
|
|
|
|
if(pcibiossi == nil)
|
|
return -1;
|
|
|
|
jehanne_memset(&ci, 0, sizeof(BIOS32ci));
|
|
ci.ebx = (BUSBNO(tbdf)<<8)|(BUSDNO(tbdf)<<3)|BUSFNO(tbdf);
|
|
ci.edi = rno;
|
|
if(read){
|
|
ci.eax = 0xB109;
|
|
if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
|
|
return ci.ecx & 0xFFFF;
|
|
}
|
|
else{
|
|
ci.eax = 0xB10C;
|
|
ci.ecx = data & 0xFFFF;
|
|
if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
|
|
return 0;
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
static int
|
|
pcicfgrw32bios(int tbdf, int rno, int data, int read)
|
|
{
|
|
BIOS32ci ci;
|
|
|
|
if(pcibiossi == nil)
|
|
return -1;
|
|
|
|
jehanne_memset(&ci, 0, sizeof(BIOS32ci));
|
|
ci.ebx = (BUSBNO(tbdf)<<8)|(BUSDNO(tbdf)<<3)|BUSFNO(tbdf);
|
|
ci.edi = rno;
|
|
if(read){
|
|
ci.eax = 0xB10A;
|
|
if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
|
|
return ci.ecx;
|
|
}
|
|
else{
|
|
ci.eax = 0xB10D;
|
|
ci.ecx = data;
|
|
if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
|
|
return 0;
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
static BIOS32si*
|
|
pcibiosinit(void)
|
|
{
|
|
BIOS32ci ci;
|
|
BIOS32si *si;
|
|
|
|
if((si = bios32open("$PCI")) == nil)
|
|
return nil;
|
|
|
|
jehanne_memset(&ci, 0, sizeof(BIOS32ci));
|
|
ci.eax = 0xB101;
|
|
if(bios32ci(si, &ci) || ci.edx != ((' '<<24)|('I'<<16)|('C'<<8)|'P')){
|
|
jehanne_free(si);
|
|
return nil;
|
|
}
|
|
if(ci.eax & 0x01)
|
|
pcimaxdno = 31;
|
|
else
|
|
pcimaxdno = 15;
|
|
pcimaxbno = ci.ecx & 0xff;
|
|
|
|
return si;
|
|
}
|
|
|
|
void
|
|
pcibussize(Pcidev *root, uint32_t *msize, uint32_t *iosize)
|
|
{
|
|
*msize = 0;
|
|
*iosize = 0;
|
|
pcibusmap(root, msize, iosize, 0);
|
|
}
|
|
|
|
static void
|
|
pcicfginit(void)
|
|
{
|
|
char *p;
|
|
Pcidev **list;
|
|
uint32_t mema, ioa;
|
|
int bno, n, pcibios;
|
|
|
|
lock(&pcicfginitlock);
|
|
if(pcicfgmode != -1)
|
|
goto out;
|
|
|
|
pcibios = 0;
|
|
if(getconf("*nobios"))
|
|
nobios = 1;
|
|
else if(getconf("*pcibios"))
|
|
pcibios = 1;
|
|
if(getconf("*nopcirouting"))
|
|
nopcirouting = 1;
|
|
|
|
/*
|
|
* Try to determine which PCI configuration mode is implemented.
|
|
* Mode2 uses a byte at 0xCF8 and another at 0xCFA; Mode1 uses
|
|
* a DWORD at 0xCF8 and another at 0xCFC and will pass through
|
|
* any non-DWORD accesses as normal I/O cycles. There shouldn't be
|
|
* a device behind these addresses so if Mode1 accesses fail try
|
|
* for Mode2 (Mode2 is deprecated).
|
|
*/
|
|
if(!pcibios){
|
|
/*
|
|
* Bits [30:24] of PciADDR must be 0,
|
|
* according to the spec.
|
|
*/
|
|
n = inl(PciADDR);
|
|
if(!(n & 0x7F000000)){
|
|
outl(PciADDR, 0x80000000);
|
|
outb(PciADDR+3, 0);
|
|
if(inl(PciADDR) & 0x80000000){
|
|
pcicfgmode = 1;
|
|
pcimaxdno = 31;
|
|
}
|
|
}
|
|
outl(PciADDR, n);
|
|
|
|
if(pcicfgmode < 0){
|
|
/*
|
|
* The 'key' part of PciCSE should be 0.
|
|
*/
|
|
n = inb(PciCSE);
|
|
if(!(n & 0xF0)){
|
|
outb(PciCSE, 0x0E);
|
|
if(inb(PciCSE) == 0x0E){
|
|
pcicfgmode = 2;
|
|
pcimaxdno = 15;
|
|
}
|
|
}
|
|
outb(PciCSE, n);
|
|
}
|
|
}
|
|
|
|
if(pcicfgmode < 0 || pcibios) {
|
|
if((pcibiossi = pcibiosinit()) == nil)
|
|
goto out;
|
|
pcicfgrw8 = pcicfgrw8bios;
|
|
pcicfgrw16 = pcicfgrw16bios;
|
|
pcicfgrw32 = pcicfgrw32bios;
|
|
pcicfgmode = 3;
|
|
}
|
|
|
|
jehanne_fmtinstall('T', tbdffmt);
|
|
|
|
if(p = getconf("*pcimaxbno"))
|
|
pcimaxbno = jehanne_strtoul(p, 0, 0);
|
|
if(p = getconf("*pcimaxdno")){
|
|
n = jehanne_strtoul(p, 0, 0);
|
|
if(n < pcimaxdno)
|
|
pcimaxdno = n;
|
|
}
|
|
|
|
list = &pciroot;
|
|
for(bno = 0; bno <= pcimaxbno; bno++) {
|
|
int sbno = bno;
|
|
bno = pcilscan(bno, list, nil);
|
|
|
|
while(*list)
|
|
list = &(*list)->link;
|
|
|
|
if (sbno == 0) {
|
|
Pcidev *pci;
|
|
|
|
/*
|
|
* If we have found a PCI-to-Cardbus bridge, make sure
|
|
* it has no valid mappings anymore.
|
|
*/
|
|
for(pci = pciroot; pci != nil; pci = pci->link){
|
|
if (pci->ccrb == 6 && pci->ccru == 7) {
|
|
uint16_t bcr;
|
|
|
|
/* reset the cardbus */
|
|
bcr = pcicfgr16(pci, PciBCR);
|
|
pcicfgw16(pci, PciBCR, 0x40 | bcr);
|
|
delay(50);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
if(pciroot == nil)
|
|
goto out;
|
|
|
|
if(nobios) {
|
|
/*
|
|
* Work out how big the top bus is
|
|
*/
|
|
pcibussize(pciroot, &mema, &ioa);
|
|
|
|
/*
|
|
* Align the windows and map it
|
|
*/
|
|
ioa = 0x1000;
|
|
mema = 0x90000000;
|
|
|
|
DBG("Mask sizes: mem=%lux io=%lux\n", mema, ioa);
|
|
|
|
pcibusmap(pciroot, &mema, &ioa, 1);
|
|
DBG("Sizes2: mem=%lux io=%lux\n", mema, ioa);
|
|
|
|
goto out;
|
|
}
|
|
|
|
if(!nopcirouting)
|
|
pcirouting();
|
|
|
|
out:
|
|
pcireservemem();
|
|
unlock(&pcicfginitlock);
|
|
|
|
if(getconf("*pcihinv"))
|
|
pcihinv(nil);
|
|
}
|
|
|
|
static void
|
|
pcireservemem(void)
|
|
{
|
|
int i;
|
|
Pcidev *p;
|
|
|
|
/*
|
|
* mark all the physical address space claimed by pci devices
|
|
* as in use, so that upaalloc doesn't give it out.
|
|
*/
|
|
for(p=pciroot; p; p=p->list)
|
|
for(i=0; i<nelem(p->mem); i++)
|
|
if(p->mem[i].bar && (p->mem[i].bar&1) == 0)
|
|
memreserve(p->mem[i].bar&~0x0F, p->mem[i].size);
|
|
}
|
|
|
|
static int
|
|
pcicfgrw8raw(int tbdf, int rno, int data, int read)
|
|
{
|
|
int o, type, x;
|
|
|
|
if(pcicfgmode == -1)
|
|
pcicfginit();
|
|
|
|
if(BUSBNO(tbdf))
|
|
type = 0x01;
|
|
else
|
|
type = 0x00;
|
|
x = -1;
|
|
if(BUSDNO(tbdf) > pcimaxdno)
|
|
return x;
|
|
|
|
lock(&pcicfglock);
|
|
switch(pcicfgmode){
|
|
|
|
case 1:
|
|
o = rno & 0x03;
|
|
rno &= ~0x03;
|
|
outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
|
|
if(read)
|
|
x = inb(PciDATA+o);
|
|
else
|
|
outb(PciDATA+o, data);
|
|
outl(PciADDR, 0);
|
|
break;
|
|
|
|
case 2:
|
|
outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
|
|
outb(PciFORWARD, BUSBNO(tbdf));
|
|
if(read)
|
|
x = inb((0xC000|(BUSDNO(tbdf)<<8)) + rno);
|
|
else
|
|
outb((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
|
|
outb(PciCSE, 0);
|
|
break;
|
|
}
|
|
unlock(&pcicfglock);
|
|
|
|
return x;
|
|
}
|
|
|
|
int
|
|
pcicfgr8(Pcidev* pcidev, int rno)
|
|
{
|
|
return pcicfgrw8(pcidev->tbdf, rno, 0, 1);
|
|
}
|
|
|
|
void
|
|
pcicfgw8(Pcidev* pcidev, int rno, int data)
|
|
{
|
|
pcicfgrw8(pcidev->tbdf, rno, data, 0);
|
|
}
|
|
|
|
static int
|
|
pcicfgrw16raw(int tbdf, int rno, int data, int read)
|
|
{
|
|
int o, type, x;
|
|
|
|
if(pcicfgmode == -1)
|
|
pcicfginit();
|
|
|
|
if(BUSBNO(tbdf))
|
|
type = 0x01;
|
|
else
|
|
type = 0x00;
|
|
x = -1;
|
|
if(BUSDNO(tbdf) > pcimaxdno)
|
|
return x;
|
|
|
|
lock(&pcicfglock);
|
|
switch(pcicfgmode){
|
|
|
|
case 1:
|
|
o = rno & 0x02;
|
|
rno &= ~0x03;
|
|
outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
|
|
if(read)
|
|
x = ins(PciDATA+o);
|
|
else
|
|
outs(PciDATA+o, data);
|
|
outl(PciADDR, 0);
|
|
break;
|
|
|
|
case 2:
|
|
outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
|
|
outb(PciFORWARD, BUSBNO(tbdf));
|
|
if(read)
|
|
x = ins((0xC000|(BUSDNO(tbdf)<<8)) + rno);
|
|
else
|
|
outs((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
|
|
outb(PciCSE, 0);
|
|
break;
|
|
}
|
|
unlock(&pcicfglock);
|
|
|
|
return x;
|
|
}
|
|
|
|
int
|
|
pcicfgr16(Pcidev* pcidev, int rno)
|
|
{
|
|
return pcicfgrw16(pcidev->tbdf, rno, 0, 1);
|
|
}
|
|
|
|
void
|
|
pcicfgw16(Pcidev* pcidev, int rno, int data)
|
|
{
|
|
pcicfgrw16(pcidev->tbdf, rno, data, 0);
|
|
}
|
|
|
|
static int
|
|
pcicfgrw32raw(int tbdf, int rno, int data, int read)
|
|
{
|
|
int type, x;
|
|
|
|
if(pcicfgmode == -1)
|
|
pcicfginit();
|
|
|
|
if(BUSBNO(tbdf))
|
|
type = 0x01;
|
|
else
|
|
type = 0x00;
|
|
x = -1;
|
|
if(BUSDNO(tbdf) > pcimaxdno)
|
|
return x;
|
|
|
|
lock(&pcicfglock);
|
|
switch(pcicfgmode){
|
|
|
|
case 1:
|
|
rno &= ~0x03;
|
|
outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
|
|
if(read)
|
|
x = inl(PciDATA);
|
|
else
|
|
outl(PciDATA, data);
|
|
outl(PciADDR, 0);
|
|
break;
|
|
|
|
case 2:
|
|
outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
|
|
outb(PciFORWARD, BUSBNO(tbdf));
|
|
if(read)
|
|
x = inl((0xC000|(BUSDNO(tbdf)<<8)) + rno);
|
|
else
|
|
outl((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
|
|
outb(PciCSE, 0);
|
|
break;
|
|
}
|
|
unlock(&pcicfglock);
|
|
|
|
return x;
|
|
}
|
|
|
|
int
|
|
pcicfgr32(Pcidev* pcidev, int rno)
|
|
{
|
|
return pcicfgrw32(pcidev->tbdf, rno, 0, 1);
|
|
}
|
|
|
|
void
|
|
pcicfgw32(Pcidev* pcidev, int rno, int data)
|
|
{
|
|
pcicfgrw32(pcidev->tbdf, rno, data, 0);
|
|
}
|
|
|
|
Pcidev*
|
|
pcimatch(Pcidev* prev, int vid, int did)
|
|
{
|
|
if(pcicfgmode == -1)
|
|
pcicfginit();
|
|
|
|
if(prev == nil)
|
|
prev = pcilist;
|
|
else
|
|
prev = prev->list;
|
|
|
|
while(prev != nil){
|
|
if((vid == 0 || prev->vid == vid)
|
|
&& (did == 0 || prev->did == did))
|
|
break;
|
|
prev = prev->list;
|
|
}
|
|
return prev;
|
|
}
|
|
|
|
Pcidev*
|
|
pcimatchtbdf(int tbdf)
|
|
{
|
|
Pcidev *pcidev;
|
|
|
|
if(pcicfgmode == -1)
|
|
pcicfginit();
|
|
|
|
for(pcidev = pcilist; pcidev != nil; pcidev = pcidev->list) {
|
|
if(pcidev->tbdf == tbdf)
|
|
break;
|
|
}
|
|
return pcidev;
|
|
}
|
|
|
|
uint8_t
|
|
pciipin(Pcidev *pci, uint8_t pin)
|
|
{
|
|
if (pci == nil)
|
|
pci = pcilist;
|
|
|
|
while (pci) {
|
|
uint8_t intl;
|
|
|
|
if (pcicfgr8(pci, PciINTP) == pin && pci->intl != 0 && pci->intl != 0xff)
|
|
return pci->intl;
|
|
|
|
if (pci->bridge && (intl = pciipin(pci->bridge, pin)) != 0)
|
|
return intl;
|
|
|
|
pci = pci->list;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
pcilhinv(Pcidev* p)
|
|
{
|
|
int i;
|
|
Pcidev *t;
|
|
|
|
if(p == nil) {
|
|
p = pciroot;
|
|
jehanne_print("bus dev type vid did intl memory\n");
|
|
}
|
|
for(t = p; t != nil; t = t->link) {
|
|
jehanne_print("%d %2d/%d %.2ux %.2ux %.2ux %.4ux %.4ux %3d ",
|
|
BUSBNO(t->tbdf), BUSDNO(t->tbdf), BUSFNO(t->tbdf),
|
|
t->ccrb, t->ccru, t->ccrp, t->vid, t->did, t->intl);
|
|
|
|
for(i = 0; i < nelem(p->mem); i++) {
|
|
if(t->mem[i].size == 0)
|
|
continue;
|
|
jehanne_print("%d:%.8lux %d ", i,
|
|
t->mem[i].bar, t->mem[i].size);
|
|
}
|
|
if(t->ioa.bar || t->ioa.size)
|
|
jehanne_print("ioa:%.8lux %d ", t->ioa.bar, t->ioa.size);
|
|
if(t->mema.bar || t->mema.size)
|
|
jehanne_print("mema:%.8lux %d ", t->mema.bar, t->mema.size);
|
|
if(t->bridge)
|
|
jehanne_print("->%d", BUSBNO(t->bridge->tbdf));
|
|
jehanne_print("\n");
|
|
}
|
|
while(p != nil) {
|
|
if(p->bridge != nil)
|
|
pcilhinv(p->bridge);
|
|
p = p->link;
|
|
}
|
|
}
|
|
|
|
void
|
|
pcihinv(Pcidev* p)
|
|
{
|
|
if(pcicfgmode == -1)
|
|
pcicfginit();
|
|
lock(&pcicfginitlock);
|
|
pcilhinv(p);
|
|
unlock(&pcicfginitlock);
|
|
}
|
|
|
|
void
|
|
pcireset(void)
|
|
{
|
|
Pcidev *p;
|
|
|
|
if(pcicfgmode == -1)
|
|
pcicfginit();
|
|
|
|
for(p = pcilist; p != nil; p = p->list) {
|
|
/* don't mess with the bridges */
|
|
if(p->ccrb == 0x06)
|
|
continue;
|
|
pciclrbme(p);
|
|
}
|
|
}
|
|
|
|
void
|
|
pcisetioe(Pcidev* p)
|
|
{
|
|
p->pcr |= IOen;
|
|
pcicfgw16(p, PciPCR, p->pcr);
|
|
}
|
|
|
|
void
|
|
pciclrioe(Pcidev* p)
|
|
{
|
|
p->pcr &= ~IOen;
|
|
pcicfgw16(p, PciPCR, p->pcr);
|
|
}
|
|
|
|
void
|
|
pcisetbme(Pcidev* p)
|
|
{
|
|
p->pcr |= MASen;
|
|
pcicfgw16(p, PciPCR, p->pcr);
|
|
}
|
|
|
|
void
|
|
pciclrbme(Pcidev* p)
|
|
{
|
|
p->pcr &= ~MASen;
|
|
pcicfgw16(p, PciPCR, p->pcr);
|
|
}
|
|
|
|
void
|
|
pcisetmwi(Pcidev* p)
|
|
{
|
|
p->pcr |= MemWrInv;
|
|
pcicfgw16(p, PciPCR, p->pcr);
|
|
}
|
|
|
|
void
|
|
pciclrmwi(Pcidev* p)
|
|
{
|
|
p->pcr &= ~MemWrInv;
|
|
pcicfgw16(p, PciPCR, p->pcr);
|
|
}
|
|
|
|
static int
|
|
enumcaps(Pcidev *p, int (*fmatch)(Pcidev*, int, int, int), int arg)
|
|
{
|
|
int i, r, cap, off;
|
|
|
|
/* status register bit 4 has capabilities */
|
|
if((pcicfgr16(p, PciPSR) & 1<<4) == 0)
|
|
return -1;
|
|
switch(pcicfgr8(p, PciHDT) & 0x7F){
|
|
default:
|
|
return -1;
|
|
case 0: /* etc */
|
|
case 1: /* pci to pci bridge */
|
|
off = 0x34;
|
|
break;
|
|
case 2: /* cardbus bridge */
|
|
off = 0x14;
|
|
break;
|
|
}
|
|
for(i = 48; i--;){
|
|
off = pcicfgr8(p, off);
|
|
if(off < 0x40 || (off & 3))
|
|
break;
|
|
off &= ~3;
|
|
cap = pcicfgr8(p, off);
|
|
if(cap == 0xff)
|
|
break;
|
|
r = (*fmatch)(p, cap, off, arg);
|
|
if(r < 0)
|
|
break;
|
|
if(r == 0)
|
|
return off;
|
|
off++;
|
|
}
|
|
return -1;
|
|
}
|
|
|
|
static int
|
|
matchcap(Pcidev* _, int cap, int __, int arg)
|
|
{
|
|
return cap != arg;
|
|
}
|
|
|
|
static int
|
|
matchhtcap(Pcidev *p, int cap, int off, int arg)
|
|
{
|
|
int mask;
|
|
|
|
if(cap != PciCapHTC)
|
|
return 1;
|
|
if(arg == 0x00 || arg == 0x20)
|
|
mask = 0xE0;
|
|
else
|
|
mask = 0xF8;
|
|
cap = pcicfgr8(p, off+3);
|
|
return (cap & mask) != arg;
|
|
}
|
|
|
|
int
|
|
pcicap(Pcidev *p, int cap)
|
|
{
|
|
return enumcaps(p, matchcap, cap);
|
|
}
|
|
|
|
int
|
|
pcihtcap(Pcidev *p, int cap)
|
|
{
|
|
return enumcaps(p, matchhtcap, cap);
|
|
}
|
|
|
|
static int
|
|
pcigetpmrb(Pcidev* p)
|
|
{
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if(p->pmrb != 0)
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return p->pmrb;
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|
return p->pmrb = pcicap(p, PciCapPMG);
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|
}
|
|
|
|
int
|
|
pcigetpms(Pcidev* p)
|
|
{
|
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int pmcsr, ptr;
|
|
|
|
if((ptr = pcigetpmrb(p)) == -1)
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|
return -1;
|
|
|
|
/*
|
|
* Power Management Register Block:
|
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* offset 0: Capability ID
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|
* 1: next item pointer
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|
* 2: capabilities
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|
* 4: control/status
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|
* 6: bridge support extensions
|
|
* 7: data
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|
*/
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pmcsr = pcicfgr16(p, ptr+4);
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|
|
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return pmcsr & 0x0003;
|
|
}
|
|
|
|
int
|
|
pcisetpms(Pcidev* p, int state)
|
|
{
|
|
int ostate, pmc, pmcsr, ptr;
|
|
|
|
if((ptr = pcigetpmrb(p)) == -1)
|
|
return -1;
|
|
|
|
pmc = pcicfgr16(p, ptr+2);
|
|
pmcsr = pcicfgr16(p, ptr+4);
|
|
ostate = pmcsr & 0x0003;
|
|
pmcsr &= ~0x0003;
|
|
|
|
switch(state){
|
|
default:
|
|
return -1;
|
|
case 0:
|
|
break;
|
|
case 1:
|
|
if(!(pmc & 0x0200))
|
|
return -1;
|
|
break;
|
|
case 2:
|
|
if(!(pmc & 0x0400))
|
|
return -1;
|
|
break;
|
|
case 3:
|
|
break;
|
|
}
|
|
pmcsr |= state;
|
|
pcicfgw16(p, ptr+4, pmcsr);
|
|
|
|
return ostate;
|
|
}
|
|
|
|
int
|
|
pcinextcap(Pcidev *pci, int offset)
|
|
{
|
|
if(offset == 0) {
|
|
if((pcicfgr16(pci, PciPSR) & (1<<4)) == 0)
|
|
return 0; /* no capabilities */
|
|
offset = PciCAP-1;
|
|
}
|
|
return pcicfgr8(pci, offset+1) & ~3;
|
|
}
|