601 lines
13 KiB
C
601 lines
13 KiB
C
/* Copyright (C) Charles Forsyth
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* See /doc/license/NOTICE.Plan9-9k.txt for details about the licensing.
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*/
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/* Portions of this file are Copyright (C) 2015-2018 Giacomo Tesio <giacomo@tesio.it>
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* See /doc/license/gpl-2.0.txt for details about the licensing.
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*/
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/* Portions of this file are Copyright (C) 9front's team.
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* See /doc/license/9front-mit for details about the licensing.
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* See http://code.9front.org/hg/plan9front/ for a list of authors.
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "ureg.h"
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#include "mp.h"
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#include "sipi.h"
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/* filled in by pcmpinit or acpiinit */
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Bus* mpbus;
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Bus* mpbuslast;
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int mpisabus = -1;
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int mpeisabus = -1;
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Apic *mpioapic[MaxAPICNO+1];
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Apic *mpapic[MaxAPICNO+1];
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int
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mpintrinit(Bus* bus, PCMPintr* intr, int vno, int irq)
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{
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int el, po, v;
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/*
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* Parse an I/O or Local APIC interrupt table entry and
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* return the encoded vector.
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*/
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v = vno;
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po = intr->flags & PcmpPOMASK;
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el = intr->flags & PcmpELMASK;
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switch(intr->intr){
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default: /* PcmpINT */
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v |= ApicFIXED; /* no-op */
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break;
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case PcmpNMI:
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v |= ApicNMI;
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po = PcmpHIGH;
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el = PcmpEDGE;
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break;
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case PcmpSMI:
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v |= ApicSMI;
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break;
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case PcmpExtINT:
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v |= ApicExtINT;
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/*
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* The AMI Goliath doesn't boot successfully with it's LINTR0
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* entry which decodes to low+level. The PPro manual says ExtINT
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* should be level, whereas the Pentium is edge. Setting the
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* Goliath to edge+high seems to cure the problem. Other PPro
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* MP tables (e.g. ASUS P/I-P65UP5 have a entry which decodes
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* to edge+high, so who knows.
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* Perhaps it would be best just to not set an ExtINT entry at
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* all, it shouldn't be needed for SMP mode.
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*/
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po = PcmpHIGH;
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el = PcmpEDGE;
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break;
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}
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/*
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*/
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if(bus->type == BusEISA && !po && !el /*&& !(i8259elcr & (1<<irq))*/){
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po = PcmpHIGH;
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el = PcmpEDGE;
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}
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if(!po)
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po = bus->po;
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if(po == PcmpLOW)
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v |= ApicLOW;
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else if(po != PcmpHIGH){
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print("mpintrinit: bad polarity 0x%uX\n", po);
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return ApicIMASK;
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}
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if(!el)
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el = bus->el;
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if(el == PcmpLEVEL)
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v |= ApicLEVEL;
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else if(el != PcmpEDGE){
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print("mpintrinit: bad trigger 0x%uX\n", el);
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return ApicIMASK;
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}
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return v;
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}
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uint64_t
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tscticks(uint64_t *hz)
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{
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if(hz != nil)
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*hz = m->cpuhz;
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cycles(&m->tscticks); /* Uses the rdtsc instruction */
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return m->tscticks;
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}
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void
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syncclock(void)
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{
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uint64_t x;
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if(arch->fastclock != tscticks)
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return;
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if(m->machno == 0){
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wrmsr(0x10, 0);
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m->tscticks = 0;
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} else {
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x = MACHP(0)->tscticks;
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while(x == MACHP(0)->tscticks)
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;
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wrmsr(0x10, MACHP(0)->tscticks);
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cycles(&m->tscticks);
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}
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}
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void
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mpinit(void)
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{
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int ncpu, i;
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Apic *apic;
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char *cp;
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i8259init();
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syncclock();
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if(getconf("*apicdebug")){
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Bus *b;
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Aintr *ai;
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PCMPintr *pi;
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for(i=0; i<=MaxAPICNO; i++){
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if(apic = mpapic[i])
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print("LAPIC%d: pa=%lux va=%#p flags=%x\n",
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i, apic->paddr, apic->addr, apic->flags);
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if(apic = mpioapic[i])
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print("IOAPIC%d: pa=%lux va=%#p flags=%x gsibase=%d mre=%d\n",
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i, apic->paddr, apic->addr, apic->flags, apic->gsibase, apic->mre);
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}
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for(b = mpbus; b; b = b->next){
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print("BUS%d type=%d flags=%x\n", b->busno, b->type, b->po|b->el);
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for(ai = b->aintr; ai; ai = ai->next){
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if(pi = ai->intr)
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print("\ttype=%d irq=%d (%d [%c]) apic=%d intin=%d flags=%x\n",
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pi->type, pi->irq, pi->irq>>2, "ABCD"[pi->irq&3],
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pi->apicno, pi->intin, pi->flags);
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}
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}
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}
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apic = nil;
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for(i=0; i<=MaxAPICNO; i++){
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if(mpapic[i] == nil)
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continue;
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if(mpapic[i]->flags & PcmpBP){
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apic = mpapic[i];
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break;
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}
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}
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if(apic == nil){
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panic("mpinit: no bootstrap processor");
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return;
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}
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apic->online = 1;
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lapicinit(apic);
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/*
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* These interrupts are local to the processor
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* and do not appear in the I/O APIC so it is OK
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* to set them now.
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*/
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intrenable(IrqTIMER, lapicclock, 0, BUSUNKNOWN, "clock");
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intrenable(IrqERROR, lapicerror, 0, BUSUNKNOWN, "lapicerror");
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intrenable(IrqSPURIOUS, lapicspurious, 0, BUSUNKNOWN, "lapicspurious");
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lapiconline();
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/*
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* Initialise the application processors.
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*/
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if(cp = getconf("*ncpu")){
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ncpu = strtol(cp, 0, 0);
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if(ncpu < 1)
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ncpu = 1;
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else if(ncpu > MACHMAX)
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ncpu = MACHMAX;
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}
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else
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ncpu = MACHMAX;
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memmove((void*)APBOOTSTRAP, sipihandler, sizeof(sipihandler));
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for(i=0; i<nelem(mpapic); i++){
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if((apic = mpapic[i]) == nil)
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continue;
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if(apic->machno >= MACHMAX)
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continue;
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if(ncpu <= 1)
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break;
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if((apic->flags & (PcmpBP|PcmpEN)) == PcmpEN){
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mpstartap(apic);
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sys->nmach++;
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ncpu--;
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}
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}
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/*
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* we don't really know the number of processors till
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* here.
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*
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* set sys->copymode here if nmach > 1.
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* Should look for an ExtINT line and enable it.
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*/
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if(X86FAMILY(m->cpuidax) == 3 || sys->nmach > 1)
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sys->copymode = 1;
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}
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static int
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mpintrcpu(void)
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{
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static Lock physidlock;
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static int physid;
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int i;
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/*
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* The bulk of this code was written ~1995, when there was
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* one architecture and one generation of hardware, the number
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* of CPUs was up to 4(8) and the choices for interrupt routing
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* were physical, or flat logical (optionally with lowest
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* priority interrupt). Logical mode hasn't scaled well with
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* the increasing number of packages/cores/threads, so the
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* fall-back is to physical mode, which works across all processor
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* generations, both AMD and Intel, using the APIC and xAPIC.
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*
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* Interrupt routing policy can be set here.
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* Currently, just assign each interrupt to a different CPU on
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* a round-robin basis. Some idea of the packages/cores/thread
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* topology would be useful here, e.g. to not assign interrupts
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* to more than one thread in a core, or to use a "noise" core.
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* But, as usual, Intel make that an onerous task.
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*/
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lock(&physidlock);
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for(;;){
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i = physid++;
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if(physid >= nelem(mpapic))
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physid = 0;
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if(mpapic[i] == nil)
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continue;
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if(mpapic[i]->online)
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break;
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}
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unlock(&physidlock);
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return mpapic[i]->apicno;
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}
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/*
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* With the APIC a unique vector can be assigned to each
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* request to enable an interrupt. There are two reasons this
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* is a good idea:
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* 1) to prevent lost interrupts, no more than 2 interrupts
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* should be assigned per block of 16 vectors (there is an
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* in-service entry and a holding entry for each priority
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* level and there is one priority level per block of 16
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* interrupts).
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* 2) each input pin on the IOAPIC will receive a different
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* vector regardless of whether the devices on that pin use
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* the same IRQ as devices on another pin.
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*/
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static int
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allocvector(void)
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{
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static int round = 0, num = 0;
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static Lock l;
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int vno;
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lock(&l);
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vno = VectorAPIC + num;
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if(vno < MaxVectorAPIC-7)
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num += 8;
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else
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num = ++round % 8;
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unlock(&l);
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return vno;
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}
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static int
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mpintrenablex(Vctl* v, int tbdf)
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{
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Bus *bus;
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Aintr *aintr;
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Apic *apic;
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Pcidev *pcidev;
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int bno, dno, pin, hi, irq, lo, n, type, vno;
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type = BUSTYPE(tbdf);
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bno = BUSBNO(tbdf);
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dno = BUSDNO(tbdf);
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pin = 0;
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pcidev = nil;
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if(type == BusPCI){
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if(pcidev = pcimatchtbdf(tbdf))
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pin = pcicfgr8(pcidev, PciINTP);
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} else if(type == BusISA)
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bno = mpisabus;
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Findbus:
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for(bus = mpbus; bus != nil; bus = bus->next){
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if(bus->type != type)
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continue;
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if(bus->busno == bno)
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break;
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}
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if(bus == nil){
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/*
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* if the PCI device is behind a PCI-PCI bridge thats not described
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* by the MP or ACPI tables then walk up the bus translating interrupt
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* pin to parent bus.
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*/
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if(pcidev && pcidev->parent && pin > 0){
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pin = ((dno+(pin-1))%4)+1;
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pcidev = pcidev->parent;
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bno = BUSBNO(pcidev->tbdf);
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dno = BUSDNO(pcidev->tbdf);
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goto Findbus;
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}
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print("mpintrenable: can't find bus type %d, number %d\n", type, bno);
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return -1;
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}
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/*
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* For PCI devices the interrupt pin (INT[ABCD]) and device
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* number are encoded into the entry irq field, so create something
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* to match on.
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*/
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if(bus->type == BusPCI){
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if(pin > 0)
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irq = (dno<<2)|(pin-1);
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else
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irq = -1;
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}
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else
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irq = v->irq;
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/*
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* Find a matching interrupt entry from the list of interrupts
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* attached to this bus.
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*/
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for(aintr = bus->aintr; aintr; aintr = aintr->next){
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if(aintr->intr->irq != irq)
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continue;
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if(0){
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PCMPintr* p = aintr->intr;
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print("mpintrenablex: bus %d intin %d irq %d\n",
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p->busno, p->intin, p->irq);
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}
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/*
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* Check if already enabled. Multifunction devices may share
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* INT[A-D]# so, if already enabled, check the polarity matches
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* and the trigger is level.
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*
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* Should check the devices differ only in the function number,
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* but that can wait for the planned enable/disable rewrite.
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* The RDT read here is safe for now as currently interrupts
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* are never disabled once enabled.
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*/
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apic = aintr->apic;
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ioapicrdtr(apic, aintr->intr->intin, 0, &lo);
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if(!(lo & ApicIMASK)){
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vno = lo & 0xFF;
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if(0) print("%s vector %d (!imask)\n", v->name, vno);
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n = mpintrinit(bus, aintr->intr, vno, v->irq);
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n |= ApicPHYSICAL; /* no-op */
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lo &= ~(ApicRemoteIRR|ApicDELIVS);
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if(n != lo){
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print("mpintrenable: multiple botch irq %d, tbdf %uX, lo %8.8uX, n %8.8uX\n",
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v->irq, tbdf, lo, n);
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return -1;
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}
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v->isr = lapicisr;
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v->eoi = lapiceoi;
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return vno;
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}
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vno = allocvector();
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hi = mpintrcpu()<<24;
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lo = mpintrinit(bus, aintr->intr, vno, v->irq);
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lo |= ApicPHYSICAL; /* no-op */
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if(lo & ApicIMASK){
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print("mpintrenable: disabled irq %d, tbdf %uX, lo %8.8uX, hi %8.8uX\n",
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v->irq, tbdf, lo, hi);
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return -1;
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}
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if((apic->flags & PcmpEN) && apic->type == PcmpIOAPIC)
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ioapicrdtw(apic, aintr->intr->intin, hi, lo);
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v->isr = lapicisr;
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v->eoi = lapiceoi;
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return vno;
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}
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return -1;
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}
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enum {
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MSICtrl = 0x02, /* message control register (16 bit) */
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MSIAddr = 0x04, /* message address register (64 bit) */
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MSIData32 = 0x08, /* message data register for 32 bit MSI (16 bit) */
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MSIData64 = 0x0C, /* message data register for 64 bit MSI (16 bit) */
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};
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enum {
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HTMSIMapping = 0xA8,
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HTMSIFlags = 0x02,
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HTMSIFlagsEn = 0x01,
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};
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static int
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htmsicapenable(Pcidev *p)
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{
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return -1;
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#if 0
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int cap, flags;
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if((cap = pcihtcap(p, HTMSIMapping)) <= 0)
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return -1;
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flags = pcicfgr8(p, cap + HTMSIFlags);
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if((flags & HTMSIFlagsEn) == 0)
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pcicfgw8(p, cap + HTMSIFlags, flags | HTMSIFlagsEn);
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return 0;
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#endif
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}
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static int
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htmsienable(Pcidev *pdev)
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{
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Pcidev *p;
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p = nil;
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while((p = pcimatch(p, 0x1022, 0)) != nil)
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if(p->did == 0x1103 || p->did == 0x1203)
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break;
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if(p == nil)
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return 0; /* not hypertransport platform */
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p = nil;
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while((p = pcimatch(p, 0x10de, 0)) != nil){
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switch(p->did){
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case 0x02f0: /* NVIDIA NFORCE C51 MEMC0 */
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case 0x02f1: /* NVIDIA NFORCE C51 MEMC1 */
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case 0x02f2: /* NVIDIA NFORCE C51 MEMC2 */
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case 0x02f3: /* NVIDIA NFORCE C51 MEMC3 */
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case 0x02f4: /* NVIDIA NFORCE C51 MEMC4 */
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case 0x02f5: /* NVIDIA NFORCE C51 MEMC5 */
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case 0x02f6: /* NVIDIA NFORCE C51 MEMC6 */
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case 0x02f7: /* NVIDIA NFORCE C51 MEMC7 */
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case 0x0369: /* NVIDIA NFORCE MCP55 MEMC */
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htmsicapenable(p);
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break;
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}
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}
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if(htmsicapenable(pdev) == 0)
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return 0;
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for(p = pdev->parent; p != nil; p = p->parent)
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if(htmsicapenable(p) == 0)
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return 0;
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return -1;
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}
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static int
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msiintrenable(Vctl *v)
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{
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int tbdf, vno, cap, cpu, ok64;
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Pcidev *pci;
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if(getconf("*nomsi") != nil)
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return -1;
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tbdf = v->tbdf;
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if(tbdf == BUSUNKNOWN || BUSTYPE(tbdf) != BusPCI)
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return -1;
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pci = pcimatchtbdf(tbdf);
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if(pci == nil) {
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print("msiintrenable: could not find Pcidev for tbdf %uX\n", tbdf);
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return -1;
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}
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if(htmsienable(pci) < 0)
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return -1;
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cap = pcicap(pci, PciCapMSI);
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if(cap < 0)
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return -1;
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vno = allocvector();
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cpu = mpintrcpu();
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ok64 = (pcicfgr16(pci, cap + MSICtrl) & (1<<7)) != 0;
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pcicfgw32(pci, cap + MSIAddr, (0xFEE << 20) | (cpu << 12));
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if(ok64) pcicfgw32(pci, cap + MSIAddr + 4, 0);
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pcicfgw16(pci, cap + (ok64 ? MSIData64 : MSIData32), vno | (1<<14));
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pcicfgw16(pci, cap + MSICtrl, 1);
|
|
v->isr = lapicisr;
|
|
v->eoi = lapiceoi;
|
|
return vno;
|
|
}
|
|
|
|
int
|
|
mpintrenable(Vctl* v)
|
|
{
|
|
int irq, tbdf, vno;
|
|
|
|
vno = msiintrenable(v);
|
|
if(vno != -1)
|
|
return vno;
|
|
|
|
/*
|
|
* If the bus is known, try it.
|
|
* BUSUNKNOWN is given both by [E]ISA devices and by
|
|
* interrupts local to the processor (local APIC, coprocessor
|
|
* breakpoint and page-fault).
|
|
*/
|
|
tbdf = v->tbdf;
|
|
if(tbdf != BUSUNKNOWN && (vno = mpintrenablex(v, tbdf)) != -1)
|
|
return vno;
|
|
|
|
irq = v->irq;
|
|
if(irq >= IrqLINT0 && irq <= MaxIrqLAPIC){
|
|
if(irq != IrqSPURIOUS)
|
|
v->isr = lapiceoi;
|
|
return VectorPIC+irq;
|
|
}
|
|
if(irq < 0 || irq > MaxIrqPIC){
|
|
print("mpintrenable: irq %d out of range\n", irq);
|
|
return -1;
|
|
}
|
|
|
|
/*
|
|
* Either didn't find it or have to try the default buses
|
|
* (ISA and EISA). This hack is due to either over-zealousness
|
|
* or laziness on the part of some manufacturers.
|
|
*
|
|
* The MP configuration table on some older systems
|
|
* (e.g. ASUS PCI/E-P54NP4) has an entry for the EISA bus
|
|
* but none for ISA. It also has the interrupt type and
|
|
* polarity set to 'default for this bus' which wouldn't
|
|
* be compatible with ISA.
|
|
*/
|
|
if(mpeisabus != -1){
|
|
vno = mpintrenablex(v, MKBUS(BusEISA, 0, 0, 0));
|
|
if(vno != -1)
|
|
return vno;
|
|
}
|
|
if(mpisabus != -1){
|
|
vno = mpintrenablex(v, MKBUS(BusISA, 0, 0, 0));
|
|
if(vno != -1)
|
|
return vno;
|
|
}
|
|
print("mpintrenable: out of choices eisa %d isa %d tbdf %uX irq %d\n",
|
|
mpeisabus, mpisabus, v->tbdf, v->irq);
|
|
return -1;
|
|
}
|
|
|
|
void
|
|
mpshutdown(void)
|
|
{
|
|
/*
|
|
* Park application processors.
|
|
*/
|
|
if(m->machno != 0){
|
|
splhi();
|
|
arch->introff();
|
|
for(;;) idle();
|
|
}
|
|
delay(1000);
|
|
splhi();
|
|
|
|
/*
|
|
* INIT all excluding self.
|
|
*/
|
|
lapicicrw(0, 0x000C0000|ApicINIT);
|
|
|
|
pcireset();
|
|
}
|