1229 lines
27 KiB
C
1229 lines
27 KiB
C
/* Copyright (C) Charles Forsyth
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* See /doc/license/NOTICE.Plan9-9k.txt for details about the licensing.
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*/
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/* Portions of this file are Copyright (C) 9front's team.
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* See /doc/license/9front-mit for details about the licensing.
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* See http://code.9front.org/hg/plan9front/ for a list of authors.
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*/
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/*
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* Realtek RTL8110S/8169S Gigabit Ethernet Controllers.
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* Mostly there. There are some magic register values used
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* which are not described in any datasheet or driver but seem
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* to be necessary.
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* No tuning has been done. Only tested on an RTL8110S, there
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* are slight differences between the chips in the series so some
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* tweaks may be needed.
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "../port/error.h"
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#include "../port/netif.h"
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#include "etherif.h"
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#include "ethermii.h"
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enum { /* registers */
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Idr0 = 0x00, /* MAC address */
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Mar0 = 0x08, /* Multicast address */
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Dtccr = 0x10, /* Dump Tally Counter Command */
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Tnpds = 0x20, /* Transmit Normal Priority Descriptors */
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Thpds = 0x28, /* Transmit High Priority Descriptors */
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Flash = 0x30, /* Flash Memory Read/Write */
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Erbcr = 0x34, /* Early Receive Byte Count */
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Ersr = 0x36, /* Early Receive Status */
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Cr = 0x37, /* Command Register */
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Tppoll = 0x38, /* Transmit Priority Polling */
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Imr = 0x3C, /* Interrupt Mask */
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Isr = 0x3E, /* Interrupt Status */
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Tcr = 0x40, /* Transmit Configuration */
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Rcr = 0x44, /* Receive Configuration */
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Tctr = 0x48, /* Timer Count */
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Mpc = 0x4C, /* Missed Packet Counter */
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Cr9346 = 0x50, /* 9346 Command Register */
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Config0 = 0x51, /* Configuration Register 0 */
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Config1 = 0x52, /* Configuration Register 1 */
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Config2 = 0x53, /* Configuration Register 2 */
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Config3 = 0x54, /* Configuration Register 3 */
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Config4 = 0x55, /* Configuration Register 4 */
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Config5 = 0x56, /* Configuration Register 5 */
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Timerint = 0x58, /* Timer Interrupt */
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Mulint = 0x5C, /* Multiple Interrupt Select */
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Phyar = 0x60, /* PHY Access */
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Tbicsr0 = 0x64, /* TBI Control and Status */
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Tbianar = 0x68, /* TBI Auto-Negotiation Advertisment */
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Tbilpar = 0x6A, /* TBI Auto-Negotiation Link Partner */
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Phystatus = 0x6C, /* PHY Status */
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Pmch = 0x6F, /* power management */
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Ldps = 0x82, /* link down power saving */
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Rms = 0xDA, /* Receive Packet Maximum Size */
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Cplusc = 0xE0, /* C+ Command */
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Coal = 0xE2, /* Interrupt Mitigation (Coalesce) */
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Rdsar = 0xE4, /* Receive Descriptor Start Address */
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Etx = 0xEC, /* Early Transmit Threshold */
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};
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enum { /* Dtccr */
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Cmd = 0x00000008, /* Command */
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};
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enum { /* Cr */
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Te = 0x04, /* Transmitter Enable */
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Re = 0x08, /* Receiver Enable */
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Rst = 0x10, /* Software Reset */
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};
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enum { /* Tppoll */
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Fswint = 0x01, /* Forced Software Interrupt */
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Npq = 0x40, /* Normal Priority Queue polling */
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Hpq = 0x80, /* High Priority Queue polling */
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};
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enum { /* Imr/Isr */
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Rok = 0x0001, /* Receive OK */
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Rer = 0x0002, /* Receive Error */
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Tok = 0x0004, /* Transmit OK */
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Ter = 0x0008, /* Transmit Error */
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Rdu = 0x0010, /* Receive Descriptor Unavailable */
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Punlc = 0x0020, /* Packet Underrun or Link Change */
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Fovw = 0x0040, /* Receive FIFO Overflow */
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Tdu = 0x0080, /* Transmit Descriptor Unavailable */
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Swint = 0x0100, /* Software Interrupt */
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Timeout = 0x4000, /* Timer */
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Serr = 0x8000, /* System Error */
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};
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enum { /* Tcr */
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MtxdmaSHIFT = 8, /* Max. DMA Burst Size */
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MtxdmaMASK = 0x00000700,
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Mtxdmaunlimited = 0x00000700,
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Acrc = 0x00010000, /* Append CRC (not) */
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Lbk0 = 0x00020000, /* Loopback Test 0 */
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Lbk1 = 0x00040000, /* Loopback Test 1 */
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Ifg2 = 0x00080000, /* Interframe Gap 2 */
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HwveridSHIFT = 23, /* Hardware Version ID */
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HwveridMASK = 0x7C800000,
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Macv01 = 0x00000000, /* RTL8169 */
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Macv02 = 0x00800000, /* RTL8169S/8110S */
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Macv03 = 0x04000000, /* RTL8169S/8110S */
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Macv04 = 0x10000000, /* RTL8169SB/8110SB */
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Macv05 = 0x18000000, /* RTL8169SC/8110SC */
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Macv07 = 0x24800000, /* RTL8102e */
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Macv07a = 0x34800000, /* RTL8102e */
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Macv11 = 0x30000000, /* RTL8168B/8111B */
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Macv12 = 0x38000000, /* RTL8169B/8111B */
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Macv12a = 0x3c000000, /* RTL8169C/8111C */
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Macv13 = 0x34000000, /* RTL8101E */
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Macv14 = 0x30800000, /* RTL8100E */
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Macv15 = 0x38800000, /* RTL8100E */
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// Macv19 = 0x3c000000, /* dup Macv12a: RTL8111c-gr */
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Macv25 = 0x28000000, /* RTL8168D */
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Macv26 = 0x48000000, /* RTL8111/8168B */
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Macv27 = 0x2c800000, /* RTL8111e */
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Macv28 = 0x2c000000, /* RTL8111/8168B */
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Macv29 = 0x40800000, /* RTL8101/8102E */
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Macv30 = 0x24000000, /* RTL8101E? (untested) */
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Macv40 = 0x4c000000, /* RTL8168G */
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Macv44 = 0x5c800000, /* RTL8411B */
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Macv45 = 0x50800000, /* RTL8168GU */
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Ifg0 = 0x01000000, /* Interframe Gap 0 */
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Ifg1 = 0x02000000, /* Interframe Gap 1 */
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};
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enum { /* Rcr */
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Aap = 0x00000001, /* Accept All Packets */
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Apm = 0x00000002, /* Accept Physical Match */
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Am = 0x00000004, /* Accept Multicast */
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Ab = 0x00000008, /* Accept Broadcast */
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Ar = 0x00000010, /* Accept Runt */
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Aer = 0x00000020, /* Accept Error */
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Sel9356 = 0x00000040, /* 9356 EEPROM used */
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MrxdmaSHIFT = 8, /* Max. DMA Burst Size */
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MrxdmaMASK = 0x00000700,
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Mrxdmaunlimited = 0x00000700,
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RxfthSHIFT = 13, /* Receive Buffer Length */
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RxfthMASK = 0x0000E000,
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Rxfth256 = 0x00008000,
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Rxfthnone = 0x0000E000,
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Rer8 = 0x00010000, /* Accept Error Packets > 8 bytes */
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MulERINT = 0x01000000, /* Multiple Early Interrupt Select */
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};
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enum { /* Cr9346 */
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Eedo = 0x01, /* */
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Eedi = 0x02, /* */
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Eesk = 0x04, /* */
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Eecs = 0x08, /* */
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Eem0 = 0x40, /* Operating Mode */
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Eem1 = 0x80,
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};
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enum { /* Phyar */
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DataMASK = 0x0000FFFF, /* 16-bit GMII/MII Register Data */
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DataSHIFT = 0,
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RegaddrMASK = 0x001F0000, /* 5-bit GMII/MII Register Address */
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RegaddrSHIFT = 16,
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Flag = 0x80000000, /* */
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};
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enum { /* Phystatus */
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Fd = 0x01, /* Full Duplex */
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Linksts = 0x02, /* Link Status */
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Speed10 = 0x04, /* */
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Speed100 = 0x08, /* */
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Speed1000 = 0x10, /* */
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Rxflow = 0x20, /* */
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Txflow = 0x40, /* */
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Entbi = 0x80, /* */
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};
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enum { /* Cplusc */
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Txenb = 0x0001, /* enable C+ transmit mode */
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Rxenb = 0x0002, /* enable C+ receive mode */
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Mulrw = 0x0008, /* PCI Multiple R/W Enable */
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Dac = 0x0010, /* PCI Dual Address Cycle Enable */
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Rxchksum = 0x0020, /* Receive Checksum Offload Enable */
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Rxvlan = 0x0040, /* Receive VLAN De-tagging Enable */
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Macstatdis = 0x0080, /* Disable Mac Statistics */
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Endian = 0x0200, /* Endian Mode */
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};
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typedef struct D D; /* Transmit/Receive Descriptor */
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struct D {
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uint32_t control;
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uint32_t vlan;
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uint32_t addrlo;
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uint32_t addrhi;
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};
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enum { /* Transmit Descriptor control */
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TxflMASK = 0x0000FFFF, /* Transmit Frame Length */
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TxflSHIFT = 0,
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Tcps = 0x00010000, /* TCP Checksum Offload */
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Udpcs = 0x00020000, /* UDP Checksum Offload */
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Ipcs = 0x00040000, /* IP Checksum Offload */
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Lgsen = 0x08000000, /* TSO; WARNING: contains lark's vomit */
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};
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enum { /* Receive Descriptor control */
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RxflMASK = 0x00001FFF, /* Receive Frame Length */
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Tcpf = 0x00004000, /* TCP Checksum Failure */
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Udpf = 0x00008000, /* UDP Checksum Failure */
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Ipf = 0x00010000, /* IP Checksum Failure */
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Pid0 = 0x00020000, /* Protocol ID0 */
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Pid1 = 0x00040000, /* Protocol ID1 */
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Crce = 0x00080000, /* CRC Error */
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Runt = 0x00100000, /* Runt Packet */
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Res = 0x00200000, /* Receive Error Summary */
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Rwt = 0x00400000, /* Receive Watchdog Timer Expired */
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Fovf = 0x00800000, /* FIFO Overflow */
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Bovf = 0x01000000, /* Buffer Overflow */
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Bar = 0x02000000, /* Broadcast Address Received */
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Pam = 0x04000000, /* Physical Address Matched */
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Mar = 0x08000000, /* Multicast Address Received */
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};
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enum { /* General Descriptor control */
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Ls = 0x10000000, /* Last Segment Descriptor */
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Fs = 0x20000000, /* First Segment Descriptor */
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Eor = 0x40000000, /* End of Descriptor Ring */
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Own = 0x80000000, /* Ownership */
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};
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/*
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*/
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enum { /* Ring sizes (<= 1024) */
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Ntd = 64, /* Transmit Ring */
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Nrd = 256, /* Receive Ring */
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Mtu = ETHERMAXTU,
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Mps = ROUNDUP(ETHERMAXTU+4, 128),
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};
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typedef struct Dtcc Dtcc;
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struct Dtcc {
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uint64_t txok;
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uint64_t rxok;
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uint64_t txer;
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uint32_t rxer;
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uint16_t misspkt;
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uint16_t fae;
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uint32_t tx1col;
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uint32_t txmcol;
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uint64_t rxokph;
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uint64_t rxokbrd;
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uint32_t rxokmu;
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uint16_t txabt;
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uint16_t txundrn;
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};
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enum { /* Variants */
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Rtl8100e = (0x8136<<16)|0x10EC, /* RTL810[01]E: pci -e */
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Rtl8169c = (0x0116<<16)|0x16EC, /* RTL8169C+ (USR997902) */
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Rtl8169sc = (0x8167<<16)|0x10EC, /* RTL8169SC */
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Rtl8168b = (0x8168<<16)|0x10EC, /* RTL8168B: pci-e */
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Rtl8169 = (0x8169<<16)|0x10EC, /* RTL8169 */
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};
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typedef struct Ctlr Ctlr;
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typedef struct Ctlr {
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Lock l;
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int port;
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Pcidev* pcidev;
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Ctlr* next;
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int active;
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QLock alock; /* attach */
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int init; /* */
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Rendez reset;
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int pciv; /* */
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int macv; /* MAC version */
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int phyv; /* PHY version */
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int pcie; /* flag: pci-express device? */
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uint64_t mchash; /* multicast hash */
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Mii* mii;
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D* td; /* descriptor ring */
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Block** tb; /* transmit buffers */
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int ntd;
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int tdh; /* head - producer index (host) */
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int tdt; /* tail - consumer index (NIC) */
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int ntq;
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D* rd; /* descriptor ring */
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Block** rb; /* receive buffers */
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int nrd;
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int rdh; /* head - producer index (NIC) */
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int rdt; /* tail - consumer index (host) */
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int nrq;
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int tcr; /* transmit configuration register */
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int rcr; /* receive configuration register */
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int imr;
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QLock slock; /* statistics */
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Dtcc* dtcc;
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uint32_t txdu;
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uint32_t tcpf;
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uint32_t udpf;
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uint32_t ipf;
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uint32_t fovf;
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uint32_t rer;
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uint32_t rdu;
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uint32_t punlc;
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uint32_t serr;
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uint32_t fovw;
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uint32_t mcast;
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uint32_t frag; /* partial packets; rb was too small */
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} Ctlr;
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static Ctlr* rtl8169ctlrhead;
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static Ctlr* rtl8169ctlrtail;
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#define csr8r(c, r) (inb((c)->port+(r)))
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#define csr16r(c, r) (ins((c)->port+(r)))
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#define csr32r(c, r) (inl((c)->port+(r)))
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#define csr8w(c, r, b) (outb((c)->port+(r), (uint8_t)(b)))
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#define csr16w(c, r, w) (outs((c)->port+(r), (uint16_t)(w)))
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#define csr32w(c, r, l) (outl((c)->port+(r), (uint32_t)(l)))
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static int
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rtl8169miimir(Mii* mii, int pa, int ra)
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{
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uint32_t r;
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int timeo;
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Ctlr *ctlr;
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if(pa != 1)
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return -1;
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ctlr = mii->ctlr;
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r = (ra<<16) & RegaddrMASK;
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csr32w(ctlr, Phyar, r);
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delay(1);
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for(timeo = 0; timeo < 2000; timeo++){
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if((r = csr32r(ctlr, Phyar)) & Flag)
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break;
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microdelay(100);
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}
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if(!(r & Flag))
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return -1;
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return (r & DataMASK)>>DataSHIFT;
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}
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static int
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rtl8169miimiw(Mii* mii, int pa, int ra, int data)
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{
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uint32_t r;
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int timeo;
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Ctlr *ctlr;
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if(pa != 1)
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return -1;
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ctlr = mii->ctlr;
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r = Flag|((ra<<16) & RegaddrMASK)|((data<<DataSHIFT) & DataMASK);
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csr32w(ctlr, Phyar, r);
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delay(1);
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for(timeo = 0; timeo < 2000; timeo++){
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if(!((r = csr32r(ctlr, Phyar)) & Flag))
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break;
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microdelay(100);
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}
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if(r & Flag)
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return -1;
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return 0;
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}
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static int
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rtl8169mii(Ctlr* ctlr)
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{
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MiiPhy *phy;
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/*
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* Link management.
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*/
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if((ctlr->mii = jehanne_malloc(sizeof(Mii))) == nil)
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return -1;
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ctlr->mii->mir = rtl8169miimir;
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ctlr->mii->miw = rtl8169miimiw;
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ctlr->mii->ctlr = ctlr;
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/*
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* PHY wakeup
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*/
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switch(ctlr->macv){
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case Macv25:
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case Macv28:
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case Macv29:
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case Macv30:
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csr8w(ctlr, Pmch, csr8r(ctlr, Pmch) | 0x80);
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break;
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}
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rtl8169miimiw(ctlr->mii, 1, 0x1f, 0);
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rtl8169miimiw(ctlr->mii, 1, 0x0e, 0);
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/*
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* Get rev number out of Phyidr2 so can config properly.
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* There's probably more special stuff for Macv0[234] needed here.
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*/
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ctlr->phyv = rtl8169miimir(ctlr->mii, 1, Phyidr2) & 0x0F;
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if(ctlr->macv == Macv02){
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csr8w(ctlr, Ldps, 1); /* magic */
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rtl8169miimiw(ctlr->mii, 1, 0x0B, 0x0000); /* magic */
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}
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if(mii(ctlr->mii, (1<<1)) == 0 || (phy = ctlr->mii->curphy) == nil){
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jehanne_free(ctlr->mii);
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ctlr->mii = nil;
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return -1;
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}
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jehanne_print("rtl8169: oui %#ux phyno %d, macv = %#8.8ux phyv = %#4.4ux\n",
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phy->oui, phy->phyno, ctlr->macv, ctlr->phyv);
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miireset(ctlr->mii);
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microdelay(100);
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miiane(ctlr->mii, ~0, ~0, ~0);
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return 0;
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}
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static void
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rtl8169promiscuous(void* arg, int on)
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{
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Ether *edev;
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Ctlr * ctlr;
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edev = arg;
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ctlr = edev->ctlr;
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ilock(&ctlr->l);
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if(on)
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ctlr->rcr |= Aap;
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else
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ctlr->rcr &= ~Aap;
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csr32w(ctlr, Rcr, ctlr->rcr);
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iunlock(&ctlr->l);
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}
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enum {
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/* everyone else uses 0x04c11db7, but they both produce the same crc */
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Etherpolybe = 0x04c11db6,
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Bytemask = (1<<8) - 1,
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};
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static uint32_t
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ethercrcbe(uint8_t *addr, int32_t len)
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{
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int i, j;
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uint32_t c, crc, carry;
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|
|
crc = (uint32_t)~0UL;
|
|
for (i = 0; i < len; i++) {
|
|
c = addr[i];
|
|
for (j = 0; j < 8; j++) {
|
|
carry = ((crc & (1UL << 31))? 1: 0) ^ (c & 1);
|
|
crc <<= 1;
|
|
c >>= 1;
|
|
if (carry)
|
|
crc = (crc ^ Etherpolybe) | carry;
|
|
}
|
|
}
|
|
return crc;
|
|
}
|
|
|
|
static uint32_t
|
|
swabl(uint32_t l)
|
|
{
|
|
return l>>24 | (l>>8) & (Bytemask<<8) |
|
|
(l<<8) & (Bytemask<<16) | l<<24;
|
|
}
|
|
|
|
static void
|
|
rtl8169multicast(void* ether, uint8_t *eaddr, int add)
|
|
{
|
|
Ether *edev;
|
|
Ctlr *ctlr;
|
|
|
|
if (!add)
|
|
return; /* ok to keep receiving on old mcast addrs */
|
|
|
|
edev = ether;
|
|
ctlr = edev->ctlr;
|
|
ilock(&ctlr->l);
|
|
|
|
ctlr->mchash |= 1ULL << (ethercrcbe(eaddr, Eaddrlen) >> 26);
|
|
|
|
ctlr->rcr |= Am;
|
|
csr32w(ctlr, Rcr, ctlr->rcr);
|
|
|
|
/* pci-e variants reverse the order of the hash byte registers */
|
|
if (ctlr->pcie) {
|
|
csr32w(ctlr, Mar0, swabl(ctlr->mchash>>32));
|
|
csr32w(ctlr, Mar0+4, swabl(ctlr->mchash));
|
|
} else {
|
|
csr32w(ctlr, Mar0, ctlr->mchash);
|
|
csr32w(ctlr, Mar0+4, ctlr->mchash>>32);
|
|
}
|
|
|
|
iunlock(&ctlr->l);
|
|
}
|
|
|
|
static long
|
|
rtl8169ifstat(Ether* edev, void* a, long n, uint32_t offset)
|
|
{
|
|
char *p;
|
|
Ctlr *ctlr;
|
|
Dtcc *dtcc;
|
|
int i, l, r, timeo;
|
|
|
|
p = smalloc(READSTR);
|
|
|
|
ctlr = edev->ctlr;
|
|
qlock(&ctlr->slock);
|
|
|
|
if(waserror()){
|
|
qunlock(&ctlr->slock);
|
|
jehanne_free(p);
|
|
nexterror();
|
|
}
|
|
|
|
csr32w(ctlr, Dtccr+4, 0);
|
|
csr32w(ctlr, Dtccr, PCIWADDR32(ctlr->dtcc)|Cmd);
|
|
for(timeo = 0; timeo < 1000; timeo++){
|
|
if(!(csr32r(ctlr, Dtccr) & Cmd))
|
|
break;
|
|
delay(1);
|
|
}
|
|
if(csr32r(ctlr, Dtccr) & Cmd)
|
|
error(Eio);
|
|
dtcc = ctlr->dtcc;
|
|
|
|
edev->netif.oerrs = dtcc->txer;
|
|
edev->netif.crcs = dtcc->rxer;
|
|
edev->netif.frames = dtcc->fae;
|
|
edev->netif.buffs = dtcc->misspkt;
|
|
edev->netif.overflows = ctlr->txdu+ctlr->rdu;
|
|
|
|
if(n == 0){
|
|
qunlock(&ctlr->slock);
|
|
poperror();
|
|
jehanne_free(p);
|
|
return 0;
|
|
}
|
|
|
|
l = jehanne_snprint(p, READSTR, "TxOk: %llud\n", dtcc->txok);
|
|
l += jehanne_snprint(p+l, READSTR-l, "RxOk: %llud\n", dtcc->rxok);
|
|
l += jehanne_snprint(p+l, READSTR-l, "TxEr: %llud\n", dtcc->txer);
|
|
l += jehanne_snprint(p+l, READSTR-l, "RxEr: %ud\n", dtcc->rxer);
|
|
l += jehanne_snprint(p+l, READSTR-l, "MissPkt: %ud\n", dtcc->misspkt);
|
|
l += jehanne_snprint(p+l, READSTR-l, "FAE: %ud\n", dtcc->fae);
|
|
l += jehanne_snprint(p+l, READSTR-l, "Tx1Col: %ud\n", dtcc->tx1col);
|
|
l += jehanne_snprint(p+l, READSTR-l, "TxMCol: %ud\n", dtcc->txmcol);
|
|
l += jehanne_snprint(p+l, READSTR-l, "RxOkPh: %llud\n", dtcc->rxokph);
|
|
l += jehanne_snprint(p+l, READSTR-l, "RxOkBrd: %llud\n", dtcc->rxokbrd);
|
|
l += jehanne_snprint(p+l, READSTR-l, "RxOkMu: %ud\n", dtcc->rxokmu);
|
|
l += jehanne_snprint(p+l, READSTR-l, "TxAbt: %ud\n", dtcc->txabt);
|
|
l += jehanne_snprint(p+l, READSTR-l, "TxUndrn: %ud\n", dtcc->txundrn);
|
|
|
|
l += jehanne_snprint(p+l, READSTR-l, "serr: %ud\n", ctlr->serr);
|
|
l += jehanne_snprint(p+l, READSTR-l, "fovw: %ud\n", ctlr->fovw);
|
|
|
|
l += jehanne_snprint(p+l, READSTR-l, "txdu: %ud\n", ctlr->txdu);
|
|
l += jehanne_snprint(p+l, READSTR-l, "tcpf: %ud\n", ctlr->tcpf);
|
|
l += jehanne_snprint(p+l, READSTR-l, "udpf: %ud\n", ctlr->udpf);
|
|
l += jehanne_snprint(p+l, READSTR-l, "ipf: %ud\n", ctlr->ipf);
|
|
l += jehanne_snprint(p+l, READSTR-l, "fovf: %ud\n", ctlr->fovf);
|
|
l += jehanne_snprint(p+l, READSTR-l, "rer: %ud\n", ctlr->rer);
|
|
l += jehanne_snprint(p+l, READSTR-l, "rdu: %ud\n", ctlr->rdu);
|
|
l += jehanne_snprint(p+l, READSTR-l, "punlc: %ud\n", ctlr->punlc);
|
|
|
|
l += jehanne_snprint(p+l, READSTR-l, "tcr: %#8.8ux\n", ctlr->tcr);
|
|
l += jehanne_snprint(p+l, READSTR-l, "rcr: %#8.8ux\n", ctlr->rcr);
|
|
l += jehanne_snprint(p+l, READSTR-l, "multicast: %ud\n", ctlr->mcast);
|
|
|
|
if(ctlr->mii != nil && ctlr->mii->curphy != nil){
|
|
l += jehanne_snprint(p+l, READSTR-l, "phy: ");
|
|
for(i = 0; i < NMiiPhyr; i++){
|
|
if(i && ((i & 0x07) == 0))
|
|
l += jehanne_snprint(p+l, READSTR-l, "\n ");
|
|
r = miimir(ctlr->mii, i);
|
|
l += jehanne_snprint(p+l, READSTR-l, " %4.4ux", r);
|
|
}
|
|
jehanne_snprint(p+l, READSTR-l, "\n");
|
|
}
|
|
|
|
n = readstr(offset, a, n, p);
|
|
|
|
qunlock(&ctlr->slock);
|
|
poperror();
|
|
jehanne_free(p);
|
|
|
|
return n;
|
|
}
|
|
|
|
static void
|
|
rtl8169halt(Ctlr* ctlr)
|
|
{
|
|
csr8w(ctlr, Cr, 0);
|
|
csr16w(ctlr, Imr, 0);
|
|
csr16w(ctlr, Isr, ~0);
|
|
}
|
|
|
|
static int
|
|
rtl8169reset(Ctlr* ctlr)
|
|
{
|
|
uint32_t r;
|
|
int timeo;
|
|
|
|
/*
|
|
* Soft reset the controller.
|
|
*/
|
|
csr8w(ctlr, Cr, Rst);
|
|
for(r = timeo = 0; timeo < 1000; timeo++){
|
|
r = csr8r(ctlr, Cr);
|
|
if(!(r & Rst))
|
|
break;
|
|
delay(1);
|
|
}
|
|
rtl8169halt(ctlr);
|
|
|
|
if(r & Rst)
|
|
return -1;
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
rtl8169replenish(Ctlr* ctlr)
|
|
{
|
|
D *d;
|
|
int x;
|
|
Block *bp;
|
|
|
|
x = ctlr->rdt;
|
|
while(NEXT(x, ctlr->nrd) != ctlr->rdh){
|
|
bp = iallocb(Mps);
|
|
if(bp == nil){
|
|
iprint("rtl8169: no available buffers\n");
|
|
break;
|
|
}
|
|
ctlr->rb[x] = bp;
|
|
ctlr->nrq++;
|
|
d = &ctlr->rd[x];
|
|
d->addrlo = PCIWADDR32(bp->rp);
|
|
d->addrhi = 0;
|
|
coherence();
|
|
d->control = (d->control & Eor) | Own | BALLOC(bp);
|
|
x = NEXT(x, ctlr->nrd);
|
|
ctlr->rdt = x;
|
|
}
|
|
}
|
|
|
|
static int
|
|
rtl8169init(Ether* edev)
|
|
{
|
|
int i;
|
|
uint32_t r;
|
|
Block *bp;
|
|
Ctlr *ctlr;
|
|
uint16_t cplusc;
|
|
|
|
ctlr = edev->ctlr;
|
|
ilock(&ctlr->l);
|
|
|
|
rtl8169reset(ctlr);
|
|
|
|
jehanne_memset(ctlr->td, 0, sizeof(D)*ctlr->ntd);
|
|
ctlr->tdh = ctlr->tdt = ctlr->ntq = 0;
|
|
ctlr->td[ctlr->ntd-1].control = Eor;
|
|
for(i = 0; i < ctlr->ntd; i++)
|
|
if(bp = ctlr->tb[i]){
|
|
ctlr->tb[i] = nil;
|
|
freeb(bp);
|
|
}
|
|
|
|
jehanne_memset(ctlr->rd, 0, sizeof(D)*ctlr->nrd);
|
|
ctlr->rdh = ctlr->rdt = ctlr->nrq = 0;
|
|
ctlr->rd[ctlr->nrd-1].control = Eor;
|
|
for(i = 0; i < ctlr->nrd; i++)
|
|
if(bp = ctlr->rb[i]){
|
|
ctlr->rb[i] = nil;
|
|
freeb(bp);
|
|
}
|
|
|
|
rtl8169replenish(ctlr);
|
|
|
|
cplusc = csr16r(ctlr, Cplusc);
|
|
cplusc &= ~(Endian|Rxchksum);
|
|
cplusc |= Txenb|Mulrw;
|
|
switch(ctlr->macv){
|
|
case Macv40:
|
|
case Macv44:
|
|
cplusc |= Macstatdis;
|
|
break;
|
|
default:
|
|
cplusc |= Rxenb;
|
|
break;
|
|
}
|
|
csr16w(ctlr, Cplusc, cplusc);
|
|
|
|
csr32w(ctlr, Tnpds+4, 0);
|
|
csr32w(ctlr, Tnpds, PCIWADDR32(ctlr->td));
|
|
csr32w(ctlr, Rdsar+4, 0);
|
|
csr32w(ctlr, Rdsar, PCIWADDR32(ctlr->rd));
|
|
|
|
csr8w(ctlr, Cr, Te|Re);
|
|
|
|
csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
|
|
ctlr->tcr = csr32r(ctlr, Tcr);
|
|
ctlr->rcr = Rxfthnone|Mrxdmaunlimited|Ab|Am|Apm;
|
|
ctlr->mchash = 0;
|
|
csr32w(ctlr, Mar0, 0);
|
|
csr32w(ctlr, Mar0+4, 0);
|
|
csr32w(ctlr, Rcr, ctlr->rcr);
|
|
|
|
/* maximum packet sizes, unlimited */
|
|
csr8w(ctlr, Etx, 0x3f);
|
|
csr16w(ctlr, Rms, 0x3fff);
|
|
|
|
csr16w(ctlr, Coal, 0);
|
|
|
|
/* no early rx interrupts */
|
|
r = csr16r(ctlr, Mulint) & 0xF000;
|
|
csr16w(ctlr, Mulint, r);
|
|
|
|
ctlr->imr = Serr|Fovw|Punlc|Rdu|Ter|Rer|Rok|Tdu;
|
|
csr16w(ctlr, Imr, ctlr->imr);
|
|
|
|
csr32w(ctlr, Mpc, 0);
|
|
|
|
iunlock(&ctlr->l);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
rtl8169reseter(void *arg)
|
|
{
|
|
Ether *edev;
|
|
Ctlr *ctlr;
|
|
|
|
edev = arg;
|
|
|
|
for(;;){
|
|
rtl8169init(edev);
|
|
|
|
ctlr = edev->ctlr;
|
|
qunlock(&ctlr->alock);
|
|
|
|
while(waserror())
|
|
;
|
|
sleep(&ctlr->reset, return0, nil);
|
|
poperror();
|
|
|
|
qlock(&ctlr->alock);
|
|
}
|
|
}
|
|
|
|
static void
|
|
rtl8169attach(Ether* edev)
|
|
{
|
|
int timeo;
|
|
Ctlr *ctlr;
|
|
|
|
ctlr = edev->ctlr;
|
|
qlock(&ctlr->alock);
|
|
if(!ctlr->init){
|
|
ctlr->ntd = Ntd;
|
|
ctlr->nrd = Nrd;
|
|
ctlr->tb = jehanne_malloc(ctlr->ntd*sizeof(Block*));
|
|
ctlr->rb = jehanne_malloc(ctlr->nrd*sizeof(Block*));
|
|
ctlr->td = jehanne_mallocalign(sizeof(D)*ctlr->ntd, 256, 0, 0);
|
|
ctlr->rd = jehanne_mallocalign(sizeof(D)*ctlr->nrd, 256, 0, 0);
|
|
ctlr->dtcc = jehanne_mallocalign(sizeof(Dtcc), 64, 0, 0);
|
|
if(ctlr->rb == nil || ctlr->rb == nil ||
|
|
ctlr->rd == nil || ctlr->rd == nil || ctlr->dtcc == nil){
|
|
jehanne_free(ctlr->tb);
|
|
ctlr->tb = nil;
|
|
jehanne_free(ctlr->rb);
|
|
ctlr->rb = nil;
|
|
jehanne_free(ctlr->td);
|
|
ctlr->td = nil;
|
|
jehanne_free(ctlr->rd);
|
|
ctlr->rd = nil;
|
|
jehanne_free(ctlr->dtcc);
|
|
ctlr->dtcc = nil;
|
|
qunlock(&ctlr->alock);
|
|
error(Enomem);
|
|
}
|
|
ctlr->init = 1;
|
|
kproc("rtl8169", rtl8169reseter, edev);
|
|
|
|
/* rtl8169reseter() does qunlock(&ctlr->alock) when complete */
|
|
qlock(&ctlr->alock);
|
|
}
|
|
qunlock(&ctlr->alock);
|
|
|
|
/*
|
|
* Wait for link to be ready.
|
|
*/
|
|
for(timeo = 0; timeo < 35; timeo++){
|
|
if(miistatus(ctlr->mii) == 0)
|
|
break;
|
|
delay(100); /* print fewer miistatus messages */
|
|
}
|
|
}
|
|
|
|
static void
|
|
rtl8169link(Ether* edev)
|
|
{
|
|
uint32_t r;
|
|
int limit;
|
|
Ctlr *ctlr;
|
|
|
|
ctlr = edev->ctlr;
|
|
|
|
r = csr8r(ctlr, Phystatus);
|
|
/*
|
|
* Maybe the link changed - do we care very much?
|
|
* Could stall transmits if no link, maybe?
|
|
*/
|
|
edev->netif.link = (r & Linksts) != 0;
|
|
|
|
limit = 256*1024;
|
|
if(r & Speed10){
|
|
edev->netif.mbps = 10;
|
|
limit = 65*1024;
|
|
} else if(r & Speed100)
|
|
edev->netif.mbps = 100;
|
|
else if(r & Speed1000)
|
|
edev->netif.mbps = 1000;
|
|
|
|
if(edev->netif.oq != nil)
|
|
qsetlimit(edev->netif.oq, limit);
|
|
}
|
|
|
|
static void
|
|
rtl8169transmit(Ether* edev)
|
|
{
|
|
D *d;
|
|
Block *bp;
|
|
Ctlr *ctlr;
|
|
int x;
|
|
|
|
ctlr = edev->ctlr;
|
|
|
|
if(!canlock(&ctlr->l))
|
|
return;
|
|
for(x = ctlr->tdh; ctlr->ntq > 0; x = NEXT(x, ctlr->ntd)){
|
|
d = &ctlr->td[x];
|
|
if(d->control & Own)
|
|
break;
|
|
|
|
/*
|
|
* Free it up.
|
|
* Need to clean the descriptor here? Not really.
|
|
* Simple freeb for now (no chain and freeblist).
|
|
* Use ntq count for now.
|
|
*/
|
|
freeb(ctlr->tb[x]);
|
|
ctlr->tb[x] = nil;
|
|
ctlr->ntq--;
|
|
}
|
|
ctlr->tdh = x;
|
|
|
|
x = ctlr->tdt;
|
|
while(ctlr->ntq < (ctlr->ntd-1)){
|
|
if((bp = qget(edev->netif.oq)) == nil)
|
|
break;
|
|
|
|
d = &ctlr->td[x];
|
|
d->addrlo = PCIWADDR32(bp->rp);
|
|
d->addrhi = 0;
|
|
coherence();
|
|
d->control = (d->control & Eor) | Own | Fs | Ls | BLEN(bp);
|
|
|
|
ctlr->tb[x] = bp;
|
|
ctlr->ntq++;
|
|
|
|
x = NEXT(x, ctlr->ntd);
|
|
}
|
|
if(x != ctlr->tdt)
|
|
ctlr->tdt = x;
|
|
else if(ctlr->ntq >= (ctlr->ntd-1))
|
|
ctlr->txdu++;
|
|
|
|
if(ctlr->ntq > 0){
|
|
coherence();
|
|
csr8w(ctlr, Tppoll, Npq);
|
|
}
|
|
unlock(&ctlr->l);
|
|
}
|
|
|
|
static void
|
|
rtl8169receive(Ether* edev)
|
|
{
|
|
D *d;
|
|
Block *bp;
|
|
Ctlr *ctlr;
|
|
uint32_t control;
|
|
int x;
|
|
|
|
ctlr = edev->ctlr;
|
|
x = ctlr->rdh;
|
|
for(;;){
|
|
d = &ctlr->rd[x];
|
|
if((control = d->control) & Own)
|
|
break;
|
|
|
|
bp = ctlr->rb[x];
|
|
ctlr->rb[x] = nil;
|
|
ctlr->nrq--;
|
|
|
|
x = NEXT(x, ctlr->nrd);
|
|
ctlr->rdh = x;
|
|
|
|
if(ctlr->nrq < ctlr->nrd/2)
|
|
rtl8169replenish(ctlr);
|
|
|
|
if((control & (Fs|Ls|Res)) == (Fs|Ls)){
|
|
bp->wp = bp->rp + (control & RxflMASK) - 4;
|
|
|
|
if(control & Fovf)
|
|
ctlr->fovf++;
|
|
if(control & Mar)
|
|
ctlr->mcast++;
|
|
|
|
switch(control & (Pid1|Pid0)){
|
|
default:
|
|
break;
|
|
case Pid0:
|
|
if(control & Tcpf){
|
|
ctlr->tcpf++;
|
|
break;
|
|
}
|
|
bp->flag |= Btcpck;
|
|
break;
|
|
case Pid1:
|
|
if(control & Udpf){
|
|
ctlr->udpf++;
|
|
break;
|
|
}
|
|
bp->flag |= Budpck;
|
|
break;
|
|
case Pid1|Pid0:
|
|
if(control & Ipf){
|
|
ctlr->ipf++;
|
|
break;
|
|
}
|
|
bp->flag |= Bipck;
|
|
break;
|
|
}
|
|
etheriq(edev, bp, 1);
|
|
}else{
|
|
if(!(control & Res))
|
|
ctlr->frag++;
|
|
freeb(bp);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void
|
|
rtl8169restart(Ctlr *ctlr)
|
|
{
|
|
ctlr->imr = 0;
|
|
rtl8169halt(ctlr);
|
|
wakeup(&ctlr->reset);
|
|
}
|
|
|
|
static void
|
|
rtl8169interrupt(Ureg* _, void* arg)
|
|
{
|
|
Ctlr *ctlr;
|
|
Ether *edev;
|
|
uint32_t isr;
|
|
|
|
edev = arg;
|
|
ctlr = edev->ctlr;
|
|
|
|
while((isr = csr16r(ctlr, Isr)) != 0 && isr != 0xFFFF){
|
|
csr16w(ctlr, Isr, isr);
|
|
if((isr & ctlr->imr) == 0)
|
|
break;
|
|
|
|
if(isr & Serr)
|
|
ctlr->serr++;
|
|
if(isr & Fovw)
|
|
ctlr->fovw++;
|
|
if(isr & Rer)
|
|
ctlr->rer++;
|
|
if(isr & Rdu)
|
|
ctlr->rdu++;
|
|
if(isr & Punlc)
|
|
ctlr->punlc++;
|
|
|
|
if(isr & (Serr|Fovw)){
|
|
rtl8169restart(ctlr);
|
|
break;
|
|
}
|
|
|
|
if(isr & (Punlc|Rdu|Rer|Rok))
|
|
rtl8169receive(edev);
|
|
|
|
if(isr & (Tdu|Ter|Tok))
|
|
rtl8169transmit(edev);
|
|
|
|
if(isr & Punlc)
|
|
rtl8169link(edev);
|
|
}
|
|
}
|
|
|
|
int
|
|
vetmacv(Ctlr *ctlr, uint32_t *macv)
|
|
{
|
|
*macv = csr32r(ctlr, Tcr) & HwveridMASK;
|
|
switch(*macv){
|
|
default:
|
|
return -1;
|
|
case Macv01:
|
|
case Macv02:
|
|
case Macv03:
|
|
case Macv04:
|
|
case Macv05:
|
|
case Macv07:
|
|
case Macv07a:
|
|
case Macv11:
|
|
case Macv12:
|
|
case Macv12a:
|
|
case Macv13:
|
|
case Macv14:
|
|
case Macv15:
|
|
case Macv25:
|
|
case Macv26:
|
|
case Macv27:
|
|
case Macv28:
|
|
case Macv29:
|
|
case Macv30:
|
|
case Macv40:
|
|
case Macv44:
|
|
case Macv45:
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
rtl8169pci(void)
|
|
{
|
|
Pcidev *p;
|
|
Ctlr *ctlr;
|
|
int i, port, pcie;
|
|
uint32_t macv;
|
|
|
|
p = nil;
|
|
while(p = pcimatch(p, 0, 0)){
|
|
if(p->ccrb != 0x02 || p->ccru != 0)
|
|
continue;
|
|
|
|
pcie = 0;
|
|
switch(i = ((p->did<<16)|p->vid)){
|
|
default:
|
|
continue;
|
|
case Rtl8100e: /* RTL810[01]E ? */
|
|
case Rtl8168b: /* RTL8168B */
|
|
pcie = 1;
|
|
break;
|
|
case Rtl8169c: /* RTL8169C */
|
|
case Rtl8169sc: /* RTL8169SC */
|
|
case Rtl8169: /* RTL8169 */
|
|
break;
|
|
case (0xC107<<16)|0x1259: /* Corega CG-LAPCIGT */
|
|
i = Rtl8169;
|
|
break;
|
|
}
|
|
|
|
port = p->mem[0].bar & ~0x01;
|
|
if(ioalloc(port, p->mem[0].size, 0, "rtl8169") < 0){
|
|
jehanne_print("rtl8169: port %#ux in use\n", port);
|
|
continue;
|
|
}
|
|
ctlr = jehanne_malloc(sizeof(Ctlr));
|
|
if(ctlr == nil){
|
|
jehanne_print("rtl8169: can't allocate memory\n");
|
|
iofree(port);
|
|
continue;
|
|
}
|
|
ctlr->port = port;
|
|
ctlr->pcidev = p;
|
|
ctlr->pciv = i;
|
|
ctlr->pcie = pcie;
|
|
|
|
if(vetmacv(ctlr, &macv) == -1){
|
|
iofree(port);
|
|
jehanne_free(ctlr);
|
|
jehanne_print("rtl8169: unknown mac %.4ux %.8ux\n", p->did, macv);
|
|
continue;
|
|
}
|
|
|
|
if(pcigetpms(p) > 0){
|
|
pcisetpms(p, 0);
|
|
|
|
for(i = 0; i < 6; i++)
|
|
pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
|
|
pcicfgw8(p, PciINTL, p->intl);
|
|
pcicfgw8(p, PciLTR, p->ltr);
|
|
pcicfgw8(p, PciCLS, p->cls);
|
|
pcicfgw16(p, PciPCR, p->pcr);
|
|
}
|
|
|
|
if(rtl8169reset(ctlr)){
|
|
iofree(port);
|
|
jehanne_free(ctlr);
|
|
jehanne_print("rtl8169: reset failed\n");
|
|
continue;
|
|
}
|
|
|
|
/*
|
|
* Extract the chip hardware version,
|
|
* needed to configure each properly.
|
|
*/
|
|
ctlr->macv = macv;
|
|
|
|
rtl8169mii(ctlr);
|
|
|
|
pcisetbme(p);
|
|
|
|
if(rtl8169ctlrhead != nil)
|
|
rtl8169ctlrtail->next = ctlr;
|
|
else
|
|
rtl8169ctlrhead = ctlr;
|
|
rtl8169ctlrtail = ctlr;
|
|
}
|
|
}
|
|
|
|
static int
|
|
rtl8169pnp(Ether* edev)
|
|
{
|
|
uint32_t r;
|
|
Ctlr *ctlr;
|
|
uint8_t ea[Eaddrlen];
|
|
static int once;
|
|
|
|
if(once == 0){
|
|
once = 1;
|
|
rtl8169pci();
|
|
}
|
|
|
|
/*
|
|
* Any adapter matches if no edev->port is supplied,
|
|
* otherwise the ports must match.
|
|
*/
|
|
for(ctlr = rtl8169ctlrhead; ctlr != nil; ctlr = ctlr->next){
|
|
if(ctlr->active)
|
|
continue;
|
|
if(edev->port == 0 || edev->port == ctlr->port){
|
|
ctlr->active = 1;
|
|
break;
|
|
}
|
|
}
|
|
if(ctlr == nil)
|
|
return -1;
|
|
|
|
edev->ctlr = ctlr;
|
|
edev->port = ctlr->port;
|
|
edev->irq = ctlr->pcidev->intl;
|
|
edev->tbdf = ctlr->pcidev->tbdf;
|
|
edev->netif.mbps = 100;
|
|
edev->maxmtu = Mtu;
|
|
|
|
/*
|
|
* Check if the adapter's station address is to be overridden.
|
|
* If not, read it from the device and set in edev->ea.
|
|
*/
|
|
jehanne_memset(ea, 0, Eaddrlen);
|
|
if(jehanne_memcmp(ea, edev->ea, Eaddrlen) == 0){
|
|
r = csr32r(ctlr, Idr0);
|
|
edev->ea[0] = r;
|
|
edev->ea[1] = r>>8;
|
|
edev->ea[2] = r>>16;
|
|
edev->ea[3] = r>>24;
|
|
r = csr32r(ctlr, Idr0+4);
|
|
edev->ea[4] = r;
|
|
edev->ea[5] = r>>8;
|
|
}
|
|
|
|
edev->attach = rtl8169attach;
|
|
edev->transmit = rtl8169transmit;
|
|
edev->interrupt = rtl8169interrupt;
|
|
edev->ifstat = rtl8169ifstat;
|
|
|
|
edev->netif.arg = edev;
|
|
edev->netif.promiscuous = rtl8169promiscuous;
|
|
edev->netif.multicast = rtl8169multicast;
|
|
|
|
rtl8169link(edev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
ether8169link(void)
|
|
{
|
|
addethercard("rtl8169", rtl8169pnp);
|
|
}
|