464 lines
10 KiB
C
464 lines
10 KiB
C
/* Copyright (C) Charles Forsyth
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* See /doc/license/NOTICE.Plan9-9k.txt for details about the licensing.
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*/
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/* Portions of this file are Copyright (C) 2015-2018 Giacomo Tesio <giacomo@tesio.it>
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* See /doc/license/gpl-2.0.txt for details about the licensing.
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*/
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/* Portions of this file are Copyright (C) 9front's team.
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* See /doc/license/9front-mit for details about the licensing.
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* See http://code.9front.org/hg/plan9front/ for a list of authors.
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*/
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typedef struct BIOS32si BIOS32si;
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typedef struct BIOS32ci BIOS32ci;
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typedef struct Confmem Confmem;
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typedef struct Fxsave Fxsave;
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typedef struct IOConf IOConf;
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typedef struct ISAConf ISAConf;
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typedef struct Label Label;
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typedef struct Lock Lock;
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typedef struct LockEntry LockEntry;
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typedef struct MCPU MCPU;
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typedef struct MFPU MFPU;
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typedef struct MMU MMU;
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typedef struct MMMU MMMU;
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typedef struct Mach Mach;
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typedef uint64_t Mpl;
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typedef Mpl Mreg; /* GAK */
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typedef struct Segdesc Segdesc;
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typedef struct Pcidev Pcidev;
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typedef struct PFPU PFPU;
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typedef struct PMMU PMMU;
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typedef struct PNOTIFY PNOTIFY;
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typedef struct PPAGE PPAGE;
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typedef uint64_t PTE;
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typedef struct RMap RMap;
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typedef struct Proc Proc;
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typedef struct Sys Sys;
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typedef uint64_t uintmem; /* horrible name */
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typedef long Tval;
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typedef struct Ureg Ureg;
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typedef struct Vctl Vctl;
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typedef struct PCArch PCArch;
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typedef union FPsave FPsave;
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typedef struct Fxsave Fxsave;
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typedef struct FPstate FPstate;
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typedef struct PCMmap PCMmap;
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#pragma incomplete BIOS32si
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#pragma incomplete Ureg
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#define MAXSYSARG 6 /* for mount(fd, afd, mpt, flag, arg, dc) */
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/*
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* parameters for sysproc.c
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*/
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#define AOUT_MAGIC (S_MAGIC)
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#define ELF_MAGIC (ELF_MAG)
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/*
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* machine dependent definitions used by ../port/portdat.h
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*/
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struct Lock
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{
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uint64_t sr;
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uintptr_t pc;
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Proc *lp;
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Mach *lm;
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uint32_t key;
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uint16_t isilock;
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long lockcycles;
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};
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struct Label
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{
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uintptr_t sp;
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uintptr_t pc;
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uintptr_t regs[14];
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};
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/*
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* FPsave.status
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*/
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enum
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{
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/* this is a state */
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FPinit= 0,
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FPactive= 1,
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FPinactive= 2,
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/* the following is a bit that can be or'd into the state */
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FPillegal= 0x100,
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};
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/*
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* the FP regs must be stored here, not somewhere pointed to from here.
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* port code assumes this.
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*/
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struct Fxsave {
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uint16_t fcw; /* x87 control word */
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uint16_t fsw; /* x87 status word */
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uint8_t ftw; /* x87 tag word */
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uint8_t zero; /* 0 */
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uint16_t fop; /* last x87 opcode */
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uint64_t rip; /* last x87 instruction pointer */
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uint64_t rdp; /* last x87 data pointer */
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uint32_t mxcsr; /* MMX control and status */
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uint32_t mxcsrmask; /* supported MMX feature bits */
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uint8_t st[128]; /* shared 64-bit media and x87 regs */
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uint8_t xmm[256]; /* 128-bit media regs */
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uint8_t ign[96]; /* reserved, ignored */
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};
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union FPsave {
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uint8_t align[512+15];
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Fxsave;
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};
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struct Segdesc
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{
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uint32_t d0;
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uint32_t d1;
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};
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/*
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* MMU structure for PDP, PD, PT pages.
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*/
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struct MMU
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{
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MMU* next;
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uintptr_t* page;
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int index;
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int level;
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};
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/*
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* MMU stuff in Proc
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*/
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#define NCOLOR 1
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struct PMMU
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{
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MMU* mmuhead;
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MMU* mmutail;
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MMU* kmaphead;
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MMU* kmaptail;
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unsigned long kmapcount;
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unsigned long kmapindex;
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unsigned long mmucount;
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};
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/*
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* things saved in the Proc structure during a notify
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*/
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struct PNOTIFY
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{
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char emptiness;
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};
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struct IOConf
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{
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int nomsi;
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int nolegacyprobe; /* acpi tells us. all negated in case acpi unavailable */
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int noi8042kbd;
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int novga;
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int nocmos;
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};
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extern IOConf ioconf;
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#include "../port/portdat.h"
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/*
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* CPU stuff in Mach.
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*/
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struct MCPU {
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uint32_t cpuinfo[2][4]; /* CPUID instruction output E[ABCD]X */
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int ncpuinfos; /* number of standard entries */
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int ncpuinfoe; /* number of extended entries */
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int isintelcpu; /* */
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};
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/*
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* FPU stuff in Mach.
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*/
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struct MFPU {
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uint16_t fcw; /* x87 control word */
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uint32_t mxcsr; /* MMX control and status */
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uint32_t mxcsrmask; /* supported MMX feature bits */
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};
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/*
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* MMU stuff in Mach.
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*/
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typedef struct {
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uint32_t _0_;
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uint32_t rsp0[2];
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uint32_t rsp1[2];
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uint32_t rsp2[2];
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uint32_t _28_[2];
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uint32_t ist[14];
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uint16_t _92_[5];
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uint16_t iomap;
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} Tss;
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struct MMMU
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{
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uint64_t* pml4; /* pml4 base for this processor (va) */
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Tss* tss; /* tss for this processor */
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Segdesc* gdt; /* gdt for this processor */
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uint64_t mmumap[4]; /* bitmap of pml4 entries for zapping */
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MMU* mmufree; /* freelist for MMU structures */
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unsigned long mmucount; /* number of MMU structures in freelist */
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};
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/*
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* Per processor information.
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*
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* The offsets of the first few elements may be known
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* to low-level assembly code, so do not re-order:
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* machno - no dependency, convention
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* splpc - splhi, spllo, splx
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* proc - syscallentry
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*/
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struct Mach
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{
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uint64_t machno; /* physical id of processor */
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uint64_t splpc; /* pc of last caller to splhi */
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Proc* proc; /* current process on this processor */
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uint64_t tmp0; /* for syscallentry */
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uint64_t tmp1; /* for syscallentry */
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int apicno;
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int online;
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int mode; /* fold into online? GAK */
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void* dbgreg; /* registers for debugging this processor */
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void* dbgsp; /* sp for debugging this processor */
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MMMU;
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uintptr_t stack;
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uint8_t* vsvm;
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uint64_t ticks; /* of the clock since boot time */
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Label sched; /* scheduler wakeup */
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Lock alarmlock; /* access to alarm list */
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void* alarm; /* alarms bound to this clock */
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int inclockintr;
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Proc* readied; /* for runproc */
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uint64_t schedticks; /* next forced context switch */
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int color;
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int tlbfault;
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int tlbpurge;
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int pfault;
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int cs;
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int syscall;
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int load;
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int intr;
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int mmuflush; /* make current proc flush it's mmu state */
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int ilockdepth;
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uintptr_t ilockpc;
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Perf perf; /* performance counters */
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void (*perfintr)(Ureg*, void*);
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int lastintr;
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int loopconst;
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Lock apictimerlock;
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uint64_t cyclefreq; /* Frequency of user readable cycle counter */
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uint64_t cpuhz;
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int cpumhz;
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int cpuidax;
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int cpuidcx;
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int cpuiddx;
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char cpuidid[16];
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char* cpuidtype;
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int havetsc;
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int havepge;
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uint64_t tscticks;
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uint64_t rdtsc;
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// LockEntry locks[8];
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MFPU FPU;
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MCPU;
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};
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struct Confmem
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{
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uintptr_t base;
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unsigned long npage;
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uintptr_t kbase;
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uintptr_t klimit;
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};
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/*
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* This is the low memory map, between 0x100000 and 0x110000.
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* It is located there to allow fundamental datastructures to be
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* created and used before knowing where free memory begins
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* (e.g. there may be modules located after the kernel BSS end).
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* The layout is known in the bootstrap code in l32p.s.
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* It is logically two parts: the per processor data structures
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* for the bootstrap processor (stack, Mach, vsvm, and page tables),
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* and the global information about the system (syspage, ptrpage).
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* Some of the elements must be aligned on page boundaries, hence
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* the unions.
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*/
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struct Sys
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{
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Ureg* boot_regs;
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unsigned int nmach; /* processors */
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unsigned int nproc; /* processes */
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unsigned int monitor; /* has monitor? */
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unsigned int npages; /* total physical pages of memory */
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unsigned int upages; /* user page pool */
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unsigned int nimage; /* number of images */
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Confmem mem[16]; /* physical memory */
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unsigned int copymode; /* 0 is copy on write, 1 is copy on reference */
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unsigned int ialloc; /* max interrupt time allocation in bytes */
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unsigned int pipeqsize; /* size in bytes of pipe queues */
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int nuart; /* number of uart devices */
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char* architecture;
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uint64_t ticks;
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Mach* machptr[MACHMAX];
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uint64_t pmstart; /* physical memory */
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uint64_t pmoccupied; /* how much is occupied */
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uint64_t pmunassigned; /* how much to keep back from page pool */
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uint64_t pmpaged; /* how much assigned to page pool */
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};
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extern Sys* sys;
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extern uint32_t MemMin; /* set by entry.S */
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/*
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* KMap
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*/
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typedef void KMap;
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#define VA(k) (void*)(k)
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/*
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* routines for things outside the PC model, like power management
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*/
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struct PCArch
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{
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char* id;
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int (*ident)(void); /* this should be in the model */
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void (*reset)(void); /* this should be in the model */
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int (*serialpower)(int); /* 1 == on, 0 == off */
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int (*modempower)(int); /* 1 == on, 0 == off */
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void (*intrinit)(void);
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int (*intrenable)(Vctl*);
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int (*intrvecno)(int);
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int (*intrdisable)(int);
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void (*introff)(void);
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void (*intron)(void);
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void (*clockenable)(void);
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uint64_t (*fastclock)(uint64_t*);
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void (*timerset)(uint64_t);
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};
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extern PCArch *arch; /* PC architecture */
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/* cpuid instruction result register bits */
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enum {
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/* cx */
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Monitor = 1<<3,
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/* dx */
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Fpuonchip = 1<<0,
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Vmex = 1<<1, /* virtual-mode extensions */
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Pse = 1<<3, /* page size extensions */
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Tsc = 1<<4, /* time-stamp counter */
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Cpumsr = 1<<5, /* model-specific registers, rdmsr/wrmsr */
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Pae = 1<<6, /* physical-addr extensions */
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Mce = 1<<7, /* machine-check exception */
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Cmpxchg8b = 1<<8,
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Cpuapic = 1<<9,
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Mtrr = 1<<12, /* memory-type range regs. */
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Pge = 1<<13, /* page global extension */
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Mca = 1<<14, /* machine-check architecture */
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Pat = 1<<16, /* page attribute table */
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Pse2 = 1<<17, /* more page size extensions */
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Clflush = 1<<19,
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Acpif = 1<<22, /* therm control msr */
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Mmx = 1<<23,
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Fxsr = 1<<24, /* have SSE FXSAVE/FXRSTOR */
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Sse = 1<<25, /* thus sfence instr. */
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Sse2 = 1<<26, /* thus mfence & lfence instr.s */
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Rdrnd = 1<<30, /* RDRAND support bit */
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};
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/* Informations about active processors for
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* bootstrap and shutdown.
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*/
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struct
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{
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char machs[MACHMAX]; /* bitmap of active CPUs */
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int exiting; /* shutdown */
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int ispanic; /* shutdown in response to a panic */
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int thunderbirdsarego; /* F.A.B. */
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}active;
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/*
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* a parsed plan9.ini line
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*/
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#define NISAOPT 8
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struct ISAConf {
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char* type;
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uintptr_t port;
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int irq;
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uint32_t dma;
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uintptr_t mem;
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usize size;
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uint32_t freq;
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int tbdf; /* type+busno+devno+funcno */
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int nopt;
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char* opt[NISAOPT];
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};
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typedef struct BIOS32ci { /* BIOS32 Calling Interface */
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uint32_t eax;
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uint32_t ebx;
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uint32_t ecx;
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uint32_t edx;
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uint32_t esi;
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uint32_t edi;
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} BIOS32ci;
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#define MACHP(n) (sys->machptr[n])
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/*
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* The Mach structures must be available via the per-processor
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* MMU information array machptr, mainly for disambiguation and access to
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* the clock which is only maintained by the bootstrap processor (0).
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*/
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register Mach* m asm("r15");
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register Proc* up asm("r14");
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/*
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* Horrid.
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*/
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#ifdef _DBGC_
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#define DBGFLG (dbgflg[_DBGC_])
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#else
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#define DBGFLG (0)
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#endif /* _DBGC_ */
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#define DBG(...) if(!DBGFLG){}else dbgprint(__VA_ARGS__)
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extern char dbgflg[256];
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#define dbgprint jehanne_print /* for now */
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