465 lines
11 KiB
C
465 lines
11 KiB
C
/*
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* This file is part of the UCB release of Plan 9. It is subject to the license
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* terms in the LICENSE file found in the top-level directory of this
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* distribution and at http://akaros.cs.berkeley.edu/files/Plan9License. No
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* part of the UCB release of Plan 9, including this file, may be copied,
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* modified, propagated, or distributed except according to the terms contained
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* in the LICENSE file.
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*/
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/*
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* Generic VGA registers.
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*/
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enum {
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MiscW = 0x03C2, /* Miscellaneous Output (W) */
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MiscR = 0x03CC, /* Miscellaneous Output (R) */
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Status0 = 0x03C2, /* Input status 0 (R) */
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Status1 = 0x03DA, /* Input Status 1 (R) */
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FeatureR = 0x03CA, /* Feature Control (R) */
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FeatureW = 0x03DA, /* Feature Control (W) */
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Seqx = 0x03C4, /* Sequencer Index, Data at Seqx+1 */
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Crtx = 0x03D4, /* CRT Controller Index, Data at Crtx+1 */
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Grx = 0x03CE, /* Graphics Controller Index, Data at Grx+1 */
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Attrx = 0x03C0, /* Attribute Controller Index and Data */
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PaddrW = 0x03C8, /* Palette Address Register, write */
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Pdata = 0x03C9, /* Palette Data Register */
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Pixmask = 0x03C6, /* Pixel Mask Register */
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PaddrR = 0x03C7, /* Palette Address Register, read */
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Pstatus = 0x03C7, /* DAC Status (RO) */
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Pcolours = 256, /* Palette */
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Red = 0,
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Green = 1,
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Blue = 2,
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Pblack = 0x00,
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Pwhite = 0xFF,
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};
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enum {
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RefFreq = 14318180, /* External Reference Clock frequency */
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VgaFreq0 = 25175000,
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VgaFreq1 = 28322000,
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};
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enum {
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Namelen = 32,
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};
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typedef struct Ctlr Ctlr;
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typedef struct Vga Vga;
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typedef struct Ctlr {
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char name[Namelen+1];
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void (*snarf)(Vga*, Ctlr*);
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void (*options)(Vga*, Ctlr*);
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void (*init)(Vga*, Ctlr*);
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void (*load)(Vga*, Ctlr*);
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void (*dump)(Vga*, Ctlr*);
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char* type;
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uint32_t flag;
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Ctlr* link;
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} Ctlr;
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enum { /* flag */
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Fsnarf = 0x00000001, /* snarf done */
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Foptions = 0x00000002, /* options done */
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Finit = 0x00000004, /* init done */
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Fload = 0x00000008, /* load done */
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Fdump = 0x00000010, /* dump done */
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Ferror = 0x00000020, /* error during snarf */
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Hpclk2x8 = 0x00000100, /* have double 8-bit mode */
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Upclk2x8 = 0x00000200, /* use double 8-bit mode */
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Henhanced = 0x00000400, /* have enhanced mode */
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Uenhanced = 0x00000800, /* use enhanced mode */
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Hpvram = 0x00001000, /* have parallel VRAM */
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Upvram = 0x00002000, /* use parallel VRAM */
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Hextsid = 0x00004000, /* have external SID mode */
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Uextsid = 0x00008000, /* use external SID mode */
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Hclk2 = 0x00010000, /* have clock-doubler */
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Uclk2 = 0x00020000, /* use clock-doubler */
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Hlinear = 0x00040000, /* have linear-address mode */
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Ulinear = 0x00080000, /* use linear-address mode */
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Hclkdiv = 0x00100000, /* have a clock-divisor */
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Uclkdiv = 0x00200000, /* use clock-divisor */
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Hsid32 = 0x00400000, /* have a 32-bit (as opposed to 64-bit) SID */
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};
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typedef struct Attr Attr;
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typedef struct Attr {
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char* attr;
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char* val;
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Attr* next;
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} Attr;
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typedef struct Mode {
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char type[Namelen+1]; /* monitor type e.g. "vs1782" */
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char size[Namelen+1]; /* size e.g. "1376x1024x8" */
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char chan[Namelen+1]; /* channel descriptor, e.g. "m8" or "r8g8b8a8" */
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char name[Namelen+1]; /* optional */
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int frequency; /* Dot Clock (MHz) */
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int deffrequency; /* Default dot clock if calculation can't be done */
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int x; /* Horizontal Display End (Crt01), from .size[] */
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int y; /* Vertical Display End (Crt18), from .size[] */
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int z; /* depth, from .size[] */
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int ht; /* Horizontal Total (Crt00) */
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int shb; /* Start Horizontal Blank (Crt02) */
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int ehb; /* End Horizontal Blank (Crt03) */
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int shs; /* optional Start Horizontal Sync (Crt04) */
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int ehs; /* optional End Horizontal Sync (Crt05) */
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int vt; /* Vertical Total (Crt06) */
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int vrs; /* Vertical Retrace Start (Crt10) */
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int vre; /* Vertical Retrace End (Crt11) */
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int vbs; /* optional Vertical Blank Start */
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int vbe; /* optional Vertical Blank End */
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uint32_t videobw;
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char hsync;
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char vsync;
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char interlace;
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Attr* attr;
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} Mode;
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/*
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* The sizes of the register sets are large as many SVGA and GUI chips have extras.
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* The Crt registers are uint16_ts in order to keep overflow bits handy.
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* The clock elements are used for communication between the VGA, RAMDAC and clock chips;
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* they can use them however they like, it's assumed they will be used compatibly.
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*
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* The mode->x, mode->y coordinates are the physical size of the screen.
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* Virtx and virty are the coordinates of the underlying memory image.
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* This can be used to implement panning around a larger screen or to cope
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* with chipsets that need the in-memory pixel line width to be a round number.
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* For example, virge.c uses this because the Savage chipset needs the pixel
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* width to be a multiple of 16. Also, mga2164w.c needs the pixel width
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* to be a multiple of 128.
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*
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* Vga->panning differentiates between these two uses of virtx, virty.
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*
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* (14 October 2001, rsc) Most drivers don't know the difference between
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* mode->x and virtx, a bug that should be corrected. Vga.c, virge.c, and
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* mga2164w.c know. For the others, the computation that sets crt[0x13]
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* should use virtx instead of mode->x (and maybe other places change too,
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* dependent on the driver).
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*/
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typedef struct Vga {
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uint8_t misc;
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uint8_t feature;
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uint8_t sequencer[256];
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uint16_t crt[256];
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uint8_t graphics[256];
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uint8_t attribute[256];
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uint8_t pixmask;
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uint8_t pstatus;
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uint8_t palette[Pcolours][3];
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uint32_t f[2]; /* clock */
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uint32_t d[2];
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uint32_t i[2];
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uint32_t m[2];
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uint32_t n[2];
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uint32_t p[2];
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uint32_t q[2];
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uint32_t r[2];
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uint32_t vma; /* video memory linear-address alignment */
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uint32_t vmb; /* video memory linear-address base */
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uint32_t apz; /* aperture size */
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uint32_t vmz; /* video memory size */
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uint32_t membw; /* memory bandwidth, MB/s */
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long offset; /* BIOS string offset */
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char* bios; /* matching BIOS string */
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Pcidev* pci; /* matching PCI device if any */
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Mode* mode;
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uint32_t virtx; /* resolution of virtual screen */
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uint32_t virty;
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int panning; /* pan the virtual screen */
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Ctlr* ctlr;
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Ctlr* ramdac;
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Ctlr* clock;
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Ctlr* hwgc;
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Ctlr* vesa;
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Ctlr* link;
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int linear;
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Attr* attr;
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void* private;
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} Vga;
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/* 3dfx.c */
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extern Ctlr tdfx;
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extern Ctlr tdfxhwgc;
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/* ark2000pv.c */
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extern Ctlr ark2000pv;
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extern Ctlr ark2000pvhwgc;
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/* att20c49x.c */
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extern Ctlr att20c490;
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extern Ctlr att20c491;
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extern Ctlr att20c492;
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/* att21c498.c */
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extern uint8_t attdaci(uint8_t);
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extern void attdaco(uint8_t, uint8_t);
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extern Ctlr att21c498;
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/* bt485.c */
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extern uint8_t bt485i(uint8_t);
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extern void bt485o(uint8_t, uint8_t);
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extern Ctlr bt485;
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/* ch9294.c */
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extern Ctlr ch9294;
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/* clgd542x.c */
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extern void clgd54xxclock(Vga*, Ctlr*);
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extern Ctlr clgd542x;
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extern Ctlr clgd542xhwgc;
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/* clgd546x.c */
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extern Ctlr clgd546x;
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extern Ctlr clgd546xhwgc;
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/* ct65540.c */
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extern Ctlr ct65540;
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extern Ctlr ct65545;
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extern Ctlr ct65545hwgc;
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/* cyber938x.c */
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extern Ctlr cyber938x;
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extern Ctlr cyber938xhwgc;
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/* data.c */
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extern int cflag;
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extern int dflag;
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extern Ctlr *ctlrs[];
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extern uint16_t dacxreg[4];
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/* db.c */
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extern char* dbattr(Attr*, char*);
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extern int dbctlr(char*, Vga*);
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extern Mode* dbmode(char*, char*, char*);
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extern void dbdumpmode(Mode*);
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/* error.c */
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extern void error(char*, ...);
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extern void trace(char*, ...);
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extern int vflag, Vflag;
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/* et4000.c */
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extern Ctlr et4000;
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/* et4000hwgc.c */
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extern Ctlr et4000hwgc;
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/* hiqvideo.c */
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extern Ctlr hiqvideo;
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extern Ctlr hiqvideohwgc;
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/* i81x.c */
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extern Ctlr i81x;
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extern Ctlr i81xhwgc;
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/* ibm8514.c */
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extern Ctlr ibm8514;
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/* icd2061a.c */
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extern Ctlr icd2061a;
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/* ics2494.c */
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extern Ctlr ics2494;
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extern Ctlr ics2494a;
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/* ics534x.c */
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extern Ctlr ics534x;
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/* io.c */
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extern uint8_t inportb(int32_t);
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extern void outportb(int32_t, uint8_t);
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extern uint16_t inportw(int32_t);
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extern void outportw(int32_t, uint16_t);
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extern uint32_t inportl(int32_t);
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extern void outportl(int32_t, uint32_t);
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extern char* vgactlr(char*, char*);
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extern void vgactlw(char*, char*);
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extern char* readbios(int32_t, int32_t);
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extern void dumpbios(int32_t);
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extern void error(char*, ...);
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extern void* alloc(uint32_t);
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extern void printitem(char*, char*);
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extern void printreg(uint32_t);
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extern void printflag(uint32_t);
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extern void setpalette(int, int, int, int);
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extern int curprintindex;
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/* mach32.c */
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extern Ctlr mach32;
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/* mach64.c */
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extern Ctlr mach64;
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/* mach64xx.c */
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extern Ctlr mach64xx;
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extern Ctlr mach64xxhwgc;
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/* main.c */
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extern char* chanstr[];
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extern void resyncinit(Vga*, Ctlr*, uint32_t, uint32_t);
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extern void sequencer(Vga*, int);
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extern void main(int, char*[]);
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Biobuf stdout;
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/* mga2164w.c */
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extern Ctlr mga2164w;
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extern Ctlr mga2164whwgc;
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/* neomagic.c */
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extern Ctlr neomagic;
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extern Ctlr neomagichwgc;
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/* nvidia.c */
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extern Ctlr nvidia;
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extern Ctlr nvidiahwgc;
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/* radeon.c */
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extern Ctlr radeon;
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extern Ctlr radeonhwgc;
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/* palette.c */
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extern Ctlr palette;
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/* pci.c */
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typedef struct Pcidev Pcidev;
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extern int pcicfgr8(Pcidev*, int);
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extern int pcicfgr16(Pcidev*, int);
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extern int pcicfgr32(Pcidev*, int);
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extern void pcicfgw8(Pcidev*, int, int);
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extern void pcicfgw16(Pcidev*, int, int);
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extern void pcicfgw32(Pcidev*, int, int);
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extern void pcihinv(Pcidev*);
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extern Pcidev* pcimatch(Pcidev*, int, int);
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/* rgb524.c */
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extern Ctlr rgb524;
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/* rgb524mn.c */
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extern uint8_t (*rgb524mnxi)(Vga*, int);
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extern void (*rgb524mnxo)(Vga*, int, uint8_t);
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extern Ctlr rgb524mn;
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/* s3801.c */
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extern Ctlr s3801;
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extern Ctlr s3805;
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/* s3928.c */
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extern Ctlr s3928;
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/* s3clock.c */
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extern Ctlr s3clock;
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/* s3generic.c */
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extern Ctlr s3generic;
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/* s3hwgc.c */
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extern Ctlr bt485hwgc;
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extern Ctlr rgb524hwgc;
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extern Ctlr s3hwgc;
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extern Ctlr tvp3020hwgc;
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extern Ctlr tvp3026hwgc;
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/* sc15025.c */
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extern Ctlr sc15025;
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/* stg1702.c */
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extern Ctlr stg1702;
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/* t2r4.c */
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extern Ctlr t2r4;
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extern Ctlr t2r4hwgc;
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/* trio64.c */
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extern void trio64clock(Vga*, Ctlr*);
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extern Ctlr trio64;
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/* tvp3020.c */
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extern uint8_t tvp3020i(uint8_t);
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extern uint8_t tvp3020xi(uint8_t);
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extern void tvp3020o(uint8_t, uint8_t);
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extern void tvp3020xo(uint8_t, uint8_t);
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extern Ctlr tvp3020;
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/* tvp3025.c */
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extern Ctlr tvp3025;
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/* tvp3025clock.c */
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extern Ctlr tvp3025clock;
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/* tvp3026.c */
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extern uint8_t tvp3026xi(uint8_t);
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extern void tvp3026xo(uint8_t, uint8_t);
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extern Ctlr tvp3026;
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/* tvp3026clock.c */
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extern Ctlr tvp3026clock;
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/* vga.c */
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extern uint8_t vgai(int32_t);
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extern uint8_t vgaxi(int32_t, uint8_t);
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extern void vgao(int32_t, uint8_t);
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extern void vgaxo(int32_t, uint8_t, uint8_t);
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extern Ctlr generic;
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/* vesa.c */
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extern Ctlr vesa;
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extern Ctlr softhwgc; /* has to go somewhere */
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extern int dbvesa(Vga*);
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extern Mode *dbvesamode(char*);
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extern void vesatextmode(void);
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/* virge.c */
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extern Ctlr virge;
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/* vision864.c */
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extern Ctlr vision864;
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/* vision964.c */
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extern Ctlr vision964;
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/* vision968.c */
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extern Ctlr vision968;
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/* vmware.c */
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extern Ctlr vmware;
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extern Ctlr vmwarehwgc;
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/* w30c516.c */
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extern Ctlr w30c516;
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/* mga4xx.c */
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extern Ctlr mga4xx;
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extern Ctlr mga4xxhwgc;
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#pragma varargck argpos error 1
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#pragma varargck argpos trace 1
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